From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8012BA328D for ; Tue, 22 Oct 2019 17:28:31 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 446961BEEB; Tue, 22 Oct 2019 17:28:31 +0200 (CEST) Received: from foss.arm.com (unknown [217.140.110.172]) by dpdk.org (Postfix) with ESMTP id 6BA3A1BEE3 for ; Tue, 22 Oct 2019 17:28:29 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EF9CE1766; Tue, 22 Oct 2019 08:28:19 -0700 (PDT) Received: from net-arm-thunderx2-01.test.ast.arm.com (net-arm-thunderx2-01.shanghai.arm.com [10.169.40.40]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 7859B3F71A; Tue, 22 Oct 2019 08:28:10 -0700 (PDT) From: Gavin Hu To: dev@dpdk.org Cc: nd@arm.com, david.marchand@redhat.com, maxime.coquelin@redhat.com, tiwei.bie@intel.com, thomas@monjalon.net, rasland@mellanox.com, matan@mellanox.com, shahafs@mellanox.com, viacheslavo@mellanox.com, arybchenko@solarflare.com, stephen@networkplumber.org, hemant.agrawal@nxp.com, jerinj@marvell.com, pbhagavatula@marvell.com, Honnappa.Nagarahalli@arm.com, ruifeng.wang@arm.com, phil.yang@arm.com, joyce.kong@arm.com, steve.capper@arm.com Date: Tue, 22 Oct 2019 23:27:52 +0800 Message-Id: <1571758074-16445-2-git-send-email-gavin.hu@arm.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1571758074-16445-1-git-send-email-gavin.hu@arm.com> References: <1571758074-16445-1-git-send-email-gavin.hu@arm.com> Subject: [dpdk-dev] [PATCH v1 1/3] eal/arm64: relax the io barrier for aarch64 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Armv8's peripheral coherence order is a total order on all reads and writes to that peripheral.[1] The Peripheral coherence order for a Memory-mapped peripheral signifies the order in which accesses arrive at the endpoint. For a read or a write RW1 and a read or a write RW2 to the same peripheral, then RW1 will appear in the Peripheral coherence order for the peripheral before RW2 if either of the following cases apply: 1. RW1 and RW2 are accesses using Non-cacheable or Device attributes and RW1 is Ordered-before RW2. 2. RW1 and RW2 are accesses using Device-nGnRE or Device-nGnRnE attributes and RW1 appears in program order before RW2. On arm platforms, all the PCI resources are mapped to nGnRE device memory [2], the above case 2 holds true, that means the perepheral coherence order applies here and just a compiler barrier is sufficient for rte io barriers. [1] Section B2.3.4 of ARMARM, https://developer.arm.com/docs/ddi0487/lates t/arm-architecture-reference-manual-armv8-for-armv8-a-architecture-profile [2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/ tree/drivers/pci/pci-sysfs.c?h=v5.4-rc3#n1204 Signed-off-by: Gavin Hu Reviewed-by: Steve Capper Reviewed-by: Phil Yang --- lib/librte_eal/common/include/arch/arm/rte_atomic_64.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h index 859ae12..fd63956 100644 --- a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h +++ b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h @@ -34,11 +34,11 @@ extern "C" { #define rte_smp_rmb() dmb(ishld) -#define rte_io_mb() rte_mb() +#define rte_io_mb() rte_compiler_barrier() -#define rte_io_wmb() rte_wmb() +#define rte_io_wmb() rte_compiler_barrier() -#define rte_io_rmb() rte_rmb() +#define rte_io_rmb() rte_compiler_barrier() #define rte_cio_wmb() dmb(oshst) -- 2.7.4