From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 72D10A0351; Mon, 18 Nov 2019 11:07:20 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id DF2F22BAA; Mon, 18 Nov 2019 11:07:16 +0100 (CET) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by dpdk.org (Postfix) with ESMTP id 54DCE2BA8 for ; Mon, 18 Nov 2019 11:07:16 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id DBFC731B; Mon, 18 Nov 2019 02:07:15 -0800 (PST) Received: from net-arm-thunderx2-01.test.ast.arm.com (net-arm-thunderx2-01.shanghai.arm.com [10.169.40.40]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 162E83F703; Mon, 18 Nov 2019 02:07:11 -0800 (PST) From: Joyce Kong To: dev@dpdk.org Cc: nd@arm.com, thomas@monjalon.net, jerinj@marvell.com, stephen@networkplumber.org, mb@smartsharesystems.com, david.marchand@redhat.com, honnappa.nagarahalli@arm.com, gavin.hu@arm.com, ravi1.kumar@amd.com, rmody@marvell.com, shshaikh@marvell.com, xuanziyang2@huawei.com, cloud.wangxiaoyun@huawei.com, zhouguoyang@huawei.com Date: Mon, 18 Nov 2019 18:06:54 +0800 Message-Id: <1574071619-10407-2-git-send-email-joyce.kong@arm.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1574071619-10407-1-git-send-email-joyce.kong@arm.com> References: <1574071619-10407-1-git-send-email-joyce.kong@arm.com> In-Reply-To: <1571125801-45773-1-git-send-email-joyce.kong@arm.com> References: <1571125801-45773-1-git-send-email-joyce.kong@arm.com> Subject: [dpdk-dev] [PATCH v3 1/6] lib/eal: implement the family of rte bit operation APIs X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Archived-At: List-Archive: There are a lot functions of bit operations scattered and duplicated in PMDs, consolidating them into a common API family is necessary. Furthermore, when the bit operation is applied to the IO devices, use __ATOMIC_ACQ_REL to ensure the ordering for io bit operation. Signed-off-by: Joyce Kong Reviewed-by: Gavin Hu Reviewed-by: Phil Yang --- doc/api/doxy-api-index.md | 3 +- lib/librte_eal/common/Makefile | 1 + lib/librte_eal/common/include/rte_bitops.h | 474 +++++++++++++++++++++ lib/librte_eal/common/meson.build | 1 + 4 files changed, 478 insertions(+), 1 deletion(-) create mode 100644 lib/librte_eal/common/include/rte_bitops.h diff --git a/doc/api/doxy-api-index.md b/doc/api/doxy-api-index.md index dff496be0..1aed266d3 100644 --- a/doc/api/doxy-api-index.md +++ b/doc/api/doxy-api-index.md @@ -181,4 +181,5 @@ The public API headers are grouped by topics: [common] (@ref rte_common.h), [experimental APIs] (@ref rte_compat.h), [ABI versioning] (@ref rte_function_versioning.h), - [version] (@ref rte_version.h) + [version] (@ref rte_version.h), + [bitops] (@ref rte_bitops.h) diff --git a/lib/librte_eal/common/Makefile b/lib/librte_eal/common/Makefile index c2c6d92cd..dd025c130 100644 --- a/lib/librte_eal/common/Makefile +++ b/lib/librte_eal/common/Makefile @@ -19,6 +19,7 @@ INC += rte_malloc.h rte_keepalive.h rte_time.h INC += rte_service.h rte_service_component.h INC += rte_bitmap.h rte_vfio.h rte_hypervisor.h rte_test.h INC += rte_reciprocal.h rte_fbarray.h rte_uuid.h +INC += rte_bitops.h GENERIC_INC := rte_atomic.h rte_byteorder.h rte_cycles.h rte_prefetch.h GENERIC_INC += rte_memcpy.h rte_cpuflags.h diff --git a/lib/librte_eal/common/include/rte_bitops.h b/lib/librte_eal/common/include/rte_bitops.h new file mode 100644 index 000000000..16c0a23f7 --- /dev/null +++ b/lib/librte_eal/common/include/rte_bitops.h @@ -0,0 +1,474 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2019 Arm Limited + */ + +#ifndef _RTE_BITOPS_H_ +#define _RTE_BITOPS_H_ + +/** + * @file + * Bit Operations + * + * This file defines a API for bit operations without/with memory ordering. + */ + +#include +#include +#include + +/*---------------------------- 32 bit operations ----------------------------*/ + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Get the target bit from a 32-bit value without memory ordering. + * + * @param nr + * The target bit to get. + * @param addr + * The address holding the bit. + * @return + * The target bit. + */ +__rte_experimental +static inline uint32_t +rte_get_bit32_relaxed(unsigned int nr, unsigned long *addr) +{ + assert(nr < 32); + + uint32_t mask = 1UL << nr; + return __atomic_load_n(addr, __ATOMIC_RELAXED) & mask; +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Set the target bit in a 32-bit value to 1 without memory ordering. + * + * @param nr + * The target bit to set. + * @param addr + * The address holding the bit. + */ +__rte_experimental +static inline void +rte_set_bit32_relaxed(unsigned int nr, unsigned long *addr) +{ + assert(nr < 32); + + uint32_t mask = 1UL << nr; + __atomic_fetch_or(addr, mask, __ATOMIC_RELAXED); +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Clear the target bit in a 32-bit value to 0 without memory ordering. + * + * @param nr + * The target bit to clear. + * @param addr + * The address holding the bit. + */ +__rte_experimental +static inline void +rte_clear_bit32_relaxed(unsigned int nr, unsigned long *addr) +{ + assert(nr < 32); + + uint32_t mask = 1UL << nr; + __atomic_fetch_and(addr, ~mask, __ATOMIC_RELAXED); +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Return the original bit from a 32-bit value, then set it to 1 without + * memory ordering. + * + * @param nr + * The target bit to get and set. + * @param addr + * The address holding the bit. + * @return + * The original bit. + */ +__rte_experimental +static inline uint32_t +rte_test_and_set_bit32_relaxed(unsigned int nr, unsigned long *addr) +{ + assert(nr < 32); + + uint32_t mask = 1UL << nr; + return __atomic_fetch_or(addr, mask, __ATOMIC_RELAXED) & mask; +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Return the original bit from a 32-bit value, then clear it to 0 without + * memory ordering. + * + * @param nr + * The target bit to get and clear. + * @param addr + * The address holding the bit. + * @return + * The original bit. + */ +__rte_experimental +static inline uint32_t +rte_test_and_clear_bit32_relaxed(unsigned int nr, unsigned long *addr) +{ + assert(nr < 32); + + uint32_t mask = 1UL << nr; + return __atomic_fetch_and(addr, ~mask, __ATOMIC_RELAXED) & mask; +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Get the target bit from a 32-bit value with memory ordering. + * + * @param nr + * The target bit to get. + * @param addr + * The address holding the bit. + * @return + * The target bit. + */ +__rte_experimental +static inline uint32_t +rte_get_bit32(unsigned int nr, unsigned long *addr) +{ + assert(nr < 32); + + uint32_t mask = 1UL << nr; + return __atomic_load_n(addr, __ATOMIC_ACQUIRE) & mask; +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Set the target bit in a 32-bit value to 1 with memory ordering. + * + * @param nr + * The target bit to set. + * @param addr + * The address holding the bit. + */ +__rte_experimental +static inline void +rte_set_bit32(unsigned int nr, unsigned long *addr) +{ + assert(nr < 32); + + uint32_t mask = 1UL << nr; + __atomic_fetch_or(addr, mask, __ATOMIC_ACQ_REL); +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Clear the target bit in a 32-bit value to 0 with memory ordering. + * + * @param nr + * The target bit to clear. + * @param addr + * The address holding the bit. + */ +__rte_experimental +static inline void +rte_clear_bit32(unsigned int nr, unsigned long *addr) +{ + assert(nr < 32); + + uint32_t mask = 1UL << nr; + __atomic_fetch_and(addr, ~mask, __ATOMIC_ACQ_REL); +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Return the original bit from a 32-bit value, then set it to 1 with + * memory ordering. + * + * @param nr + * The target bit to get and set. + * @param addr + * The address holding the bit. + * @return + * The original bit. + */ +__rte_experimental +static inline uint32_t +rte_test_and_set_bit32(unsigned int nr, unsigned long *addr) +{ + assert(nr < 32); + + uint32_t mask = 1UL << nr; + return __atomic_fetch_or(addr, mask, __ATOMIC_ACQ_REL) & mask; +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Return the original bit from a 32-bit value, then clear it to 0 with + * memory ordering. + * + * @param nr + * The target bit to get and clear. + * @param addr + * The address holding the bit. + * @return + * The original bit. + */ +__rte_experimental +static inline uint32_t +rte_test_and_clear_bit32(unsigned int nr, unsigned long *addr) +{ + assert(nr < 32); + + uint32_t mask = 1UL << nr; + return __atomic_fetch_and(addr, ~mask, __ATOMIC_ACQ_REL) & mask; +} + +/*---------------------------- 64 bit operations ----------------------------*/ + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Get the target bit from a 64-bit value without memory ordering. + * + * @param nr + * The target bit to get. + * @param addr + * The address holding the bit. + * @return + * The target bit. + */ +__rte_experimental +static inline uint64_t +rte_get_bit64_relaxed(unsigned int nr, unsigned long *addr) +{ + assert(nr < 64); + + uint64_t mask = 1UL << nr; + return __atomic_load_n(addr, __ATOMIC_RELAXED) & mask; +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Set the target bit in a 64-bit value to 1 without memory ordering. + * + * @param nr + * The target bit to set. + * @param addr + * The address holding the bit. + */ +__rte_experimental +static inline void +rte_set_bit64_relaxed(unsigned int nr, unsigned long *addr) +{ + assert(nr < 64); + + uint64_t mask = 1UL << nr; + __atomic_fetch_or(addr, mask, __ATOMIC_RELAXED); +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Clear the target bit in a 64-bit value to 0 without memory ordering. + * + * @param nr + * The target bit to clear. + * @param addr + * The address holding the bit. + */ +__rte_experimental +static inline void +rte_clear_bit64_relaxed(unsigned int nr, unsigned long *addr) +{ + assert(nr < 64); + + uint64_t mask = 1UL << nr; + __atomic_fetch_and(addr, ~mask, __ATOMIC_RELAXED); +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Return the original bit from a 64-bit value, then set it to 1 without + * memory ordering. + * + * @param nr + * The target bit to get and set. + * @param addr + * The address holding the bit. + * @return + * The original bit. + */ +__rte_experimental +static inline uint64_t +rte_test_and_set_bit64_relaxed(unsigned int nr, unsigned long *addr) +{ + assert(nr < 64); + + uint64_t mask = 1UL << nr; + return __atomic_fetch_or(addr, mask, __ATOMIC_RELAXED) & mask; +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Return the original bit from a 64-bit value, then clear it to 0 without + * memory ordering. + * + * @param nr + * The target bit to get and clear. + * @param addr + * The address holding the bit. + * @return + * The original bit. + */ +__rte_experimental +static inline uint64_t +rte_test_and_clear_bit64_relaxed(unsigned int nr, unsigned long *addr) +{ + assert(nr < 64); + + uint64_t mask = 1UL << nr; + return __atomic_fetch_and(addr, ~mask, __ATOMIC_RELAXED) & mask; +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Get the target bit from a 64-bit value with memory ordering. + * + * @param nr + * The target bit to get. + * @param addr + * The address holding the bit. + * @return + * The target bit. + */ +__rte_experimental +static inline uint64_t +rte_get_bit64(unsigned int nr, unsigned long *addr) +{ + assert(nr < 64); + + uint64_t mask = 1UL << nr; + return __atomic_load_n(addr, __ATOMIC_ACQUIRE) & mask; +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Set the target bit in a 64-bit value to 1 with memory ordering. + * + * @param nr + * The target bit to set. + * @param addr + * The address holding the bit. + */ +__rte_experimental +static inline void +rte_set_bit64(unsigned int nr, unsigned long *addr) +{ + assert(nr < 64); + + uint64_t mask = 1UL << nr; + __atomic_fetch_or(addr, mask, __ATOMIC_ACQ_REL); +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Clear the target bit in a 64-bit value to 0 with memory ordering. + * + * @param nr + * The target bit to clear. + * @param addr + * The address holding the bit. + */ +__rte_experimental +static inline void +rte_clear_bit64(unsigned int nr, unsigned long *addr) +{ + assert(nr < 64); + + uint64_t mask = 1UL << nr; + __atomic_fetch_and(addr, ~mask, __ATOMIC_ACQ_REL); +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Return the original bit from a 64-bit value, then set it to 1 with + * memory ordering. + * + * @param nr + * The target bit to get and set. + * @param addr + * The address holding the bit. + * @return + * The original bit. + */ +__rte_experimental +static inline uint64_t +rte_test_and_set_bit64(unsigned int nr, unsigned long *addr) +{ + assert(nr < 64); + + uint64_t mask = 1UL << nr; + return __atomic_fetch_or(addr, mask, __ATOMIC_ACQ_REL) & mask; +} + +/** + * @warning + * @b EXPERIMENTAL: this API may change, or be removed, without prior notice + * + * Return the original bit from a 64-bit value, then clear it to 0 with + * memory ordering. + * + * @param nr + * The target bit to get and clear. + * @param addr + * The address holding the bit. + * @return + * The original bit. + */ +__rte_experimental +static inline uint64_t +rte_test_and_clear_bit64(unsigned int nr, unsigned long *addr) +{ + assert(nr < 64); + + uint64_t mask = 1UL << nr; + return __atomic_fetch_and(addr, ~mask, __ATOMIC_ACQ_REL) & mask; +} +#endif /* _RTE_BITOPS_H_ */ diff --git a/lib/librte_eal/common/meson.build b/lib/librte_eal/common/meson.build index d6a149bec..e2f9c163c 100644 --- a/lib/librte_eal/common/meson.build +++ b/lib/librte_eal/common/meson.build @@ -52,6 +52,7 @@ common_headers = files( 'include/rte_alarm.h', 'include/rte_branch_prediction.h', 'include/rte_bus.h', + 'include/rte_bitops.h', 'include/rte_bitmap.h', 'include/rte_class.h', 'include/rte_common.h', -- 2.17.1