From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7EF14A04F3; Fri, 20 Dec 2019 04:10:31 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 8F7F41BE3D; Fri, 20 Dec 2019 04:10:30 +0100 (CET) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by dpdk.org (Postfix) with ESMTP id 6E0535B3C for ; Fri, 20 Dec 2019 04:10:28 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B5DC830E; Thu, 19 Dec 2019 19:10:27 -0800 (PST) Received: from net-arm-thunderx2-01.test.ast.arm.com (net-arm-thunderx2-01.shanghai.arm.com [10.169.40.68]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id E8C493F719; Thu, 19 Dec 2019 19:10:22 -0800 (PST) From: Gavin Hu To: dev@dpdk.org Cc: nd@arm.com, david.marchand@redhat.com, maxime.coquelin@redhat.com, tiwei.bie@intel.com, thomas@monjalon.net, rasland@mellanox.com, matan@mellanox.com, shahafs@mellanox.com, viacheslavo@mellanox.com, arybchenko@solarflare.com, stephen@networkplumber.org, hemant.agrawal@nxp.com, jerinj@marvell.com, pbhagavatula@marvell.com, Honnappa.Nagarahalli@arm.com, ruifeng.wang@arm.com, phil.yang@arm.com, joyce.kong@arm.com, steve.capper@arm.com Date: Fri, 20 Dec 2019 11:09:48 +0800 Message-Id: <1576811391-19131-1-git-send-email-gavin.hu@arm.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1571758074-16445-1-git-send-email-gavin.hu@arm.com> References: <1571758074-16445-1-git-send-email-gavin.hu@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [dpdk-dev] [PATCH v2 0/3] relax io barrier for aarch64 and use smp barriers for virtual pci memory X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Armv8's peripheral coherence order is a total order on all reads and writes to that peripheral, that makes a compiler barrier is enough for abstracted rte io barrier. For virtual PCI devices, the virtual device memory is actually normal memory and the Hypervisor view of things takes precedence and they are within a smp configuration and smp barriers should be used, the relaxed io barrier for aarch64 becomes insufficient. Note for the ordering of other MMIO device memories, other than PCI, stronger barriers might be required, which depends on the memory attributes assigned to the memory regions. So far I did not find occurrences of such io barriers used in non-PCI device memories within DPDK. V2: - remove virtio_pci_read/write64 APIs definitions, they are not needed and generate compiling errors like " error: unused function 'virtio_pci_write64' [-Werror,-Wunused-function]" - update the reference link to kernel source code Gavin Hu (3): eal/arm64: relax the io barrier for aarch64 net/virtio: virtual PCI requires smp barriers crypto/virtio: virtual PCI requires smp barriers drivers/crypto/virtio/virtio_pci.c | 108 +++++++++++++++------ drivers/net/virtio/virtio_pci.c | 108 +++++++++++++++------ .../common/include/arch/arm/rte_atomic_64.h | 6 +- 3 files changed, 159 insertions(+), 63 deletions(-) -- 2.7.4