From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id CD53CA051A; Fri, 17 Jan 2020 12:01:46 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 762D52B83; Fri, 17 Jan 2020 12:01:46 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by dpdk.org (Postfix) with ESMTP id B39102B83 for ; Fri, 17 Jan 2020 12:01:45 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from viacheslavo@mellanox.com) with ESMTPS (AES256-SHA encrypted); 17 Jan 2020 13:01:40 +0200 Received: from pegasus11.mtr.labs.mlnx (pegasus11.mtr.labs.mlnx [10.210.16.104]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 00HB1eOv006770; Fri, 17 Jan 2020 13:01:40 +0200 Received: from pegasus11.mtr.labs.mlnx (localhost [127.0.0.1]) by pegasus11.mtr.labs.mlnx (8.14.7/8.14.7) with ESMTP id 00HB1eXe004768; Fri, 17 Jan 2020 11:01:40 GMT Received: (from viacheslavo@localhost) by pegasus11.mtr.labs.mlnx (8.14.7/8.14.7/Submit) id 00HB1djT004767; Fri, 17 Jan 2020 11:01:39 GMT X-Authentication-Warning: pegasus11.mtr.labs.mlnx: viacheslavo set sender to viacheslavo@mellanox.com using -f From: Viacheslav Ovsiienko To: dev@dpdk.org Cc: matan@mellanox.com, rasland@mellanox.com, ferruh.yigit@intel.com, stable@dpdk.org Date: Fri, 17 Jan 2020 11:01:34 +0000 Message-Id: <1579258894-4680-1-git-send-email-viacheslavo@mellanox.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1576828138-13063-1-git-send-email-viacheslavo@mellanox.com> References: <1576828138-13063-1-git-send-email-viacheslavo@mellanox.com> Subject: [dpdk-dev] [PATCH v2] net/mlx5: fix shared metadata matcher field setup X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Matcher is flow table related structure providing the flow pattern to be translated directly in hardware controlling data. Some fields in this structure might be split (by software) between multiple items. For example, the metadata register c0 field in the matcher might be split into two independent subfields - the source vport index and META item value. These subfields have no permanent assigned masks, the actual configuration is queried from the kernel drivers in runtime. To handle source vport value (the port of e-Switch which is origin of the packet) the kernel might use the dedicated vport field in the matcher or the part of register c0 field, depending on configuration. To setup the matcher structure fields the macro MLX5_SET is used. MLX5_SET configures the specified 32-bit field as whole entity. For metadata register c0 we should take into account the provided mask in order to configure the specified subfield bits only, otherwise setting vport overrides the META values and vice versa. Fixes: acfcd5c52f94 ("net/mlx5: update meta register matcher set") Cc: stable@dpdk.org Signed-off-by: Viacheslav Ovsiienko Acked-by: Matan Azrad --- v1: - http://patches.dpdk.org/patch/64068/ v2: - update commit message - update headline "net/mlx5: fix matcher metadata register c0 field setup" drivers/net/mlx5/mlx5_flow_dv.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index 5bd1b1c..2b70788 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -5748,6 +5748,7 @@ struct field_modify_info modify_tcp[] = { MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2); void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2); + uint32_t temp; data &= mask; switch (reg_type) { @@ -5760,8 +5761,18 @@ struct field_modify_info modify_tcp[] = { MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data); break; case REG_C_0: - MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, mask); - MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, data); + /* + * The metadata register C0 field might be divided into + * source vport index and META item value, we should set + * this field according to specified mask, not as whole one. + */ + temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0); + temp |= mask; + MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp); + temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0); + temp &= ~mask; + temp |= data; + MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp); break; case REG_C_1: MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask); -- 1.8.3.1