From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 716F2A051A; Fri, 17 Jan 2020 15:59:36 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 4A91F1AFF; Fri, 17 Jan 2020 15:59:36 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by dpdk.org (Postfix) with ESMTP id 437561AFF for ; Fri, 17 Jan 2020 15:59:35 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from viacheslavo@mellanox.com) with ESMTPS (AES256-SHA encrypted); 17 Jan 2020 16:59:34 +0200 Received: from pegasus11.mtr.labs.mlnx (pegasus11.mtr.labs.mlnx [10.210.16.104]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 00HExYAI027271; Fri, 17 Jan 2020 16:59:34 +0200 Received: from pegasus11.mtr.labs.mlnx (localhost [127.0.0.1]) by pegasus11.mtr.labs.mlnx (8.14.7/8.14.7) with ESMTP id 00HExYSn019815; Fri, 17 Jan 2020 14:59:34 GMT Received: (from viacheslavo@localhost) by pegasus11.mtr.labs.mlnx (8.14.7/8.14.7/Submit) id 00HExXg1019814; Fri, 17 Jan 2020 14:59:33 GMT X-Authentication-Warning: pegasus11.mtr.labs.mlnx: viacheslavo set sender to viacheslavo@mellanox.com using -f From: Viacheslav Ovsiienko To: dev@dpdk.org Cc: matan@mellanox.com, rasland@mellanox.com, ferruh.yigit@intel.com, stable@dpdk.org Date: Fri, 17 Jan 2020 14:59:32 +0000 Message-Id: <1579273172-19188-1-git-send-email-viacheslavo@mellanox.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1577197235-26433-1-git-send-email-viacheslavo@mellanox.com> References: <1577197235-26433-1-git-send-email-viacheslavo@mellanox.com> Subject: [dpdk-dev] [PATCH v2] net/mlx5: fix metadata item endianness conversion X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The mlx5 datapath does not implement any endianness conversions for the metadata being sent and received to provide the better performance (because these conversions would be performed for each packet). These metadata are also involved into flow processing (there might be some flows matching on metadata patterns or setting the new metadata values) inside the NIC. It order to configure hardware in correct way all necessary endianness conversions are done by rte_flow handling code (only once on flow creation). This patch fixes one of these conversions for the little-endian hosts in case if META/MARK items are less than 32 bits. Fixes: acfcd5c52f94 ("net/mlx5: update meta register matcher set") Cc: stable@dpdk.org Signed-off-by: Viacheslav Ovsiienko Acked-by: Matan Azrad --- v1: - http://patchwork.dpdk.org/patch/64125/ v2: - commit message is rewritten drivers/net/mlx5/mlx5_flow_dv.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index dd21bc6..e8a764c 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -5909,8 +5909,12 @@ struct field_modify_info modify_tcp[] = { struct mlx5_priv *priv = dev->data->dev_private; uint32_t msk_c0 = priv->sh->dv_regc0_mask; uint32_t shl_c0 = rte_bsf32(msk_c0); +#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN + uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask); - msk_c0 = rte_cpu_to_be_32(msk_c0); + value >>= shr_c0; + mask >>= shr_c0; +#endif value <<= shl_c0; mask <<= shl_c0; assert(msk_c0); -- 1.8.3.1