[dpdk-dev] [PATCH 0/6] code improvements for OCTEON TX crypto PMDs

[dpdk-dev] [PATCH 0/6] code improvements for OCTEON TX crypto PMDs

[Anoob Joseph]

This series has code improvements, bug fixes and capabilities
changes supported with new firmware for OCTEON TX crypto PMDs.

Anoob Joseph (1):
  common/cpt: remove redundant bitswaps

Archana Muniganti (3):
  crypto/octeontx2: add AES-GCM capabilities supported with new firmware
  common/cpt: fix error path when cipher and auth key are not set
  common/cpt: fix fill_sg_comp api for zero datalen

Sucharitha Sarananaga (1):
  common/cpt: support variable key size for HMAC

Sunila Sahu (1):
  common/cpt: removes self assignment code

 drivers/common/cpt/cpt_mcode_defines.h             | 47 +++--------
 drivers/common/cpt/cpt_ucode.h                     | 91 +++++++++++-----------
 drivers/common/cpt/cpt_ucode_asym.h                |  1 -
 .../crypto/octeontx/otx_cryptodev_capabilities.c   | 30 +++----
 .../crypto/octeontx2/otx2_cryptodev_capabilities.c | 34 ++++----
 5 files changed, 87 insertions(+), 116 deletions(-)

-- 
2.7.4

[dpdk-dev] [PATCH 1/6] common/cpt: remove redundant bitswaps

[Anoob Joseph]

The structures can be written for direct h/w usage to avoid multiple
bitswaps.

Signed-off-by: Anoob Joseph <anoobj@marvell.com>
---
 drivers/common/cpt/cpt_mcode_defines.h | 45 +++++++---------------------------
 drivers/common/cpt/cpt_ucode.h         | 34 +++++++++----------------
 2 files changed, 20 insertions(+), 59 deletions(-)

diff --git a/drivers/common/cpt/cpt_mcode_defines.h b/drivers/common/cpt/cpt_mcode_defines.h
index d830bef..8bb09e6 100644
--- a/drivers/common/cpt/cpt_mcode_defines.h
+++ b/drivers/common/cpt/cpt_mcode_defines.h
@@ -267,41 +267,16 @@ struct cpt_sess_misc {
 	phys_addr_t ctx_dma_addr;
 };
 
-typedef union {
-	uint64_t flags;
-	struct {
-#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
-		uint64_t enc_cipher   : 4;
-		uint64_t reserved1    : 1;
-		uint64_t aes_key      : 2;
-		uint64_t iv_source    : 1;
-		uint64_t hash_type    : 4;
-		uint64_t reserved2    : 3;
-		uint64_t auth_input_type : 1;
-		uint64_t mac_len      : 8;
-		uint64_t reserved3    : 8;
-		uint64_t encr_offset  : 16;
-		uint64_t iv_offset    : 8;
-		uint64_t auth_offset  : 8;
-#else
-		uint64_t auth_offset  : 8;
-		uint64_t iv_offset    : 8;
-		uint64_t encr_offset  : 16;
-		uint64_t reserved3    : 8;
-		uint64_t mac_len      : 8;
-		uint64_t auth_input_type : 1;
-		uint64_t reserved2    : 3;
-		uint64_t hash_type    : 4;
-		uint64_t iv_source    : 1;
-		uint64_t aes_key      : 2;
-		uint64_t reserved1    : 1;
-		uint64_t enc_cipher   : 4;
-#endif
-	} e;
-} encr_ctrl_t;
-
 typedef struct {
-	encr_ctrl_t enc_ctrl;
+	uint64_t iv_source      : 1;
+	uint64_t aes_key        : 2;
+	uint64_t rsvd_60        : 1;
+	uint64_t enc_cipher     : 4;
+	uint64_t auth_input_type : 1;
+	uint64_t rsvd_52_54     : 3;
+	uint64_t hash_type      : 4;
+	uint64_t mac_len        : 8;
+	uint64_t rsvd_39_0      : 40;
 	uint8_t  encr_key[32];
 	uint8_t  encr_iv[16];
 } mc_enc_context_t;
@@ -444,8 +419,6 @@ typedef mc_hash_type_t auth_type_t;
 
 /* Helper macros */
 
-#define CPT_P_ENC_CTRL(fctx)  fctx->enc.enc_ctrl.e
-
 #define SRC_IOV_SIZE \
 	(sizeof(iov_ptr_t) + (sizeof(buf_ptr_t) * CPT_MAX_SG_CNT))
 #define DST_IOV_SIZE \
diff --git a/drivers/common/cpt/cpt_ucode.h b/drivers/common/cpt/cpt_ucode.h
index d5a0135..24b53a1 100644
--- a/drivers/common/cpt/cpt_ucode.h
+++ b/drivers/common/cpt/cpt_ucode.h
@@ -149,7 +149,7 @@ static __rte_always_inline void
 cpt_fc_ciph_set_key_passthrough(struct cpt_ctx *cpt_ctx, mc_fc_context_t *fctx)
 {
 	cpt_ctx->enc_cipher = 0;
-	CPT_P_ENC_CTRL(fctx).enc_cipher = 0;
+	fctx->enc.enc_cipher = 0;
 }
 
 static __rte_always_inline void
@@ -171,7 +171,7 @@ cpt_fc_ciph_set_key_set_aes_key_type(mc_fc_context_t *fctx, uint16_t key_len)
 		CPT_LOG_DP_ERR("Invalid AES key len");
 		return;
 	}
-	CPT_P_ENC_CTRL(fctx).aes_key = aes_key_type;
+	fctx->enc.aes_key = aes_key_type;
 }
 
 static __rte_always_inline void
@@ -218,7 +218,6 @@ cpt_fc_ciph_set_key(void *ctx, cipher_type_t type, const uint8_t *key,
 {
 	struct cpt_ctx *cpt_ctx = ctx;
 	mc_fc_context_t *fctx = &cpt_ctx->fctx;
-	uint64_t *ctrl_flags = NULL;
 	int ret;
 
 	ret = cpt_fc_ciph_set_type(type, cpt_ctx, key_len);
@@ -226,19 +225,17 @@ cpt_fc_ciph_set_key(void *ctx, cipher_type_t type, const uint8_t *key,
 		return -1;
 
 	if (cpt_ctx->fc_type == FC_GEN) {
-		ctrl_flags = (uint64_t *)&(fctx->enc.enc_ctrl.flags);
-		*ctrl_flags = rte_be_to_cpu_64(*ctrl_flags);
 		/*
 		 * We need to always say IV is from DPTR as user can
 		 * sometimes iverride IV per operation.
 		 */
-		CPT_P_ENC_CTRL(fctx).iv_source = CPT_FROM_DPTR;
+		fctx->enc.iv_source = CPT_FROM_DPTR;
 	}
 
 	switch (type) {
 	case PASSTHROUGH:
 		cpt_fc_ciph_set_key_passthrough(cpt_ctx, fctx);
-		goto fc_success;
+		goto success;
 	case DES3_CBC:
 		/* CPT performs DES using 3DES with the 8B DES-key
 		 * replicated 2 more times to match the 24B 3DES-key.
@@ -255,7 +252,7 @@ cpt_fc_ciph_set_key(void *ctx, cipher_type_t type, const uint8_t *key,
 		break;
 	case DES3_ECB:
 		/* For DES3_ECB IV need to be from CTX. */
-		CPT_P_ENC_CTRL(fctx).iv_source = CPT_FROM_CTX;
+		fctx->enc.iv_source = CPT_FROM_CTX;
 		break;
 	case AES_CBC:
 	case AES_ECB:
@@ -273,7 +270,7 @@ cpt_fc_ciph_set_key(void *ctx, cipher_type_t type, const uint8_t *key,
 			 * and nothing else
 			 */
 			if (!key)
-				goto fc_success;
+				goto success;
 		}
 		cpt_fc_ciph_set_key_set_aes_key_type(fctx, key_len);
 		break;
@@ -305,14 +302,10 @@ cpt_fc_ciph_set_key(void *ctx, cipher_type_t type, const uint8_t *key,
 
 	/* For GMAC auth, cipher must be NULL */
 	if (cpt_ctx->hash_type != GMAC_TYPE)
-		CPT_P_ENC_CTRL(fctx).enc_cipher = type;
+		fctx->enc.enc_cipher = type;
 
 	memcpy(fctx->enc.encr_key, key, key_len);
 
-fc_success:
-	if (ctrl_flags != NULL)
-		*ctrl_flags = rte_cpu_to_be_64(*ctrl_flags);
-
 success:
 	cpt_ctx->enc_cipher = type;
 
@@ -2494,7 +2487,6 @@ cpt_fc_auth_set_key(void *ctx, auth_type_t type, const uint8_t *key,
 {
 	struct cpt_ctx *cpt_ctx = ctx;
 	mc_fc_context_t *fctx = &cpt_ctx->fctx;
-	uint64_t *ctrl_flags = NULL;
 
 	if ((type >= ZUC_EIA3) && (type <= KASUMI_F9_ECB)) {
 		uint32_t keyx[4];
@@ -2545,15 +2537,12 @@ cpt_fc_auth_set_key(void *ctx, auth_type_t type, const uint8_t *key,
 			cpt_ctx->fc_type = HASH_HMAC;
 	}
 
-	ctrl_flags = (uint64_t *)&fctx->enc.enc_ctrl.flags;
-	*ctrl_flags = rte_be_to_cpu_64(*ctrl_flags);
-
 	/* For GMAC auth, cipher must be NULL */
 	if (type == GMAC_TYPE)
-		CPT_P_ENC_CTRL(fctx).enc_cipher = 0;
+		fctx->enc.enc_cipher = 0;
 
-	CPT_P_ENC_CTRL(fctx).hash_type = cpt_ctx->hash_type = type;
-	CPT_P_ENC_CTRL(fctx).mac_len = cpt_ctx->mac_len = mac_len;
+	fctx->enc.hash_type = cpt_ctx->hash_type = type;
+	fctx->enc.mac_len = cpt_ctx->mac_len = mac_len;
 
 	if (key_len) {
 		cpt_ctx->hmac = 1;
@@ -2563,9 +2552,8 @@ cpt_fc_auth_set_key(void *ctx, auth_type_t type, const uint8_t *key,
 		memset(fctx->hmac.ipad, 0, sizeof(fctx->hmac.ipad));
 		memset(fctx->hmac.opad, 0, sizeof(fctx->hmac.opad));
 		memcpy(fctx->hmac.opad, key, key_len);
-		CPT_P_ENC_CTRL(fctx).auth_input_type = 1;
+		fctx->enc.auth_input_type = 1;
 	}
-	*ctrl_flags = rte_cpu_to_be_64(*ctrl_flags);
 	return 0;
 }
 
-- 
2.7.4

[dpdk-dev] [PATCH 2/6] crypto/octeontx2: add AES-GCM capabilities supported with new firmware

[Anoob Joseph]

From: Archana Muniganti <marchana@marvell.com>

OCTEON TX2 crypto PMD supports digest lengths from 4 to 16 bytes
with new firmware.

Signed-off-by: Archana Muniganti <marchana@marvell.com>
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
---
 drivers/crypto/octeontx2/otx2_cryptodev_capabilities.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.c b/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.c
index 83f885c..2ddf628 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.c
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.c
@@ -577,9 +577,9 @@ rte_cryptodev_capabilities otx2_cpt_capabilities[] = {
 					.increment = 8
 				},
 				.digest_size = {
-					.min = 8,
+					.min = 4,
 					.max = 16,
-					.increment = 4
+					.increment = 1
 				},
 				.aad_size = {
 					.min = 0,
-- 
2.7.4

[dpdk-dev] [PATCH 3/6] common/cpt: support variable key size for HMAC

[Anoob Joseph]

From: Sucharitha Sarananaga <ssarananaga@marvell.com>

HMAC algorithms supports key lengths from 1 to 1024 bytes.

Signed-off-by: Archana Muniganti <marchana@marvell.com>
Signed-off-by: Sucharitha Sarananaga <ssarananaga@marvell.com>
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
---
 drivers/common/cpt/cpt_mcode_defines.h             |  2 +-
 drivers/common/cpt/cpt_ucode.h                     | 15 ++++++-----
 .../crypto/octeontx/otx_cryptodev_capabilities.c   | 30 +++++++++++-----------
 .../crypto/octeontx2/otx2_cryptodev_capabilities.c | 30 +++++++++++-----------
 4 files changed, 40 insertions(+), 37 deletions(-)

diff --git a/drivers/common/cpt/cpt_mcode_defines.h b/drivers/common/cpt/cpt_mcode_defines.h
index 8bb09e6..69d831b 100644
--- a/drivers/common/cpt/cpt_mcode_defines.h
+++ b/drivers/common/cpt/cpt_mcode_defines.h
@@ -320,7 +320,7 @@ struct cpt_ctx {
 		mc_zuc_snow3g_ctx_t zs_ctx;
 		mc_kasumi_ctx_t k_ctx;
 	};
-	uint8_t  auth_key[64];
+	uint8_t  auth_key[1024];
 };
 
 /* Prime and order fields of built-in elliptic curves */
diff --git a/drivers/common/cpt/cpt_ucode.h b/drivers/common/cpt/cpt_ucode.h
index 24b53a1..4ef87c2 100644
--- a/drivers/common/cpt/cpt_ucode.h
+++ b/drivers/common/cpt/cpt_ucode.h
@@ -230,6 +230,9 @@ cpt_fc_ciph_set_key(void *ctx, cipher_type_t type, const uint8_t *key,
 		 * sometimes iverride IV per operation.
 		 */
 		fctx->enc.iv_source = CPT_FROM_DPTR;
+
+		if (cpt_ctx->auth_key_len > 64)
+			return -1;
 	}
 
 	switch (type) {
@@ -2537,6 +2540,9 @@ cpt_fc_auth_set_key(void *ctx, auth_type_t type, const uint8_t *key,
 			cpt_ctx->fc_type = HASH_HMAC;
 	}
 
+	if (cpt_ctx->fc_type == FC_GEN && key_len > 64)
+		return -1;
+
 	/* For GMAC auth, cipher must be NULL */
 	if (type == GMAC_TYPE)
 		fctx->enc.enc_cipher = 0;
@@ -2551,7 +2557,9 @@ cpt_fc_auth_set_key(void *ctx, auth_type_t type, const uint8_t *key,
 		cpt_ctx->auth_key_len = key_len;
 		memset(fctx->hmac.ipad, 0, sizeof(fctx->hmac.ipad));
 		memset(fctx->hmac.opad, 0, sizeof(fctx->hmac.opad));
-		memcpy(fctx->hmac.opad, key, key_len);
+
+		if (key_len <= 64)
+			memcpy(fctx->hmac.opad, key, key_len);
 		fctx->enc.auth_input_type = 1;
 	}
 	return 0;
@@ -2736,11 +2744,6 @@ fill_sess_auth(struct rte_crypto_sym_xform *xform,
 		return -1;
 	}
 
-	if (a_form->key.length > 64) {
-		CPT_LOG_DP_ERR("Auth key length is big");
-		return -1;
-	}
-
 	switch (a_form->algo) {
 	case RTE_CRYPTO_AUTH_SHA1_HMAC:
 		/* Fall through */
diff --git a/drivers/crypto/octeontx/otx_cryptodev_capabilities.c b/drivers/crypto/octeontx/otx_cryptodev_capabilities.c
index 1174ee4..3f734b2 100644
--- a/drivers/crypto/octeontx/otx_cryptodev_capabilities.c
+++ b/drivers/crypto/octeontx/otx_cryptodev_capabilities.c
@@ -141,9 +141,9 @@ static const struct rte_cryptodev_capabilities otx_sym_capabilities[] = {
 				.algo = RTE_CRYPTO_AUTH_SHA1_HMAC,
 				.block_size = 64,
 				.key_size = {
-					.min = 64,
-					.max = 64,
-					.increment = 0
+					.min = 1,
+					.max = 1024,
+					.increment = 1
 				},
 				.digest_size = {
 					.min = 20,
@@ -181,9 +181,9 @@ static const struct rte_cryptodev_capabilities otx_sym_capabilities[] = {
 				.algo = RTE_CRYPTO_AUTH_SHA224_HMAC,
 				.block_size = 64,
 					.key_size = {
-					.min = 64,
-					.max = 64,
-					.increment = 0
+					.min = 1,
+					.max = 1024,
+					.increment = 1
 				},
 				.digest_size = {
 					.min = 28,
@@ -221,9 +221,9 @@ static const struct rte_cryptodev_capabilities otx_sym_capabilities[] = {
 				.algo = RTE_CRYPTO_AUTH_SHA256_HMAC,
 				.block_size = 64,
 				.key_size = {
-					.min = 64,
-					.max = 64,
-					.increment = 0
+					.min = 1,
+					.max = 1024,
+					.increment = 1
 				},
 				.digest_size = {
 					.min = 32,
@@ -261,9 +261,9 @@ static const struct rte_cryptodev_capabilities otx_sym_capabilities[] = {
 				.algo = RTE_CRYPTO_AUTH_SHA384_HMAC,
 				.block_size = 64,
 				.key_size = {
-					.min = 64,
-					.max = 64,
-					.increment = 0
+					.min = 1,
+					.max = 1024,
+					.increment = 1
 				},
 				.digest_size = {
 					.min = 48,
@@ -301,9 +301,9 @@ static const struct rte_cryptodev_capabilities otx_sym_capabilities[] = {
 				.algo = RTE_CRYPTO_AUTH_SHA512_HMAC,
 				.block_size = 128,
 				.key_size = {
-					.min = 64,
-					.max = 64,
-					.increment = 0
+					.min = 1,
+					.max = 1024,
+					.increment = 1
 				},
 				.digest_size = {
 					.min = 64,
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.c b/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.c
index 2ddf628..3eb3d85 100644
--- a/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.c
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.c
@@ -142,9 +142,9 @@ rte_cryptodev_capabilities otx2_cpt_capabilities[] = {
 				.algo = RTE_CRYPTO_AUTH_SHA1_HMAC,
 				.block_size = 64,
 				.key_size = {
-					.min = 64,
-					.max = 64,
-					.increment = 0
+					.min = 1,
+					.max = 1024,
+					.increment = 1
 				},
 				.digest_size = {
 					.min = 20,
@@ -182,9 +182,9 @@ rte_cryptodev_capabilities otx2_cpt_capabilities[] = {
 				.algo = RTE_CRYPTO_AUTH_SHA224_HMAC,
 				.block_size = 64,
 					.key_size = {
-					.min = 64,
-					.max = 64,
-					.increment = 0
+					.min = 1,
+					.max = 1024,
+					.increment = 1
 				},
 				.digest_size = {
 					.min = 28,
@@ -222,9 +222,9 @@ rte_cryptodev_capabilities otx2_cpt_capabilities[] = {
 				.algo = RTE_CRYPTO_AUTH_SHA256_HMAC,
 				.block_size = 64,
 				.key_size = {
-					.min = 64,
-					.max = 64,
-					.increment = 0
+					.min = 1,
+					.max = 1024,
+					.increment = 1
 				},
 				.digest_size = {
 					.min = 32,
@@ -262,9 +262,9 @@ rte_cryptodev_capabilities otx2_cpt_capabilities[] = {
 				.algo = RTE_CRYPTO_AUTH_SHA384_HMAC,
 				.block_size = 64,
 				.key_size = {
-					.min = 64,
-					.max = 64,
-					.increment = 0
+					.min = 1,
+					.max = 1024,
+					.increment = 1
 				},
 				.digest_size = {
 					.min = 48,
@@ -302,9 +302,9 @@ rte_cryptodev_capabilities otx2_cpt_capabilities[] = {
 				.algo = RTE_CRYPTO_AUTH_SHA512_HMAC,
 				.block_size = 128,
 				.key_size = {
-					.min = 64,
-					.max = 64,
-					.increment = 0
+					.min = 1,
+					.max = 1024,
+					.increment = 1
 				},
 				.digest_size = {
 					.min = 64,
-- 
2.7.4

[dpdk-dev] [PATCH 4/6] common/cpt: fix error path when cipher and auth key are not set

[Anoob Joseph]

From: Archana Muniganti <marchana@marvell.com>

Returning error when cipher and auth key are not getting set

Fixes: 6cc54096520d ("crypto/octeontx: add supported sessions")

Signed-off-by: Archana Muniganti <marchana@marvell.com>
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
---
 drivers/common/cpt/cpt_ucode.h | 32 +++++++++++++++++++++-----------
 1 file changed, 21 insertions(+), 11 deletions(-)

diff --git a/drivers/common/cpt/cpt_ucode.h b/drivers/common/cpt/cpt_ucode.h
index 4ef87c2..081249c 100644
--- a/drivers/common/cpt/cpt_ucode.h
+++ b/drivers/common/cpt/cpt_ucode.h
@@ -298,7 +298,7 @@ cpt_fc_ciph_set_key(void *ctx, cipher_type_t type, const uint8_t *key,
 		cpt_fc_ciph_set_key_kasumi_f8_cbc(cpt_ctx, key, key_len);
 		goto success;
 	default:
-		break;
+		return -1;
 	}
 
 	/* Only for FC_GEN case */
@@ -2616,10 +2616,13 @@ fill_sess_aead(struct rte_crypto_sym_xform *xform,
 	sess->iv_length = aead_form->iv.length;
 	sess->aad_length = aead_form->aad_length;
 
-	cpt_fc_ciph_set_key(ctx, enc_type, aead_form->key.data,
-			aead_form->key.length, NULL);
+	if (unlikely(cpt_fc_ciph_set_key(ctx, enc_type, aead_form->key.data,
+			aead_form->key.length, NULL)))
+		return -1;
 
-	cpt_fc_auth_set_key(ctx, auth_type, NULL, 0, aead_form->digest_length);
+	if (unlikely(cpt_fc_auth_set_key(ctx, auth_type, NULL, 0,
+			aead_form->digest_length)))
+		return -1;
 
 	return 0;
 }
@@ -2719,8 +2722,9 @@ fill_sess_cipher(struct rte_crypto_sym_xform *xform,
 	sess->iv_length = c_form->iv.length;
 	sess->is_null = is_null;
 
-	cpt_fc_ciph_set_key(SESS_PRIV(sess), enc_type, c_form->key.data,
-			    c_form->key.length, NULL);
+	if (unlikely(cpt_fc_ciph_set_key(SESS_PRIV(sess), enc_type,
+			c_form->key.data, c_form->key.length, NULL)))
+		return -1;
 
 	return 0;
 }
@@ -2814,8 +2818,10 @@ fill_sess_auth(struct rte_crypto_sym_xform *xform,
 		sess->auth_iv_offset = a_form->iv.offset;
 		sess->auth_iv_length = a_form->iv.length;
 	}
-	cpt_fc_auth_set_key(SESS_PRIV(sess), auth_type, a_form->key.data,
-			    a_form->key.length, a_form->digest_length);
+	if (unlikely(cpt_fc_auth_set_key(SESS_PRIV(sess), auth_type,
+			a_form->key.data, a_form->key.length,
+			a_form->digest_length)))
+		return -1;
 
 	return 0;
 }
@@ -2858,9 +2864,13 @@ fill_sess_gmac(struct rte_crypto_sym_xform *xform,
 	sess->iv_length = a_form->iv.length;
 	sess->mac_len = a_form->digest_length;
 
-	cpt_fc_ciph_set_key(ctx, enc_type, a_form->key.data,
-			a_form->key.length, NULL);
-	cpt_fc_auth_set_key(ctx, auth_type, NULL, 0, a_form->digest_length);
+	if (unlikely(cpt_fc_ciph_set_key(ctx, enc_type, a_form->key.data,
+			a_form->key.length, NULL)))
+		return -1;
+
+	if (unlikely(cpt_fc_auth_set_key(ctx, auth_type, NULL, 0,
+			a_form->digest_length)))
+		return -1;
 
 	return 0;
 }
-- 
2.7.4

[dpdk-dev] [PATCH 5/6] common/cpt: fix fill_sg_comp api for zero datalen

[Anoob Joseph]

From: Archana Muniganti <marchana@marvell.com>

fill_sg_comp_from_iov() prepares gather components for i/p IOV
buffers and extra buf. This API is failing to create a gather component
for extra_buf when IOV buf len is zero. Though there is enough space
to accommodate extra_buf, because of pre-decrementing of extra_buf
length from aggregate size, this issue is seen.

Fixes: b74652f3a91f ("common/cpt: add microcode interface for encryption")

Signed-off-by: Archana Muniganti <marchana@marvell.com>
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
---
 drivers/common/cpt/cpt_ucode.h | 12 +++++-------
 1 file changed, 5 insertions(+), 7 deletions(-)

diff --git a/drivers/common/cpt/cpt_ucode.h b/drivers/common/cpt/cpt_ucode.h
index 081249c..c310ea7 100644
--- a/drivers/common/cpt/cpt_ucode.h
+++ b/drivers/common/cpt/cpt_ucode.h
@@ -373,7 +373,7 @@ fill_sg_comp_from_iov(sg_comp_t *list,
 {
 	int32_t j;
 	uint32_t extra_len = extra_buf ? extra_buf->size : 0;
-	uint32_t size = *psize - extra_len;
+	uint32_t size = *psize;
 	buf_ptr_t *bufs;
 
 	bufs = from->bufs;
@@ -382,9 +382,6 @@ fill_sg_comp_from_iov(sg_comp_t *list,
 		uint32_t e_len;
 		sg_comp_t *to = &list[i >> 2];
 
-		if (!bufs[j].size)
-			continue;
-
 		if (unlikely(from_offset)) {
 			if (from_offset >= bufs[j].size) {
 				from_offset -= bufs[j].size;
@@ -416,18 +413,19 @@ fill_sg_comp_from_iov(sg_comp_t *list,
 				to->u.s.len[i % 4] = rte_cpu_to_be_16(e_len);
 			}
 
+			extra_len = RTE_MIN(extra_len, size);
 			/* Insert extra data ptr */
 			if (extra_len) {
 				i++;
 				to = &list[i >> 2];
 				to->u.s.len[i % 4] =
-					rte_cpu_to_be_16(extra_buf->size);
+					rte_cpu_to_be_16(extra_len);
 				to->ptr[i % 4] =
 					rte_cpu_to_be_64(extra_buf->dma_addr);
-
-				/* size already decremented by extra len */
+				size -= extra_len;
 			}
 
+			next_len = RTE_MIN(next_len, size);
 			/* insert the rest of the data */
 			if (next_len) {
 				i++;
-- 
2.7.4

[dpdk-dev] [PATCH 6/6] common/cpt: removes self assignment code

[Anoob Joseph]

From: Sunila Sahu <ssahu@marvell.com>

This fixes coverity issue of self assignment.

Coverity issue: 353635

Signed-off-by: Sunila Sahu <ssahu@marvell.com>
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
---
 drivers/common/cpt/cpt_ucode_asym.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/common/cpt/cpt_ucode_asym.h b/drivers/common/cpt/cpt_ucode_asym.h
index 881959e..a67efb3 100644
--- a/drivers/common/cpt/cpt_ucode_asym.h
+++ b/drivers/common/cpt/cpt_ucode_asym.h
@@ -888,7 +888,6 @@ cpt_ecpm_prep(struct rte_crypto_ecpm_op_param *ecpm,
 	vq_cmd_w0.s.param1 = curveid;
 	vq_cmd_w0.s.param2 = ecpm->scalar.length;
 	vq_cmd_w0.s.dlen = dlen;
-	vq_cmd_w0.u64 = vq_cmd_w0.u64;
 
 	/* Filling cpt_request_info structure */
 	req->ist.ei0 = vq_cmd_w0.u64;
-- 
2.7.4

Re: [dpdk-dev] [PATCH 0/6] code improvements for OCTEON TX crypto PMDs

[Anoob Joseph]

Hi Akhil,

This series is ready for merge, if you don't have any comments. 

Thanks,
Anoob

> -----Original Message-----
> From: Anoob Joseph <anoobj@marvell.com>
> Sent: Wednesday, February 5, 2020 6:46 PM
> To: Akhil Goyal <akhil.goyal@nxp.com>
> Cc: Anoob Joseph <anoobj@marvell.com>; dev@dpdk.org
> Subject: [PATCH 0/6] code improvements for OCTEON TX crypto PMDs
> 
> This series has code improvements, bug fixes and capabilities changes supported
> with new firmware for OCTEON TX crypto PMDs.
> 
> Anoob Joseph (1):
>   common/cpt: remove redundant bitswaps
> 
> Archana Muniganti (3):
>   crypto/octeontx2: add AES-GCM capabilities supported with new firmware
>   common/cpt: fix error path when cipher and auth key are not set
>   common/cpt: fix fill_sg_comp api for zero datalen
> 
> Sucharitha Sarananaga (1):
>   common/cpt: support variable key size for HMAC
> 
> Sunila Sahu (1):
>   common/cpt: removes self assignment code
> 
>  drivers/common/cpt/cpt_mcode_defines.h             | 47 +++--------
>  drivers/common/cpt/cpt_ucode.h                     | 91 +++++++++++-----------
>  drivers/common/cpt/cpt_ucode_asym.h                |  1 -
>  .../crypto/octeontx/otx_cryptodev_capabilities.c   | 30 +++----
>  .../crypto/octeontx2/otx2_cryptodev_capabilities.c | 34 ++++----
>  5 files changed, 87 insertions(+), 116 deletions(-)
> 
> --
> 2.7.4

Re: [dpdk-dev] [PATCH 0/6] code improvements for OCTEON TX crypto PMDs

[Akhil Goyal]

> 
> Hi Akhil,
> 
> This series is ready for merge, if you don't have any comments.
> 

Applied to dpdk-next-crypto

Thanks.