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* [dpdk-dev] [PATCH v1 00/14] bbdev new features
@ 2020-02-27  4:38 Nicolas Chautru
  2020-02-27  4:38 ` [dpdk-dev] [PATCH v1 01/14] bbdev: add capability flag for filler bits inclusion in HARQ Nicolas Chautru
                   ` (14 more replies)
  0 siblings, 15 replies; 115+ messages in thread
From: Nicolas Chautru @ 2020-02-27  4:38 UTC (permalink / raw)
  To: thomas, akhil.goyal, dev; +Cc: ferruh.yigit, Nicolas Chautru

This set includes extending support for the bbdev device drivers 
for 20.05 and notably add a new baseband PMD for FPGA 5GNR 
FEC implementation. 
Documentation is updated as well accordingly. 

Nic Chautru (14):
  bbdev: add capability flag for filler bits inclusion in HARQ
  bbdev: expose device HARQ buffer size at device level
  baseband/turbo_sw: fix the exposed LLR decimals assumption
  baseband/turbo_sw: support large size code block
  test-bbdev: rename FPGA LTE macros to be more explicit
  test-bbdev: support HARQ validation
  test-bbdev: support for performance tests
  test-bbdev: support for LDPC interrupt test
  test-bbdev: support for offload test for LDPC
  test-bbdev: vectors update
  doc: update of testbbdev documentation
  drivers/baseband: add PMD for FPGA 5GNR FEC
  test-bbdev: add support for FPGA driver initialization
  doc: add feature matrix table for bbdev devices

 .gitignore                                         |    1 +
 app/test-bbdev/Makefile                            |    3 +
 app/test-bbdev/ldpc_dec_default.data               |    2 +-
 app/test-bbdev/main.c                              |   29 +-
 app/test-bbdev/main.h                              |    9 +-
 app/test-bbdev/meson.build                         |    3 +
 app/test-bbdev/test_bbdev_perf.c                   | 1468 ++++++++++-
 app/test-bbdev/test_bbdev_vector.c                 |    9 +-
 app/test-bbdev/test_vectors/ldpc_dec_v2342.data    |  745 ------
 app/test-bbdev/test_vectors/ldpc_dec_v9503.data    |    4 +-
 .../turbo_dec_c1_k6144_r0_e34560_negllr.data       |  645 -----
 .../turbo_dec_c2_k3136_r0_e4920_sbd_negllr.data    |  676 ------
 ...bo_dec_c2_k3136_r0_e4920_sbd_negllr_crc24b.data |    5 +-
 .../turbo_enc_c2_k5952_r0_e17868_crc24b.data       |  300 ---
 .../turbo_enc_c4_k4800_r2_e14412_crc24b.data       |  252 --
 config/common_base                                 |    5 +
 doc/guides/bbdevs/features/default.ini             |   16 +
 doc/guides/bbdevs/features/fpga_5gnr_fec.ini       |   11 +
 doc/guides/bbdevs/features/fpga_lte_fec.ini        |   10 +
 doc/guides/bbdevs/features/mbc.ini                 |   14 +
 doc/guides/bbdevs/features/null.ini                |    7 +
 doc/guides/bbdevs/features/turbo_sw.ini            |   11 +
 doc/guides/bbdevs/fpga_5gnr_fec.rst                |  297 +++
 doc/guides/bbdevs/index.rst                        |    2 +
 doc/guides/bbdevs/overview.rst                     |   15 +
 doc/guides/conf.py                                 |    5 +
 doc/guides/tools/testbbdev.rst                     |  337 ++-
 drivers/baseband/Makefile                          |    2 +
 drivers/baseband/fpga_5gnr_fec/Makefile            |   29 +
 drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.c     | 2552 ++++++++++++++++++++
 drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h     |   74 +
 drivers/baseband/fpga_5gnr_fec/meson.build         |    6 +
 .../rte_pmd_bbdev_fpga_5gnr_fec_version.map        |   10 +
 drivers/baseband/meson.build                       |    2 +-
 drivers/baseband/turbo_sw/bbdev_turbo_software.c   |   15 +-
 lib/librte_bbdev/rte_bbdev.h                       |    4 +
 lib/librte_bbdev/rte_bbdev_op.h                    |   14 +-
 mk/rte.app.mk                                      |    1 +
 38 files changed, 4772 insertions(+), 2818 deletions(-)
 delete mode 100644 app/test-bbdev/test_vectors/ldpc_dec_v2342.data
 delete mode 100644 app/test-bbdev/test_vectors/turbo_dec_c1_k6144_r0_e34560_negllr.data
 delete mode 100644 app/test-bbdev/test_vectors/turbo_dec_c2_k3136_r0_e4920_sbd_negllr.data
 delete mode 100644 app/test-bbdev/test_vectors/turbo_enc_c2_k5952_r0_e17868_crc24b.data
 delete mode 100644 app/test-bbdev/test_vectors/turbo_enc_c4_k4800_r2_e14412_crc24b.data
 create mode 100644 doc/guides/bbdevs/features/default.ini
 create mode 100644 doc/guides/bbdevs/features/fpga_5gnr_fec.ini
 create mode 100644 doc/guides/bbdevs/features/fpga_lte_fec.ini
 create mode 100644 doc/guides/bbdevs/features/mbc.ini
 create mode 100644 doc/guides/bbdevs/features/null.ini
 create mode 100644 doc/guides/bbdevs/features/turbo_sw.ini
 create mode 100644 doc/guides/bbdevs/fpga_5gnr_fec.rst
 create mode 100644 doc/guides/bbdevs/overview.rst
 create mode 100644 drivers/baseband/fpga_5gnr_fec/Makefile
 create mode 100644 drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.c
 create mode 100644 drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h
 create mode 100644 drivers/baseband/fpga_5gnr_fec/meson.build
 create mode 100644 drivers/baseband/fpga_5gnr_fec/rte_pmd_bbdev_fpga_5gnr_fec_version.map

-- 
1.8.3.1


^ permalink raw reply	[flat|nested] 115+ messages in thread

* [dpdk-dev] [PATCH v1 01/14] bbdev: add capability flag for filler bits inclusion in HARQ
  2020-02-27  4:38 [dpdk-dev] [PATCH v1 00/14] bbdev new features Nicolas Chautru
@ 2020-02-27  4:38 ` Nicolas Chautru
  2020-02-27  4:38 ` [dpdk-dev] [PATCH v1 02/14] bbdev: expose device HARQ buffer size at device level Nicolas Chautru
                   ` (13 subsequent siblings)
  14 siblings, 0 replies; 115+ messages in thread
From: Nicolas Chautru @ 2020-02-27  4:38 UTC (permalink / raw)
  To: thomas, akhil.goyal, dev; +Cc: ferruh.yigit, Nic Chautru

From: Nic Chautru <nicolas.chautru@intel.com>

Adding capability flag for device variants when HARQ buffer
may or may not include the filler bits.
Minor cosmetic changes in same file.

Signed-off-by: Nic Chautru <nicolas.chautru@intel.com>
---
 lib/librte_bbdev/rte_bbdev.h    |  2 ++
 lib/librte_bbdev/rte_bbdev_op.h | 12 ++++++++++--
 2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/lib/librte_bbdev/rte_bbdev.h b/lib/librte_bbdev/rte_bbdev.h
index 591fb79..b2da190 100644
--- a/lib/librte_bbdev/rte_bbdev.h
+++ b/lib/librte_bbdev/rte_bbdev.h
@@ -607,6 +607,7 @@ struct __rte_cache_aligned rte_bbdev {
  * @param ops
  *   Pointer array where operations will be dequeued to. Must have at least
  *   @p num_ops entries
+ *   ie. A pointer to a table of void * pointers (ops) that will be filled.
  * @param num_ops
  *   The maximum number of operations to dequeue.
  *
@@ -638,6 +639,7 @@ struct __rte_cache_aligned rte_bbdev {
  * @param ops
  *   Pointer array where operations will be dequeued to. Must have at least
  *   @p num_ops entries
+ *   ie. A pointer to a table of void * pointers (ops) that will be filled.
  * @param num_ops
  *   The maximum number of operations to dequeue.
  *
diff --git a/lib/librte_bbdev/rte_bbdev_op.h b/lib/librte_bbdev/rte_bbdev_op.h
index 1e119a7..062f9ff 100644
--- a/lib/librte_bbdev/rte_bbdev_op.h
+++ b/lib/librte_bbdev/rte_bbdev_op.h
@@ -31,8 +31,11 @@
 #define RTE_BBDEV_TURBO_MAX_TB_SIZE (391656)
 /* Maximum size of Code Block (36.212, Table 5.1.3-3) */
 #define RTE_BBDEV_TURBO_MAX_CB_SIZE (6144)
-/* Maximum size of Code Block  */
+/* Maximum size of Code Block */
 #define RTE_BBDEV_LDPC_MAX_CB_SIZE (8448)
+/* Minimum size of Code Block */
+#define RTE_BBDEV_LDPC_MIN_CB_SIZE (40)
+
 /* Minimum size of Code Block (36.212, Table 5.1.3-3) */
 #define RTE_BBDEV_TURBO_MIN_CB_SIZE (40)
 /* Maximum size of circular buffer */
@@ -177,7 +180,12 @@ enum rte_bbdev_op_ldpcdec_flag_bitmasks {
 	/** Set if a device supports loop-back access to
 	 *  HARQ internal memory. Intended for troubleshooting.
 	 */
-	RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK = (1ULL << 17)
+	RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK = (1ULL << 17),
+	/** Set if a device includes LLR filler bits in the circular buffer
+	 *  for HARQ memory. If not set, it is assumed the filler are not in
+	 *  HARQ memory and handled directory by the LDPC decoder.
+	 */
+	RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_FILLERS = (1ULL << 18)
 };
 
 /** Flags for LDPC encoder operation and capability structure */
-- 
1.8.3.1


^ permalink raw reply	[flat|nested] 115+ messages in thread

* [dpdk-dev] [PATCH v1 02/14] bbdev: expose device HARQ buffer size at device level
  2020-02-27  4:38 [dpdk-dev] [PATCH v1 00/14] bbdev new features Nicolas Chautru
  2020-02-27  4:38 ` [dpdk-dev] [PATCH v1 01/14] bbdev: add capability flag for filler bits inclusion in HARQ Nicolas Chautru
@ 2020-02-27  4:38 ` Nicolas Chautru
  2020-02-27  4:38 ` [dpdk-dev] [PATCH v1 03/14] baseband/turbo_sw: fix the exposed LLR decimals assumption Nicolas Chautru
                   ` (12 subsequent siblings)
  14 siblings, 0 replies; 115+ messages in thread
From: Nicolas Chautru @ 2020-02-27  4:38 UTC (permalink / raw)
  To: thomas, akhil.goyal, dev; +Cc: ferruh.yigit, Nic Chautru

From: Nic Chautru <nicolas.chautru@intel.com>

This exposes the HARQ buffer size at the device driver level
instead of using the capability of a specific operation.

This is currently not yet used by a device until
future commit.

Signed-off-by: Nic Chautru <nicolas.chautru@intel.com>
---
 drivers/baseband/turbo_sw/bbdev_turbo_software.c | 2 +-
 lib/librte_bbdev/rte_bbdev.h                     | 2 ++
 lib/librte_bbdev/rte_bbdev_op.h                  | 2 --
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/baseband/turbo_sw/bbdev_turbo_software.c b/drivers/baseband/turbo_sw/bbdev_turbo_software.c
index f2fe7a2..6d5e080 100644
--- a/drivers/baseband/turbo_sw/bbdev_turbo_software.c
+++ b/drivers/baseband/turbo_sw/bbdev_turbo_software.c
@@ -219,7 +219,6 @@ struct turbo_sw_queue {
 					RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE,
 			.llr_size = 8,
 			.llr_decimals = 2,
-			.harq_memory_size = 0,
 			.num_buffers_src =
 					RTE_BBDEV_LDPC_MAX_CODE_BLOCKS,
 			.num_buffers_hard_out =
@@ -251,6 +250,7 @@ struct turbo_sw_queue {
 	dev_info->default_queue_conf = default_queue_conf;
 	dev_info->capabilities = bbdev_capabilities;
 	dev_info->min_alignment = 64;
+	dev_info->harq_buffer_size = 0;
 
 	rte_bbdev_log_debug("got device info from %u\n", dev->data->dev_id);
 }
diff --git a/lib/librte_bbdev/rte_bbdev.h b/lib/librte_bbdev/rte_bbdev.h
index b2da190..38d9d50 100644
--- a/lib/librte_bbdev/rte_bbdev.h
+++ b/lib/librte_bbdev/rte_bbdev.h
@@ -307,6 +307,8 @@ struct rte_bbdev_driver_info {
 	bool queue_intr_supported;
 	/** Minimum alignment of buffers, in bytes */
 	uint16_t min_alignment;
+	/** HARQ memory available in kB */
+	uint32_t harq_buffer_size;
 	/** Default queue configuration used if none is supplied  */
 	struct rte_bbdev_queue_conf default_queue_conf;
 	/** Device operation capabilities */
diff --git a/lib/librte_bbdev/rte_bbdev_op.h b/lib/librte_bbdev/rte_bbdev_op.h
index 062f9ff..8122089 100644
--- a/lib/librte_bbdev/rte_bbdev_op.h
+++ b/lib/librte_bbdev/rte_bbdev_op.h
@@ -712,8 +712,6 @@ struct rte_bbdev_op_cap_ldpc_dec {
 	int8_t llr_size;
 	/** LLR numbers of decimals bit for arithmetic representation */
 	int8_t llr_decimals;
-	/** Amount of memory for HARQ in external DDR in MB */
-	uint16_t harq_memory_size;
 	/** Num input code block buffers */
 	uint16_t num_buffers_src;
 	/** Num hard output code block buffers */
-- 
1.8.3.1


^ permalink raw reply	[flat|nested] 115+ messages in thread

* [dpdk-dev] [PATCH v1 03/14] baseband/turbo_sw: fix the exposed LLR decimals assumption
  2020-02-27  4:38 [dpdk-dev] [PATCH v1 00/14] bbdev new features Nicolas Chautru
  2020-02-27  4:38 ` [dpdk-dev] [PATCH v1 01/14] bbdev: add capability flag for filler bits inclusion in HARQ Nicolas Chautru
  2020-02-27  4:38 ` [dpdk-dev] [PATCH v1 02/14] bbdev: expose device HARQ buffer size at device level Nicolas Chautru
@ 2020-02-27  4:38 ` Nicolas Chautru
  2020-02-27  4:38 ` [dpdk-dev] [PATCH v1 04/14] baseband/turbo_sw: support large size code block Nicolas Chautru
                   ` (11 subsequent siblings)
  14 siblings, 0 replies; 115+ messages in thread
From: Nicolas Chautru @ 2020-02-27  4:38 UTC (permalink / raw)
  To: thomas, akhil.goyal, dev; +Cc: ferruh.yigit, Nic Chautru

From: Nic Chautru <nicolas.chautru@intel.com>

The actual LLR representation was incorrectly assumed to be 2
instead of 4. This would impact wireless performance but is not
critical to be back ported on LTS branches.

Fixes: c769c711757a ("baseband/turbo_sw: extend for 5G")

Signed-off-by: Nic Chautru <nicolas.chautru@intel.com>
---
 drivers/baseband/turbo_sw/bbdev_turbo_software.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/baseband/turbo_sw/bbdev_turbo_software.c b/drivers/baseband/turbo_sw/bbdev_turbo_software.c
index 6d5e080..5ca8ca1 100644
--- a/drivers/baseband/turbo_sw/bbdev_turbo_software.c
+++ b/drivers/baseband/turbo_sw/bbdev_turbo_software.c
@@ -218,7 +218,7 @@ struct turbo_sw_queue {
 					RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE |
 					RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE,
 			.llr_size = 8,
-			.llr_decimals = 2,
+			.llr_decimals = 4,
 			.num_buffers_src =
 					RTE_BBDEV_LDPC_MAX_CODE_BLOCKS,
 			.num_buffers_hard_out =
-- 
1.8.3.1


^ permalink raw reply	[flat|nested] 115+ messages in thread

* [dpdk-dev] [PATCH v1 04/14] baseband/turbo_sw: support large size code block
  2020-02-27  4:38 [dpdk-dev] [PATCH v1 00/14] bbdev new features Nicolas Chautru
                   ` (2 preceding siblings ...)
  2020-02-27  4:38 ` [dpdk-dev] [PATCH v1 03/14] baseband/turbo_sw: fix the exposed LLR decimals assumption Nicolas Chautru
@ 2020-02-27  4:38 ` Nicolas Chautru
  2020-02-27  4:38 ` [dpdk-dev] [PATCH v1 05/14] test-bbdev: rename FPGA LTE macros to be more explicit Nicolas Chautru
                   ` (10 subsequent siblings)
  14 siblings, 0 replies; 115+ messages in thread
From: Nicolas Chautru @ 2020-02-27  4:38 UTC (permalink / raw)
  To: thomas, akhil.goyal, dev; +Cc: ferruh.yigit, Nic Chautru

From: Nic Chautru <nicolas.chautru@intel.com>

This is to support cases when the input data for
decoding a code block is larger than 64kB and would
not fit as a contiguous block of data into one
mbuf. In that case the length from the opearation
supersedes the mbug default structure.

Signed-off-by: Nic Chautru <nicolas.chautru@intel.com>
---
 app/test-bbdev/test_bbdev_perf.c                 | 40 +++++++++++++++++++-----
 drivers/baseband/turbo_sw/bbdev_turbo_software.c | 11 ++++---
 2 files changed, 39 insertions(+), 12 deletions(-)

diff --git a/app/test-bbdev/test_bbdev_perf.c b/app/test-bbdev/test_bbdev_perf.c
index d8db58e..d46966d 100644
--- a/app/test-bbdev/test_bbdev_perf.c
+++ b/app/test-bbdev/test_bbdev_perf.c
@@ -764,6 +764,7 @@ typedef int (test_case_function)(struct active_device *ad,
 {
 	int ret;
 	unsigned int i, j;
+	bool large_input = false;
 
 	for (i = 0; i < n; ++i) {
 		char *data;
@@ -774,24 +775,47 @@ typedef int (test_case_function)(struct active_device *ad,
 				op_type, n * ref_entries->nb_segments,
 				mbuf_pool->size);
 
-		TEST_ASSERT_SUCCESS(((seg->length + RTE_PKTMBUF_HEADROOM) >
-				(uint32_t)UINT16_MAX),
-				"Given data is bigger than allowed mbuf segment size");
-
+		if (seg->length > 64000) {
+			/*
+			 * Special case when DPDK mbuf cannot handle
+			 * the required input size
+			 */
+			printf("Warning: Larger input size than DPDK mbuf %d\n",
+					seg->length);
+			large_input = true;
+		} else {
+			TEST_ASSERT_SUCCESS(
+					((seg->length + RTE_PKTMBUF_HEADROOM)
+					> (uint32_t)UINT16_MAX),
+					"Given data is bigger than allowed mbuf segment size"
+					);
+		}
 		bufs[i].data = m_head;
 		bufs[i].offset = 0;
 		bufs[i].length = 0;
 
 		if ((op_type == DATA_INPUT) || (op_type == DATA_HARQ_INPUT)) {
-			data = rte_pktmbuf_append(m_head, seg->length);
-			TEST_ASSERT_NOT_NULL(data,
+			if ((op_type == DATA_INPUT) && large_input) {
+				/* Allocate a fake overused mbuf */
+				data = rte_malloc(NULL, 128 * 1024, 0);
+				memcpy(data, seg->addr, seg->length);
+				m_head->buf_addr = data;
+				m_head->buf_iova = rte_mem_virt2phy(data);
+				m_head->data_off = 0;
+				m_head->data_len = seg->length;
+			} else {
+				data = rte_pktmbuf_append(m_head, seg->length);
+				TEST_ASSERT_NOT_NULL(data,
 					"Couldn't append %u bytes to mbuf from %d data type mbuf pool",
 					seg->length, op_type);
 
-			TEST_ASSERT(data == RTE_PTR_ALIGN(data, min_alignment),
+				TEST_ASSERT(data == RTE_PTR_ALIGN(
+						data, min_alignment),
 					"Data addr in mbuf (%p) is not aligned to device min alignment (%u)",
 					data, min_alignment);
-			rte_memcpy(data, seg->addr, seg->length);
+				rte_memcpy(data, seg->addr, seg->length);
+			}
+
 			bufs[i].length += seg->length;
 
 			for (j = 1; j < ref_entries->nb_segments; ++j) {
diff --git a/drivers/baseband/turbo_sw/bbdev_turbo_software.c b/drivers/baseband/turbo_sw/bbdev_turbo_software.c
index 5ca8ca1..ea3fecb 100644
--- a/drivers/baseband/turbo_sw/bbdev_turbo_software.c
+++ b/drivers/baseband/turbo_sw/bbdev_turbo_software.c
@@ -1335,7 +1335,7 @@ struct turbo_sw_queue {
 
 static inline void
 process_ldpc_dec_cb(struct turbo_sw_queue *q, struct rte_bbdev_dec_op *op,
-		uint8_t c, uint16_t out_length, uint16_t e,
+		uint8_t c, uint16_t out_length, uint32_t e,
 		struct rte_mbuf *m_in,
 		struct rte_mbuf *m_out_head, struct rte_mbuf *m_out,
 		struct rte_mbuf *m_harq_in,
@@ -1617,8 +1617,8 @@ struct turbo_sw_queue {
 		struct rte_bbdev_stats *queue_stats)
 {
 	uint8_t c, r = 0;
-	uint16_t e, out_length;
-	uint16_t crc24_overlap = 0;
+	uint32_t e;
+	uint16_t out_length, crc24_overlap = 0;
 	struct rte_bbdev_op_ldpc_dec *dec = &op->ldpc_dec;
 	struct rte_mbuf *m_in = dec->input.data;
 	struct rte_mbuf *m_harq_in = dec->harq_combined_input.data;
@@ -1661,7 +1661,10 @@ struct turbo_sw_queue {
 			e = (r < dec->tb_params.cab) ?
 				dec->tb_params.ea : dec->tb_params.eb;
 
-		seg_total_left = rte_pktmbuf_data_len(m_in) - in_offset;
+		if (e < 64000) /* Special case handling when overusing mbuf */
+			seg_total_left = rte_pktmbuf_data_len(m_in) - in_offset;
+		else
+			seg_total_left = e;
 
 		process_ldpc_dec_cb(q, op, c, out_length, e,
 				m_in, m_out_head, m_out,
-- 
1.8.3.1


^ permalink raw reply	[flat|nested] 115+ messages in thread

* [dpdk-dev] [PATCH v1 05/14] test-bbdev: rename FPGA LTE macros to be more explicit
  2020-02-27  4:38 [dpdk-dev] [PATCH v1 00/14] bbdev new features Nicolas Chautru
                   ` (3 preceding siblings ...)
  2020-02-27  4:38 ` [dpdk-dev] [PATCH v1 04/14] baseband/turbo_sw: support large size code block Nicolas Chautru
@ 2020-02-27  4:38 ` Nicolas Chautru
  2020-02-27  4:39 ` [dpdk-dev] [PATCH v1 06/14] test-bbdev: support HARQ validation Nicolas Chautru
                   ` (9 subsequent siblings)
  14 siblings, 0 replies; 115+ messages in thread
From: Nicolas Chautru @ 2020-02-27  4:38 UTC (permalink / raw)
  To: thomas, akhil.goyal, dev; +Cc: ferruh.yigit, Nic Chautru

From: Nic Chautru <nicolas.chautru@intel.com>

Self-contained and cosmetic renaming of macro to be more explict.

Signed-off-by: Nic Chautru <nicolas.chautru@intel.com>
---
 app/test-bbdev/test_bbdev_perf.c | 51 +++++++++++++++-------------------------
 1 file changed, 19 insertions(+), 32 deletions(-)

diff --git a/app/test-bbdev/test_bbdev_perf.c b/app/test-bbdev/test_bbdev_perf.c
index d46966d..aa8bb71 100644
--- a/app/test-bbdev/test_bbdev_perf.c
+++ b/app/test-bbdev/test_bbdev_perf.c
@@ -18,10 +18,6 @@
 #include <rte_hexdump.h>
 #include <rte_interrupts.h>
 
-#ifdef RTE_LIBRTE_PMD_BBDEV_FPGA_LTE_FEC
-#include <fpga_lte_fec.h>
-#endif
-
 #include "main.h"
 #include "test_bbdev_vector.h"
 
@@ -31,15 +27,16 @@
 #define TEST_REPETITIONS 1000
 
 #ifdef RTE_LIBRTE_PMD_BBDEV_FPGA_LTE_FEC
-#define FPGA_PF_DRIVER_NAME ("intel_fpga_lte_fec_pf")
-#define FPGA_VF_DRIVER_NAME ("intel_fpga_lte_fec_vf")
-#define VF_UL_QUEUE_VALUE 4
-#define VF_DL_QUEUE_VALUE 4
-#define UL_BANDWIDTH 3
-#define DL_BANDWIDTH 3
-#define UL_LOAD_BALANCE 128
-#define DL_LOAD_BALANCE 128
-#define FLR_TIMEOUT 610
+#include <fpga_lte_fec.h>
+#define FPGA_LTE_PF_DRIVER_NAME ("intel_fpga_lte_fec_pf")
+#define FPGA_LTE_VF_DRIVER_NAME ("intel_fpga_lte_fec_vf")
+#define VF_UL_4G_QUEUE_VALUE 4
+#define VF_DL_4G_QUEUE_VALUE 4
+#define UL_4G_BANDWIDTH 3
+#define DL_4G_BANDWIDTH 3
+#define UL_4G_LOAD_BALANCE 128
+#define DL_4G_LOAD_BALANCE 128
+#define FLR_4G_TIMEOUT 610
 #endif
 
 #define OPS_CACHE_SIZE 256U
@@ -521,11 +518,11 @@ typedef int (test_case_function)(struct active_device *ad,
  */
 #ifdef RTE_LIBRTE_PMD_BBDEV_FPGA_LTE_FEC
 	if ((get_init_device() == true) &&
-		(!strcmp(info->drv.driver_name, FPGA_PF_DRIVER_NAME))) {
+		(!strcmp(info->drv.driver_name, FPGA_LTE_PF_DRIVER_NAME))) {
 		struct fpga_lte_fec_conf conf;
 		unsigned int i;
 
-		printf("Configure FPGA FEC Driver %s with default values\n",
+		printf("Configure FPGA LTE FEC Driver %s with default values\n",
 				info->drv.driver_name);
 
 		/* clear default configuration before initialization */
@@ -539,22 +536,22 @@ typedef int (test_case_function)(struct active_device *ad,
 
 		for (i = 0; i < FPGA_LTE_FEC_NUM_VFS; ++i) {
 			/* Number of UL queues per VF (fpga supports 8 VFs) */
-			conf.vf_ul_queues_number[i] = VF_UL_QUEUE_VALUE;
+			conf.vf_ul_queues_number[i] = VF_UL_4G_QUEUE_VALUE;
 			/* Number of DL queues per VF (fpga supports 8 VFs) */
-			conf.vf_dl_queues_number[i] = VF_DL_QUEUE_VALUE;
+			conf.vf_dl_queues_number[i] = VF_DL_4G_QUEUE_VALUE;
 		}
 
 		/* UL bandwidth. Needed for schedule algorithm */
-		conf.ul_bandwidth = UL_BANDWIDTH;
+		conf.ul_bandwidth = UL_4G_BANDWIDTH;
 		/* DL bandwidth */
-		conf.dl_bandwidth = DL_BANDWIDTH;
+		conf.dl_bandwidth = DL_4G_BANDWIDTH;
 
 		/* UL & DL load Balance Factor to 64 */
-		conf.ul_load_balance = UL_LOAD_BALANCE;
-		conf.dl_load_balance = DL_LOAD_BALANCE;
+		conf.ul_load_balance = UL_4G_LOAD_BALANCE;
+		conf.dl_load_balance = DL_4G_LOAD_BALANCE;
 
 		/**< FLR timeout value */
-		conf.flr_time_out = FLR_TIMEOUT;
+		conf.flr_time_out = FLR_4G_TIMEOUT;
 
 		/* setup FPGA PF with configuration information */
 		ret = fpga_lte_fec_configure(info->dev_name, &conf);
@@ -2862,11 +2859,6 @@ typedef int (test_case_function)(struct active_device *ad,
 
 		start_time = rte_rdtsc_precise();
 
-		/*
-		 * printf("Latency Debug %d\n",
-		 * ops_enq[0]->ldpc_enc.cb_params.z_c); REMOVEME
-		 */
-
 		enq = rte_bbdev_enqueue_ldpc_enc_ops(dev_id, queue_id,
 				&ops_enq[enq], burst_sz);
 		TEST_ASSERT(enq == burst_sz,
@@ -2892,11 +2884,6 @@ typedef int (test_case_function)(struct active_device *ad,
 			TEST_ASSERT_SUCCESS(ret, "Validation failed!");
 		}
 
-		/*
-		 * printf("Ready to free - deq %d num_to_process %d\n", FIXME
-		 *		deq, num_to_process);
-		 * printf("cache %d\n", ops_enq[0]->mempool->cache_size);
-		 */
 		rte_bbdev_enc_op_free_bulk(ops_enq, deq);
 		dequeued += deq;
 	}
-- 
1.8.3.1


^ permalink raw reply	[flat|nested] 115+ messages in thread

* [dpdk-dev] [PATCH v1 06/14] test-bbdev: support HARQ validation
  2020-02-27  4:38 [dpdk-dev] [PATCH v1 00/14] bbdev new features Nicolas Chautru
                   ` (4 preceding siblings ...)
  2020-02-27  4:38 ` [dpdk-dev] [PATCH v1 05/14] test-bbdev: rename FPGA LTE macros to be more explicit Nicolas Chautru
@ 2020-02-27  4:39 ` Nicolas Chautru
  2020-02-27  4:39 ` [dpdk-dev] [PATCH v1 07/14] test-bbdev: support for performance tests Nicolas Chautru
                   ` (8 subsequent siblings)
  14 siblings, 0 replies; 115+ messages in thread
From: Nicolas Chautru @ 2020-02-27  4:39 UTC (permalink / raw)
  To: thomas, akhil.goyal, dev; +Cc: ferruh.yigit, Nic Chautru

From: Nic Chautru <nicolas.chautru@intel.com>

Adding functionality to validate HARQ for different
devices implementation.
Adding capacity to fetch HARQ data when required as
part of this validation.

Signed-off-by: Nic Chautru <nicolas.chautru@intel.com>
---
 app/test-bbdev/test_bbdev_perf.c   | 552 ++++++++++++++++++++++++++++++++-----
 app/test-bbdev/test_bbdev_vector.c |   9 +-
 2 files changed, 492 insertions(+), 69 deletions(-)

diff --git a/app/test-bbdev/test_bbdev_perf.c b/app/test-bbdev/test_bbdev_perf.c
index aa8bb71..978ccd6 100644
--- a/app/test-bbdev/test_bbdev_perf.c
+++ b/app/test-bbdev/test_bbdev_perf.c
@@ -44,14 +44,25 @@
 
 #define SYNC_WAIT 0
 #define SYNC_START 1
+#define INVALID_OPAQUE -1
 
 #define INVALID_QUEUE_ID -1
+/* Increment for next code block in external HARQ memory */
+#define HARQ_INCR 32768
+/* Headroom for filler LLRs insertion in HARQ buffer */
+#define FILLER_HEADROOM 1024
 
 static struct test_bbdev_vector test_vector;
 
 /* Switch between PMD and Interrupt for throughput TC */
 static bool intr_enabled;
 
+/* LLR arithmetic representation for numerical conversion */
+static int ldpc_llr_decimals;
+static int ldpc_llr_size;
+/* Keep track of the LDPC decoder device capability flag */
+static uint32_t ldpc_cap_flags;
+
 /* Represents tested active devices */
 static struct active_device {
 	const char *driver_name;
@@ -293,7 +304,7 @@ typedef int (test_case_function)(struct active_device *ad,
 				return TEST_FAILED;
 			}
 			if (intr_enabled && !(cap->capability_flags &
-					RTE_BBDEV_TURBO_ENC_INTERRUPTS)) {
+					RTE_BBDEV_LDPC_ENC_INTERRUPTS)) {
 				printf(
 					"Dequeue interrupts are not supported!\n");
 				return TEST_FAILED;
@@ -336,12 +347,19 @@ typedef int (test_case_function)(struct active_device *ad,
 				return TEST_FAILED;
 			}
 			if (intr_enabled && !(cap->capability_flags &
-					RTE_BBDEV_TURBO_DEC_INTERRUPTS)) {
+					RTE_BBDEV_LDPC_DEC_INTERRUPTS)) {
 				printf(
 					"Dequeue interrupts are not supported!\n");
 				return TEST_FAILED;
 			}
-
+			if (intr_enabled && (test_vector.ldpc_dec.op_flags &
+				(RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE |
+				RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE |
+				RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK
+					))) {
+				printf("Skip loop-back with interrupt\n");
+				return TEST_FAILED;
+			}
 			return TEST_SUCCESS;
 		}
 	}
@@ -377,7 +395,8 @@ typedef int (test_case_function)(struct active_device *ad,
 	snprintf(pool_name, sizeof(pool_name), "%s_pool_%u", op_type_str,
 			dev_id);
 	return rte_pktmbuf_pool_create(pool_name, mbuf_pool_size, 0, 0,
-			RTE_MAX(max_seg_sz + RTE_PKTMBUF_HEADROOM,
+			RTE_MAX(max_seg_sz + RTE_PKTMBUF_HEADROOM
+					+ FILLER_HEADROOM,
 			(unsigned int)RTE_MBUF_DEFAULT_BUF_SIZE), socket_id);
 }
 
@@ -432,27 +451,33 @@ typedef int (test_case_function)(struct active_device *ad,
 		return TEST_SUCCESS;
 
 	/* Inputs */
-	mbuf_pool_size = optimal_mempool_size(ops_pool_size * in->nb_segments);
-	mp = create_mbuf_pool(in, ad->dev_id, socket_id, mbuf_pool_size, "in");
-	TEST_ASSERT_NOT_NULL(mp,
-			"ERROR Failed to create %u items input pktmbuf pool for dev %u on socket %u.",
-			mbuf_pool_size,
-			ad->dev_id,
-			socket_id);
-	ad->in_mbuf_pool = mp;
+	if (in->nb_segments > 0) {
+		mbuf_pool_size = optimal_mempool_size(ops_pool_size *
+				in->nb_segments);
+		mp = create_mbuf_pool(in, ad->dev_id, socket_id,
+				mbuf_pool_size, "in");
+		TEST_ASSERT_NOT_NULL(mp,
+				"ERROR Failed to create %u items input pktmbuf pool for dev %u on socket %u.",
+				mbuf_pool_size,
+				ad->dev_id,
+				socket_id);
+		ad->in_mbuf_pool = mp;
+	}
 
 	/* Hard outputs */
-	mbuf_pool_size = optimal_mempool_size(ops_pool_size *
-			hard_out->nb_segments);
-	mp = create_mbuf_pool(hard_out, ad->dev_id, socket_id, mbuf_pool_size,
-			"hard_out");
-	TEST_ASSERT_NOT_NULL(mp,
-			"ERROR Failed to create %u items hard output pktmbuf pool for dev %u on socket %u.",
-			mbuf_pool_size,
-			ad->dev_id,
-			socket_id);
-	ad->hard_out_mbuf_pool = mp;
-
+	if (hard_out->nb_segments > 0) {
+		mbuf_pool_size = optimal_mempool_size(ops_pool_size *
+				hard_out->nb_segments);
+		mp = create_mbuf_pool(hard_out, ad->dev_id, socket_id,
+				mbuf_pool_size,
+				"hard_out");
+		TEST_ASSERT_NOT_NULL(mp,
+				"ERROR Failed to create %u items hard output pktmbuf pool for dev %u on socket %u.",
+				mbuf_pool_size,
+				ad->dev_id,
+				socket_id);
+		ad->hard_out_mbuf_pool = mp;
+	}
 
 	/* Soft outputs */
 	if (soft_out->nb_segments > 0) {
@@ -907,6 +932,45 @@ typedef int (test_case_function)(struct active_device *ad,
 	}
 }
 
+/*
+ * We may have to insert filler bits
+ * when they are required by the HARQ assumption
+ */
+static void
+ldpc_add_filler(struct rte_bbdev_op_data *input_ops,
+		const uint16_t n, struct test_op_params *op_params)
+{
+	struct rte_bbdev_op_ldpc_dec dec = op_params->ref_dec_op->ldpc_dec;
+
+	if (input_ops == NULL)
+		return;
+	/* No need to add filler if not required by device */
+	if (!(ldpc_cap_flags &
+			RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_FILLERS))
+		return;
+	/* No need to add filler for loopback operation */
+	if (dec.op_flags & RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK)
+		return;
+
+	uint16_t i, j, parity_offset;
+	for (i = 0; i < n; ++i) {
+		struct rte_mbuf *m = input_ops[i].data;
+		int8_t *llr = rte_pktmbuf_mtod_offset(m, int8_t *,
+				input_ops[i].offset);
+		parity_offset = (dec.basegraph == 1 ? 20 : 8)
+				* dec.z_c - dec.n_filler;
+		uint16_t new_hin_size = input_ops[i].length + dec.n_filler;
+		m->data_len = new_hin_size;
+		input_ops[i].length = new_hin_size;
+		for (j = new_hin_size - 1; j >= parity_offset + dec.n_filler;
+				j--)
+			llr[j] = llr[j - dec.n_filler];
+		uint16_t llr_max_pre_scaling = (1 << (ldpc_llr_size - 1)) - 1;
+		for (j = 0; j < dec.n_filler; j++)
+			llr[parity_offset + j] = llr_max_pre_scaling;
+	}
+}
+
 static void
 ldpc_input_llr_scaling(struct rte_bbdev_op_data *input_ops,
 		const uint16_t n, const int8_t llr_size,
@@ -929,7 +993,9 @@ typedef int (test_case_function)(struct active_device *ad,
 					++byte_idx) {
 
 				llr_tmp = llr[byte_idx];
-				if (llr_decimals == 2)
+				if (llr_decimals == 4)
+					llr_tmp *= 8;
+				else if (llr_decimals == 2)
 					llr_tmp *= 2;
 				else if (llr_decimals == 0)
 					llr_tmp /= 2;
@@ -997,12 +1063,24 @@ typedef int (test_case_function)(struct active_device *ad,
 			capabilities->cap.turbo_dec.max_llr_modulus);
 
 	if (test_vector.op_type == RTE_BBDEV_OP_LDPC_DEC) {
-		ldpc_input_llr_scaling(*queue_ops[DATA_INPUT], n,
-			capabilities->cap.ldpc_dec.llr_size,
-			capabilities->cap.ldpc_dec.llr_decimals);
-		ldpc_input_llr_scaling(*queue_ops[DATA_HARQ_INPUT], n,
-				capabilities->cap.ldpc_dec.llr_size,
-				capabilities->cap.ldpc_dec.llr_decimals);
+		bool loopback = op_params->ref_dec_op->ldpc_dec.op_flags &
+				RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK;
+		bool llr_comp = op_params->ref_dec_op->ldpc_dec.op_flags &
+				RTE_BBDEV_LDPC_LLR_COMPRESSION;
+		bool harq_comp = op_params->ref_dec_op->ldpc_dec.op_flags &
+				RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION;
+		ldpc_llr_decimals = capabilities->cap.ldpc_dec.llr_decimals;
+		ldpc_llr_size = capabilities->cap.ldpc_dec.llr_size;
+		ldpc_cap_flags = capabilities->cap.ldpc_dec.capability_flags;
+		if (!loopback && !llr_comp)
+			ldpc_input_llr_scaling(*queue_ops[DATA_INPUT], n,
+					ldpc_llr_size, ldpc_llr_decimals);
+		if (!loopback && !harq_comp)
+			ldpc_input_llr_scaling(*queue_ops[DATA_HARQ_INPUT], n,
+					ldpc_llr_size, ldpc_llr_decimals);
+		if (!loopback)
+			ldpc_add_filler(*queue_ops[DATA_HARQ_INPUT], n,
+					op_params);
 	}
 
 	return 0;
@@ -1165,17 +1243,21 @@ typedef int (test_case_function)(struct active_device *ad,
 		ops[i]->ldpc_dec.op_flags = ldpc_dec->op_flags;
 		ops[i]->ldpc_dec.code_block_mode = ldpc_dec->code_block_mode;
 
-		ops[i]->ldpc_dec.hard_output = hard_outputs[start_idx + i];
-		ops[i]->ldpc_dec.input = inputs[start_idx + i];
+		if (hard_outputs != NULL)
+			ops[i]->ldpc_dec.hard_output =
+					hard_outputs[start_idx + i];
+		if (inputs != NULL)
+			ops[i]->ldpc_dec.input =
+					inputs[start_idx + i];
 		if (soft_outputs != NULL)
 			ops[i]->ldpc_dec.soft_output =
-				soft_outputs[start_idx + i];
+					soft_outputs[start_idx + i];
 		if (harq_inputs != NULL)
 			ops[i]->ldpc_dec.harq_combined_input =
 					harq_inputs[start_idx + i];
 		if (harq_outputs != NULL)
 			ops[i]->ldpc_dec.harq_combined_output =
-				harq_outputs[start_idx + i];
+					harq_outputs[start_idx + i];
 	}
 }
 
@@ -1217,7 +1299,22 @@ typedef int (test_case_function)(struct active_device *ad,
 check_dec_status_and_ordering(struct rte_bbdev_dec_op *op,
 		unsigned int order_idx, const int expected_status)
 {
-	TEST_ASSERT(op->status == expected_status,
+	int status = op->status;
+	/* ignore parity mismatch false alarms for long iterations */
+	{
+		if (!(expected_status & (1 << RTE_BBDEV_SYNDROME_ERROR)) &&
+				(status & (1 << RTE_BBDEV_SYNDROME_ERROR))) {
+			printf("WARNING: Ignore Syndrome Check mismatch\n");
+			status -= (1 << RTE_BBDEV_SYNDROME_ERROR);
+		}
+		if ((expected_status & (1 << RTE_BBDEV_SYNDROME_ERROR)) &&
+				!(status & (1 << RTE_BBDEV_SYNDROME_ERROR))) {
+			printf("WARNING: Ignore Syndrome Check mismatch\n");
+			status += (1 << RTE_BBDEV_SYNDROME_ERROR);
+		}
+	}
+
+	TEST_ASSERT(status == expected_status,
 			"op_status (%d) != expected_status (%d)",
 			op->status, expected_status);
 
@@ -1236,9 +1333,10 @@ typedef int (test_case_function)(struct active_device *ad,
 			"op_status (%d) != expected_status (%d)",
 			op->status, expected_status);
 
-	TEST_ASSERT((void *)(uintptr_t)order_idx == op->opaque_data,
-			"Ordering error, expected %p, got %p",
-			(void *)(uintptr_t)order_idx, op->opaque_data);
+	if (op->opaque_data != (void *)(uintptr_t)INVALID_OPAQUE)
+		TEST_ASSERT((void *)(uintptr_t)order_idx == op->opaque_data,
+				"Ordering error, expected %p, got %p",
+				(void *)(uintptr_t)order_idx, op->opaque_data);
 
 	return TEST_SUCCESS;
 }
@@ -1282,6 +1380,170 @@ typedef int (test_case_function)(struct active_device *ad,
 	return TEST_SUCCESS;
 }
 
+
+/* Compute K0 for a given configuration for HARQ output length computation */
+static inline uint16_t
+get_k0(uint16_t n_cb, uint16_t z_c, uint8_t basegraph, uint8_t rv_index)
+{
+	if (rv_index == 0)
+		return 0;
+	uint16_t n = (basegraph == 1 ? 66 : 50) * z_c;
+	if (n_cb == n) {
+		if (rv_index == 1)
+			return (basegraph == 1 ? 17 : 13) * z_c;
+		else if (rv_index == 2)
+			return (basegraph == 1 ? 33 : 25) * z_c;
+		else
+			return (basegraph == 1 ? 56 : 43) * z_c;
+	}
+	/* LBRM case - includes a division by N */
+	if (rv_index == 1)
+		return (((basegraph == 1 ? 17 : 13) * n_cb)
+				/ n) * z_c;
+	else if (rv_index == 2)
+		return (((basegraph == 1 ? 33 : 25) * n_cb)
+				/ n) * z_c;
+	else
+		return (((basegraph == 1 ? 56 : 43) * n_cb)
+				/ n) * z_c;
+}
+
+/* HARQ output length including the Filler bits */
+static inline uint16_t
+compute_Harq_Len(struct rte_bbdev_op_ldpc_dec *ops_ld) {
+	uint16_t k0 = 0;
+	uint8_t max_rv = (ops_ld->rv_index == 1) ? 3 : ops_ld->rv_index;
+	k0 = get_k0(ops_ld->n_cb, ops_ld->z_c, ops_ld->basegraph, max_rv);
+	/* Compute RM out size and number of rows */
+	uint16_t parity_offset = (ops_ld->basegraph == 1 ? 20 : 8)
+			* ops_ld->z_c - ops_ld->n_filler;
+	uint16_t deRmOutSize = RTE_MIN(
+			k0 + ops_ld->cb_params.e +
+			((k0 > parity_offset) ?
+					0 : ops_ld->n_filler),
+					ops_ld->n_cb);
+	uint16_t numRows = ((deRmOutSize + ops_ld->z_c - 1)
+			/ ops_ld->z_c);
+	uint16_t harq_output_len = numRows * ops_ld->z_c;
+	return harq_output_len;
+}
+
+static inline int
+validate_op_harq_chain(struct rte_bbdev_op_data *op,
+		struct op_data_entries *orig_op,
+		struct rte_bbdev_op_ldpc_dec *ops_ld)
+{
+	uint8_t i;
+	uint32_t j, jj, k;
+	struct rte_mbuf *m = op->data;
+	uint8_t nb_dst_segments = orig_op->nb_segments;
+	uint32_t total_data_size = 0;
+	int8_t *harq_orig, *harq_out, abs_harq_origin;
+	uint32_t byte_error = 0, cum_error = 0, error;
+	int16_t llr_max = (1 << (ldpc_llr_size - ldpc_llr_decimals)) - 1;
+	int16_t llr_max_pre_scaling = (1 << (ldpc_llr_size - 1)) - 1;
+	uint16_t parity_offset;
+
+	TEST_ASSERT(nb_dst_segments == m->nb_segs,
+			"Number of segments differ in original (%u) and filled (%u) op",
+			nb_dst_segments, m->nb_segs);
+
+	/* Validate each mbuf segment length */
+	for (i = 0; i < nb_dst_segments; ++i) {
+		/* Apply offset to the first mbuf segment */
+		uint16_t offset = (i == 0) ? op->offset : 0;
+		uint16_t data_len = rte_pktmbuf_data_len(m) - offset;
+		total_data_size += orig_op->segments[i].length;
+
+		TEST_ASSERT(orig_op->segments[i].length <
+				(uint32_t)(data_len + 64),
+				"Length of segment differ in original (%u) and filled (%u) op",
+				orig_op->segments[i].length, data_len);
+		harq_orig = (int8_t *) orig_op->segments[i].addr;
+		harq_out = rte_pktmbuf_mtod_offset(m, int8_t *, offset);
+
+		if (!(ldpc_cap_flags &
+				RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_FILLERS
+				) || (ops_ld->op_flags &
+				RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK)) {
+			data_len -= ops_ld->z_c;
+			parity_offset = data_len;
+		} else {
+			/* Compute RM out size and number of rows */
+			parity_offset = (ops_ld->basegraph == 1 ? 20 : 8)
+					* ops_ld->z_c - ops_ld->n_filler;
+			uint16_t deRmOutSize = compute_Harq_Len(ops_ld) -
+					ops_ld->n_filler;
+			if (data_len > deRmOutSize)
+				data_len = deRmOutSize;
+			if (data_len > orig_op->segments[i].length)
+				data_len = orig_op->segments[i].length;
+		}
+		/*
+		 * HARQ output can have minor differences
+		 * due to integer representation and related scaling
+		 */
+		for (j = 0, jj = 0; j < data_len; j++, jj++) {
+			if (j == parity_offset) {
+				/* Special Handling of the filler bits */
+				for (k = 0; k < ops_ld->n_filler; k++) {
+					if (harq_out[jj] !=
+							llr_max_pre_scaling) {
+						printf("HARQ Filler issue %d: %d %d\n",
+							jj, harq_out[jj],
+							llr_max);
+						byte_error++;
+					}
+					jj++;
+				}
+			}
+			if (!(ops_ld->op_flags &
+				RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK)) {
+				if (ldpc_llr_decimals > 1)
+					harq_out[jj] = (harq_out[jj] + 1)
+						>> (ldpc_llr_decimals - 1);
+				/* Saturated to S7 */
+				if (harq_orig[j] > llr_max)
+					harq_orig[j] = llr_max;
+				if (harq_orig[j] < -llr_max)
+					harq_orig[j] = -llr_max;
+			}
+			if (harq_orig[j] != harq_out[jj]) {
+				error = (harq_orig[j] > harq_out[jj]) ?
+						harq_orig[j] - harq_out[jj] :
+						harq_out[jj] - harq_orig[j];
+				abs_harq_origin = harq_orig[j] > 0 ?
+							harq_orig[j] :
+							-harq_orig[j];
+				/* Residual quantization error */
+				if ((error > 8 && (abs_harq_origin <
+						(llr_max - 16))) ||
+						(error > 16)) {
+					printf("HARQ mismatch %d: exp %d act %d => %d\n",
+							j, harq_orig[j],
+							harq_out[jj], error);
+					byte_error++;
+					cum_error += error;
+				}
+			}
+		}
+		m = m->next;
+	}
+
+	if (byte_error)
+		TEST_ASSERT(byte_error <= 1,
+				"HARQ output mismatch (%d) %d",
+				byte_error, cum_error);
+
+	/* Validate total mbuf pkt length */
+	uint32_t pkt_len = rte_pktmbuf_pkt_len(op->data) - op->offset;
+	TEST_ASSERT(total_data_size < pkt_len + 64,
+			"Length of data differ in original (%u) and filled (%u) op",
+			total_data_size, pkt_len);
+
+	return TEST_SUCCESS;
+}
+
 static int
 validate_dec_op(struct rte_bbdev_dec_op **ops, const uint16_t n,
 		struct rte_bbdev_dec_op *ref_op, const int vector_mask)
@@ -1325,7 +1587,6 @@ typedef int (test_case_function)(struct active_device *ad,
 	return TEST_SUCCESS;
 }
 
-
 static int
 validate_ldpc_dec_op(struct rte_bbdev_dec_op **ops, const uint16_t n,
 		struct rte_bbdev_dec_op *ref_op, const int vector_mask)
@@ -1357,8 +1618,15 @@ typedef int (test_case_function)(struct active_device *ad,
 			TEST_ASSERT(ops_td->iter_count <= ref_td->iter_count,
 					"Returned iter_count (%d) > expected iter_count (%d)",
 					ops_td->iter_count, ref_td->iter_count);
-		/* We can ignore data when the decoding failed to converge */
-		if ((ops[i]->status &  (1 << RTE_BBDEV_SYNDROME_ERROR)) == 0)
+		/*
+		 * We can ignore output data when the decoding failed to
+		 * converge or for loop-back cases
+		 */
+		if (!check_bit(ops[i]->ldpc_dec.op_flags,
+				RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK
+				) && (
+				ops[i]->status & (1 << RTE_BBDEV_SYNDROME_ERROR
+						)) == 0)
 			TEST_ASSERT_SUCCESS(validate_op_chain(hard_output,
 					hard_data_orig),
 					"Hard output buffers (CB=%u) are not equal",
@@ -1371,12 +1639,18 @@ typedef int (test_case_function)(struct active_device *ad,
 					i);
 		if (ref_op->ldpc_dec.op_flags &
 				RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE) {
-			ldpc_input_llr_scaling(harq_output, 1, 8, 0);
-			TEST_ASSERT_SUCCESS(validate_op_chain(harq_output,
-					harq_data_orig),
+			TEST_ASSERT_SUCCESS(validate_op_harq_chain(harq_output,
+					harq_data_orig, ops_td),
 					"HARQ output buffers (CB=%u) are not equal",
 					i);
 		}
+		if (ref_op->ldpc_dec.op_flags &
+				RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK)
+			TEST_ASSERT_SUCCESS(validate_op_harq_chain(harq_output,
+					harq_data_orig, ops_td),
+					"HARQ output buffers (CB=%u) are not equal",
+					i);
+
 	}
 
 	return TEST_SUCCESS;
@@ -1715,6 +1989,105 @@ typedef int (test_case_function)(struct active_device *ad,
 	return ret;
 }
 
+
+/* Push back the HARQ output from DDR to host */
+static void
+retrieve_harq_ddr(uint16_t dev_id, uint16_t queue_id,
+		struct rte_bbdev_dec_op **ops,
+		const uint16_t n)
+{
+	uint16_t j;
+	int save_status, ret;
+	uint32_t harq_offset = (uint32_t) queue_id * HARQ_INCR * 1024;
+	struct rte_bbdev_dec_op *ops_deq[MAX_BURST];
+	uint32_t flags = ops[0]->ldpc_dec.op_flags;
+	bool loopback = flags & RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK;
+	bool mem_out = flags & RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_OUT_ENABLE;
+	bool hc_out = flags & RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE;
+	bool h_comp = flags & RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION;
+	for (j = 0; j < n; ++j) {
+		if ((loopback && mem_out) || hc_out) {
+			save_status = ops[j]->status;
+			ops[j]->ldpc_dec.op_flags =
+				RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK +
+				RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_IN_ENABLE;
+			if (h_comp)
+				ops[j]->ldpc_dec.op_flags +=
+					RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION;
+			ops[j]->ldpc_dec.harq_combined_input.offset =
+					harq_offset;
+			ops[j]->ldpc_dec.harq_combined_output.offset = 0;
+			harq_offset += HARQ_INCR;
+			if (!loopback)
+				ops[j]->ldpc_dec.harq_combined_input.length =
+				ops[j]->ldpc_dec.harq_combined_output.length;
+			rte_bbdev_enqueue_ldpc_dec_ops(dev_id, queue_id,
+					&ops[j], 1);
+			ret = 0;
+			while (ret == 0)
+				ret = rte_bbdev_dequeue_ldpc_dec_ops(
+						dev_id, queue_id,
+						&ops_deq[j], 1);
+			ops[j]->ldpc_dec.op_flags = flags;
+			ops[j]->status = save_status;
+		}
+	}
+}
+
+/*
+ * Push back the HARQ output from HW DDR to Host
+ * Preload HARQ memory input and adjust HARQ offset
+ */
+static void
+preload_harq_ddr(uint16_t dev_id, uint16_t queue_id,
+		struct rte_bbdev_dec_op **ops, const uint16_t n,
+		bool preload)
+{
+	uint16_t j;
+	int ret;
+	uint32_t harq_offset = (uint32_t) queue_id * HARQ_INCR * 1024;
+	struct rte_bbdev_op_data save_hc_in, save_hc_out;
+	struct rte_bbdev_dec_op *ops_deq[MAX_BURST];
+	uint32_t flags = ops[0]->ldpc_dec.op_flags;
+	bool mem_in = flags & RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_IN_ENABLE;
+	bool hc_in = flags & RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE;
+	bool mem_out = flags & RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_OUT_ENABLE;
+	bool hc_out = flags & RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE;
+	bool h_comp = flags & RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION;
+	for (j = 0; j < n; ++j) {
+		if ((mem_in || hc_in) && preload) {
+			save_hc_in = ops[j]->ldpc_dec.harq_combined_input;
+			save_hc_out = ops[j]->ldpc_dec.harq_combined_output;
+			ops[j]->ldpc_dec.op_flags =
+				RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK +
+				RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_OUT_ENABLE;
+			if (h_comp)
+				ops[j]->ldpc_dec.op_flags +=
+					RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION;
+			ops[j]->ldpc_dec.harq_combined_output.offset =
+					harq_offset;
+			ops[j]->ldpc_dec.harq_combined_input.offset = 0;
+			rte_bbdev_enqueue_ldpc_dec_ops(dev_id, queue_id,
+					&ops[j], 1);
+			ret = 0;
+			while (ret == 0)
+				ret = rte_bbdev_dequeue_ldpc_dec_ops(
+					dev_id, queue_id, &ops_deq[j], 1);
+			ops[j]->ldpc_dec.op_flags = flags;
+			ops[j]->ldpc_dec.harq_combined_input = save_hc_in;
+			ops[j]->ldpc_dec.harq_combined_output = save_hc_out;
+		}
+		/* Adjust HARQ offset when we reach external DDR */
+		if (mem_in || hc_in)
+			ops[j]->ldpc_dec.harq_combined_input.offset
+				= harq_offset;
+		if (mem_out || hc_out)
+			ops[j]->ldpc_dec.harq_combined_output.offset
+				= harq_offset;
+		harq_offset += HARQ_INCR;
+	}
+}
+
 static void
 dequeue_event_callback(uint16_t dev_id,
 		enum rte_bbdev_event_type event, void *cb_arg,
@@ -1750,13 +2123,22 @@ typedef int (test_case_function)(struct active_device *ad,
 	burst_sz = rte_atomic16_read(&tp->burst_sz);
 	num_ops = tp->op_params->num_to_process;
 
-	if (test_vector.op_type == RTE_BBDEV_OP_TURBO_DEC ||
-			test_vector.op_type == RTE_BBDEV_OP_LDPC_DEC)
+	if (test_vector.op_type == RTE_BBDEV_OP_TURBO_DEC)
 		deq = rte_bbdev_dequeue_dec_ops(dev_id, queue_id,
 				&tp->dec_ops[
 					rte_atomic16_read(&tp->nb_dequeued)],
 				burst_sz);
-	else
+	else if (test_vector.op_type == RTE_BBDEV_OP_LDPC_DEC)
+		deq = rte_bbdev_dequeue_ldpc_dec_ops(dev_id, queue_id,
+				&tp->dec_ops[
+					rte_atomic16_read(&tp->nb_dequeued)],
+				burst_sz);
+	else if (test_vector.op_type == RTE_BBDEV_OP_LDPC_ENC)
+		deq = rte_bbdev_dequeue_ldpc_enc_ops(dev_id, queue_id,
+				&tp->enc_ops[
+					rte_atomic16_read(&tp->nb_dequeued)],
+				burst_sz);
+	else /*RTE_BBDEV_OP_TURBO_ENC*/
 		deq = rte_bbdev_dequeue_enc_ops(dev_id, queue_id,
 				&tp->enc_ops[
 					rte_atomic16_read(&tp->nb_dequeued)],
@@ -2133,6 +2515,12 @@ typedef int (test_case_function)(struct active_device *ad,
 	int i, j, ret;
 	struct rte_bbdev_info info;
 	uint16_t num_to_enq;
+	bool extDdr = check_bit(ldpc_cap_flags,
+			RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_OUT_ENABLE);
+	bool loopback = check_bit(ref_op->ldpc_dec.op_flags,
+			RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK);
+	bool hc_out = check_bit(ref_op->ldpc_dec.op_flags,
+			RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE);
 
 	TEST_ASSERT_SUCCESS((burst_sz > MAX_BURST),
 			"BURST_SIZE should be <= %u", MAX_BURST);
@@ -2170,13 +2558,18 @@ typedef int (test_case_function)(struct active_device *ad,
 
 	for (i = 0; i < TEST_REPETITIONS; ++i) {
 		for (j = 0; j < num_ops; ++j) {
-			mbuf_reset(ops_enq[j]->ldpc_dec.hard_output.data);
-			if (check_bit(ref_op->ldpc_dec.op_flags,
-					RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE))
+			if (!loopback)
+				mbuf_reset(
+				ops_enq[j]->ldpc_dec.hard_output.data);
+			if (hc_out || loopback)
 				mbuf_reset(
 				ops_enq[j]->ldpc_dec.harq_combined_output.data);
 		}
-
+		if (extDdr) {
+			bool preload = i == (TEST_REPETITIONS - 1);
+			preload_harq_ddr(tp->dev_id, queue_id, ops_enq,
+					num_ops, preload);
+		}
 		start_time = rte_rdtsc_precise();
 
 		for (enq = 0, deq = 0; enq < num_ops;) {
@@ -2207,6 +2600,10 @@ typedef int (test_case_function)(struct active_device *ad,
 		tp->iter_count = RTE_MAX(ops_enq[i]->ldpc_dec.iter_count,
 				tp->iter_count);
 	}
+	if (extDdr) {
+		/* Read loopback is not thread safe */
+		retrieve_harq_ddr(tp->dev_id, queue_id, ops_enq, num_ops);
+	}
 
 	if (test_vector.op_type != RTE_BBDEV_OP_NONE) {
 		ret = validate_ldpc_dec_op(ops_deq, num_ops, ref_op,
@@ -2696,6 +3093,8 @@ typedef int (test_case_function)(struct active_device *ad,
 	uint16_t i, j, dequeued;
 	struct rte_bbdev_dec_op *ops_enq[MAX_BURST], *ops_deq[MAX_BURST];
 	uint64_t start_time = 0, last_time = 0;
+	bool extDdr = ldpc_cap_flags &
+			RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_OUT_ENABLE;
 
 	for (i = 0, dequeued = 0; dequeued < num_to_process; ++i) {
 		uint16_t enq = 0, deq = 0;
@@ -2708,6 +3107,15 @@ typedef int (test_case_function)(struct active_device *ad,
 		ret = rte_bbdev_dec_op_alloc_bulk(mempool, ops_enq, burst_sz);
 		TEST_ASSERT_SUCCESS(ret,
 				"rte_bbdev_dec_op_alloc_bulk() failed");
+
+		/* For latency tests we need to disable early termination */
+		if (check_bit(ref_op->ldpc_dec.op_flags,
+				RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE))
+			ref_op->ldpc_dec.op_flags -=
+					RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE;
+		ref_op->ldpc_dec.iter_max = 6;
+		ref_op->ldpc_dec.iter_count = ref_op->ldpc_dec.iter_max;
+
 		if (test_vector.op_type != RTE_BBDEV_OP_NONE)
 			copy_reference_ldpc_dec_op(ops_enq, burst_sz, dequeued,
 					bufs->inputs,
@@ -2717,6 +3125,10 @@ typedef int (test_case_function)(struct active_device *ad,
 					bufs->harq_outputs,
 					ref_op);
 
+		if (extDdr)
+			preload_harq_ddr(dev_id, queue_id, ops_enq,
+					burst_sz, true);
+
 		/* Set counter to validate the ordering */
 		for (j = 0; j < burst_sz; ++j)
 			ops_enq[j]->opaque_data = (void *)(uintptr_t)j;
@@ -2743,6 +3155,9 @@ typedef int (test_case_function)(struct active_device *ad,
 		*min_time = RTE_MIN(*min_time, last_time);
 		*total_time += last_time;
 
+		if (extDdr)
+			retrieve_harq_ddr(dev_id, queue_id, ops_enq, burst_sz);
+
 		if (test_vector.op_type != RTE_BBDEV_OP_NONE) {
 			ret = validate_ldpc_dec_op(ops_deq, burst_sz, ref_op,
 					vector_mask);
@@ -2752,7 +3167,6 @@ typedef int (test_case_function)(struct active_device *ad,
 		rte_bbdev_dec_op_free_bulk(ops_enq, deq);
 		dequeued += deq;
 	}
-
 	return i;
 }
 
@@ -2844,7 +3258,6 @@ typedef int (test_case_function)(struct active_device *ad,
 			burst_sz = num_to_process - dequeued;
 
 		ret = rte_bbdev_enc_op_alloc_bulk(mempool, ops_enq, burst_sz);
-
 		TEST_ASSERT_SUCCESS(ret,
 				"rte_bbdev_enc_op_alloc_bulk() failed");
 		if (test_vector.op_type != RTE_BBDEV_OP_NONE)
@@ -3081,6 +3494,8 @@ typedef int (test_case_function)(struct active_device *ad,
 	uint64_t enq_start_time, deq_start_time;
 	uint64_t enq_sw_last_time, deq_last_time;
 	struct rte_bbdev_stats stats;
+	bool extDdr = ldpc_cap_flags &
+			RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_OUT_ENABLE;
 
 	for (i = 0, dequeued = 0; dequeued < num_to_process; ++i) {
 		uint16_t enq = 0, deq = 0;
@@ -3098,6 +3513,10 @@ typedef int (test_case_function)(struct active_device *ad,
 					bufs->harq_outputs,
 					ref_op);
 
+		if (extDdr)
+			preload_harq_ddr(dev_id, queue_id, ops_enq,
+					burst_sz, true);
+
 		/* Start time meas for enqueue function offload latency */
 		enq_start_time = rte_rdtsc_precise();
 		do {
@@ -3105,13 +3524,13 @@ typedef int (test_case_function)(struct active_device *ad,
 					&ops_enq[enq], burst_sz - enq);
 		} while (unlikely(burst_sz != enq));
 
+		enq_sw_last_time = rte_rdtsc_precise() - enq_start_time;
 		ret = get_bbdev_queue_stats(dev_id, queue_id, &stats);
 		TEST_ASSERT_SUCCESS(ret,
 				"Failed to get stats for queue (%u) of device (%u)",
 				queue_id, dev_id);
 
-		enq_sw_last_time = rte_rdtsc_precise() - enq_start_time -
-				stats.acc_offload_cycles;
+		enq_sw_last_time -= stats.acc_offload_cycles;
 		time_st->enq_sw_max_time = RTE_MAX(time_st->enq_sw_max_time,
 				enq_sw_last_time);
 		time_st->enq_sw_min_time = RTE_MIN(time_st->enq_sw_min_time,
@@ -3144,9 +3563,14 @@ typedef int (test_case_function)(struct active_device *ad,
 
 		/* Dequeue remaining operations if needed*/
 		while (burst_sz != deq)
-			deq += rte_bbdev_dequeue_dec_ops(dev_id, queue_id,
+			deq += rte_bbdev_dequeue_ldpc_dec_ops(dev_id, queue_id,
 					&ops_deq[deq], burst_sz - deq);
 
+		if (extDdr) {
+			/* Read loopback is not thread safe */
+			retrieve_harq_ddr(dev_id, queue_id, ops_enq, burst_sz);
+		}
+
 		rte_bbdev_dec_op_free_bulk(ops_enq, deq);
 		dequeued += deq;
 	}
@@ -3173,7 +3597,8 @@ typedef int (test_case_function)(struct active_device *ad,
 			burst_sz = num_to_process - dequeued;
 
 		ret = rte_bbdev_enc_op_alloc_bulk(mempool, ops_enq, burst_sz);
-		TEST_ASSERT_SUCCESS(ret, "rte_bbdev_op_alloc_bulk() failed");
+		TEST_ASSERT_SUCCESS(ret,
+				"rte_bbdev_enc_op_alloc_bulk() failed");
 		if (test_vector.op_type != RTE_BBDEV_OP_NONE)
 			copy_reference_enc_op(ops_enq, burst_sz, dequeued,
 					bufs->inputs,
@@ -3187,13 +3612,13 @@ typedef int (test_case_function)(struct active_device *ad,
 					&ops_enq[enq], burst_sz - enq);
 		} while (unlikely(burst_sz != enq));
 
+		enq_sw_last_time = rte_rdtsc_precise() - enq_start_time;
+
 		ret = get_bbdev_queue_stats(dev_id, queue_id, &stats);
 		TEST_ASSERT_SUCCESS(ret,
 				"Failed to get stats for queue (%u) of device (%u)",
 				queue_id, dev_id);
-
-		enq_sw_last_time = rte_rdtsc_precise() - enq_start_time -
-				stats.acc_offload_cycles;
+		enq_sw_last_time -= stats.acc_offload_cycles;
 		time_st->enq_sw_max_time = RTE_MAX(time_st->enq_sw_max_time,
 				enq_sw_last_time);
 		time_st->enq_sw_min_time = RTE_MIN(time_st->enq_sw_min_time,
@@ -3255,7 +3680,8 @@ typedef int (test_case_function)(struct active_device *ad,
 			burst_sz = num_to_process - dequeued;
 
 		ret = rte_bbdev_enc_op_alloc_bulk(mempool, ops_enq, burst_sz);
-		TEST_ASSERT_SUCCESS(ret, "rte_bbdev_op_alloc_bulk() failed");
+		TEST_ASSERT_SUCCESS(ret,
+				"rte_bbdev_enc_op_alloc_bulk() failed");
 		if (test_vector.op_type != RTE_BBDEV_OP_NONE)
 			copy_reference_ldpc_enc_op(ops_enq, burst_sz, dequeued,
 					bufs->inputs,
@@ -3269,13 +3695,13 @@ typedef int (test_case_function)(struct active_device *ad,
 					&ops_enq[enq], burst_sz - enq);
 		} while (unlikely(burst_sz != enq));
 
+		enq_sw_last_time = rte_rdtsc_precise() - enq_start_time;
 		ret = get_bbdev_queue_stats(dev_id, queue_id, &stats);
 		TEST_ASSERT_SUCCESS(ret,
 				"Failed to get stats for queue (%u) of device (%u)",
 				queue_id, dev_id);
 
-		enq_sw_last_time = rte_rdtsc_precise() - enq_start_time -
-				stats.acc_offload_cycles;
+		enq_sw_last_time -= stats.acc_offload_cycles;
 		time_st->enq_sw_max_time = RTE_MAX(time_st->enq_sw_max_time,
 				enq_sw_last_time);
 		time_st->enq_sw_min_time = RTE_MIN(time_st->enq_sw_min_time,
diff --git a/app/test-bbdev/test_bbdev_vector.c b/app/test-bbdev/test_bbdev_vector.c
index 77356cb..50d1da0 100644
--- a/app/test-bbdev/test_bbdev_vector.c
+++ b/app/test-bbdev/test_bbdev_vector.c
@@ -197,6 +197,9 @@
 	else if (!strcmp(token,
 			"RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_OUT_ENABLE"))
 		*op_flag_value = RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_OUT_ENABLE;
+	else if (!strcmp(token,
+			"RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK"))
+		*op_flag_value = RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK;
 	else {
 		printf("The given value is not a LDPC decoder flag\n");
 		return -1;
@@ -943,16 +946,10 @@
 	unsigned char i;
 	struct rte_bbdev_op_ldpc_dec *ldpc_dec = &vector->ldpc_dec;
 
-	if (vector->entries[DATA_INPUT].nb_segments == 0)
-		return -1;
-
 	for (i = 0; i < vector->entries[DATA_INPUT].nb_segments; i++)
 		if (vector->entries[DATA_INPUT].segments[i].addr == NULL)
 			return -1;
 
-	if (vector->entries[DATA_HARD_OUTPUT].nb_segments == 0)
-		return -1;
-
 	for (i = 0; i < vector->entries[DATA_HARD_OUTPUT].nb_segments; i++)
 		if (vector->entries[DATA_HARD_OUTPUT].segments[i].addr == NULL)
 			return -1;
-- 
1.8.3.1


^ permalink raw reply	[flat|nested] 115+ messages in thread

* [dpdk-dev] [PATCH v1 07/14] test-bbdev: support for performance tests
  2020-02-27  4:38 [dpdk-dev] [PATCH v1 00/14] bbdev new features Nicolas Chautru
                   ` (5 preceding siblings ...)
  2020-02-27  4:39 ` [dpdk-dev] [PATCH v1 06/14] test-bbdev: support HARQ validation Nicolas Chautru
@ 2020-02-27  4:39 ` Nicolas Chautru
  2020-02-27  4:39 ` [dpdk-dev] [PATCH v1 08/14] test-bbdev: support for LDPC interrupt test Nicolas Chautru
                   ` (7 subsequent siblings)
  14 siblings, 0 replies; 115+ messages in thread
From: Nicolas Chautru @ 2020-02-27  4:39 UTC (permalink / raw)
  To: thomas, akhil.goyal, dev; +Cc: ferruh.yigit, Nic Chautru

From: Nic Chautru <nicolas.chautru@intel.com>

Includes support for BLER wireless performance test with
new arguments for SNR and number of iterations for 5G.

Signed-off-by: Nic Chautru <nicolas.chautru@intel.com>
---
 app/test-bbdev/main.c            |  29 ++-
 app/test-bbdev/main.h            |   9 +-
 app/test-bbdev/test_bbdev_perf.c | 523 ++++++++++++++++++++++++++++++++++++++-
 3 files changed, 548 insertions(+), 13 deletions(-)

diff --git a/app/test-bbdev/main.c b/app/test-bbdev/main.c
index 8a42115..ff65173 100644
--- a/app/test-bbdev/main.c
+++ b/app/test-bbdev/main.c
@@ -29,6 +29,8 @@
 	unsigned int num_ops;
 	unsigned int burst_sz;
 	unsigned int num_lcores;
+	double snr;
+	unsigned int iter_max;
 	char test_vector_filename[PATH_MAX];
 	bool init_device;
 } test_params;
@@ -140,6 +142,18 @@
 	return test_params.num_lcores;
 }
 
+double
+get_snr(void)
+{
+	return test_params.snr;
+}
+
+unsigned int
+get_iter_max(void)
+{
+	return test_params.iter_max;
+}
+
 bool
 get_init_device(void)
 {
@@ -180,12 +194,15 @@
 		{ "test-cases", 1, 0, 'c' },
 		{ "test-vector", 1, 0, 'v' },
 		{ "lcores", 1, 0, 'l' },
+		{ "snr", 1, 0, 's' },
+		{ "iter_max", 6, 0, 't' },
 		{ "init-device", 0, 0, 'i'},
 		{ "help", 0, 0, 'h' },
 		{ NULL,  0, 0, 0 }
 	};
+	tp->iter_max = DEFAULT_ITER;
 
-	while ((opt = getopt_long(argc, argv, "hin:b:c:v:l:", lgopts,
+	while ((opt = getopt_long(argc, argv, "hin:b:c:v:l:s:t:", lgopts,
 			&option_index)) != EOF)
 		switch (opt) {
 		case 'n':
@@ -237,6 +254,16 @@
 					sizeof(tp->test_vector_filename),
 					"%s", optarg);
 			break;
+		case 's':
+			TEST_ASSERT(strlen(optarg) > 0,
+					"SNR is not provided");
+			tp->snr = strtod(optarg, NULL);
+			break;
+		case 't':
+			TEST_ASSERT(strlen(optarg) > 0,
+					"Iter_max is not provided");
+			tp->iter_max = strtol(optarg, NULL, 10);
+			break;
 		case 'l':
 			TEST_ASSERT(strlen(optarg) > 0,
 					"Num of lcores is not provided");
diff --git a/app/test-bbdev/main.h b/app/test-bbdev/main.h
index 23b4d58..fb3dec8 100644
--- a/app/test-bbdev/main.h
+++ b/app/test-bbdev/main.h
@@ -19,6 +19,8 @@
 #define MAX_BURST 512U
 #define DEFAULT_BURST 32U
 #define DEFAULT_OPS 64U
+#define DEFAULT_ITER 6U
+
 
 
 #define TEST_ASSERT(cond, msg, ...) do {  \
@@ -104,8 +106,7 @@ struct test_command {
 		.command = RTE_STR(name), \
 		.callback = test_func_##name, \
 	}; \
-	static void __attribute__((constructor, used)) \
-	test_register_##name(void) \
+	RTE_INIT(test_register_##name) \
 	{ \
 		add_test_command(&test_struct_##name); \
 	}
@@ -118,6 +119,10 @@ struct test_command {
 
 unsigned int get_num_lcores(void);
 
+double get_snr(void);
+
+unsigned int get_iter_max(void);
+
 bool get_init_device(void);
 
 #endif
diff --git a/app/test-bbdev/test_bbdev_perf.c b/app/test-bbdev/test_bbdev_perf.c
index 978ccd6..7bc824b 100644
--- a/app/test-bbdev/test_bbdev_perf.c
+++ b/app/test-bbdev/test_bbdev_perf.c
@@ -111,6 +111,8 @@ struct thread_params {
 	double ops_per_sec;
 	double mbps;
 	uint8_t iter_count;
+	double iter_average;
+	double bler;
 	rte_atomic16_t nb_dequeued;
 	rte_atomic16_t processing_status;
 	rte_atomic16_t burst_sz;
@@ -1204,6 +1206,213 @@ typedef int (test_case_function)(struct active_device *ad,
 	}
 }
 
+
+/* Returns a random number drawn from a normal distribution
+ * with mean of 0 and variance of 1
+ * Marsaglia algorithm
+ */
+static double
+randn(int n)
+{
+	double S, Z, U1, U2, u, v, fac;
+
+	do {
+		U1 = (double)rand() / RAND_MAX;
+		U2 = (double)rand() / RAND_MAX;
+		u = 2. * U1 - 1.;
+		v = 2. * U2 - 1.;
+		S = u * u + v * v;
+	} while (S >= 1 || S == 0);
+	fac = sqrt(-2. * log(S) / S);
+	Z = (n % 2) ? u * fac : v * fac;
+	return Z;
+}
+
+static inline double
+maxstar(double A, double B)
+{
+	if (fabs(A - B) > 5)
+		return fmax(A, B);
+	else
+		return fmax(A, B) + log1p(exp(-fabs(A - B)));
+}
+
+
+/*
+ * Generate Qm LLRS for Qm==6
+ * Modulation, AWGN and LLR estimation from max log development
+ */
+static void
+gen_qm6_llr(int8_t *llrs, uint32_t i, double N0, double llr_max)
+{
+	int qm = 6;
+	int qam = 64;
+	int m, k;
+	double I, Q, p0, p1, llr_, b[qm], log_syml_prob[qam];
+	/* 5.1.4 of TS38.211 */
+	const double symbols_I[64] = {
+			3, 3, 1, 1, 3, 3, 1, 1, 5, 5, 7, 7, 5, 5, 7, 7,
+			3, 3, 1, 1, 3, 3, 1, 1, 5, 5, 7, 7, 5, 5, 7, 7,
+			-3, -3, -1, -1, -3, -3, -1, -1, -5, -5, -7, -7,
+			-5, -5, -7, -7, -3, -3, -1, -1, -3, -3, -1, -1,
+			-5, -5, -7, -7, -5, -5, -7, -7};
+	const double symbols_Q[64] = {
+			3, 1, 3, 1, 5, 7, 5, 7, 3, 1, 3, 1, 5, 7, 5, 7,
+			-3, -1, -3, -1, -5, -7, -5, -7, -3, -1, -3, -1,
+			-5, -7, -5, -7, 3, 1, 3, 1, 5, 7, 5, 7, 3, 1, 3, 1,
+			5, 7, 5, 7, -3, -1, -3, -1, -5, -7, -5, -7,
+			-3, -1, -3, -1, -5, -7, -5, -7};
+	/* Average constellation point energy */
+	N0 *= 42.0;
+	for (k = 0; k < qm; k++)
+		b[k] = llrs[qm * i + k] < 0 ? 1.0 : 0.0;
+	/* 5.1.4 of TS38.211 */
+	I = (1 - 2 * b[0])*(4 - (1 - 2 * b[2]) * (2 - (1 - 2 * b[4])));
+	Q = (1 - 2 * b[1])*(4 - (1 - 2 * b[3]) * (2 - (1 - 2 * b[5])));
+	/* AWGN channel */
+	I += sqrt(N0 / 2) * randn(0);
+	Q += sqrt(N0 / 2) * randn(1);
+	/*
+	 * Calculate the log of the probability that each of
+	 * the constellation points was transmitted
+	 */
+	for (m = 0; m < qam; m++)
+		log_syml_prob[m] = -(pow(I - symbols_I[m], 2.0)
+				+ pow(Q - symbols_Q[m], 2.0)) / N0;
+	/* Calculate an LLR for each of the k_64QAM bits in the set */
+	for (k = 0; k < qm; k++) {
+		p0 = -999999;
+		p1 = -999999;
+		/* For each constellation point */
+		for (m = 0; m < qam; m++) {
+			if ((m >> (qm - k - 1)) & 1)
+				p1 = maxstar(p1, log_syml_prob[m]);
+			else
+				p0 = maxstar(p0, log_syml_prob[m]);
+		}
+		/* Calculate the LLR */
+		llr_ = p0 - p1;
+		llr_ *= (1 << ldpc_llr_decimals);
+		llr_ = round(llr_);
+		if (llr_ > llr_max)
+			llr_ = llr_max;
+		if (llr_ < -llr_max)
+			llr_ = -llr_max;
+		llrs[qm * i + k] = (int8_t) llr_;
+	}
+}
+
+/*
+ * Generate Qm LLRS for Qm==4
+ * Modulation, AWGN and LLR estimation from max log development
+ */
+static void
+gen_qm4_llr(int8_t *llrs, uint32_t i, double N0, double llr_max)
+{
+	int qm = 4;
+	int qam = 16;
+	int m, k;
+	double I, Q, p0, p1, llr_, b[qm], log_syml_prob[qam];
+	/* 5.1.4 of TS38.211 */
+	const double symbols_I[16] = {1, 1, 3, 3, 1, 1, 3, 3,
+			-1, -1, -3, -3, -1, -1, -3, -3};
+	const double symbols_Q[16] = {1, 3, 1, 3, -1, -3, -1, -3,
+			1, 3, 1, 3, -1, -3, -1, -3};
+	/* Average constellation point energy */
+	N0 *= 10.0;
+	for (k = 0; k < qm; k++)
+		b[k] = llrs[qm * i + k] < 0 ? 1.0 : 0.0;
+	/* 5.1.4 of TS38.211 */
+	I = (1 - 2 * b[0]) * (2 - (1 - 2 * b[2]));
+	Q = (1 - 2 * b[1]) * (2 - (1 - 2 * b[3]));
+	/* AWGN channel */
+	I += sqrt(N0 / 2) * randn(0);
+	Q += sqrt(N0 / 2) * randn(1);
+	/*
+	 * Calculate the log of the probability that each of
+	 * the constellation points was transmitted
+	 */
+	for (m = 0; m < qam; m++)
+		log_syml_prob[m] = -(pow(I - symbols_I[m], 2.0)
+				+ pow(Q - symbols_Q[m], 2.0)) / N0;
+	/* Calculate an LLR for each of the k_64QAM bits in the set */
+	for (k = 0; k < qm; k++) {
+		p0 = -999999;
+		p1 = -999999;
+		/* For each constellation point */
+		for (m = 0; m < qam; m++) {
+			if ((m >> (qm - k - 1)) & 1)
+				p1 = maxstar(p1, log_syml_prob[m]);
+			else
+				p0 = maxstar(p0, log_syml_prob[m]);
+		}
+		/* Calculate the LLR */
+		llr_ = p0 - p1;
+		llr_ *= (1 << ldpc_llr_decimals);
+		llr_ = round(llr_);
+		if (llr_ > llr_max)
+			llr_ = llr_max;
+		if (llr_ < -llr_max)
+			llr_ = -llr_max;
+		llrs[qm * i + k] = (int8_t) llr_;
+	}
+}
+
+static void
+gen_qm2_llr(int8_t *llrs, uint32_t j, double N0, double llr_max)
+{
+	double b, b1, n;
+	double coeff = 2.0 * sqrt(N0);
+
+	/* Ignore in vectors rare quasi null LLRs not to be saturated */
+	if (llrs[j] < 8 && llrs[j] > -8)
+		return;
+
+	/* Note don't change sign here */
+	n = randn(j % 2);
+	b1 = ((llrs[j] > 0 ? 2.0 : -2.0)
+			+ coeff * n) / N0;
+	b = b1 * (1 << ldpc_llr_decimals);
+	b = round(b);
+	if (b > llr_max)
+		b = llr_max;
+	if (b < -llr_max)
+		b = -llr_max;
+	llrs[j] = (int8_t) b;
+}
+
+/* Generate LLR for a given SNR */
+static void
+generate_llr_input(uint16_t n, struct rte_bbdev_op_data *inputs,
+		struct rte_bbdev_dec_op *ref_op)
+{
+	struct rte_mbuf *m;
+	uint16_t qm;
+	uint32_t i, j, e, range;
+	double N0, llr_max;
+
+	e = ref_op->ldpc_dec.cb_params.e;
+	qm = ref_op->ldpc_dec.q_m;
+	llr_max = (1 << (ldpc_llr_size - 1)) - 1;
+	range = e / qm;
+	N0 = 1.0 / pow(10.0, get_snr() / 10.0);
+
+	for (i = 0; i < n; ++i) {
+		m = inputs[i].data;
+		int8_t *llrs = rte_pktmbuf_mtod_offset(m, int8_t *, 0);
+		if (qm == 6) {
+			for (j = 0; j < range; ++j)
+				gen_qm6_llr(llrs, j, N0, llr_max);
+		} else if (qm == 4) {
+			for (j = 0; j < range; ++j)
+				gen_qm4_llr(llrs, j, N0, llr_max);
+		} else {
+			for (j = 0; j < e; ++j)
+				gen_qm2_llr(llrs, j, N0, llr_max);
+		}
+	}
+}
+
 static void
 copy_reference_ldpc_dec_op(struct rte_bbdev_dec_op **ops, unsigned int n,
 		unsigned int start_idx,
@@ -1301,7 +1510,7 @@ typedef int (test_case_function)(struct active_device *ad,
 {
 	int status = op->status;
 	/* ignore parity mismatch false alarms for long iterations */
-	{
+	if (get_iter_max() >= 10) {
 		if (!(expected_status & (1 << RTE_BBDEV_SYNDROME_ERROR)) &&
 				(status & (1 << RTE_BBDEV_SYNDROME_ERROR))) {
 			printf("WARNING: Ignore Syndrome Check mismatch\n");
@@ -1587,6 +1796,30 @@ typedef int (test_case_function)(struct active_device *ad,
 	return TEST_SUCCESS;
 }
 
+/* Check Number of code blocks errors */
+static int
+validate_ldpc_bler(struct rte_bbdev_dec_op **ops, const uint16_t n)
+{
+	unsigned int i;
+	struct op_data_entries *hard_data_orig =
+			&test_vector.entries[DATA_HARD_OUTPUT];
+	struct rte_bbdev_op_ldpc_dec *ops_td;
+	struct rte_bbdev_op_data *hard_output;
+	int errors = 0;
+	struct rte_mbuf *m;
+
+	for (i = 0; i < n; ++i) {
+		ops_td = &ops[i]->ldpc_dec;
+		hard_output = &ops_td->hard_output;
+		m = hard_output->data;
+		if (memcmp(rte_pktmbuf_mtod_offset(m, uint32_t *, 0),
+				hard_data_orig->segments[0].addr,
+				hard_data_orig->segments[0].length))
+			errors++;
+	}
+	return errors;
+}
+
 static int
 validate_ldpc_dec_op(struct rte_bbdev_dec_op **ops, const uint16_t n,
 		struct rte_bbdev_dec_op *ref_op, const int vector_mask)
@@ -2500,6 +2733,139 @@ typedef int (test_case_function)(struct active_device *ad,
 }
 
 static int
+bler_pmd_lcore_ldpc_dec(void *arg)
+{
+	struct thread_params *tp = arg;
+	uint16_t enq, deq;
+	uint64_t total_time = 0, start_time;
+	const uint16_t queue_id = tp->queue_id;
+	const uint16_t burst_sz = tp->op_params->burst_sz;
+	const uint16_t num_ops = tp->op_params->num_to_process;
+	struct rte_bbdev_dec_op *ops_enq[num_ops];
+	struct rte_bbdev_dec_op *ops_deq[num_ops];
+	struct rte_bbdev_dec_op *ref_op = tp->op_params->ref_dec_op;
+	struct test_buffers *bufs = NULL;
+	int i, j, ret;
+	float parity_bler = 0;
+	struct rte_bbdev_info info;
+	uint16_t num_to_enq;
+	bool extDdr = check_bit(ldpc_cap_flags,
+			RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_OUT_ENABLE);
+	bool loopback = check_bit(ref_op->ldpc_dec.op_flags,
+			RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK);
+	bool hc_out = check_bit(ref_op->ldpc_dec.op_flags,
+			RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE);
+
+	TEST_ASSERT_SUCCESS((burst_sz > MAX_BURST),
+			"BURST_SIZE should be <= %u", MAX_BURST);
+
+	rte_bbdev_info_get(tp->dev_id, &info);
+
+	TEST_ASSERT_SUCCESS((num_ops > info.drv.queue_size_lim),
+			"NUM_OPS cannot exceed %u for this device",
+			info.drv.queue_size_lim);
+
+	bufs = &tp->op_params->q_bufs[GET_SOCKET(info.socket_id)][queue_id];
+
+	while (rte_atomic16_read(&tp->op_params->sync) == SYNC_WAIT)
+		rte_pause();
+
+	ret = rte_bbdev_dec_op_alloc_bulk(tp->op_params->mp, ops_enq, num_ops);
+	TEST_ASSERT_SUCCESS(ret, "Allocation failed for %d ops", num_ops);
+
+	/* For BLER tests we need to enable early termination */
+	if (!check_bit(ref_op->ldpc_dec.op_flags,
+			RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE))
+		ref_op->ldpc_dec.op_flags +=
+				RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE;
+	ref_op->ldpc_dec.iter_max = get_iter_max();
+	ref_op->ldpc_dec.iter_count = ref_op->ldpc_dec.iter_max;
+
+	if (test_vector.op_type != RTE_BBDEV_OP_NONE)
+		copy_reference_ldpc_dec_op(ops_enq, num_ops, 0, bufs->inputs,
+				bufs->hard_outputs, bufs->soft_outputs,
+				bufs->harq_inputs, bufs->harq_outputs, ref_op);
+	generate_llr_input(num_ops, bufs->inputs, ref_op);
+
+	/* Set counter to validate the ordering */
+	for (j = 0; j < num_ops; ++j)
+		ops_enq[j]->opaque_data = (void *)(uintptr_t)j;
+
+	for (i = 0; i < 1; ++i) { /* Could add more iterations */
+		for (j = 0; j < num_ops; ++j) {
+			if (!loopback)
+				mbuf_reset(
+				ops_enq[j]->ldpc_dec.hard_output.data);
+			if (hc_out || loopback)
+				mbuf_reset(
+				ops_enq[j]->ldpc_dec.harq_combined_output.data);
+		}
+		if (extDdr) {
+			bool preload = i == (TEST_REPETITIONS - 1);
+			preload_harq_ddr(tp->dev_id, queue_id, ops_enq,
+					num_ops, preload);
+		}
+		start_time = rte_rdtsc_precise();
+
+		for (enq = 0, deq = 0; enq < num_ops;) {
+			num_to_enq = burst_sz;
+
+			if (unlikely(num_ops - enq < num_to_enq))
+				num_to_enq = num_ops - enq;
+
+			enq += rte_bbdev_enqueue_ldpc_dec_ops(tp->dev_id,
+					queue_id, &ops_enq[enq], num_to_enq);
+
+			deq += rte_bbdev_dequeue_ldpc_dec_ops(tp->dev_id,
+					queue_id, &ops_deq[deq], enq - deq);
+		}
+
+		/* dequeue the remaining */
+		while (deq < enq) {
+			deq += rte_bbdev_dequeue_ldpc_dec_ops(tp->dev_id,
+					queue_id, &ops_deq[deq], enq - deq);
+		}
+
+		total_time += rte_rdtsc_precise() - start_time;
+	}
+
+	tp->iter_count = 0;
+	tp->iter_average = 0;
+	/* get the max of iter_count for all dequeued ops */
+	for (i = 0; i < num_ops; ++i) {
+		tp->iter_count = RTE_MAX(ops_enq[i]->ldpc_dec.iter_count,
+				tp->iter_count);
+		tp->iter_average += (double) ops_enq[i]->ldpc_dec.iter_count;
+		if (ops_enq[i]->status & (1 << RTE_BBDEV_SYNDROME_ERROR))
+			parity_bler += 1.0;
+	}
+
+	parity_bler /= num_ops; /* This one is based on SYND */
+	tp->iter_average /= num_ops;
+	tp->bler = (double) validate_ldpc_bler(ops_deq, num_ops) / num_ops;
+
+	if (test_vector.op_type != RTE_BBDEV_OP_NONE
+			&& tp->bler == 0
+			&& parity_bler == 0
+			&& !hc_out) {
+		ret = validate_ldpc_dec_op(ops_deq, num_ops, ref_op,
+				tp->op_params->vector_mask);
+		TEST_ASSERT_SUCCESS(ret, "Validation failed!");
+	}
+
+	rte_bbdev_dec_op_free_bulk(ops_enq, num_ops);
+
+	double tb_len_bits = calc_ldpc_dec_TB_size(ref_op);
+	tp->ops_per_sec = ((double)num_ops * 1) /
+			((double)total_time / (double)rte_get_tsc_hz());
+	tp->mbps = (((double)(num_ops * 1 * tb_len_bits)) /
+			1000000.0) / ((double)total_time /
+			(double)rte_get_tsc_hz());
+
+	return TEST_SUCCESS;
+}
+
+static int
 throughput_pmd_lcore_ldpc_dec(void *arg)
 {
 	struct thread_params *tp = arg;
@@ -2544,7 +2910,7 @@ typedef int (test_case_function)(struct active_device *ad,
 			RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE))
 		ref_op->ldpc_dec.op_flags -=
 				RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE;
-	ref_op->ldpc_dec.iter_max = 6;
+	ref_op->ldpc_dec.iter_max = get_iter_max();
 	ref_op->ldpc_dec.iter_count = ref_op->ldpc_dec.iter_max;
 
 	if (test_vector.op_type != RTE_BBDEV_OP_NONE)
@@ -2825,27 +3191,147 @@ typedef int (test_case_function)(struct active_device *ad,
 		used_cores, total_mops, total_mbps);
 }
 
+/* Aggregate the performance results over the number of cores used */
 static void
 print_dec_throughput(struct thread_params *t_params, unsigned int used_cores)
 {
-	unsigned int iter = 0;
+	unsigned int core_idx = 0;
 	double total_mops = 0, total_mbps = 0;
 	uint8_t iter_count = 0;
 
-	for (iter = 0; iter < used_cores; iter++) {
+	for (core_idx = 0; core_idx < used_cores; core_idx++) {
 		printf(
 			"Throughput for core (%u): %.8lg Ops/s, %.8lg Mbps @ max %u iterations\n",
-			t_params[iter].lcore_id, t_params[iter].ops_per_sec,
-			t_params[iter].mbps, t_params[iter].iter_count);
-		total_mops += t_params[iter].ops_per_sec;
-		total_mbps += t_params[iter].mbps;
-		iter_count = RTE_MAX(iter_count, t_params[iter].iter_count);
+			t_params[core_idx].lcore_id,
+			t_params[core_idx].ops_per_sec,
+			t_params[core_idx].mbps,
+			t_params[core_idx].iter_count);
+		total_mops += t_params[core_idx].ops_per_sec;
+		total_mbps += t_params[core_idx].mbps;
+		iter_count = RTE_MAX(iter_count,
+				t_params[core_idx].iter_count);
 	}
 	printf(
 		"\nTotal throughput for %u cores: %.8lg MOPS, %.8lg Mbps @ max %u iterations\n",
 		used_cores, total_mops, total_mbps, iter_count);
 }
 
+/* Aggregate the performance results over the number of cores used */
+static void
+print_dec_bler(struct thread_params *t_params, unsigned int used_cores)
+{
+	unsigned int core_idx = 0;
+	double total_mbps = 0, total_bler = 0, total_iter = 0;
+	double snr = get_snr();
+
+	for (core_idx = 0; core_idx < used_cores; core_idx++) {
+		printf("Core%u BLER %.1f %% - Iters %.1f - Tp %.1f Mbps %s\n",
+				t_params[core_idx].lcore_id,
+				t_params[core_idx].bler * 100,
+				t_params[core_idx].iter_average,
+				t_params[core_idx].mbps,
+				get_vector_filename());
+		total_mbps += t_params[core_idx].mbps;
+		total_bler += t_params[core_idx].bler;
+		total_iter += t_params[core_idx].iter_average;
+	}
+	total_bler /= used_cores;
+	total_iter /= used_cores;
+
+	printf("SNR %.2f BLER %.1f %% - Iterations %.1f %d - Tp %.1f Mbps %s\n",
+			snr, total_bler * 100, total_iter, get_iter_max(),
+			total_mbps, get_vector_filename());
+}
+
+/*
+ * Test function that determines BLER wireless performance
+ */
+static int
+bler_test(struct active_device *ad,
+		struct test_op_params *op_params)
+{
+	int ret;
+	unsigned int lcore_id, used_cores = 0;
+	struct thread_params *t_params;
+	struct rte_bbdev_info info;
+	lcore_function_t *bler_function;
+	uint16_t num_lcores;
+	const char *op_type_str;
+
+	rte_bbdev_info_get(ad->dev_id, &info);
+
+	op_type_str = rte_bbdev_op_type_str(test_vector.op_type);
+	TEST_ASSERT_NOT_NULL(op_type_str, "Invalid op type: %u",
+			test_vector.op_type);
+
+	printf("+ ------------------------------------------------------- +\n");
+	printf("== test: bler\ndev: %s, nb_queues: %u, burst size: %u, num ops: %u, num_lcores: %u, op type: %s, itr mode: %s, GHz: %lg\n",
+			info.dev_name, ad->nb_queues, op_params->burst_sz,
+			op_params->num_to_process, op_params->num_lcores,
+			op_type_str,
+			intr_enabled ? "Interrupt mode" : "PMD mode",
+			(double)rte_get_tsc_hz() / 1000000000.0);
+
+	/* Set number of lcores */
+	num_lcores = (ad->nb_queues < (op_params->num_lcores))
+			? ad->nb_queues
+			: op_params->num_lcores;
+
+	/* Allocate memory for thread parameters structure */
+	t_params = rte_zmalloc(NULL, num_lcores * sizeof(struct thread_params),
+			RTE_CACHE_LINE_SIZE);
+	TEST_ASSERT_NOT_NULL(t_params, "Failed to alloc %zuB for t_params",
+			RTE_ALIGN(sizeof(struct thread_params) * num_lcores,
+				RTE_CACHE_LINE_SIZE));
+
+	if (test_vector.op_type == RTE_BBDEV_OP_LDPC_DEC)
+		bler_function = bler_pmd_lcore_ldpc_dec;
+	else
+		return TEST_SKIPPED;
+
+	rte_atomic16_set(&op_params->sync, SYNC_WAIT);
+
+	/* Master core is set at first entry */
+	t_params[0].dev_id = ad->dev_id;
+	t_params[0].lcore_id = rte_lcore_id();
+	t_params[0].op_params = op_params;
+	t_params[0].queue_id = ad->queue_ids[used_cores++];
+	t_params[0].iter_count = 0;
+
+	RTE_LCORE_FOREACH_SLAVE(lcore_id) {
+		if (used_cores >= num_lcores)
+			break;
+
+		t_params[used_cores].dev_id = ad->dev_id;
+		t_params[used_cores].lcore_id = lcore_id;
+		t_params[used_cores].op_params = op_params;
+		t_params[used_cores].queue_id = ad->queue_ids[used_cores];
+		t_params[used_cores].iter_count = 0;
+
+		rte_eal_remote_launch(bler_function,
+				&t_params[used_cores++], lcore_id);
+	}
+
+	rte_atomic16_set(&op_params->sync, SYNC_START);
+	ret = bler_function(&t_params[0]);
+
+	/* Master core is always used */
+	for (used_cores = 1; used_cores < num_lcores; used_cores++)
+		ret |= rte_eal_wait_lcore(t_params[used_cores].lcore_id);
+
+	print_dec_bler(t_params, num_lcores);
+
+	/* Return if test failed */
+	if (ret) {
+		rte_free(t_params);
+		return ret;
+	}
+
+	/* Function to print something  here*/
+	rte_free(t_params);
+	return ret;
+}
+
 /*
  * Test function that determines how long an enqueue + dequeue of a burst
  * takes on available lcores.
@@ -3113,7 +3599,7 @@ typedef int (test_case_function)(struct active_device *ad,
 				RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE))
 			ref_op->ldpc_dec.op_flags -=
 					RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE;
-		ref_op->ldpc_dec.iter_max = 6;
+		ref_op->ldpc_dec.iter_max = get_iter_max();
 		ref_op->ldpc_dec.iter_count = ref_op->ldpc_dec.iter_max;
 
 		if (test_vector.op_type != RTE_BBDEV_OP_NONE)
@@ -3971,6 +4457,12 @@ typedef int (test_case_function)(struct active_device *ad,
 }
 
 static int
+bler_tc(void)
+{
+	return run_test_case(bler_test);
+}
+
+static int
 throughput_tc(void)
 {
 	return run_test_case(throughput_test);
@@ -4000,6 +4492,16 @@ typedef int (test_case_function)(struct active_device *ad,
 	return run_test_case(throughput_test);
 }
 
+static struct unit_test_suite bbdev_bler_testsuite = {
+	.suite_name = "BBdev BLER Tests",
+	.setup = testsuite_setup,
+	.teardown = testsuite_teardown,
+	.unit_test_cases = {
+		TEST_CASE_ST(ut_setup, ut_teardown, bler_tc),
+		TEST_CASES_END() /**< NULL terminate unit test array */
+	}
+};
+
 static struct unit_test_suite bbdev_throughput_testsuite = {
 	.suite_name = "BBdev Throughput Tests",
 	.setup = testsuite_setup,
@@ -4051,6 +4553,7 @@ typedef int (test_case_function)(struct active_device *ad,
 	}
 };
 
+REGISTER_TEST_COMMAND(bler, bbdev_bler_testsuite);
 REGISTER_TEST_COMMAND(throughput, bbdev_throughput_testsuite);
 REGISTER_TEST_COMMAND(validation, bbdev_validation_testsuite);
 REGISTER_TEST_COMMAND(latency, bbdev_latency_testsuite);
-- 
1.8.3.1


^ permalink raw reply	[flat|nested] 115+ messages in thread

* [dpdk-dev] [PATCH v1 08/14] test-bbdev: support for LDPC interrupt test
  2020-02-27  4:38 [dpdk-dev] [PATCH v1 00/14] bbdev new features Nicolas Chautru
                   ` (6 preceding siblings ...)
  2020-02-27  4:39 ` [dpdk-dev] [PATCH v1 07/14] test-bbdev: support for performance tests Nicolas Chautru
@ 2020-02-27  4:39 ` Nicolas Chautru
  2020-02-27  4:39 ` [dpdk-dev] [PATCH v1 09/14] test-bbdev: support for offload test for LDPC Nicolas Chautru
                   ` (6 subsequent siblings)
  14 siblings, 0 replies; 115+ messages in thread
From: Nicolas Chautru @ 2020-02-27  4:39 UTC (permalink / raw)
  To: thomas, akhil.goyal, dev; +Cc: ferruh.yigit, Nic Chautru

From: Nic Chautru <nicolas.chautru@intel.com>

Adding missing implementation for the interrupt tests
for LDPC encoder and decoders.

Signed-off-by: Nic Chautru <nicolas.chautru@intel.com>
---
 app/test-bbdev/test_bbdev_perf.c | 202 ++++++++++++++++++++++++++++++++++++++-
 1 file changed, 200 insertions(+), 2 deletions(-)

diff --git a/app/test-bbdev/test_bbdev_perf.c b/app/test-bbdev/test_bbdev_perf.c
index 7bc824b..8fcdda0 100644
--- a/app/test-bbdev/test_bbdev_perf.c
+++ b/app/test-bbdev/test_bbdev_perf.c
@@ -745,6 +745,9 @@ typedef int (test_case_function)(struct active_device *ad,
 	/* Clear active devices structs. */
 	memset(active_devs, 0, sizeof(active_devs));
 	nb_active_devs = 0;
+
+	/* Disable interrupts */
+	intr_enabled = false;
 }
 
 static int
@@ -2457,6 +2460,109 @@ typedef int (test_case_function)(struct active_device *ad,
 }
 
 static int
+throughput_intr_lcore_ldpc_dec(void *arg)
+{
+	struct thread_params *tp = arg;
+	unsigned int enqueued;
+	const uint16_t queue_id = tp->queue_id;
+	const uint16_t burst_sz = tp->op_params->burst_sz;
+	const uint16_t num_to_process = tp->op_params->num_to_process;
+	struct rte_bbdev_dec_op *ops[num_to_process];
+	struct test_buffers *bufs = NULL;
+	struct rte_bbdev_info info;
+	int ret, i, j;
+	struct rte_bbdev_dec_op *ref_op = tp->op_params->ref_dec_op;
+	uint16_t num_to_enq, enq;
+
+	bool loopback = check_bit(ref_op->ldpc_dec.op_flags,
+			RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK);
+	bool hc_out = check_bit(ref_op->ldpc_dec.op_flags,
+			RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE);
+
+	TEST_ASSERT_SUCCESS((burst_sz > MAX_BURST),
+			"BURST_SIZE should be <= %u", MAX_BURST);
+
+	TEST_ASSERT_SUCCESS(rte_bbdev_queue_intr_enable(tp->dev_id, queue_id),
+			"Failed to enable interrupts for dev: %u, queue_id: %u",
+			tp->dev_id, queue_id);
+
+	rte_bbdev_info_get(tp->dev_id, &info);
+
+	TEST_ASSERT_SUCCESS((num_to_process > info.drv.queue_size_lim),
+			"NUM_OPS cannot exceed %u for this device",
+			info.drv.queue_size_lim);
+
+	bufs = &tp->op_params->q_bufs[GET_SOCKET(info.socket_id)][queue_id];
+
+	rte_atomic16_clear(&tp->processing_status);
+	rte_atomic16_clear(&tp->nb_dequeued);
+
+	while (rte_atomic16_read(&tp->op_params->sync) == SYNC_WAIT)
+		rte_pause();
+
+	ret = rte_bbdev_dec_op_alloc_bulk(tp->op_params->mp, ops,
+				num_to_process);
+	TEST_ASSERT_SUCCESS(ret, "Allocation failed for %d ops",
+			num_to_process);
+	if (test_vector.op_type != RTE_BBDEV_OP_NONE)
+		copy_reference_ldpc_dec_op(ops, num_to_process, 0, bufs->inputs,
+				bufs->hard_outputs, bufs->soft_outputs,
+				bufs->harq_inputs, bufs->harq_outputs, ref_op);
+
+	/* Set counter to validate the ordering */
+	for (j = 0; j < num_to_process; ++j)
+		ops[j]->opaque_data = (void *)(uintptr_t)j;
+
+	for (j = 0; j < TEST_REPETITIONS; ++j) {
+		for (i = 0; i < num_to_process; ++i) {
+			if (!loopback)
+				rte_pktmbuf_reset(
+					ops[i]->ldpc_dec.hard_output.data);
+			if (hc_out || loopback)
+				mbuf_reset(
+				ops[i]->ldpc_dec.harq_combined_output.data);
+		}
+
+		tp->start_time = rte_rdtsc_precise();
+		for (enqueued = 0; enqueued < num_to_process;) {
+			num_to_enq = burst_sz;
+
+			if (unlikely(num_to_process - enqueued < num_to_enq))
+				num_to_enq = num_to_process - enqueued;
+
+			enq = 0;
+			do {
+				enq += rte_bbdev_enqueue_ldpc_dec_ops(
+						tp->dev_id,
+						queue_id, &ops[enqueued],
+						num_to_enq);
+			} while (unlikely(num_to_enq != enq));
+			enqueued += enq;
+
+			/* Write to thread burst_sz current number of enqueued
+			 * descriptors. It ensures that proper number of
+			 * descriptors will be dequeued in callback
+			 * function - needed for last batch in case where
+			 * the number of operations is not a multiple of
+			 * burst size.
+			 */
+			rte_atomic16_set(&tp->burst_sz, num_to_enq);
+
+			/* Wait until processing of previous batch is
+			 * completed
+			 */
+			while (rte_atomic16_read(&tp->nb_dequeued) !=
+					(int16_t) enqueued)
+				rte_pause();
+		}
+		if (j != TEST_REPETITIONS - 1)
+			rte_atomic16_clear(&tp->nb_dequeued);
+	}
+
+	return TEST_SUCCESS;
+}
+
+static int
 throughput_intr_lcore_dec(void *arg)
 {
 	struct thread_params *tp = arg;
@@ -2635,6 +2741,98 @@ typedef int (test_case_function)(struct active_device *ad,
 	return TEST_SUCCESS;
 }
 
+
+static int
+throughput_intr_lcore_ldpc_enc(void *arg)
+{
+	struct thread_params *tp = arg;
+	unsigned int enqueued;
+	const uint16_t queue_id = tp->queue_id;
+	const uint16_t burst_sz = tp->op_params->burst_sz;
+	const uint16_t num_to_process = tp->op_params->num_to_process;
+	struct rte_bbdev_enc_op *ops[num_to_process];
+	struct test_buffers *bufs = NULL;
+	struct rte_bbdev_info info;
+	int ret, i, j;
+	uint16_t num_to_enq, enq;
+
+	TEST_ASSERT_SUCCESS((burst_sz > MAX_BURST),
+			"BURST_SIZE should be <= %u", MAX_BURST);
+
+	TEST_ASSERT_SUCCESS(rte_bbdev_queue_intr_enable(tp->dev_id, queue_id),
+			"Failed to enable interrupts for dev: %u, queue_id: %u",
+			tp->dev_id, queue_id);
+
+	rte_bbdev_info_get(tp->dev_id, &info);
+
+	TEST_ASSERT_SUCCESS((num_to_process > info.drv.queue_size_lim),
+			"NUM_OPS cannot exceed %u for this device",
+			info.drv.queue_size_lim);
+
+	bufs = &tp->op_params->q_bufs[GET_SOCKET(info.socket_id)][queue_id];
+
+	rte_atomic16_clear(&tp->processing_status);
+	rte_atomic16_clear(&tp->nb_dequeued);
+
+	while (rte_atomic16_read(&tp->op_params->sync) == SYNC_WAIT)
+		rte_pause();
+
+	ret = rte_bbdev_enc_op_alloc_bulk(tp->op_params->mp, ops,
+			num_to_process);
+	TEST_ASSERT_SUCCESS(ret, "Allocation failed for %d ops",
+			num_to_process);
+	if (test_vector.op_type != RTE_BBDEV_OP_NONE)
+		copy_reference_ldpc_enc_op(ops, num_to_process, 0,
+				bufs->inputs, bufs->hard_outputs,
+				tp->op_params->ref_enc_op);
+
+	/* Set counter to validate the ordering */
+	for (j = 0; j < num_to_process; ++j)
+		ops[j]->opaque_data = (void *)(uintptr_t)j;
+
+	for (j = 0; j < TEST_REPETITIONS; ++j) {
+		for (i = 0; i < num_to_process; ++i)
+			rte_pktmbuf_reset(ops[i]->turbo_enc.output.data);
+
+		tp->start_time = rte_rdtsc_precise();
+		for (enqueued = 0; enqueued < num_to_process;) {
+			num_to_enq = burst_sz;
+
+			if (unlikely(num_to_process - enqueued < num_to_enq))
+				num_to_enq = num_to_process - enqueued;
+
+			enq = 0;
+			do {
+				enq += rte_bbdev_enqueue_ldpc_enc_ops(
+						tp->dev_id,
+						queue_id, &ops[enqueued],
+						num_to_enq);
+			} while (unlikely(enq != num_to_enq));
+			enqueued += enq;
+
+			/* Write to thread burst_sz current number of enqueued
+			 * descriptors. It ensures that proper number of
+			 * descriptors will be dequeued in callback
+			 * function - needed for last batch in case where
+			 * the number of operations is not a multiple of
+			 * burst size.
+			 */
+			rte_atomic16_set(&tp->burst_sz, num_to_enq);
+
+			/* Wait until processing of previous batch is
+			 * completed
+			 */
+			while (rte_atomic16_read(&tp->nb_dequeued) !=
+					(int16_t) enqueued)
+				rte_pause();
+		}
+		if (j != TEST_REPETITIONS - 1)
+			rte_atomic16_clear(&tp->nb_dequeued);
+	}
+
+	return TEST_SUCCESS;
+}
+
 static int
 throughput_pmd_lcore_dec(void *arg)
 {
@@ -3378,11 +3576,11 @@ typedef int (test_case_function)(struct active_device *ad,
 		if (test_vector.op_type == RTE_BBDEV_OP_TURBO_DEC)
 			throughput_function = throughput_intr_lcore_dec;
 		else if (test_vector.op_type == RTE_BBDEV_OP_LDPC_DEC)
-			throughput_function = throughput_intr_lcore_dec;
+			throughput_function = throughput_intr_lcore_ldpc_dec;
 		else if (test_vector.op_type == RTE_BBDEV_OP_TURBO_ENC)
 			throughput_function = throughput_intr_lcore_enc;
 		else if (test_vector.op_type == RTE_BBDEV_OP_LDPC_ENC)
-			throughput_function = throughput_intr_lcore_enc;
+			throughput_function = throughput_intr_lcore_ldpc_enc;
 		else
 			throughput_function = throughput_intr_lcore_enc;
 
-- 
1.8.3.1


^ permalink raw reply	[flat|nested] 115+ messages in thread

* [dpdk-dev] [PATCH v1 09/14] test-bbdev: support for offload test for LDPC
  2020-02-27  4:38 [dpdk-dev] [PATCH v1 00/14] bbdev new features Nicolas Chautru
                   ` (7 preceding siblings ...)
  2020-02-27  4:39 ` [dpdk-dev] [PATCH v1 08/14] test-bbdev: support for LDPC interrupt test Nicolas Chautru
@ 2020-02-27  4:39 ` Nicolas Chautru
  2020-02-27  4:39 ` [dpdk-dev] [PATCH v1 10/14] test-bbdev: vectors update Nicolas Chautru
                   ` (5 subsequent siblings)
  14 siblings, 0 replies; 115+ messages in thread
From: Nicolas Chautru @ 2020-02-27  4:39 UTC (permalink / raw)
  To: thomas, akhil.goyal, dev; +Cc: ferruh.yigit, Nic Chautru

From: Nic Chautru <nicolas.chautru@intel.com>

Adding support for the offload latency tests when
using the LDPC encoder and decoder operations.

Signed-off-by: Nic Chautru <nicolas.chautru@intel.com>
---
 app/test-bbdev/test_bbdev_perf.c | 26 +++++++++++++++++++-------
 1 file changed, 19 insertions(+), 7 deletions(-)

diff --git a/app/test-bbdev/test_bbdev_perf.c b/app/test-bbdev/test_bbdev_perf.c
index 8fcdda0..1017b97 100644
--- a/app/test-bbdev/test_bbdev_perf.c
+++ b/app/test-bbdev/test_bbdev_perf.c
@@ -4538,7 +4538,7 @@ typedef int (test_case_function)(struct active_device *ad,
 offload_latency_empty_q_test_dec(uint16_t dev_id, uint16_t queue_id,
 		const uint16_t num_to_process, uint16_t burst_sz,
 		uint64_t *deq_total_time, uint64_t *deq_min_time,
-		uint64_t *deq_max_time)
+		uint64_t *deq_max_time, const enum rte_bbdev_op_type op_type)
 {
 	int i, deq_total;
 	struct rte_bbdev_dec_op *ops[MAX_BURST];
@@ -4552,7 +4552,12 @@ typedef int (test_case_function)(struct active_device *ad,
 
 		if (unlikely(num_to_process - deq_total < burst_sz))
 			burst_sz = num_to_process - deq_total;
-		rte_bbdev_dequeue_dec_ops(dev_id, queue_id, ops, burst_sz);
+		if (op_type == RTE_BBDEV_OP_TURBO_DEC)
+			rte_bbdev_dequeue_dec_ops(dev_id, queue_id, ops,
+					burst_sz);
+		else
+			rte_bbdev_dequeue_ldpc_dec_ops(dev_id, queue_id, ops,
+								burst_sz);
 
 		deq_last_time = rte_rdtsc_precise() - deq_start_time;
 		*deq_max_time = RTE_MAX(*deq_max_time, deq_last_time);
@@ -4567,7 +4572,7 @@ typedef int (test_case_function)(struct active_device *ad,
 offload_latency_empty_q_test_enc(uint16_t dev_id, uint16_t queue_id,
 		const uint16_t num_to_process, uint16_t burst_sz,
 		uint64_t *deq_total_time, uint64_t *deq_min_time,
-		uint64_t *deq_max_time)
+		uint64_t *deq_max_time, const enum rte_bbdev_op_type op_type)
 {
 	int i, deq_total;
 	struct rte_bbdev_enc_op *ops[MAX_BURST];
@@ -4580,7 +4585,12 @@ typedef int (test_case_function)(struct active_device *ad,
 
 		if (unlikely(num_to_process - deq_total < burst_sz))
 			burst_sz = num_to_process - deq_total;
-		rte_bbdev_dequeue_enc_ops(dev_id, queue_id, ops, burst_sz);
+		if (op_type == RTE_BBDEV_OP_LDPC_ENC)
+			rte_bbdev_dequeue_ldpc_enc_ops(dev_id, queue_id, ops,
+					burst_sz);
+		else
+			rte_bbdev_dequeue_enc_ops(dev_id, queue_id, ops,
+								burst_sz);
 
 		deq_last_time = rte_rdtsc_precise() - deq_start_time;
 		*deq_max_time = RTE_MAX(*deq_max_time, deq_last_time);
@@ -4590,6 +4600,7 @@ typedef int (test_case_function)(struct active_device *ad,
 
 	return i;
 }
+
 #endif
 
 static int
@@ -4627,14 +4638,15 @@ typedef int (test_case_function)(struct active_device *ad,
 	printf("== test: offload latency empty dequeue\ndev: %s, burst size: %u, num ops: %u, op type: %s\n",
 			info.dev_name, burst_sz, num_to_process, op_type_str);
 
-	if (op_type == RTE_BBDEV_OP_TURBO_DEC)
+	if (op_type == RTE_BBDEV_OP_TURBO_DEC ||
+			op_type == RTE_BBDEV_OP_LDPC_DEC)
 		iter = offload_latency_empty_q_test_dec(ad->dev_id, queue_id,
 				num_to_process, burst_sz, &deq_total_time,
-				&deq_min_time, &deq_max_time);
+				&deq_min_time, &deq_max_time, op_type);
 	else
 		iter = offload_latency_empty_q_test_enc(ad->dev_id, queue_id,
 				num_to_process, burst_sz, &deq_total_time,
-				&deq_min_time, &deq_max_time);
+				&deq_min_time, &deq_max_time, op_type);
 
 	if (iter <= 0)
 		return TEST_FAILED;
-- 
1.8.3.1


^ permalink raw reply	[flat|nested] 115+ messages in thread

* [dpdk-dev] [PATCH v1 10/14] test-bbdev: vectors update
  2020-02-27  4:38 [dpdk-dev] [PATCH v1 00/14] bbdev new features Nicolas Chautru
                   ` (8 preceding siblings ...)
  2020-02-27  4:39 ` [dpdk-dev] [PATCH v1 09/14] test-bbdev: support for offload test for LDPC Nicolas Chautru
@ 2020-02-27  4:39 ` Nicolas Chautru
  2020-02-27  4:39 ` [dpdk-dev] [PATCH v1 11/14] doc: update of testbbdev documentation Nicolas Chautru
                   ` (4 subsequent siblings)
  14 siblings, 0 replies; 115+ messages in thread
From: Nicolas Chautru @ 2020-02-27  4:39 UTC (permalink / raw)
  To: thomas, akhil.goyal, dev; +Cc: ferruh.yigit, Nic Chautru

From: Nic Chautru <nicolas.chautru@intel.com>

Modification to vectors parameters used for unit test
for coverage and performance test of bbdev drivers
across all devices.
Reducing list for focused coverage when required.

Signed-off-by: Nic Chautru <nicolas.chautru@intel.com>
---
 app/test-bbdev/ldpc_dec_default.data               |   2 +-
 app/test-bbdev/test_vectors/ldpc_dec_v2342.data    | 745 ---------------------
 app/test-bbdev/test_vectors/ldpc_dec_v9503.data    |   4 +-
 .../turbo_dec_c1_k6144_r0_e34560_negllr.data       | 645 ------------------
 .../turbo_dec_c2_k3136_r0_e4920_sbd_negllr.data    | 676 -------------------
 ...bo_dec_c2_k3136_r0_e4920_sbd_negllr_crc24b.data |   5 +-
 .../turbo_enc_c2_k5952_r0_e17868_crc24b.data       | 300 ---------
 .../turbo_enc_c4_k4800_r2_e14412_crc24b.data       | 252 -------
 8 files changed, 7 insertions(+), 2622 deletions(-)
 delete mode 100644 app/test-bbdev/test_vectors/ldpc_dec_v2342.data
 delete mode 100644 app/test-bbdev/test_vectors/turbo_dec_c1_k6144_r0_e34560_negllr.data
 delete mode 100644 app/test-bbdev/test_vectors/turbo_dec_c2_k3136_r0_e4920_sbd_negllr.data
 delete mode 100644 app/test-bbdev/test_vectors/turbo_enc_c2_k5952_r0_e17868_crc24b.data
 delete mode 100644 app/test-bbdev/test_vectors/turbo_enc_c4_k4800_r2_e14412_crc24b.data

diff --git a/app/test-bbdev/ldpc_dec_default.data b/app/test-bbdev/ldpc_dec_default.data
index 3058cc0..e53aa1b 120000
--- a/app/test-bbdev/ldpc_dec_default.data
+++ b/app/test-bbdev/ldpc_dec_default.data
@@ -1 +1 @@
-test_vectors/ldpc_dec_v2342.data
\ No newline at end of file
+test_vectors/ldpc_dec_v2342_drop.data
\ No newline at end of file
diff --git a/app/test-bbdev/test_vectors/ldpc_dec_v2342.data b/app/test-bbdev/test_vectors/ldpc_dec_v2342.data
deleted file mode 100644
index eca4131..0000000
--- a/app/test-bbdev/test_vectors/ldpc_dec_v2342.data
+++ /dev/null
@@ -1,745 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-# Copyright(c) 2019 Intel Corporation
-
-op_type =
-RTE_BBDEV_OP_LDPC_DEC
-
-input0 =
-0x7F817F81, 0x817F7F81, 0x8181817F, 0x7F817F81, 0x7F818181, 0x7F81817F, 0x7F817F81, 0x817F8181,
-0x817F8181, 0x817F8181, 0x7F818181, 0x81817F81, 0x81817F81, 0x7F7F817F, 0x817F7F7F, 0x7F7F8181,
-0x7F7F7F81, 0x7F7F817F, 0x7F81817F, 0x7F81817F, 0x7F818181, 0x8181817F, 0x8181817F, 0x7F7F817F,
-0x7F7F8181, 0x8181817F, 0x817F7F7F, 0x81818181, 0x817F7F81, 0x7F7F817F, 0x7F818181, 0x81817F7F,
-0x7F7F7F7F, 0x7F7F817F, 0x7F7F8181, 0x81817F7F, 0x817F8181, 0x7F817F81, 0x7F7F817F, 0x7F7F7F81,
-0x7F7F7F81, 0x817F8181, 0x817F7F7F, 0x817F7F81, 0x7F817F7F, 0x7F7F8181, 0x817F7F7F, 0x7F818181,
-0x7F7F7F7F, 0x7F7F7F81, 0x81817F81, 0x817F7F81, 0x7F7F7F81, 0x7F7F7F81, 0x81818181, 0x7F818181,
-0x817F8181, 0x7F818181, 0x7F817F81, 0x81817F7F, 0x7F817F7F, 0x817F7F7F, 0x7F818181, 0x7F7F8181,
-0x81817F81, 0x8181817F, 0x7F7F817F, 0x7F817F81, 0x81817F7F, 0x817F7F7F, 0x81817F81, 0x81818181,
-0x7F7F8181, 0x81817F81, 0x81817F7F, 0x817F8181, 0x7F7F817F, 0x7F818181, 0x7F81817F, 0x81817F7F,
-0x7F817F7F, 0x81817F7F, 0x7F7F817F, 0x7F818181, 0x7F817F81, 0x7F7F7F81, 0x7F7F7F7F, 0x817F8181,
-0x7F817F7F, 0x81817F81, 0x81817F81, 0x7F817F7F, 0x81817F81, 0x817F7F7F, 0x817F817F, 0x7F7F7F81,
-0x7F817F81, 0x7F7F7F7F, 0x81817F7F, 0x8181817F, 0x81817F81, 0x7F7F7F81, 0x7F7F7F7F, 0x7F817F7F,
-0x81817F7F, 0x7F7F7F81, 0x81817F81, 0x81818181, 0x7F7F7F7F, 0x7F7F817F, 0x7F7F7F81, 0x81817F81,
-0x7F817F7F, 0x7F81817F, 0x81817F81, 0x817F817F, 0x7F7F7F81, 0x817F8181, 0x81818181, 0x81817F81,
-0x7F818181, 0x817F7F81, 0x7F7F7F81, 0x7F817F7F, 0x81818181, 0x81818181, 0x817F7F7F, 0x81817F81,
-0x817F8181, 0x7F7F7F7F, 0x7F7F8181, 0x7F7F817F, 0x7F817F7F, 0x7F81817F, 0x7F7F817F, 0x7F817F7F,
-0x7F7F7F7F, 0x7F818181, 0x817F7F81, 0x817F817F, 0x7F817F81, 0x817F7F81, 0x81818181, 0x8181817F,
-0x81817F81, 0x7F817F7F, 0x817F8181, 0x7F7F7F7F, 0x7F817F81, 0x7F7F817F, 0x7F81817F, 0x817F8181,
-0x817F7F81, 0x817F817F, 0x817F817F, 0x81817F7F, 0x7F818181, 0x817F7F7F, 0x81817F7F, 0x7F7F7F81,
-0x8181817F, 0x817F7F81, 0x7F817F81, 0x81817F7F, 0x7F7F8181, 0x817F7F7F, 0x817F7F81, 0x7F7F817F,
-0x7F81817F, 0x7F81817F, 0x817F8181, 0x7F81817F, 0x81817F7F, 0x7F818181, 0x7F817F7F, 0x7F7F817F,
-0x81817F81, 0x81817F7F, 0x817F817F, 0x817F817F, 0x8181817F, 0x7F817F7F, 0x81817F7F, 0x7F818181,
-0x817F8181, 0x81817F81, 0x8181817F, 0x7F7F7F81, 0x81817F81, 0x81817F7F, 0x8181817F, 0x817F8181,
-0x8181817F, 0x8181817F, 0x817F7F7F, 0x81817F7F, 0x7F7F8181, 0x7F818181, 0x7F817F81, 0x81817F7F,
-0x817F7F81, 0x817F7F7F, 0x8181817F, 0x7F817F7F, 0x817F7F7F, 0x81817F7F, 0x7F818181, 0x7F7F7F7F,
-0x7F817F81, 0x7F7F8181, 0x817F817F, 0x7F7F7F7F, 0x817F8181, 0x81817F81, 0x7F7F817F, 0x7F817F7F,
-0x817F7F7F, 0x81817F7F, 0x7F7F7F7F, 0x7F817F81, 0x7F817F7F, 0x817F8181, 0x7F818181, 0x81817F81,
-0x7F7F817F, 0x7F817F81, 0x817F7F81, 0x7F7F817F, 0x817F817F, 0x817F817F, 0x7F7F8181, 0x7F817F81,
-0x7F818181, 0x7F7F7F7F, 0x81818181, 0x7F7F7F81, 0x81817F7F, 0x817F8181, 0x7F817F7F, 0x7F817F7F,
-0x7F7F8181, 0x81818181, 0x817F8181, 0x817F7F7F, 0x7F7F7F7F, 0x7F7F7F7F, 0x81817F81, 0x7F7F7F81,
-0x8181817F, 0x8181817F, 0x8181817F, 0x817F817F, 0x7F817F7F, 0x7F818181, 0x7F817F81, 0x7F817F81,
-0x7F7F8181, 0x817F817F, 0x81817F7F, 0x7F818181, 0x817F7F7F, 0x817F817F, 0x817F817F, 0x7F7F7F7F,
-0x817F817F, 0x8181817F, 0x7F7F7F81, 0x817F817F, 0x81817F7F, 0x7F7F8181, 0x817F817F, 0x7F818181,
-0x7F7F7F81, 0x81818181, 0x7F818181, 0x7F7F8181, 0x817F8181, 0x817F8181, 0x7F81817F, 0x81817F7F,
-0x81818181, 0x7F7F7F81, 0x817F817F, 0x7F81817F, 0x7F817F81, 0x7F817F7F, 0x7F7F817F, 0x817F7F81,
-0x817F817F, 0x7F81817F, 0x81818181, 0x817F8181, 0x7F817F81, 0x81817F81, 0x7F7F817F, 0x817F7F7F,
-0x817F8181, 0x8181817F, 0x7F817F81, 0x7F7F817F, 0x8181817F, 0x7F81817F, 0x7F818181, 0x81817F81,
-0x8181817F, 0x7F7F8181, 0x817F7F81, 0x7F7F8181, 0x7F7F817F, 0x7F818181, 0x7F7F817F, 0x81818181,
-0x81817F7F, 0x817F7F81, 0x817F8181, 0x7F817F81, 0x7F7F7F7F, 0x7F7F7F81, 0x81817F7F, 0x817F817F,
-0x7F817F81, 0x7F7F7F7F, 0x817F7F81, 0x817F8181, 0x7F7F7F7F, 0x81818181, 0x817F817F, 0x81817F7F,
-0x81817F7F, 0x7F817F7F, 0x7F7F7F7F, 0x7F818181, 0x817F8181, 0x7F817F7F, 0x81818181, 0x81818181,
-0x7F81817F, 0x81817F7F, 0x8181817F, 0x817F7F81, 0x817F817F, 0x81818181, 0x81817F7F, 0x817F7F81,
-0x81818181, 0x8181817F, 0x81817F81, 0x81817F7F, 0x7F7F817F, 0x7F7F7F81, 0x817F7F7F, 0x7F7F8181,
-0x7F7F8181, 0x8181817F, 0x7F817F7F, 0x817F7F81, 0x81817F81, 0x7F7F8181, 0x817F8181, 0x81817F7F,
-0x7F7F7F7F, 0x81818181, 0x817F8181, 0x817F7F81, 0x7F81817F, 0x7F818181, 0x7F7F817F, 0x817F8181,
-0x817F817F, 0x7F7F7F81, 0x7F818181, 0x81818181, 0x7F7F8181, 0x817F7F81, 0x7F7F8181, 0x817F7F7F,
-0x817F7F7F, 0x81817F7F, 0x7F7F817F, 0x7F817F81, 0x817F7F81, 0x817F8181, 0x817F7F81, 0x81817F81,
-0x7F81817F, 0x7F818181, 0x81818181, 0x81817F7F, 0x8181817F, 0x81817F81, 0x7F7F817F, 0x817F7F7F,
-0x817F8181, 0x7F7F7F81, 0x81818181, 0x817F8181, 0x81817F81, 0x817F817F, 0x817F7F7F, 0x81817F81,
-0x7F817F7F, 0x7F7F7F81, 0x81817F7F, 0x81818181, 0x8181817F, 0x817F7F81, 0x8181817F, 0x7F817F7F,
-0x7F817F81, 0x817F817F, 0x8181817F, 0x81818181, 0x7F817F7F, 0x817F7F81, 0x7F817F7F, 0x81818181,
-0x7F7F7F81, 0x7F7F7F81, 0x7F817F81, 0x817F7F81, 0x7F7F817F, 0x7F817F81, 0x7F817F7F, 0x7F7F7F7F,
-0x81817F7F, 0x7F81817F, 0x8181817F, 0x7F81817F, 0x81817F7F, 0x817F7F7F, 0x7F817F7F, 0x7F7F7F81,
-0x7F7F8181, 0x7F7F7F81, 0x7F7F7F81, 0x7F818181, 0x7F7F7F81, 0x8181817F, 0x7F7F7F81, 0x8181817F,
-0x817F7F81, 0x817F8181, 0x7F7F817F, 0x81818181, 0x7F7F7F7F, 0x7F817F7F, 0x81817F7F, 0x81817F7F,
-0x7F7F7F81, 0x7F818181, 0x81817F7F, 0x7F7F7F81, 0x817F817F, 0x817F7F7F, 0x7F818181, 0x7F81817F,
-0x7F81817F, 0x7F818181, 0x7F7F8181, 0x7F817F81, 0x7F7F7F7F, 0x7F817F81, 0x817F817F, 0x7F81817F,
-0x7F81817F, 0x7F7F817F, 0x7F7F7F7F, 0x81817F81, 0x81817F7F, 0x817F8181, 0x7F818181, 0x7F7F8181,
-0x7F817F81, 0x7F818181, 0x817F817F, 0x7F817F81, 0x817F817F, 0x817F7F7F, 0x7F7F8181, 0x81817F81,
-0x7F7F8181, 0x817F8181, 0x817F7F81, 0x7F818181, 0x7F817F7F, 0x81817F81, 0x7F818181, 0x7F7F817F,
-0x817F8181, 0x817F7F7F, 0x81817F81, 0x7F7F7F7F, 0x7F818181, 0x7F817F7F, 0x7F817F7F, 0x7F817F81,
-0x7F817F7F, 0x7F7F7F81, 0x817F7F81, 0x7F817F81, 0x7F81817F, 0x817F817F, 0x7F7F8181, 0x817F8181,
-0x817F8181, 0x7F7F7F81, 0x7F818181, 0x7F7F817F, 0x817F8181, 0x817F817F, 0x7F7F7F81, 0x81817F81,
-0x817F8181, 0x7F81817F, 0x7F7F7F81, 0x817F8181, 0x7F81817F, 0x817F7F7F, 0x7F7F7F7F, 0x817F8181,
-0x81817F81, 0x817F7F7F, 0x7F7F7F81, 0x817F8181, 0x7F7F8181, 0x81818181, 0x817F7F7F, 0x7F7F817F,
-0x81817F81, 0x7F81817F, 0x7F817F7F, 0x81817F81, 0x81818181, 0x7F7F7F81, 0x7F818181, 0x817F7F81,
-0x7F817F81, 0x7F7F817F, 0x817F817F, 0x7F7F7F7F, 0x7F7F7F81, 0x7F7F8181, 0x817F817F, 0x817F817F,
-0x7F7F7F81, 0x7F7F8181, 0x817F7F81, 0x81818181, 0x7F7F7F81, 0x7F7F7F7F, 0x7F817F81, 0x817F7F81,
-0x7F817F7F, 0x81817F7F, 0x7F81817F, 0x7F7F7F81, 0x7F81817F, 0x7F7F817F, 0x817F7F7F, 0x817F817F,
-0x7F817F7F, 0x8181817F, 0x817F8181, 0x81817F81, 0x81817F7F, 0x8181817F, 0x7F81817F, 0x7F7F7F7F,
-0x7F817F81, 0x7F817F81, 0x7F817F81, 0x81817F81, 0x7F817F81, 0x7F7F7F7F, 0x7F817F7F, 0x7F81817F,
-0x7F7F8181, 0x7F81817F, 0x7F7F817F, 0x7F817F81, 0x817F8181, 0x7F7F8181, 0x81818181, 0x7F7F7F81,
-0x7F7F8181, 0x817F7F81, 0x817F7F81, 0x7F7F817F, 0x81817F7F, 0x7F7F817F, 0x817F817F, 0x81817F7F,
-0x817F817F, 0x817F817F, 0x7F7F7F7F, 0x817F7F7F, 0x81818181, 0x7F81817F, 0x8181817F, 0x81817F81,
-0x7F7F7F7F, 0x817F817F, 0x7F81817F, 0x817F8181, 0x81817F81, 0x817F7F7F, 0x8181817F, 0x81817F81,
-0x81817F81, 0x7F817F81, 0x7F817F81, 0x817F7F7F, 0x81818181, 0x8181817F, 0x7F7F7F81, 0x817F7F81,
-0x7F7F7F7F, 0x7F81817F, 0x817F7F81, 0x7F81817F, 0x7F7F7F7F, 0x7F81817F, 0x7F7F8181, 0x81817F81,
-0x817F7F7F, 0x7F817F81, 0x817F8181, 0x8181817F, 0x8181817F, 0x7F817F7F, 0x7F81817F, 0x817F817F,
-0x7F818181, 0x81817F81, 0x817F7F7F, 0x8181817F, 0x817F7F7F, 0x817F7F81, 0x7F7F7F7F, 0x7F7F7F7F,
-0x81817F7F, 0x81817F81, 0x817F7F81, 0x817F7F7F, 0x817F817F, 0x81817F7F, 0x817F8181, 0x81817F7F,
-0x81817F81, 0x817F8181, 0x8181817F, 0x7F7F7F81, 0x7F7F7F81, 0x81818181, 0x817F7F7F, 0x7F817F7F,
-0x7F817F81, 0x81817F7F, 0x7F818181, 0x7F817F7F, 0x81817F81, 0x7F7F8181, 0x7F7F7F81, 0x81817F7F,
-0x7F81817F, 0x7F81817F, 0x817F817F, 0x7F817F7F, 0x7F7F7F7F, 0x7F81817F, 0x7F818181, 0x7F7F7F7F,
-0x7F7F7F81, 0x81818181, 0x7F81817F, 0x7F7F7F7F, 0x8181817F, 0x7F818181, 0x817F7F81, 0x7F818181,
-0x8181817F, 0x7F817F7F, 0x817F7F81, 0x7F7F817F, 0x7F7F7F81, 0x7F7F7F81, 0x7F817F7F, 0x817F817F,
-0x7F7F817F, 0x7F817F7F, 0x817F8181, 0x817F8181, 0x7F7F817F, 0x7F817F81, 0x817F7F7F, 0x7F7F7F81,
-0x817F7F81, 0x81817F81, 0x7F7F817F, 0x7F817F7F, 0x7F817F7F, 0x81817F81, 0x817F8181, 0x7F7F817F,
-0x817F7F7F, 0x81818181, 0x7F7F7F81, 0x7F81817F, 0x7F7F7F81, 0x817F8181, 0x8181817F, 0x7F817F81,
-0x81817F81, 0x7F7F7F81, 0x8181817F, 0x7F817F81, 0x7F7F8181, 0x817F7F81, 0x817F817F, 0x7F7F817F,
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-0x817F8181, 0x817F7F81, 0x817F8181, 0x817F7F7F, 0x7F818181, 0x7F818181, 0x81817F7F, 0x81817F81,
-0x7F7F8181, 0x7F818181, 0x81817F81, 0x7F7F817F, 0x7F7F7F81, 0x817F7F81, 0x7F7F7F81, 0x7F7F8181,
-0x817F8181, 0x8181817F, 0x81817F7F, 0x81817F7F, 0x7F7F7F7F, 0x7F7F8181, 0x81818181, 0x7F7F8181,
-0x81818181, 0x7F7F7F81, 0x7F818181, 0x7F7F8181, 0x817F7F7F, 0x81817F7F, 0x7F7F7F7F, 0x817F7F81,
-0x817F8181, 0x817F7F7F, 0x7F7F817F, 0x8181817F, 0x7F7F7F81, 0x817F8181, 0x7F7F817F, 0x817F7F81,
-0x81817F81, 0x81817F7F, 0x7F817F81, 0x817F7F81, 0x7F7F817F, 0x7F7F817F, 0x817F817F, 0x7F81817F,
-0x81817F7F, 0x817F817F, 0x7F81817F, 0x8181817F, 0x7F817F81, 0x7F81817F, 0x7F81817F, 0x7F818181,
-0x7F7F7F7F, 0x817F7F81, 0x81817F81, 0x7F817F81, 0x81818181, 0x81817F7F, 0x7F817F81, 0x7F7F7F7F,
-0x7F7F7F81, 0x81818181, 0x7F817F7F, 0x817F817F, 0x7F7F7F81, 0x81817F81, 0x817F7F81, 0x7F7F817F,
-0x81817F81, 0x7F818181, 0x7F818181, 0x81817F7F, 0x7F7F7F81, 0x817F8181, 0x81818181, 0x7F817F81,
-0x7F7F817F, 0x817F817F, 0x81817F7F, 0x817F7F7F, 0x81817F81, 0x7F7F7F7F, 0x7F817F7F, 0x81818181,
-0x81817F81, 0x81817F7F, 0x7F81817F, 0x817F7F7F, 0x7F7F7F7F, 0x81817F81, 0x7F7F7F81, 0x817F8181,
-0x81817F7F, 0x817F8181, 0x81818181, 0x817F817F, 0x817F8181, 0x7F81817F, 0x7F7F817F, 0x7F817F7F,
-0x7F7F817F, 0x817F817F, 0x817F8181, 0x8181817F, 0x817F7F7F, 0x81818181, 0x7F7F7F7F, 0x81817F7F,
-0x81817F7F, 0x7F7F7F81, 0x7F7F8181, 0x817F7F81, 0x7F7F7F81, 0x7F81817F, 0x81818181, 0x81818181,
-0x8181817F, 0x817F7F7F, 0x81817F81, 0x7F7F817F, 0x7F817F7F, 0x81817F81, 0x7F817F81, 0x81817F7F,
-0x7F81817F, 0x817F7F81, 0x7F7F7F81, 0x817F7F81, 0x7F817F7F, 0x7F7F7F7F, 0x817F817F, 0x7F7F7F7F,
-0x7F7F8181, 0x817F7F81, 0x7F7F7F7F, 0x817F7F81, 0x7F81817F, 0x817F7F81, 0x817F7F81, 0x81818181,
-0x817F817F, 0x817F817F, 0x7F81817F, 0x817F8181, 0x7F7F7F7F, 0x7F7F8181, 0x7F81817F, 0x7F7F7F81,
-0x7F7F817F, 0x7F7F817F, 0x7F7F817F, 0x7F7F7F7F, 0x7F7F7F7F, 0x817F817F, 0x817F7F7F, 0x81817F7F,
-0x81818181, 0x8181817F, 0x81817F81, 0x7F818181, 0x817F8181, 0x7F818181, 0x817F8181, 0x81818181,
-0x7F7F7F81, 0x81817F7F, 0x7F7F7F7F, 0x7F818181, 0x7F81817F, 0x7F7F7F7F, 0x81817F7F, 0x817F817F,
-0x7F7F817F, 0x8181817F, 0x7F81817F, 0x7F7F8181, 0x81817F81, 0x7F817F7F, 0x7F817F81, 0x81818181,
-0x817F7F81, 0x81818181, 0x7F81817F, 0x81818181, 0x7F817F81, 0x7F7F7F81, 0x7F7F8181, 0x7F817F81,
-0x7F817F81, 0x8181817F, 0x7F81817F, 0x817F817F, 0x817F817F, 0x81817F81, 0x817F817F, 0x81817F81,
-0x7F7F8181, 0x81817F7F, 0x7F817F81, 0x7F7F7F7F, 0x817F7F81, 0x817F8181, 0x817F817F, 0x817F7F81,
-0x81817F7F, 0x817F7F7F, 0x7F7F8181, 0x817F7F81, 0x817F7F81, 0x7F818181, 0x8181817F, 0x7F7F7F81,
-0x817F8181, 0x7F7F817F, 0x817F8181, 0x7F81817F, 0x7F81817F, 0x81817F7F, 0x7F7F7F7F, 0x817F7F7F,
-0x8181817F, 0x817F7F7F, 0x7F817F81, 0x7F817F7F, 0x81817F81, 0x81817F81, 0x81818181, 0x8181817F,
-0x817F817F, 0x7F817F7F, 0x817F817F, 0x7F7F7F7F, 0x8181817F, 0x817F817F, 0x817F817F, 0x7F817F81,
-0x8181817F, 0x8181817F, 0x7F7F8181, 0x7F818181, 0x7F817F7F, 0x8181817F, 0x81818181, 0x7F817F81,
-0x817F7F7F, 0x817F7F7F, 0x817F8181, 0x817F7F7F, 0x7F81817F, 0x7F818181, 0x817F8181, 0x7F81817F,
-0x7F817F7F, 0x8181817F, 0x817F8181, 0x817F817F, 0x817F817F, 0x81817F81, 0x8181817F, 0x7F817F81,
-0x7F7F817F, 0x7F7F7F81, 0x81817F81, 0x817F7F81, 0x7F817F7F, 0x7F81817F, 0x817F7F7F, 0x81817F81,
-0x817F817F, 0x81817F81, 0x8181817F, 0x7F817F7F, 0x817F7F7F, 0x817F7F7F, 0x7F817F81, 0x7F817F81,
-0x7F817F81, 0x817F8181, 0x7F7F8181, 0x7F7F817F, 0x7F81817F, 0x7F817F81, 0x7F7F817F, 0x7F817F81,
-0x817F8181, 0x81818181, 0x7F817F81, 0x7F7F7F81, 0x7F7F7F81, 0x7F818181, 0x817F8181, 0x817F8181,
-0x817F8181, 0x81817F7F, 0x817F7F7F, 0x7F7F7F81, 0x7F7F8181, 0x7F81817F, 0x81818181, 0x7F7F7F7F,
-0x7F818181, 0x817F817F, 0x817F7F81, 0x817F7F81, 0x8181817F, 0x817F7F81, 0x81818181, 0x817F7F81,
-0x81817F7F, 0x7F7F7F81, 0x7F817F7F, 0x7F7F8181, 0x7F7F8181, 0x7F7F817F, 0x7F7F7F7F, 0x7F7F7F7F,
-0x7F7F7F7F, 0x7F81817F, 0x81817F81, 0x7F818181, 0x7F81817F, 0x817F817F, 0x7F7F7F81, 0x7F7F817F,
-0x7F7F8181, 0x817F7F81, 0x817F7F7F, 0x7F817F7F, 0x7F81817F, 0x817F7F81, 0x8181817F, 0x81817F81,
-0x8181817F, 0x7F7F7F7F, 0x81818181, 0x7F7F7F7F, 0x81818181, 0x817F7F7F, 0x7F7F817F, 0x7F817F81,
-0x81817F81, 0x7F7F7F7F, 0x7F818181, 0x7F818181, 0x817F7F81, 0x81817F7F, 0x7F7F817F, 0x81818181,
-0x81818181, 0x7F7F8181, 0x7F7F7F7F, 0x7F7F7F7F, 0x7F817F81, 0x7F7F817F, 0x817F7F7F, 0x817F7F81,
-0x7F7F817F, 0x7F7F817F, 0x7F81817F, 0x8181817F, 0x7F7F7F81, 0x7F817F81, 0x7F7F7F7F, 0x81818181,
-0x81818181, 0x7F817F7F, 0x7F7F817F, 0x7F817F7F, 0x817F8181, 0x7F81817F, 0x8181817F, 0x81818181,
-0x7F817F7F, 0x81818181, 0x81818181, 0x81817F7F, 0x7F818181, 0x7F7F7F81, 0x81817F7F, 0x7F817F81,
-0x817F8181, 0x7F817F81, 0x817F7F7F, 0x817F8181, 0x817F817F, 0x7F7F7F7F, 0x7F7F7F81, 0x7F7F817F,
-0x7F7F8181, 0x7F81817F, 0x7F81817F, 0x7F7F7F81, 0x817F7F81, 0x7F7F7F7F, 0x81817F81, 0x81817F7F,
-0x7F817F81, 0x7F81817F, 0x7F818181, 0x817F7F7F, 0x817F817F, 0x81817F81, 0x7F817F7F, 0x7F817F81,
-0x81818181, 0x7F7F7F7F, 0x81817F7F, 0x817F7F7F, 0x7F818181, 0x7F817F7F, 0x7F7F7F7F, 0x7F7F7F81,
-0x817F7F7F, 0x81817F7F, 0x7F7F817F, 0x817F8181, 0x7F817F7F, 0x81818181, 0x817F8181, 0x817F817F,
-0x7F818181, 0x7F7F7F7F, 0x7F81817F, 0x81817F81, 0x81817F7F, 0x7F817F7F, 0x7F7F7F81, 0x817F7F81,
-0x817F7F81, 0x7F7F7F7F, 0x817F8181, 0x817F8181, 0x7F7F7F81, 0x817F7F7F, 0x81817F7F, 0x817F7F81,
-0x7F7F817F, 0x8181817F, 0x81818181, 0x817F817F, 0x7F7F7F81, 0x7F81817F, 0x7F817F81, 0x817F7F81,
-0x7F818181, 0x7F7F7F81, 0x81817F81, 0x7F817F7F, 0x81818181, 0x817F7F7F, 0x7F817F81, 0x817F8181,
-0x81817F81, 0x7F81817F, 0x7F7F8181, 0x81818181, 0x81817F7F, 0x8181817F, 0x7F81817F, 0x81817F7F,
-0x7F7F8181, 0x7F7F7F7F, 0x7F7F8181, 0x81817F81, 0x817F817F, 0x81818181, 0x817F817F, 0x817F7F81,
-0x7F7F817F, 0x817F7F81, 0x7F7F817F, 0x8181817F, 0x8181817F, 0x8181817F, 0x7F817F7F, 0x817F8181,
-0x81818181, 0x817F7F7F, 0x817F817F, 0x81818181, 0x7F81817F, 0x7F7F8181, 0x817F7F7F, 0x817F8181,
-0x817F7F81, 0x7F7F7F7F, 0x7F7F8181, 0x7F818181, 0x7F7F7F7F, 0x81817F7F, 0x81818181, 0x7F7F817F,
-0x817F817F, 0x817F7F7F, 0x7F817F7F, 0x7F7F7F7F, 0x8181817F, 0x817F7F81, 0x817F7F7F, 0x7F81817F,
-0x8181817F, 0x817F8181, 0x7F7F7F81, 0x7F817F81, 0x7F817F7F, 0x7F7F817F, 0x7F7F8181, 0x7F818181,
-0x8181817F, 0x7F7F817F, 0x7F81817F, 0x8181817F, 0x7F818181, 0x8181817F, 0x7F7F817F, 0x81817F7F,
-0x7F7F817F, 0x7F817F81, 0x817F8181, 0x817F7F7F, 0x817F817F, 0x7F818181, 0x7F817F81, 0x7F7F7F81,
-0x7F81817F, 0x817F7F81, 0x7F818181, 0x81817F81, 0x81817F81, 0x817F8181, 0x7F7F8181, 0x81818181,
-0x81818181, 0x7F81817F, 0x817F7F81, 0x7F817F81, 0x817F817F, 0x817F817F, 0x817F8181, 0x81818181,
-0x817F8181, 0x817F7F7F, 0x81817F7F, 0x81817F7F, 0x81817F81, 0x81818181, 0x7F7F8181, 0x81817F7F,
-0x7F7F7F81, 0x7F81817F, 0x81817F81, 0x7F7F817F, 0x81817F7F, 0x81817F81, 0x81818181, 0x7F7F7F7F,
-0x81817F81, 0x7F7F7F7F, 0x7F7F7F7F, 0x7F7F817F, 0x8181817F, 0x817F8181, 0x817F7F7F, 0x7F7F7F7F,
-0x81817F7F, 0x7F817F7F, 0x817F7F81, 0x7F7F817F, 0x817F7F81, 0x7F818181, 0x817F7F81, 0x81817F81,
-0x7F7F8181, 0x7F7F817F, 0x81817F7F, 0x7F818181, 0x7F7F7F81, 0x8181817F, 0x7F818181, 0x7F7F817F,
-0x7F7F7F81, 0x817F7F81, 0x7F817F7F, 0x7F818181, 0x8181817F, 0x7F7F8181, 0x81818181, 0x817F8181,
-0x7F817F7F, 0x7F81817F, 0x81818181, 0x817F8181, 0x7F81817F, 0x817F7F81, 0x81818181, 0x7F817F81,
-0x7F817F7F, 0x817F817F, 0x7F7F7F81, 0x7F7F7F81, 0x7F7F817F, 0x81818181, 0x817F8181, 0x7F7F7F7F,
-0x817F7F7F, 0x81818181, 0x81818181, 0x81818181, 0x7F7F8181, 0x7F7F817F, 0x81817F81, 0x817F7F81,
-0x7F81817F, 0x7F7F8181, 0x7F7F7F81, 0x7F817F7F, 0x81818181, 0x7F7F7F7F, 0x81817F7F, 0x7F7F7F7F,
-0x81817F7F, 0x7F7F817F, 0x7F7F7F81, 0x7F817F81, 0x817F817F, 0x7F817F81, 0x7F7F7F81, 0x7F817F7F,
-0x817F8181, 0x7F7F8181, 0x7F7F817F, 0x7F817F81, 0x81817F81, 0x81817F81, 0x817F817F, 0x7F818181,
-0x81818181, 0x817F817F, 0x817F7F81, 0x81818181, 0x817F7F7F, 0x7F7F8181, 0x7F817F81, 0x8181817F,
-0x7F7F7F81, 0x7F817F81, 0x7F7F8181, 0x81818181, 0x7F7F7F7F, 0x7F818181, 0x7F818181, 0x817F7F81,
-0x7F7F7F7F, 0x81818181, 0x7F817F7F, 0x8181817F, 0x81818181, 0x81817F7F, 0x81818181, 0x7F818181,
-0x81817F81, 0x7F81817F, 0x7F817F7F, 0x7F817F81, 0x7F81817F, 0x817F7F7F, 0x7F817F7F, 0x817F817F,
-0x817F7F7F, 0x81818181, 0x7F7F7F7F, 0x7F7F8181, 0x817F817F, 0x7F81817F, 0x81818181, 0x7F7F7F81,
-0x7F7F8181, 0x7F818181, 0x817F7F81, 0x7F818181, 0x817F817F, 0x7F817F81, 0x7F81817F, 0x7F817F7F,
-0x7F817F7F, 0x81817F7F, 0x81817F81, 0x817F7F7F, 0x81817F81, 0x817F7F81, 0x817F7F7F, 0x7F817F7F,
-0x817F817F, 0x7F7F8181, 0x817F8181, 0x817F817F, 0x7F7F7F81, 0x817F7F7F, 0x7F817F81, 0x7F817F7F,
-0x7F7F817F, 0x7F817F81, 0x81817F7F, 0x81817F81, 0x7F81817F, 0x81818181, 0x7F817F7F, 0x8181817F,
-0x817F8181, 0x7F7F7F81, 0x817F7F81, 0x817F817F, 0x817F8181, 0x7F818181, 0x7F81817F, 0x7F7F8181,
-0x7F81817F, 0x7F81817F, 0x81818181, 0x7F7F7F81, 0x7F818181, 0x817F7F81, 0x8181817F, 0x7F818181,
-0x7F7F817F, 0x81818181, 0x817F7F81, 0x7F817F81, 0x8181817F, 0x7F81817F, 0x817F8181, 0x7F7F8181,
-0x81818181, 0x7F7F817F, 0x7F818181, 0x817F7F7F, 0x817F7F81, 0x7F7F7F7F, 0x7F7F8181, 0x817F817F,
-0x817F7F81, 0x7F81817F, 0x817F817F, 0x8181817F, 0x7F7F7F81, 0x7F7F817F, 0x7F818181, 0x7F817F81,
-0x817F7F81, 0x7F818181, 0x81818181, 0x817F8181, 0x81817F7F, 0x7F817F81, 0x7F7F7F7F, 0x817F7F7F,
-0x7F7F817F, 0x817F8181, 0x817F7F7F, 0x7F817F81, 0x7F7F7F81, 0x7F818181, 0x7F81817F, 0x81818181,
-0x7F818181, 0x817F7F7F, 0x817F7F7F, 0x7F7F7F81, 0x817F8181, 0x81818181, 0x81817F81, 0x7F818181,
-0x81817F81, 0x817F8181, 0x7F81817F, 0x8181817F, 0x7F7F8181, 0x817F817F, 0x7F817F7F, 0x7F7F8181,
-0x817F7F81, 0x817F8181, 0x7F817F81, 0x7F818181, 0x7F7F8181, 0x81817F81, 0x817F817F, 0x7F81817F,
-0x7F818181, 0x7F7F7F81, 0x817F7F7F, 0x7F81817F, 0x817F7F7F, 0x8181817F, 0x81818181, 0x7F7F7F81,
-0x7F817F81, 0x7F818181, 0x7F7F817F, 0x7F817F81, 0x7F7F7F81, 0x81817F7F, 0x7F7F7F81, 0x7F7F7F81,
-0x7F817F81, 0x7F818181, 0x7F817F81, 0x7F7F7F7F, 0x7F81817F, 0x8181817F, 0x817F7F7F, 0x7F7F8181,
-0x81817F7F, 0x81817F7F, 0x7F818181, 0x81817F81, 0x81817F81, 0x7F7F817F, 0x817F8181, 0x817F8181,
-0x7F818181, 0x7F81817F, 0x8181817F, 0x7F7F817F, 0x81818181, 0x7F7F7F81, 0x81818181, 0x7F7F7F7F,
-0x817F817F, 0x7F7F7F7F, 0x7F7F8181, 0x817F817F, 0x7F818181, 0x817F7F81, 0x7F7F817F, 0x817F8181,
-0x7F817F81, 0x817F8181, 0x8181817F, 0x81817F7F, 0x7F817F81, 0x7F7F8181, 0x7F7F8181, 0x7F818181,
-0x817F8181, 0x7F7F7F81, 0x7F7F7F7F, 0x81818181, 0x7F7F7F81, 0x7F7F7F7F, 0x817F817F, 0x7F7F8181,
-0x817F7F7F, 0x7F817F81, 0x81817F81, 0x7F81817F, 0x81817F7F, 0x817F7F7F, 0x7F81817F, 0x7F817F81,
-0x7F7F7F7F, 0x817F7F7F, 0x7F817F81, 0x817F817F, 0x81817F81, 0x81817F7F, 0x7F817F81, 0x7F7F7F81,
-0x7F7F7F7F, 0x8181817F, 0x817F7F81, 0x7F81817F, 0x7F81817F, 0x81817F7F, 0x8181817F, 0x81817F7F,
-0x7F817F81, 0x7F818181, 0x817F817F, 0x81817F81, 0x7F7F8181, 0x817F7F81
-
-output0 =
-0x02524C20, 0xB9B1FEA2, 0xC1BAB7E5, 0xEF5714CB, 0x7DE6A64D, 0xA05F9DC9, 0x0747D1E3, 0x3B20BC86,
-0x6FCBDB0F, 0xF2FB7A23, 0x79D5E062, 0x5BF4E7C3, 0xD4A68A37, 0x07B4A6AD, 0x37E911F9, 0x7FE7B30A,
-0xBBC284A2, 0xD38D6136, 0x25FAB76B, 0xBEBBF534, 0x9A88F9DB, 0xE37FD52D, 0x691DD493, 0xED2F738C,
-0x89A96EA0, 0xD981246A, 0x17CC820E, 0x07E3B463, 0xC9FC2590, 0x7475A33C, 0xA5151BB4, 0x1F7E759E,
-0x9554F964, 0xD0FA01F4, 0xD31774D2, 0xEB73A9F6, 0x8C9FBCB1, 0xF83010FB, 0x1909E09F, 0xC46023EB,
-0x02AEDC62, 0xC6352CC7, 0x674BDC6D, 0xE17CD747, 0x4E25B0B3, 0x4BFF6B17, 0x12C9AAA3, 0xC2BC91CD,
-0x44BE23A2, 0x8A72A157, 0x6E0DAD1F, 0x6CA69A09, 0xB55B582E, 0x01818B31, 0x5CA5CAB6, 0x1917AB24,
-0x38F98BCD, 0x01917487, 0x05906FDD, 0x760AFCBA, 0x19671085, 0x64E3546E, 0xEC10F922, 0x3CF286CA,
-0x68E273EA, 0xF1001325, 0x5DCB3B49, 0xE9547370, 0x65D26AE6, 0xF621256C, 0x25D6D99C, 0x7862EBA0,
-0x43365DB0, 0x4DBF06C5, 0x92FCAA02, 0xB0FD58FA, 0x910E80A6, 0x93D24A67, 0x6E39B144, 0x3D46D6F6,
-0xEDC55081, 0x33CD70C7, 0xC74B6E8E, 0x91AA27B9, 0x55B3542D, 0xEBF8046A, 0xB9ABDB94, 0x97FC38A8,
-0xD5837B4D, 0x764B1809, 0xFBE2096A, 0xC23887AC, 0x2A45029B, 0xCBB7DF70, 0x674654E1, 0x0C6A06BD,
-0xB3E8853E, 0x03FCC4CE, 0x26806F2E, 0x2CEB35B0, 0x10538B03, 0x94B059B8, 0xA95E7FFA, 0x48AD3D0A,
-0xEB9091E1, 0x972E31EF, 0x5EBC6F8F, 0x947FF108, 0xCB3123FA, 0xFEE1D939, 0xF3DC5C49, 0xA92927AE,
-0xF49BB8D0, 0xAA59F730, 0x4A66D1CD, 0x030E1ADF, 0x238D5B19, 0x96F861F1, 0x915424E4, 0x9127880C,
-0x8E779839, 0x87375FCE, 0x61FB3D79, 0x96B1EE83, 0x47BF6667, 0x19E7D408, 0x7E91137F, 0x0E4AD8E8,
-0xDABD2E45, 0x9B60873F, 0xD0294A65, 0x2A38A862, 0x59DD046D, 0x9832BB79, 0xA5870DB6, 0xB3F1CC48,
-0x7E9A8132, 0xEEA2E4BC, 0xF23ED87B, 0x550E011F, 0x9620E0C0, 0xE7CF0834, 0xDEE69623, 0x6184D512,
-0xD3D55728, 0xFA7711D4, 0x9C77B0F9, 0x8A26462B, 0xB3F5C8D5, 0x1123246D, 0x78F36272, 0x940EE0F9,
-0x757BF240, 0x7EE2B6D0, 0xD40FD5A1, 0xAB4205CA, 0x96E6B758, 0xAC5F4294, 0xC9268C66, 0xB48DC535,
-0x3CF6ED4C, 0xF187EFED, 0x7A09B08D, 0x8709EFCE, 0x267B2468, 0x0015D770, 0xDF1B90BF, 0xA03DAD85,
-0x2633012E, 0xE5437125, 0x58B79AFF, 0xB929C532, 0x6D890DC9, 0x89A59AD2, 0x2BB99316, 0x41B5B0EB,
-0x7304B295, 0xB37F6708, 0x2F84A68E, 0x3637D79A, 0xDD36687B, 0x904BF7B6, 0x6A2CF453, 0x733DED54,
-0x5DF48BAA, 0xC3FCC99F, 0x8E3BE1DB, 0x61D9CF2D, 0xB7DC202B, 0xA959FF95, 0x860D0F14, 0x4008C478,
-0xD9325A51, 0x27A29D4C, 0x308FE6D4, 0x7A1AA889, 0x5BD38393, 0xCBCBFA5D, 0x7C7B
-
-basegraph=
-1
-
-z_c=
-320
-
-n_cb=
-21120
-
-q_m=
-4
-
-n_filler=
-688
-
-e =
-21592
-
-rv_index =
-0
-
-code_block_mode =
-1
-
-iter_max =
-20
-
-expected_iter_count =
-3
-
-op_flags =
-RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE, RTE_BBDEV_LDPC_CRC_TYPE_24B_CHECK
-
-expected_status =
-OK
diff --git a/app/test-bbdev/test_vectors/ldpc_dec_v9503.data b/app/test-bbdev/test_vectors/ldpc_dec_v9503.data
index e645602..7699ae3 100644
--- a/app/test-bbdev/test_vectors/ldpc_dec_v9503.data
+++ b/app/test-bbdev/test_vectors/ldpc_dec_v9503.data
@@ -1176,7 +1176,7 @@ output0 =
 0xEB989F98, 0x1141D335, 0x442C699F, 0x82E9758B, 0x267E6D4D, 0x71BAC54A, 0x2FBCBD52, 0xA0966795,
 0xEB08B437, 0x1A9899A0, 0x26484B82, 0x3AEE43A8, 0xC409BE45, 0xCF8C6EC9, 0x098DE63F, 0xC3BEA60B,
 0xCB7A5B6A, 0xCBF2A44B, 0x31E9FA4C, 0x34FD7E88, 0xA3C5AF89, 0xF13C8E2B, 0xC01C79FA, 0x622B9FD8,
-0x692D4C4F, 0x712BC24C, 0x16FBD6C3, 0x7B1BBC38, 0x63F1E328, 0x824C6F4B, 0xDC
+0x692D4C4F, 0x712BC24C, 0x16FBD6C3, 0x7B1BBC38, 0x63F1E328, 0x6F4B
 
 basegraph=
 2
@@ -1209,7 +1209,7 @@ expected_iter_count =
 3
 
 op_flags =
-RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE, RTE_BBDEV_LDPC_CRC_TYPE_24B_CHECK
+RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE, RTE_BBDEV_LDPC_CRC_TYPE_24B_CHECK, RTE_BBDEV_LDPC_CRC_TYPE_24B_DROP
 
 expected_status =
 OK
diff --git a/app/test-bbdev/test_vectors/turbo_dec_c1_k6144_r0_e34560_negllr.data b/app/test-bbdev/test_vectors/turbo_dec_c1_k6144_r0_e34560_negllr.data
deleted file mode 100644
index e946963..0000000
--- a/app/test-bbdev/test_vectors/turbo_dec_c1_k6144_r0_e34560_negllr.data
+++ /dev/null
@@ -1,645 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-# Copyright(c) 2017 Intel Corporation
-
-op_type =
-RTE_BBDEV_OP_TURBO_DEC
-
-input0 =
-0x7f7fb2e1, 0x467f05ef, 0x3cabba6a, 0x1f826cac, 0xbe817fe7, 0x584dab0f, 0xdcb55f81, 0xe47f915f,
-0x37b1a534, 0x4b478145, 0x9db5727f, 0x7fa6943f, 0x819550ea, 0xd18eb72a, 0xa0ba9c10, 0xcf7f817f,
-0x915a957f, 0x2c699d0a, 0x89815c0f, 0x7f569358, 0x1002587f, 0x54314130, 0x817f1b7e, 0x81a85e2a,
-0x5981bdf2, 0x0c81b00f, 0x6781be0e, 0x297fb17f, 0xfd811fb3, 0x7f077fdb, 0xd37fc2ab, 0x817f1024,
-0x81817f7f, 0x3d848ec6, 0x4486cd9c, 0x7f6d7f81, 0x1d7ffa93, 0x813648ca, 0xdc7f125e, 0xaa81a798,
-0x60838ef4, 0x815fcdbd, 0x81cb9d93, 0x817f8188, 0xc8c3d697, 0x817af2d6, 0x36888781, 0x818117ee,
-0x37a67fbf, 0x89f464b2, 0x7f1e7f81, 0x7fe5c17f, 0x8ca1effc, 0xed7f82cf, 0x4a7f5ac6, 0x7fffb8d6,
-0x427f7f73, 0x747f7f06, 0xdfcd22a9, 0x7fb99981, 0x76f77381, 0x2cd70f12, 0xd8b138e1, 0x81a4ea29,
-0x222db281, 0xc3a07fd2, 0x217f8177, 0xd1cd87c4, 0xd181679f, 0x7f7fdee2, 0x7c81a72f, 0x6e7f5a7f,
-0x77b0c96d, 0xff7f8110, 0xe8c6ad46, 0x376ade0a, 0x447f687f, 0x5916d238, 0x88816b81, 0xda7f6d88,
-0xe2b2b55f, 0x750f7fc8, 0xc624d47f, 0xc6837f79, 0x81de5272, 0xd0847f29, 0x81ad587f, 0x3e7f7f61,
-0xc803e070, 0x237ff600, 0x8c01815e, 0x814e0e81, 0x81657eef, 0xab2a62bc, 0x73d42cb4, 0xaaf03a8a,
-0x817fa57f, 0x5e7fe2c3, 0x6deda37f, 0x6e87818d, 0x767f6e4d, 0x5c76819a, 0x8182b6f0, 0xdcd3037f,
-0x81184c7f, 0x7ff1501c, 0x22c7f159, 0x45a6817f, 0x9b53c5e7, 0x57966a5e, 0x0a7f7f81, 0x4a5c155e,
-0xf37fff81, 0xad97f8f2, 0x052f397f, 0x79638181, 0x7f7f7f7f, 0x81e3fae4, 0x7659cf03, 0xbd7a5a81,
-0x46bcab7f, 0xa57f69a1, 0xba818186, 0x38a347a2, 0x91a88ec0, 0xd76087fc, 0x81818b8c, 0x7fa3424e,
-0x7f89ef7f, 0x81ac183d, 0x3aa8912a, 0xc4937da6, 0x7a4c136b, 0x81568e05, 0x8182812b, 0xebb17f1d,
-0x84b87f4c, 0xf4eab6c9, 0x81034197, 0x8183bd0a, 0xa1b92676, 0xceca2ef1, 0x9b7f7f7f, 0x5d813181,
-0x817fea35, 0x0a6c81b0, 0x9a559b4f, 0x93987691, 0xad819510, 0xa47ab324, 0xfa577f7f, 0xbba8ac3e,
-0x6694b753, 0xee63c4d7, 0x17b4ce81, 0x83c0dc81, 0x6a7f4481, 0x81d87fe0, 0x7f5cc5c0, 0xf828ea77,
-0xbb817fa3, 0x3e816619, 0x817f6aab, 0x26417f7f, 0x0c40817f, 0x9cf01834, 0x32b37f7f, 0xe74fd0a7,
-0x7f7f4167, 0x0e7f6ae0, 0x813d81b2, 0x8172027f, 0x4ea6c275, 0x814525de, 0x46817f7f, 0x7fcb2cd1,
-0x7f8198ca, 0x3d7f60aa, 0x8d7fac81, 0xe2c081ed, 0x656f8181, 0xb2ae9365, 0x6ddd8d81, 0x86e0be65,
-0x5495ec58, 0xcb981829, 0x429ee669, 0x81445fc5, 0xd3435724, 0xce51b323, 0x92b16972, 0xf0137f8e,
-0x7f199a7f, 0x81be813c, 0x8155817f, 0xd481037f, 0x167f8181, 0x5ad131d4, 0x7fbc4149, 0x81046d60,
-0x87174b9c, 0x94bc63ba, 0x68817c7f, 0x12ef7f8d, 0x7a81f4f6, 0x7f7f6db9, 0x4823417e, 0xa4989a48,
-0x7e4c787f, 0xa47f8123, 0x819afb20, 0xbf7f447f, 0x8d95af5c, 0x33a6812e, 0x07c75cd5, 0x337f8151,
-0xa2e5e15a, 0x847f7209, 0xf9f4b934, 0x72a77f2f, 0x1a9f2f7e, 0xac224bb2, 0x81467f0c, 0x3f8fd28d,
-0x4a78b07a, 0x5269a71e, 0x4fd57fb2, 0x0b5262bf, 0xea39ca0a, 0x577f3d1e, 0x509481d7, 0xb7816b48,
-0x35c31d7f, 0x818bdc1d, 0x24087fb9, 0x7fe27f07, 0x55866481, 0x7f9edd28, 0x07811ed1, 0x1b317fb2,
-0x8cb19dee, 0x396920a6, 0xd965dd85, 0x9ed5ff47, 0xc97f7f7f, 0x7f8c1d55, 0x06a69701, 0x9e348881,
-0x7f6cb281, 0x388181d1, 0xd07d61ac, 0x7fdef7f1, 0x08177f7f, 0xd87fa1c0, 0xfe9ebeb5, 0x813d3430,
-0x2181811e, 0xf4dab306, 0xa36bbb7f, 0x05e87f7f, 0x957ff3cd, 0xe4814219, 0x7fbf3f81, 0x818a7fab,
-0x43e081d9, 0x87c08729, 0x0db52785, 0x8181b0da, 0x4c94697e, 0x817fa9b2, 0x7f7f81d9, 0x8bda8193,
-0xb6811781, 0x81796220, 0xdb082ac1, 0x2c7f5d3b, 0x8c8103f3, 0x4dcbd01e, 0x7fc1a87f, 0x457f7f23,
-0x5e26bad6, 0x7f8174f3, 0x30109f08, 0xef8526cc, 0xe8690849, 0xd2b981b0, 0x7f7f7fb5, 0x8156ef7f,
-0x921a7f98, 0x7fe6681e, 0x244e497c, 0x5ef68149, 0xbfbcaa7f, 0xf5011204, 0xfe7f8163, 0x8cd08f31,
-0xc88a6b43, 0x7c8105b6, 0xf6d881aa, 0x074c2c2d, 0xd6815c7f, 0x1d15d265, 0xce816f0c, 0x14c77f2e,
-0x9a7f08c4, 0x1a8b8ed2, 0xbe9637ed, 0xb59fac5a, 0xa4d07f91, 0x7f847fab, 0xd981597f, 0x7328575d,
-0xb83af760, 0xb536b941, 0x81c1937f, 0x16b7814d, 0x3f7fb081, 0x7f41e102, 0x727f77ea, 0x9558c381,
-0x48ac819e, 0xa87f99f2, 0x819e7f05, 0x92816eb0, 0x59447f81, 0x4f6cb056, 0x818163a8, 0xe00a64e2,
-0x81bb7fa3, 0x7f816de7, 0x86ac6a50, 0x48a277b0, 0x8e37cd81, 0x7f88e646, 0x023351d8, 0x1ee7a64b,
-0x8145f239, 0x81810859, 0x557f7f7f, 0x6971d292, 0x813d7fdf, 0xe86cade7, 0xdab67f7f, 0x6d4f247f,
-0x9df2297f, 0x1e8172ec, 0x3f81a56d, 0x907f02d3, 0x45663970, 0x817f46a4, 0x817fd1ce, 0x9843b181,
-0x7fdf817f, 0x784881da, 0xd8a281c2, 0xd77f88d8, 0x8c81817f, 0xeb625633, 0x73fe4eae, 0x57787f19,
-0x7f81ea7f, 0xca8143c8, 0x767cbf1d, 0x7fbc81e1, 0x7f9bbeb5, 0x7fea8a12, 0x7f5c7fde, 0xb5fe1685,
-0xa4da81c8, 0x7f6b542e, 0x81814b7f, 0x6252f7d3, 0x55eebb81, 0x6a0824cf, 0x586128f0, 0xded58181,
-0xe32a819b, 0x79c67f20, 0xf2812781, 0x7f58c369, 0x7ffa2d7f, 0x817f81f4, 0x7ffc2c07, 0x457f9981,
-0xff4281c7, 0xd78e6955, 0x3e10e57f, 0x632b817f, 0x7f0197d1, 0x813e7feb, 0xf981ac81, 0x8f81317f,
-0xc37f137d, 0x01918101, 0x81b007a4, 0xaab059ad, 0x7f7f81f7, 0x6ac590a9, 0x817f81a0, 0x68816067,
-0x0ae08182, 0xb47fb268, 0x33d94a7f, 0xbf43d243, 0xccff8e4e, 0x44ebe23f, 0x0d4cfd2e, 0x7f81947f,
-0x81d1cee8, 0xda0e16a3, 0x34a74376, 0x117b81ae, 0x1d853f6b, 0x81d6d2ed, 0x8d7f5be6, 0xcf1fb4a0,
-0x3e1ec13a, 0x7fed0cf4, 0x65d3817f, 0x0a1fec83, 0x7fc4811f, 0x666381c1, 0x8147c754, 0xa9cf7f53,
-0xa076cf81, 0x4c7a4712, 0x1a814ff5, 0x9e7f8175, 0x8181698b, 0x7f1a7f63, 0x8191f19f, 0xb1037fa8,
-0x7f52aa2e, 0x42b65c09, 0x94afab7f, 0xbda37dda, 0x81f2d66b, 0x3e737f1f, 0xcb816031, 0xd56181ef,
-0x2c6ffb81, 0x44852329, 0x1b4b81cc, 0x055a7bb7, 0x4c6f2e1d, 0xb14ae1b7, 0x7f43c2c4, 0x2368b80d,
-0x7f7ffb9f, 0x990b0523, 0x74b33ea5, 0xd64c8199, 0x98ed81a2, 0x311bc8e9, 0x599963cf, 0xb0eeed4c,
-0x8181ed70, 0x42023428, 0xd00270bc, 0x812a7fd3, 0x7fc4101a, 0x3448d8db, 0x068814a8, 0xfeb5701c,
-0x46db1481, 0x3cc5b001, 0x8181c2b3, 0x9c3d7f7f, 0x7f13e346, 0x2b75819c, 0xf57fcfe1, 0xfdaac581,
-0x7f814c6f, 0x7f186b39, 0x7f818150, 0xea7f5b7f, 0x816776b0, 0xb8657f57, 0x7f447f5e, 0xc3628122,
-0x84849d7f, 0x7f8cb914, 0x92813dd5, 0x81557a3a, 0x6b4cbf7f, 0xc6818b94, 0x7fbb7f98, 0x3c88812d,
-0x8de4267f, 0x8dee81fd, 0x37f98131, 0x3d8164d2, 0xd97f8181, 0x3ccaebf9, 0x8165cb7f, 0x63cb81d3,
-0x817fea94, 0x48817fa1, 0x4ea0b16b, 0x3cb5ab6f, 0x3148f975, 0x8c7f1ab5, 0x7fae5a87, 0xad06c881,
-0x0681c187, 0x81a5a11b, 0xe29ea383, 0xf07f536d, 0x81b0e702, 0xc37fbb59, 0x9e6167e8, 0x3f55c9be,
-0x819a40a9, 0x6450b823, 0x15927b65, 0x72a149d4, 0x6c280b5c, 0x5d7fd8f3, 0x998d831a, 0xbb7f817f,
-0x10ab3f81, 0x96f65101, 0x257f743a, 0x7f04a024, 0xe0c981b4, 0x81163a22, 0x8e197481, 0x21addfdc,
-0x7f2dcdaa, 0x787f4407, 0x6b7f81ce, 0x9fd252c5, 0x85e8979b, 0xb049819d, 0x8f7f7f4d, 0xbe284c7f,
-0x78135181, 0x5d33db0a, 0x8123817f, 0x81496a7f, 0x81889281, 0x8145bf37, 0x2e9f7fdf, 0xe4543a2d,
-0x811e6024, 0x7f62e6ba, 0xaad07f1f, 0x4f73894f, 0x4c7f8181, 0x57817f06, 0xd27feb81, 0xcf1a815c,
-0xa57fbe7f, 0x684f7fdc, 0x81f6cbc0, 0xb72bf82f, 0xda6d448f, 0xc6157f36, 0x7f81407f, 0x9a8c4719,
-0x5fdf81dd, 0xaf817f0f, 0x813c11da, 0xd7ec1181, 0x570186e7, 0x8181f41e, 0xe5b8a2bb, 0x819051f3,
-0x2a7fd68f, 0x37a13ac3, 0x5b81fd38, 0x6342817f, 0x84697f6e, 0x7f5eddfa, 0x6abc81d1, 0x8151d9d8,
-0x3e5c6c53, 0x2b397fc6, 0x60d58548, 0xc540b213, 0x67815781, 0x89983030, 0x767c7f81, 0x71effe3a,
-0x817feb42, 0x05818897, 0x810ea318, 0x99bb0e8a, 0xf1dd4b7b, 0xae6dcbae, 0x8155adc0, 0x15b4c0c1,
-0x81ac9b14, 0x895057be, 0x9599d781, 0x38968fcd, 0x8171e981, 0x7a62d80c, 0x8681509a, 0x7f5d489b,
-0xa381467f, 0x7fa12952, 0xa07f8109, 0x5acd5d7f, 0xbb7fc77f, 0x531f3429, 0x7fb77f5a, 0x566d89f6,
-0x817d4c23, 0x406a81e6, 0x1381c99c, 0xad89d258, 0xa67f0cad, 0x510b916e, 0x7ffa81a1, 0x0b6a11e1,
-0x2be02284, 0x7f4e4338, 0x817fd023, 0x058174bf, 0x677f950a, 0x97a6a01d, 0x81817f81, 0x136881da,
-0x717f7f9a, 0xbf811404, 0x6714c965, 0x51828181, 0xcaf329a1, 0x8881bc0a, 0x7f7d8305, 0x2c7f5a7f,
-0x7f7f63e9, 0x797fced4, 0x818154f5, 0xf13681c4, 0xc04b1d81, 0x0e81d244, 0xbf3f66bf, 0x5a3f2d7f,
-0xfa931714, 0xce485844, 0x263ae55b, 0x7fd37f81, 0x79477ee4, 0x7f8187e0, 0x81ab8144, 0x7f8d7f7f,
-0x6f715068, 0x7f5577f6, 0x7f487f41, 0x81813b84, 0x33431981, 0x81a181c6, 0xca1b667f, 0xe75a7f71,
-0x168128b0, 0xe0a092d5, 0x6e8164de, 0x2e817f61, 0xc4b1818d, 0xea7f8a32, 0x1098817f, 0x14a18156,
-0xdd568862, 0xd3176a4b, 0x81308181, 0x697b3faa, 0xe256cecb, 0x697f1691, 0x4e228c05, 0x7fa6682a,
-0x7449816e, 0x4558a15f, 0x9f513638, 0x7f7f819c, 0x7fb77aa1, 0x5eaf4912, 0x14817f7f, 0x0853817c,
-0xa47fbe41, 0xdfd77f0e, 0x81371d7f, 0xc9cd7299, 0x81d0673a, 0xb133492f, 0xfd7f4003, 0x897f7f1c,
-0x1990d405, 0x9f3ee2bd, 0xc168817f, 0xc6f57fa4, 0x83ee483e, 0x90f781f6, 0x81dcb39d, 0xd37fe881,
-0x28819181, 0x83da81d4, 0x7251dc7a, 0x7928ffc3, 0x7bca8181, 0x7f7f817b, 0xf6fa907f, 0x37916bd4,
-0x0d3fbc7b, 0xde81bdd0, 0xa0147fdc, 0xbf0f7f0b, 0x25958132, 0x7f6c9931, 0x7f44812c, 0xd4868181,
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-0x7f7f9569, 0xa31d812f, 0x81d48457, 0x7f88bcfe, 0xd743b981, 0x7f608102, 0x18de2185, 0x81d77fc4,
-0x937f337f, 0xe67fe52e, 0x95d481da, 0x887f6071, 0x81301872, 0xd9088132, 0x7f7f5a81, 0x8181aba8,
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-0x987a5757, 0x5debc016, 0xa64eb973, 0x61a51b81, 0x66509c7f, 0xeb7ad965, 0x7ada817f, 0x4d5bf7bc,
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-0x78d73d7f, 0x7295109a, 0x05897f55, 0xbdc07281, 0x81817fe3, 0xcd157f30, 0x489ca757, 0x53468119,
-0x3f6a81b8, 0x03fe7c43, 0xb511cda3, 0xe581a17f, 0x5e3e3ec9, 0x7f507f96, 0xbe12a481, 0x81006ddd,
-0x49322cb4, 0x27f7a81e, 0xc6085618, 0x8148d270, 0x68668181, 0xec5ed498, 0xa011833a, 0x81475300,
-0x071d3a63, 0xa2c55142, 0x7fe9767f, 0x6e3c21fe, 0xeb63814a, 0x7fd57ffd, 0x9f91630b, 0x475f219f,
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-0x1b7c017e, 0x8581aac9, 0x627fa790, 0xaf837f7f, 0x69064681, 0x311d32e9, 0x6f7f0ba1, 0x7b81a1c5,
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-0xb37f7fbb, 0xc87f8ec5, 0x81b08181, 0x5bcb8136, 0x7f2524c5, 0xf5e881d8, 0x50ceaf7f, 0xf72387a1,
-0xd4c74e74, 0x663f7fe8, 0x26ae4a7f, 0x5d7f6358, 0x8178bbdb, 0x46f38102, 0xb0327f53, 0xa019f297,
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-0xaf4b817f, 0xca523d00, 0x81817fbf, 0x3b145a81, 0xec54886e, 0x81cb173e, 0x5f02667f, 0x967a8181,
-0x8a817f81, 0x3cb93c41, 0xfa811336, 0x74feb5a9, 0x821b9081, 0xaea865af, 0xf17f4e71, 0x52810059,
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-0xc37f81cd, 0x43553306, 0xa63d7f81, 0x7f7f8140, 0x7f7f818a, 0x7d82bd27, 0x817f8b7f, 0xa3579535,
-0xc2e47871, 0x81815a0b, 0x49977081, 0x724cc372, 0xc681c27f, 0x2b7cabf0, 0x3081a6ac, 0xec7f964e,
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-0xb1401a7f, 0x7fb57f9d, 0xefbb8175, 0x66892581, 0x7f06fa7f, 0x817a90f0, 0x7bd5793b, 0xc37ead24,
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-0x908164f7, 0xe41a7fc5, 0xe944503a, 0xeb4b6559, 0x22817f81, 0x816ea8ff, 0x1557e37f, 0xaa7f701c,
-0x817f828e, 0x738106c4, 0x7e0e7f05, 0xac768181, 0x17898158, 0xc081ea33, 0x827f9958, 0x3b7fd4fc,
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-0xf9a54748, 0x317d6469, 0xe0466f8a, 0xef869693, 0x3da5a9e2, 0x7f7f05a1, 0x14c68157, 0xc2148135,
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-0x9c2b817f, 0xde7ffb85, 0xe18117ca, 0x67fd7f7f, 0x3fbbf57f, 0x9b34ad7a, 0x487a543f, 0xf06322f8,
-0x9ce93023, 0x3581818a, 0x6a7f4d69, 0xad3d627f, 0xbd812c92, 0x8be4cc7f, 0x23b47fc4, 0xc87f819b,
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-0xb09f9144, 0x6ec23f94, 0xdf7f39c6, 0x48087f7f, 0xfc818184, 0x18815bc3, 0xc764598b, 0x11ed68c7,
-0x81df81bd, 0x7feceb38, 0xc90a473a, 0x81817f81, 0xef3a537f, 0x7f4d3873, 0xf45c846f, 0xfeb68afc,
-0xd326d181, 0x7fe4ae7f, 0x3e817fb5, 0x81c95de9, 0xbebdcd7f, 0x23053726, 0xdd8d8181, 0x1d545233,
-0xe37c933d, 0x81e52c1d, 0xc0ab2d81, 0x81e2667f, 0xcf2e70db, 0x9370319c, 0x21add116, 0xe6c34081,
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-0x45815295, 0x2dbc2581, 0x50bde53d, 0xcd8cb1bc, 0x2e67977f, 0x32fc789f, 0x2b81ca3f, 0xef7f7f61,
-0x19a7d611, 0x81427f81, 0xe98181fc, 0xd4397d7f, 0xd9ab7fb7, 0x819c8c92, 0xd5478339, 0xf0555aae,
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-0x707f447f, 0x9181c079, 0x72ae8173, 0x988d2a78, 0x7f814478, 0xb57fa076, 0xde7fb260, 0x17817f3b,
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-0xb2817fad, 0x5884bec5, 0xd629b07f, 0xb67f81cb, 0xcb81abe9, 0xab7f9b7f, 0x35815781, 0x85878181,
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-0x20534bc6, 0xb729727f, 0x6481de5c, 0xffc8a5e9, 0x707f25f2, 0xc674ba57, 0xe2ff9cb8, 0x02433e79,
-0x108e223b, 0x617f9cd7, 0xb5507f81, 0xa6f63ee6, 0x09b45856, 0x7e7fe581, 0xe4f8417f, 0xe11d98be,
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-0xe57f7f05, 0x16880f81, 0xa6e88184, 0x818490a2, 0xd5a87f94, 0x8b81a081, 0x38813781, 0x14a59a5a,
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-0xb18181c8, 0x7f54eb08, 0xd4c9db57, 0x68a981b2, 0x4ef17f69, 0x917f977f, 0xda38865e, 0xe97f3e5f,
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-0xd681d0b0, 0xe614c8a9, 0x53577f7f, 0xdabc3012, 0x353ecdc2, 0x81728179, 0xb660cf7f, 0xef49ca49,
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-0xcd44df7f, 0xa2878439, 0xd6f040b9, 0x6f86817f, 0xc67f7f81, 0x7f693443, 0x8d21b1ce, 0xdab1aed5,
-0x3f17ae71, 0x45b7ba7f, 0x05229255, 0xb181d8f5, 0x688681e3, 0xea81e181, 0xf57f817f, 0x7fdc5881,
-0x6e817f7f, 0x817f537a, 0x3987247f, 0x300a7f05, 0x3128057f, 0xe731b77f, 0x4881b50b, 0xb86dae65,
-0x00c015a0, 0x81397552, 0xb9bcab24, 0xf5818181, 0x57d18190, 0x81c3648d, 0xed813a67, 0x4c5d3a06,
-0x3581a4e3, 0x64db6467, 0x21af7d27, 0x5adf7f57, 0x66d9c99f, 0x5b183375, 0xbf4c41e5, 0x577f7ff0,
-0x4e818181, 0xf295493c, 0xd2c28170, 0x5c3a7f8e, 0x09c18181, 0x7f7f7f9c, 0xae675fa9, 0xf6d781a4,
-0x66ba10dc, 0x7f882981, 0xfe7f7f7f, 0x7f7ffea4, 0x2798d845, 0x899cb6fb, 0x4982bcd9, 0xc0815ab0,
-0x558181aa, 0x52110702, 0xd179e3c5, 0x482923bd, 0x187f8181, 0x81b3f6d9, 0xfd96a581, 0x2c5d1a81,
-0x6fde23dd, 0x9e815063, 0xfba49bcc, 0xfa775f4d, 0xb1b8b681, 0x81894f1b, 0x3c8163fa, 0x2d7f3d81,
-0xc57f6681, 0xbd7f7e81, 0x137f7f81, 0x6b3d6f81, 0xe5e2610d, 0xb4683186, 0x7f6e817f, 0x90c12abc,
-0x13a3502a, 0xdddeaa8c, 0x07a67f79, 0x1a5481ce, 0xb87fb01b, 0x0a4b1e7f, 0xd77ffcb7, 0x03535781,
-0x5a5f697f, 0x02ca7966, 0x379638bb, 0xc507c941, 0x5e7fdf8e, 0x7ce0c99b, 0xa162ccfd, 0xff8196cc,
-0xd43aa081, 0x67798185, 0xd6277f2e, 0x7f6dcb7f, 0x217fcd76, 0x2c88fb91, 0x06815b8f, 0xe37f7dae,
-0xe937257f, 0x648181ae, 0x21652c4f, 0xbf81685b, 0x36abe921, 0x3cb5de30, 0xa88e8162, 0xd87f812b,
-0xb981d14d, 0x75c181a7, 0xf7c08aa1, 0x57904e7f, 0xf6f688d8, 0x7fcf6281, 0xd33dbf7f, 0xc07f9a73,
-0x197f8135, 0xcabf8bc6, 0x3f81c37f, 0x487fac4f, 0x8ddc924b, 0x50257f7a, 0xf75e1496, 0x28d2d48f,
-0xcd91817f, 0x2a7f81b2, 0xbd7fb67f, 0x3b877fe1, 0x407fd8fd, 0xbc815f20, 0x7f50e581, 0x8bdfae4d,
-0xb1eb7f81, 0x07819f40, 0x3765274c, 0xde7fd081, 0xa0817f7f, 0x8dbe5081, 0xfa436f7f, 0x4848463b,
-0xc5c45cdb, 0x7f8b1865, 0x5bf381b6, 0x45aa497f, 0x7f813694, 0x54f15918, 0x72886c49, 0xe3fb31b0,
-0x0db1a582, 0x4aadce1b, 0x39926d8b, 0x9a30a85f, 0x1b606181, 0x1c6d165b, 0xfb057f4b, 0xcd7f81ec,
-0x12bf7ffb, 0x7f5f91d4, 0xca8158b7, 0x86134234, 0xf0f17f3c, 0x7f4e05c4, 0x34814f7f, 0xe5c1106a,
-0x2d50c67f, 0xb57fa18b, 0xb7816481, 0x7fffaadb, 0x607f817f, 0x5048ea81, 0x82495d02, 0x17819b7b,
-0xaba67981, 0xb5817f7f, 0xee57a2b6, 0x3591a602, 0x2885a153, 0x429ba160, 0x757fd0f5, 0x344e9d7f,
-0xc77a7f8d, 0x2a7f8160, 0x3198b27f, 0x81c552bd, 0x0374e058, 0x31605de1, 0x40d0817f, 0xb281a37c,
-0x156ce27f, 0x91893090, 0x06f58181, 0xc4487f6d, 0x0a7f7f9d, 0xc3a17141, 0xc03c39c5, 0xb581b2b5,
-0x526a7f7f, 0x7f7f7f4e, 0x7fec7f7f, 0x95cead7f, 0x161ba8d2, 0x8ad0d081, 0xe4f19557, 0x5bb6fca9,
-0x2d813a6d, 0xddbb7f81, 0x1cb1e281, 0xc2b43734, 0xd07f4641, 0x7f81bb39, 0xae9b1b81, 0xbe817f36,
-0x1caf7f81, 0x7f704922, 0x108f777f, 0x81662d7f, 0x479ca35b, 0x818513c2, 0xa41d8607, 0xd081b235,
-0xf6817fcb, 0x7f015960, 0xadb15f5b, 0x81be2abf, 0xf2b0e29f, 0x81819224, 0x38a7407f, 0xc9817b09,
-0xf307556c, 0x7f818181, 0x0281817f, 0x3fce810c, 0x18b47cd4, 0x81e2a53c, 0xe359840f, 0xe27f81ad,
-0xa1665081, 0x7ae062b6, 0xe0b27f35, 0xcd376e73, 0xd9a6d373, 0x817ffe7f, 0x02810946, 0x06498116,
-0x9b7fbb1b, 0x8d2b812a, 0xff14f781, 0x937de081, 0xb77ff44b, 0x4b2732c7, 0x0720bd96, 0x9e647f13,
-0xb831d474, 0x811d8183, 0xa5db837f, 0x8aa1b04a, 0xd4377cfd, 0x7f814241, 0xee8fec39, 0xcc81d881,
-0x2e29d770, 0x7ff76366, 0x7fbd363b, 0x74bbd13e, 0x2e817192, 0x9f6b81db, 0x44913bb3, 0x327f0de1,
-0x2d7f8881, 0x54f2afaa, 0x107f513c, 0x4c8191d1, 0x117fe67f, 0xffa21764, 0x2c931727, 0xd09ba693,
-0xf74e4882, 0x51ed8bc6, 0x3a23d683, 0x47437f70, 0x7fad8181, 0x9a610813, 0xa57ff47f, 0xbe1b5b9a,
-0xf4bf8c33, 0x43074944, 0xe4ef729b, 0x1e7165d6, 0x74e081c6, 0xe281810c, 0x2a4b81e4, 0x10ede221,
-0xc8375d7f, 0x81c07f81, 0x49cb7f83, 0x5f589c22, 0x276441a9, 0x7fe67f0b, 0x4d7f1d7f, 0x1872814a,
-0x05b6a577, 0x8140fa5d, 0xe47f9bc3, 0x44166064, 0x73896729, 0xb5c0867f, 0x247f445f, 0xccc92994,
-0x29611b37, 0x27531258, 0xeac27f9c, 0xd43f4e7f, 0xc27f170f, 0x6d9bfc37, 0xfc819181, 0x077f598a,
-0xe0c5d398, 0x7f23182f, 0xed171743, 0x20bff85d, 0xb0d0be7f, 0xb8938149, 0x45017f32, 0xcf2cc65d,
-0xdf7fc481, 0x7f380777, 0x81b8f0dc, 0xf6696596, 0xff007f29, 0x896e1abf, 0xfaac2d81, 0x5bc357ba,
-0x6a397f2e, 0xbfaeb45a, 0xd64e2b7f, 0xe49b4587, 0x565c6c51, 0x7f206a7f, 0xc381540b, 0xfc3d7f73,
-0xd4ec9f39, 0x887b7f27, 0xe3c1e07f, 0xb721523e, 0x0310819f, 0xc0c793ce, 0x387da141, 0x814f61ac,
-0xd1347fbe, 0x19244c1f, 0x8d3d58f9, 0x813a7fc9, 0xfae27f54, 0x7f39f481, 0xe37f818d, 0x034632d9,
-0x5b06c07f, 0x65ab8b36, 0x127f34b5, 0x18a681ad, 0x73510e20, 0x2f2ffa85, 0x6814ca9e, 0x5b7f7ead,
-0x08da93da, 0xc826da54, 0xc1686fd2, 0xb6f00fbc, 0x28bb5dbb, 0x7fe5297a, 0xb5ed8181, 0xccd9067f,
-0x177f1561, 0x71b41a19, 0xd9817f7f, 0x505b50c5, 0x309dc978, 0xb97f4f81, 0x4e81c219, 0x2d81d04a,
-0xdf3d5fa1, 0xfc6e5c30, 0xf7869481, 0xfc81e47f, 0x67b5817f, 0x7f72577f, 0x2c938136, 0xd576ad7f,
-0x63beb36f, 0x7fb3817f, 0xce56ca81, 0xd801e58d, 0x425f2522, 0x8a25817a, 0xdc7673c9, 0xd7b57fca,
-0x927fbe2a, 0x149b9881, 0x9ad781a9, 0x214b9d4d, 0x2dae1287, 0xfa772ca4, 0x3b7fdd35, 0xf59e4174,
-0xad3a28f5, 0x8144698d, 0x1ca792df, 0xdb7c7fd1, 0xe96d497f, 0x567fa7d9, 0x489b70cb, 0x3442de7f,
-0xa2554c37, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x4dc76c95, 0x29b78ec8, 0x3d927f7f, 0x307f93c2, 0x8181da7f, 0x99f741df, 0x6e1d417f, 0x1bbda834,
-0x954b5a9f, 0xc6817f07, 0x7fc01005, 0x3b5a81e4, 0x73cd7f5b, 0x7f817f3c, 0x8e7f812b, 0x59d48a03,
-0x982475ef, 0x65a1c068, 0x400cc79b, 0x81f231fe, 0x840329e0, 0x1f6054eb, 0xf8813d3a, 0x7f4a9296,
-0xbff677c5, 0x7f3c6f0c, 0x7f2890cd, 0xe0aaaad6, 0x81ae9428, 0x7f8117f1, 0x7f097f88, 0x7f27cfcc,
-0xca67205e, 0x815f7f37, 0x7f0ac07f, 0x717f95d2, 0x7f9232a7, 0x2bb803d4, 0x3c12c7e7, 0x937c81ea,
-0x7f1cdd3b, 0x0622b6c0, 0x62d71247, 0x811cb00b, 0xaef9e981, 0x0f818ff5, 0x740e6f53, 0x30616410,
-0x81fed3e0, 0x49167f3a, 0x4577315b, 0xe49130fa, 0x817c7f23, 0x7ffef7ec, 0x4fb47f17, 0xb365b1f8,
-0x81a09c38, 0x7f818134, 0x9568e717, 0x4ead1921, 0x8ebd9806, 0x7f911cf8, 0x8c7f5efc, 0xf29114a8,
-0x90bc6ae9, 0x0b5f26c1, 0x81bc9281, 0xf0fb5532, 0xc89ab77f, 0x7ec0b9d4, 0xf00bdcf7, 0x7f7f7a24,
-0x097ff51e, 0x64d62dfc, 0x7f7f819e, 0x34c05cc3, 0xa2957f19, 0x81101e05, 0x7fd68181, 0x1dff81af,
-0x7f81dc24, 0x7b3c6769, 0x7ac490dc, 0x814032c5, 0x9d81747f, 0x7fb46342, 0x72607faa, 0xd40c8161,
-0xa5ab574f, 0xf0838bba, 0x33fd7f47, 0x289f81be, 0x817f480f, 0x4bfa552d, 0x8ca1d5d5, 0x817f492b,
-0x418125e0, 0xe45d5af0, 0x811b1751, 0xe04d81f8, 0x7ff2917f, 0x65811a53, 0xe65da37f, 0xbafdd439,
-0x53818189, 0x752c7ebb, 0xc301567f, 0xb0816f27, 0x708166db, 0xc0b57f49, 0x3a818169, 0x4f16189c,
-0x13d6e83b, 0xd258a20d, 0x7fadbdb2, 0x7f93560d, 0x81fd5399, 0x6014dab2, 0x9cf45f1b, 0x107f71d5,
-0x352e8109, 0x5a5d6efa, 0xb458ef47, 0xb4a96098, 0x7ab91c37, 0x81bd762e, 0x816cb0d7, 0x3f9819d4,
-0x8113b97f, 0x7f09fa33, 0x9e7ffa99, 0xe98181ce, 0x4ffb3064, 0x7f0681ea, 0x81ef06ad, 0x385abdf5,
-0x1414457f, 0x18dabc5a, 0xc27e0d7f, 0xd87f8115, 0x703f7fcb, 0x300b7ff1, 0xb081f55d, 0x024d78f8,
-0x72949a16, 0x90603c38, 0x7fba6fd4, 0x4820e44f, 0xd57f81af, 0x9c7f7ef9, 0x61c6b27f, 0x81b6141f,
-0x7c52514a, 0x5f817f78, 0x668119a7, 0xe441aa7f, 0x53819553, 0x7f721521, 0xbd7f7f17, 0x593081de,
-0x8b252de8, 0x7f7f81c1, 0xaca9436e, 0xb5e0b104, 0x81e49d81, 0x75b48102, 0x5c278118, 0x9f6c36c9,
-0x509481fa, 0x53d1e640, 0x52108181, 0xeb7f7fff, 0xde417381, 0xa781cb33, 0x4fab55f4, 0x3e7d75f1,
-0xf17f0c1a, 0xe8e1817f, 0xcf1f7f81, 0x96d8ba40, 0x1318fc72, 0xd7ae3d1d, 0xf7e88126, 0x32bfe432,
-0x453f694b, 0x7f7fbab6, 0xeae7de30, 0x3d81d7d1, 0x438d9cc7, 0x387f4a05, 0x7f46ab81, 0x635bdf10,
-0xc281ae24, 0xc5c67fc4, 0x81acb53d, 0xba4f4d04, 0x424f72cc, 0xbf7faa1f, 0x55de1de8, 0x81429a1d,
-0xdec94147, 0xff007f42, 0x3fa74821, 0x0cb74e9c, 0xff81627e, 0x6343810f, 0xf7393529, 0x7f44ad81,
-0x7f811f39, 0x81e981a0, 0x8c8c4421, 0xc4819190, 0x81816881, 0x7f7fd234, 0x3688c16c, 0x9c34b357,
-0x6046e3f6, 0x86123bdc, 0xbd45957f, 0xe6cd777f, 0xe0951ce7, 0x9b7f63a6, 0x817f29c1, 0x7f5a81ca,
-0xde7ffcbe, 0x812c3207, 0xa099537b, 0x2a2f81d0, 0x16817f9a, 0xbb81817c, 0x7f81e538, 0x957a4200,
-0x81753bab, 0xaf63a506, 0x3081691c, 0xb0a47f2c, 0x0f157feb, 0x8e4330fe, 0x635b8189, 0x7f81ee34,
-0x7f40caae, 0xbce88e05, 0xabb52199, 0xd2ba102f, 0x7f7f8173, 0x810b32ab, 0x2e222781, 0x7f819951,
-0xfbc73dca, 0x5d81d181, 0x7fb09d81, 0x7faa3098, 0x7e81435b, 0x61e995d6, 0x7f7974f3, 0x7fef81f9,
-0x402faba7, 0x7a647f3c, 0x815c6826, 0xba2b2ffe, 0x7f095b7f, 0x7f9236b9, 0x9953636b, 0x344c64d2,
-0xd784acc0, 0x7f818426, 0x61ab43f8, 0xd5813c70, 0x7f817f81, 0xc9867fa8, 0x6f4b4181, 0x3881b1df,
-0x69813f27, 0x81d0780c, 0x17c84a36, 0xbf908ccc, 0x7f5e812b, 0x317f7fea, 0x7f817881, 0xf731c537,
-0x7fb221e7, 0xbae09bf7, 0xcc5d947f, 0xcfc13926, 0x6e0db67f, 0xdf17be28, 0xcaa4ea2f, 0x9870810f,
-0x357f701d, 0xa281815d, 0x91497468, 0x5fbcbeb0, 0x7fd54d81, 0x7d5e91f3, 0x8d6555f9, 0x35d416e3,
-0x9a7f8c11, 0xd875779b, 0x6b7c6681, 0x24f77f50, 0x288bd781, 0x7fad2b50, 0x637f1a23, 0x527f2ea7,
-0x277f7fc3, 0x819c13cb, 0xe1bb65f1, 0x48151c1b, 0x8e7fd27f, 0x7f7065ac, 0xfe0bb14d, 0x588e7f0c,
-0x819d7f34, 0x81c455a5, 0x4f6b7fae, 0x7fb56506, 0x7fcfd5a2, 0x3e6981dd, 0xcc814569, 0xc5fb811a,
-0xc0e07fbc, 0x817f8153, 0xac356315, 0xc94db6d8, 0x7f88e57f, 0x81e57fd0, 0x7f1f6c0f, 0x78d581e1,
-0x7f2137f6, 0x1c57815a, 0x627f55c0, 0x69e4dbcb, 0xa68181c3, 0xb9907fea, 0x55897fa0, 0x7f54a91d,
-0x3e7bb314, 0x7f167f5f, 0x75cc8181, 0x177f2fd0, 0x6d39f7e9, 0x7f817fd3, 0x7f6eb0ea, 0x817fc7ad,
-0xae5b5b04, 0x86cd281f, 0x3528fe7f, 0x87217fff, 0x87860479, 0x8b7f4510, 0x7faa816c, 0xb9d62c33,
-0xdd1c6ccc, 0xb48104fd, 0xbf508f81, 0x34994944, 0x8181b843, 0x74e47f47, 0xc6baf38e, 0x624b06cc,
-0xfdadfaeb, 0x948189ac, 0x7f7f992d, 0x813edf00, 0x81c3587f, 0x5eb2819f, 0xcee54cef, 0x277f38d9,
-0x8a187fb6, 0x9736ed05, 0xed70487f, 0x4f307fa9, 0x81ba975e, 0x81dd81ed, 0xd0da7f88, 0xf24881cc,
-0x12e656d0, 0x7f9b6a1f, 0xcf7fcf7f, 0x78787ebd, 0x7f8319f2, 0x7c7fe9ed, 0x29b381ae, 0xfa4f81cb,
-0x13cc81e2, 0x9a2aa0a8, 0x817f8112, 0xfda22318, 0x7f65e85a, 0x727f6812, 0x7f814b0b, 0xcfe2bcd5,
-0x6b816ce3, 0xb2965ab7, 0x819981bf, 0x73799635, 0x82854b71, 0xbc3e8132, 0x91c714a2, 0x81817f2e,
-0x2cc55af1, 0xb87fb038, 0x7f7f1718, 0x02ba14fe, 0x5e348128, 0x817ff97f, 0x81d03daa, 0xde37813b,
-0x443781c0, 0x0e4e32e2, 0x85a7ad81, 0xba276c16, 0xb61ed9c6, 0x81ca27d3, 0x7f762e7f, 0x4181d581,
-0x7f7f5508, 0x6eb1b250, 0x5ad47f4a, 0x7fd56756, 0xbc817f81, 0xd481a9ba, 0xf8a74db3, 0x7d1aae25,
-0x81397f36, 0x7f62a402, 0xab3b3081, 0x4c45c301, 0x3eb57f88, 0x6d2e7fdd, 0xeb1ac681, 0x813881c0,
-0x7fd127b4, 0x67e57f90, 0x4fcb6d3a, 0xc566afe7, 0xc58bdb7f, 0xe0486a7a, 0x363f8181, 0x7fdd8191,
-0x67149cc2, 0xfe7fcf00, 0x7feeb9dc, 0xccabbd95, 0x7fab347f, 0x98eda0d8, 0x7faf81a3, 0x3b8c7f0a,
-0x1c387fa7, 0x7f055ed9, 0x567fbd7f, 0x4d7f7244, 0xbb8175af, 0xef7f7f5f, 0xa9a58119, 0xada9eec7,
-0x592da3bd, 0xb5a98177, 0xe17f813e, 0x94816af7, 0x69ec7fc5, 0x7f29dd4a, 0x9481c981, 0x5d3198da,
-0xf84e81bb, 0x41817f7c, 0x7fb31b60, 0x7f7f5e03, 0xea81c490, 0x7681571c, 0x9b54b581, 0x812d993b,
-0x7fefd381, 0x7f907fe3, 0x7f81a862, 0x758181bc, 0x46d6507f, 0xae81a50a, 0xd1562a1d, 0x3dcb58d2,
-0x489e40fd, 0x7f8fa98a, 0xb07f7f81, 0x238b7b40, 0x49686384, 0xca817f4f, 0x607f7fd7, 0x3a0d81ab,
-0xb0fa42e3, 0x7f81563d, 0x829a817f, 0x51d48167, 0xcc817781, 0xd54f5638, 0x7fee1218, 0x81a49e22,
-0x0081ec2f, 0x5f5eecf5, 0x6bbc9ce7, 0xa28138d6, 0x86811081, 0x7f0283cf, 0xfff67fb7, 0x81c2814a,
-0xc7817f52, 0x85818146, 0x8781a77f, 0x8181e9f6, 0x4731f881, 0xf51a35d8, 0x236931b2, 0x6eaefadb,
-0x7f81c61c, 0x947f3d7f, 0xbcf43b52, 0xd5814849, 0x17b6e07f, 0x7f6a81b6, 0x817f8163, 0x817f595f,
-0x7fa5ae33, 0x2b63a90a, 0x77627e81, 0x81816660, 0xae7f6281, 0x26c6dedd, 0x757ff9c4, 0x7f7fce30,
-0xab9d7800, 0x68fc444b, 0x3d7ff681, 0x93264a1d, 0x81361db5, 0x817fb6d3, 0x1681136f, 0xc5655027,
-0x792781e2, 0xeaada9c7, 0x34d1817f, 0x81687fc6, 0xa88d451a, 0xdce97f0d, 0x443935cd, 0x810a68b9,
-0x73ef4023, 0x66372979, 0x9a31076e, 0x81813dee, 0x56b11a7f, 0xc76a81da, 0xe0e48181, 0x6681b8b7,
-0xa99858ec, 0x7fb38de5, 0x7f6f817f, 0x92168381, 0x53819b02, 0xc3c27f2d, 0x5299d77f, 0x81e47f60,
-0x687ffbc6, 0x7f5f9df9, 0x0ab4c09d, 0x44856927, 0x5e63405f, 0x7f9fe864, 0x8c884d25, 0x794dd01f,
-0x7f81fb68, 0x31bed5f5, 0x3e658638, 0x3e7f8151, 0x7f7ba8e4, 0x7f304a8b, 0x37c18157, 0x7fb2c6fe,
-0x7fa39bef, 0xa37ff9a1, 0x29983fc2, 0x777facc9, 0x547ff37b, 0xe6815b17, 0xec5a457f, 0xacade303,
-0x7f2603dc, 0x697fcd23, 0x7f7fd042, 0x4a81a54d, 0xd481bf87, 0x7f4e7f0c, 0x0d5c9d05, 0x26ca3c2c,
-0x4f817fe3, 0xc9368b0f, 0xaddb8181, 0xc210e075, 0x248f7f81, 0x697f7f11, 0x817f2f81, 0xef697ff1,
-0xd98181b9, 0x810a4f50, 0xbb9e045a, 0x8ea3771d, 0x787f6931, 0xfbb9812d, 0xb778f981, 0x7f354b27,
-0xfc813658, 0x25818137, 0x7f3402a1, 0x27eabd01, 0x81c18181, 0xfd7fa22c, 0x9784817f, 0x7fa57fb3,
-0xd881f3ce, 0x887f60bf, 0xdc816b0c, 0x3890b818, 0xc37fa281, 0x8f4681f5, 0xb07fb08b, 0x82ad24d0,
-0xc189ab02, 0xe3fddb8f, 0x7f744610, 0x435781b0, 0x8104f653, 0x41bb81be, 0x9a4c717f, 0xf9d4c1e4,
-0xbdc36404, 0x8ff9818a, 0x54d3ab9c, 0x24aec8ef, 0x81ac5bc8, 0x81908100, 0x74f05a0f, 0x0c5b7f2d,
-0x5279a3e3, 0x2d8169b9, 0x7fdc4897, 0x7f5f89bb, 0x9f457581, 0xde817fd7, 0x59813d7f, 0x67817fe7,
-0x7f817fd5, 0x7f5978ca, 0x23ab813a, 0x70819ce8, 0x41575433, 0xb17fa99e, 0x697f7f7f, 0x60aeb15a,
-0x7fa5a9df, 0x39818181, 0x818ea205, 0xbd819fb2, 0x7f0fa491, 0x814981d8, 0xb9c186e4, 0x817f29e5,
-0x81afcd17, 0x842f81ce, 0x058b8e1d, 0xea3da29e, 0x379f5ab7, 0x223c84c9, 0x93bcd8bc, 0xc895baea,
-0x6b7d3cc9, 0x7f2b8152, 0x7feccb81, 0x7f71634c, 0x810f7f29, 0x89c14aff, 0xc0ce05d7, 0x7aed49e1,
-0x817f4d0c, 0xeeaa0afb, 0xd7817f81, 0x6681d76a, 0xa37f4881, 0x38708103, 0x7f8181cb, 0x0a8f6639,
-0x8581aec3, 0xe82836d2, 0xda7f4781, 0x40d67ff3, 0xcc335f7f, 0xce207f44, 0xff9181f8, 0xbae52614,
-0xfccdf700, 0x9dc19f54, 0x5d7faefc, 0x5bcc2357, 0x817f7fb1, 0x6f5a9dd7, 0x81af5633, 0x810a7f59,
-0x551c8a18, 0x4b816452, 0xe981d940, 0x81d175f6, 0xee7f5746, 0x276f51b7, 0x16ae817e, 0x652063ba,
-0xd84e5e44, 0x7f385f2a, 0xa2e1b28f, 0x7f817fd2, 0xd8477f34, 0x508f31fc, 0x7e357fc7, 0x7fa07f7f,
-0x7f6d7f52, 0x7f717038, 0x7f819c3a, 0x2f973937, 0x71ac7d7f, 0x790950c2, 0x9aa97f81, 0x7f427ffe,
-0xf3f974a1, 0x8107812c, 0x817fb77f, 0x4d458151, 0xc93d2395, 0xb497d049, 0x4b955c87, 0x047eaef1,
-0xcc6c07cc, 0x5eff94ad, 0x3bed1246, 0x74d8c531, 0x815afc81, 0xaccf6eca, 0xbe4e3f64, 0x079b37b9,
-0xa0898136, 0xfe8a81b9, 0xb7df45fc, 0x7f7f7157, 0x725581a3, 0x7f0c56ec, 0xe6430781, 0x4356def3,
-0x54ca7fc7, 0x234f3eee, 0x7f270367, 0x704981c1, 0xfe623836, 0x816d2725, 0x7b9d9e81, 0x3b49d3ae,
-0xd2925440, 0x819a7fa5, 0xb025c9a5, 0xbbd77fc1, 0x81737f81, 0xbcb891ae, 0x442ab466, 0x812e41cd,
-0xbdb081a8, 0x8e7f5c2d, 0x8458dfb7, 0xd77f8130, 0x9bcbbc47, 0x783a7f5f, 0x27c4d502, 0xadf8cb31,
-0xa51e9baa, 0x814d812f, 0x7f1a7f8c, 0x1874f4be, 0x4ac57f81, 0xc7b67f37, 0xc0817ff9, 0x8c81e1ae,
-0x6f7f9331, 0xa17f7f9f, 0x7bec5242, 0x81b79554, 0xa27f7f7f, 0x181da812, 0x52e681f5, 0x5c3781fb,
-0x895981ae, 0x7f7fa003, 0x9555817f, 0x32391fdf, 0x0c7fff6a, 0xb681981d, 0x1b93a683, 0x7fc3d495,
-0x83f5810b, 0x854399a0, 0x997fd57f, 0xe87f6929, 0x7fbafb81, 0x7fe201e3, 0x7f7234b3, 0xb6889ebb,
-0x8ea7cdcf, 0xd27fab96, 0x9a562c7f, 0x6c7f7fd8, 0x2277467f, 0xb3108ed9, 0x818d0171, 0x81bc477f,
-0x650719f9, 0xba7fe501, 0x7b5796ca, 0x3fc581eb, 0x9a90469b, 0x7f041112, 0x527f7947, 0x8d3d4657,
-0x7f627fdd, 0x64053a56, 0x817739c6, 0x812268ee, 0x69ed9b7f, 0x3d7f7f1a, 0x7f2264f4, 0xb76c55f2,
-0xd06981fa, 0xa72359d6, 0x3708812f, 0x7f7a4c29, 0x467a227f, 0x685eb4c5, 0xeeeb81c1, 0x2999b5e3,
-0x7f7fa0be, 0x73586e92, 0xc7817f0a, 0xc32e7f4f, 0x819b9046, 0x8179acee, 0x29b1a517, 0x557f0ef9,
-0x8116589d, 0x557f26f3, 0x861970dd, 0xcb817fef, 0x9bb6ba72, 0xaee4ddfa, 0xd17f81c9, 0x257f76bf,
-0xb04b4df4, 0x8f7f8124, 0x818181fc, 0x4fcc8f06, 0x2f7cc181, 0x4900141a, 0xf0709c16, 0x6865b5fd,
-0xd9ab9128, 0xa2321900, 0xa1a6de7f, 0x58e47f23, 0x54ac4a45, 0x1af1e618, 0xed633c24, 0xde7f7ff7,
-0xd48139b1, 0x5a640dcf, 0x63d9de7f, 0x81669358, 0x4f4571bb, 0x7f7fa692, 0x7debaf85, 0x9d7f7f10,
-0xd9c34e9a, 0x708981e8, 0xfc838ac6, 0x430bf6b2, 0x81a1a4ee, 0x7f8181ad, 0x35e98d7b, 0x4e3681de,
-0x7f7256e9, 0x7fa3b47f, 0x5a813e7f, 0x8128aa15, 0xff42357c, 0x581e98a3, 0x81534281, 0xe58196fb,
-0x11b90c6b, 0x7f81e5e5, 0x7473f57f, 0xa9475b2c, 0x24d77fa7, 0xa27f591e, 0x7fba81a5, 0xc9f19310,
-0x3c64d05f, 0x86aca9f0, 0x69b57f01, 0xbb747fb6, 0xdd81e923, 0xbe814a26, 0xe6811b22, 0x7f817fdf,
-0x7f81e46a, 0x647f8170, 0xf2812d9b, 0x7f765fa5, 0x812dfe0e, 0x2584ed72, 0x811a7f7f, 0x417f7fee,
-0x81d28138, 0x7f8e7fff, 0x9c7e28d0, 0xa71eb5f5, 0x65993e7c, 0x927ff0e8, 0x7f5cd4ce, 0x2886b35e,
-0x7f81d3bf, 0xc2d1441e, 0x2f2cbadd, 0x8c9c4cb4, 0x34dba16b, 0xaa37c5c8, 0x5881ec6f, 0xfc7f64a4,
-0x81bb8128, 0x7395489a, 0x7f647f7f, 0x44ef7f9a, 0xc3b4d6a1, 0x8693af02, 0x87fab099, 0x7f7f2f05,
-0x0191d5f8, 0x0b4281cb, 0x615b990b, 0x554b7f4c, 0x7f7f66a2, 0x817f793b, 0x5681aa97, 0x21aea0bc,
-0x81925b0b, 0x81c69839, 0xb115814b, 0x9e81d8b0, 0xc70c6f7f, 0x8f14de16, 0x3f81b4bc, 0xaa0c25dd,
-0x81f8346b, 0x6981226b, 0x81b1817f, 0x7f2081e4, 0xa2848117, 0xe4cbcc32, 0x817081d5, 0x817dbf75,
-0x157f2614, 0x5a0477d6, 0x8b818105, 0x9e7f34d4, 0x48da3235, 0x397ff6d2, 0xa02f7092, 0x817f8b13,
-0x307b35ca, 0x783c7fe6, 0xa2c29081, 0x555b8101, 0xf764ee86, 0x463a8149, 0x577f837e, 0xb1948151,
-0xbd2f86f5, 0x6e5fc338, 0x7f67a373, 0x55817003, 0xa1e17f77, 0x8a817fff, 0x49365e44, 0x817f8933,
-0x209ba8a9, 0x7f311515, 0x7f519140, 0xa9549352, 0xbd817f8a, 0xafc4a005, 0x620d407f, 0x88302fd2,
-0x5cf481f2, 0xbd7fff40, 0x7f7f9cfb, 0x91ae81fc, 0x73f15c81, 0x93814581, 0xc7e8818c, 0xc481a1fa,
-0x99818124, 0x7fecdbf3, 0x207d8d39, 0x64818328, 0x7f9dbf5d, 0x2181f9c2, 0x817f7f8c, 0x367c1801,
-0x2a019011, 0x815f5d39, 0x81817fb8, 0x7f22815e, 0xb3ceca8f, 0xa6560501, 0xfb548181, 0x2b7ffe18,
-0x5394bb1c, 0x7f9981d9, 0x7f7fce32, 0x815ba6e4, 0xabd0d732, 0x7f5c81fa, 0x7f369f77, 0xa42b7f51,
-0x900db9cd, 0x9993bde1, 0x7fc8819a, 0x116f9310, 0x8ef767b0, 0x7a817f02, 0x56819b81, 0x29aee511,
-0x7f2b8d3a, 0x818a442a, 0x555c3ff5, 0x1d6c4929, 0x7ea9697f, 0x780b8fa6, 0x097fa426, 0x9b7f89d9,
-0x165081de, 0x45a184c0, 0x405c7fc7, 0x6bbcd6d3, 0x7b81837f, 0x33867f12, 0x878f7f62, 0xc6cf1002,
-0xad819f7f, 0x3df9422a, 0x77ca9e81, 0x684f7fca, 0x30847f81, 0x81817fda, 0xedc6a081, 0x682c00eb,
-0xca767fdd, 0x1f7fb0e3, 0x377f8a7f, 0x5e85d200, 0xb9237f1f, 0xf2817f2d, 0x0dd88132, 0x81cc0037,
-0x739b39bb, 0xb47fb83c, 0xdf7f8181, 0x7f54f610, 0xbc9e3f06, 0x5762b272, 0x81ebc628, 0x7f9845b9,
-0x7d901f63, 0x81ce7f36, 0x0ebd8e7d, 0x9a81d963, 0x644c3f81, 0x227fbdeb, 0x8e2d5f81, 0x54efc59a,
-0x94ed5511, 0x817f944b, 0x38393d81, 0x592f7ad2, 0x75814881, 0x63275d7c, 0x4a65de10, 0xeb818ff6,
-0x70f93fc1, 0xbbe83610, 0x7d94beba, 0xfd077f2f, 0x7f818181, 0xbb7f47d1, 0x4c8f7f6d, 0x587fa2fb,
-0xbd817f02, 0xae7f8123, 0x4fb981ac, 0x3fd2c446, 0x817f7fa1, 0xb28d81ce, 0x7f813fbf, 0x5a8181a8,
-0x2f6355c9, 0x75624fb5, 0x811842d0, 0x70a38146, 0xea52aef5, 0x7fffa3f0, 0x8f7fdcb0, 0xe31d81e5,
-0x7fe15a51, 0x21894817, 0x9c810f41, 0xe9428145, 0x7f819edc, 0x7feb1761, 0x81368181, 0x2c71f15e,
-0x26813c54, 0xf09c69aa, 0xd17751da, 0x25a1c23c, 0x7f812281, 0x4317b30f, 0x66908149, 0x81869b95,
-0x062874c1, 0x843481a4, 0x81743c89, 0x813e9cae, 0xd8397fd1, 0x7b495f55, 0x7f7f7f53, 0xc0b419e7,
-0xacf11d1b, 0x90a51003, 0x9efa5bb6, 0x77b8989f, 0x8b1ea17f, 0xc46537c3, 0xcca93d93, 0xa955d1db,
-0xc42743ed, 0x7f8a6442, 0x79ab8152, 0xfea48ff7, 0xfbbb819c, 0xa1be81ed, 0xa481da42, 0x477f7fd0,
-0xcc1acdfb, 0x767f1533, 0x99cdda46, 0xfb9c8109, 0x7f757f7f, 0x747f88d6, 0xb5404df1, 0x8b69b739,
-0xc762670a, 0x8125bded, 0x6481a452, 0x943e5aef, 0x7fe3557f, 0x8181bfc5, 0xb14d907f, 0x7f747f9c,
-0x54b4ff28, 0xe19d7fc2, 0x7f25887f, 0x7f6cc0b5, 0x34653ba1, 0xacd70015, 0x7901cc3b, 0xb081815e,
-0x812781fd, 0x871cd81d, 0xd1818494, 0xa97fc1ed, 0x81817f86, 0x9f3cf7da, 0x9857bb81, 0x9d1661d1,
-0x167f5814, 0x037fd0e4, 0x7f337f7f, 0x7fd40904, 0x376a4a69, 0x7f77a308, 0x73b61d36, 0xb4a318cc,
-0x7f9cc3e7, 0xe0d55532, 0xab58707f, 0x9c467f07, 0x8c7f2581, 0x60155a41, 0x7f3fd21d, 0x7f7f59a3,
-0x38176d64, 0xf77fd7a6, 0x0ed2ae81, 0x7f81cdec, 0x3c0f81a2, 0x747d9be6, 0x818c5f83, 0x432e7cfb,
-0x4a44b96b, 0xc8748423, 0x6b818181, 0xe34914d7, 0x980b64bb, 0x7fbe165f, 0x7f104bbd, 0x5c7f9d02,
-0x7f307fcc, 0x8399c1a3, 0x7233316c, 0x92aae7a6, 0x81deda79, 0x812805f0, 0x7f566985, 0xdeffbea8,
-0x2bbf427f, 0x7f819e05, 0x90811687, 0x817f81a0, 0xb581c481, 0xa05cfdd4, 0xe4983e52, 0x813e81e7,
-0x2b5ba42c, 0xf75aaf0c, 0x4bbc8181, 0x817fa502, 0x1a7f2d7f, 0xe97f0700, 0x724a5029, 0xe3700308,
-0xae7fb93c, 0x7f9581ba, 0x819d7f3d, 0x2b2ef875, 0x341c52ae, 0x21b23dfc, 0x6a82a2e1, 0xaa81ecc7,
-0xcf817ff6, 0x7fa17fb5, 0x1fc21a81, 0x817f895d, 0x54973cd6, 0x81a8c919, 0x9f4c7f38, 0x89817fd1,
-0x325d7fea, 0x959581c9, 0x711638c8, 0x07bb81c4, 0x1bf0818c, 0x346b81aa, 0x5d55817f, 0x7f7f8192,
-0x3b7f81d5, 0xe783f367, 0x863038b6, 0x7f53589b, 0x7f4de47f, 0x128165ac, 0x7fa6ccfa, 0xc19f8132,
-0xc3b3483e, 0xa63d628e, 0x2d707fd1, 0xd93a1319, 0x9197277f, 0xd77f0fbf, 0x8156da7f, 0x88819a98,
-0x3eb240f2, 0x81007fbe, 0x067fe653, 0xd3aa8150, 0xa625819b, 0x767ab13b, 0x937f817b, 0xd08181e1,
-0xa47f81b9, 0x3481bd4a, 0x65507fa7, 0xb79181d1, 0xbf1d7d3e, 0xb2818178, 0x8f329d1c, 0x2081b481,
-0x7b84a853, 0x7b679ce3, 0x9ba49881, 0x695ab122, 0x23be9081, 0xd7322a4a, 0x21db3fad, 0x81fc8145,
-0x84a1bad2, 0x9f307bb8, 0x81815581, 0xb84f1450, 0x6d3acdb7, 0xfd64811d, 0x7f8132e6, 0xd7458fee,
-0x81c54610, 0x7f7f73d1, 0x81a5c3bf, 0xe15f7fa0, 0x3c7f517f, 0x047f7fd0, 0x261e438d, 0xb3c47f34,
-0x5c81a1f6, 0xa2c62f5a, 0xe67f9255, 0x4df92530, 0x58877578, 0x817fdbd6, 0x9381d867, 0xb3815eec,
-0x3d8b8ad4, 0x814aab55, 0xa5477f7b, 0xed7f98d4, 0xae7f3681, 0x3b938138, 0x58e37f90, 0x7356b00c,
-0x754181fd, 0x3181503e, 0xc58dc451, 0x818b9cbe, 0x747fcbc4, 0x0918d1f1, 0x5b5ae00e, 0x761d6116,
-0x535ba62c, 0x8c0f22b4, 0xc98fb9ad, 0xad7f6d1d, 0x4f7fec7f, 0x1b437f35, 0x9004b258, 0x787c8d15,
-0xd04b81e6, 0x703d10f0, 0x7f7f8b89, 0x1674b61c, 0x9789ac81, 0xac6c7f58, 0x0e81ac48, 0x0881812d,
-0x117f7cc2, 0xa6bd8145, 0x59817f7f, 0x89cbb4fb, 0x697f9a81, 0x813e5281, 0xf57f4898, 0xee994b1d,
-0x60228cc5, 0x4c341db8, 0x7f6e7f63, 0x107f8151, 0x14397f55, 0x81a951d6, 0xb762ed40, 0x81c39dd6,
-0x546a0438, 0x7f8e88d7, 0x81810e7f, 0x7f7f654c, 0x3b412da8, 0x8aabcfe0, 0x4b83444b, 0x65bea3ee,
-0x507fb43f, 0x16c3c7c5, 0xe322a2d9, 0xfd5a0fd9, 0xc757577f, 0x6cd0b9af, 0xc6078100, 0x3256b728,
-0xc47fdc2f, 0x81dc4bb9, 0xd8d02073, 0xc38671f2, 0xbb9104b4, 0x7fb281b6, 0xcb817f81, 0x819f44af,
-0x29f781bc, 0xdfc231b9, 0x7fae7f43, 0x575b7f79, 0xf4c4414e, 0xe807d15c, 0xd08181ae, 0x8e81cd9f,
-0x942472c9, 0x816362dc, 0x9cba9281, 0xdc6fce74, 0x2b7f7f35, 0x37810c4f, 0xe8709e85, 0x5c7f984d,
-0x8153bc24, 0xbfe581bd, 0x9a7f9c84, 0x3be9e533, 0xb6938127, 0x82ca63d5, 0x08eeb19f, 0x59ebeb0f,
-0x4d7f14f7, 0x3c558f40, 0x62d26981, 0x8181f3a8, 0xe42585ea, 0x7f08817f, 0xaf8181a0, 0x0c5d16cd,
-0xa4dfee3d, 0x3a8182fa, 0x6381883a, 0x7fe9d01c, 0x5e659f90, 0x7f7f812f, 0x4a9d8179, 0xb1e4acf3,
-0x1b8189f9, 0xd983a4d8, 0x817f81df, 0xa2cf1f55, 0x817f337f, 0x7fa3564e, 0x14ae7c44, 0x4ca3859d,
-0x81b37fa2, 0xf8a0b7b1, 0x7f79c0cc, 0x7f3010f6, 0xa5be8c16, 0x2420b129, 0x7f7898f1, 0x7e818139,
-0x7fc919eb, 0x61819a67, 0x88928b15, 0x7eade0d3, 0x4e7fc323, 0x8deb5fe6, 0x7f3f7f9c, 0x81817fbf,
-0x989026db, 0xef81c203, 0x81e4a1e1, 0x35939d41, 0xbbaae870, 0x3d217fca, 0xddd9a1ce, 0x7f7f81a3,
-0x5bf18122, 0x81c55a52, 0xc95c450c, 0x7f5a03e6, 0x65654a14, 0x75d401f6, 0xe0cb297f, 0x5f3c8132,
-0xf7a312d3, 0x81c6d3af, 0x978e8181, 0x1476539f, 0x502534be, 0xd2909112, 0x6ad663ad, 0x7f7fbbac,
-0x8b70da23, 0x4d78af31, 0x7f8159f5, 0x81bad147, 0x348151dd, 0x5e68eace, 0xc2737fa0, 0xf97fa32e,
-0x7e7f81de, 0xa68baddb, 0xbb39817f, 0x7f9bc454, 0x6d09c327, 0xc37f3c33, 0x0a865f7f, 0xba8281e1,
-0x1a3ff406, 0x652c3fd1, 0x94af367b, 0xb381d8cb, 0x4045cce5, 0x7f7fd613, 0x795f7f42, 0xb1818193,
-0x7f371d3c, 0xef816b41, 0x2ca91acc, 0x48b5aa83, 0xaae807de, 0x26813f13, 0x81817f2a, 0x6083604f,
-0xd29e81f6, 0x7fb218ca, 0x4aa50170, 0xc2d74a22, 0x4f4971a3, 0xe9dc5f10, 0x7fb8bedf, 0x1f93814a,
-0xa97f7f0e, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
-
-hard_output0=
-0xb5bc6ac8, 0xf5373664, 0x1310345c, 0xd5bae4e7, 0x1fc9e83e, 0xebfdfded, 0x84bd86ab, 0xb7aabe00,
-0x60b44fea, 0xb9067464, 0x30325378, 0xa9195955, 0xf70c6e5c, 0x90922632, 0xc90b1cdb, 0xf2f5fb69,
-0x73056b63, 0x1a33bf3f, 0x17755b5c, 0xc58bff6d, 0x2f4390b2, 0x2869d508, 0xe7c7dfe8, 0x38552963,
-0x21da5367, 0x07282b9b, 0xa4767105, 0x1e294251, 0xe350a940, 0xb8a6aa27, 0xed12d778, 0xf10d9ece,
-0xab93527f, 0xcf2da7e7, 0x68f6d0b1, 0x811f4bca, 0x577b06b2, 0x3234f13e, 0x30bab7df, 0x8dc47655,
-0xbb843bed, 0x86da3aba, 0x30950c97, 0xdd096d7a, 0xa871fd6c, 0x8bee4e6b, 0x8fea30d0, 0x6c05b4d2,
-0xf3e144d3, 0xd24ebb1f, 0x065635e5, 0x8d3f2cf9, 0x536c6c6a, 0xfbb0a5d0, 0x3d707b42, 0xc44d5982,
-0xa5f4ad8f, 0xf32c0970, 0x1bccf1a6, 0x05916020, 0xa64fb176, 0x5ede6a35, 0xaf4966da, 0x9df5e0e7,
-0x75042abc, 0x9ef10481, 0x11ddcbc8, 0xa0f5518c, 0xd5c23418, 0x2393d558, 0xfbe7dfeb, 0xed1c64c2,
-0x86a36508, 0xde2dfb1e, 0xb8d0fef9, 0x24505232, 0xc894e71c, 0xbcc752a0, 0x40b74e83, 0x90d23c8c,
-0x728e4a61, 0x108f0b08, 0x66f522ee, 0xc258d851, 0x35a31c44, 0x11311b5b, 0xfd3d5be9, 0x5ae448ff,
-0x4f64994b, 0x5b8247a9, 0x4021114d, 0x2f0b6e82, 0x5eaa9828, 0x50ac71c0, 0xfb86ee52, 0x0dc1ac9b,
-0xbbd47645, 0x8f357115, 0x978ceea0, 0xd557db99, 0x99b30388, 0xfc9a8a1c, 0x0f75be1a, 0x50143e22,
-0x8840989b, 0x738ec50e, 0xe6b2783d, 0xf67899c8, 0x27ebed69, 0x6c415a16, 0x3a6cc2dc, 0xcd4e4e5d,
-0x6cb12b2e, 0xdb88d7c0, 0x79cd1582, 0xbc422413, 0xe72ad2f4, 0x8eaac30f, 0x0bd86747, 0x6d87f69d,
-0x15d62038, 0x4b375630, 0x0d51b859, 0x16db2cb2, 0xf210603a, 0x0abeb833, 0x55c694d0, 0xe57ca43b,
-0x0ba94428, 0x1398a406, 0xe47d3889, 0x5a20203d, 0x250d7a1a, 0xd930ffec, 0x03992e79, 0xf2759376,
-0x024ec121, 0x91fc3a2c, 0xb7e11cc5, 0x4ff7d459, 0xb8700134, 0xd6e61758, 0x4eba0a32, 0xb747e3ec,
-0x7073fad7, 0xded80f99, 0x331e2f1b, 0xfa1f1bed, 0x056424a2, 0x1d1d95e0, 0x550b9ec8, 0x51ee2a38,
-0x19525153, 0xd70c4cd5, 0x0d6cd7ad, 0xe44d1cf2, 0x30dfecda, 0xdacd7fe8, 0x7321d795, 0xddf48ef4,
-0xe271e6a4, 0x9c1feecb, 0x951fcd7b, 0x8acc5a03, 0x3fb83527, 0xe306de74, 0x7b9cd6ee, 0x8e140885,
-0xd4c91e8d, 0xe8c39733, 0x0f02f87f, 0xfb06b1b9, 0x0dc9349c, 0xf76bae8e, 0x4f642a07, 0x3d48a9aa,
-0xe3ea323a, 0xa1cd5c8a, 0x40aa0e70, 0x132042d3, 0xa9732f6c, 0xd15a00c4, 0x43d3b046, 0x9a51ebd4,
-0xc46ee0ed, 0xe2a2148b, 0xf5c478f0, 0x1fb01cf3, 0xf4f321ec, 0xd973811f, 0x11ad11b9, 0x5c67adda
-
-e =
-34560
-
-k =
-6144
-
-rv_index =
-0
-
-iter_max =
-8
-
-iter_min =
-4
-
-expected_iter_count =
-8
-
-ext_scale =
-15
-
-num_maps =
-0
-
-code_block_mode =
-1
-
-op_flags =
-RTE_BBDEV_TURBO_NEG_LLR_1_BIT_IN
-
-expected_status =
-OK
diff --git a/app/test-bbdev/test_vectors/turbo_dec_c2_k3136_r0_e4920_sbd_negllr.data b/app/test-bbdev/test_vectors/turbo_dec_c2_k3136_r0_e4920_sbd_negllr.data
deleted file mode 100644
index cbf4e72..0000000
--- a/app/test-bbdev/test_vectors/turbo_dec_c2_k3136_r0_e4920_sbd_negllr.data
+++ /dev/null
@@ -1,676 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-# Copyright(c) 2017 Intel Corporation
-
-op_type =
-RTE_BBDEV_OP_TURBO_DEC
-
-input0 =
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0xD0000000, 0x33CDC8CE, 0x4FAEE4CC, 0xC7DC23C3, 0xC306D6CA, 0x2B360A24, 0xE91C423D,
-0x1F323427, 0x4B1C33B6, 0x3EC9D0E7, 0x39204DD1, 0xCCD73C37, 0xC6F6D8E1, 0x1DF828F3, 0xDEE34025,
-0xC41EC235, 0xD035E1D8, 0x3CC32843, 0x29B60C3C, 0xE92E122E, 0x454BD4C8, 0x35D02543, 0x33E4D0AC,
-0x07AF2228, 0x38C62DD1, 0x233800C5, 0x3CC02DD1, 0x35E73B19, 0xDEBED026, 0x33C5EDD9, 0x33E51527,
-0x1F21EA18, 0xCC3E3BD2, 0x013CC14C, 0x3724D23B, 0x23CDED2D, 0x21424630, 0xC5B0E64D, 0xCFC03BEF,
-0x24294241, 0x46C526BC, 0xD82F334C, 0x1E283DCB, 0x3F3F33C7, 0x4A14D2A1, 0xD92F2AF3, 0xCFA820CC,
-0xDD30C6CB, 0x2B3ACAB7, 0x4AFE29CD, 0x25BD3200, 0x2D293323, 0xD32A3B29, 0x29E64D0C, 0xBE4BFB3C,
-0xB1DD242D, 0x0427F11D, 0x3046CFDA, 0xD633C0D5, 0xC0DDBE01, 0xDA3DD9B4, 0x3BCE3638, 0x23262CC6,
-0x432BD2AE, 0x23A9E1C7, 0x1BE45609, 0x22CD35AA, 0x32D6371F, 0xCE27352A, 0xE2B73F40, 0xC2D0CE2C,
-0xE72E3A3E, 0x2FF52147, 0xEFCF2E33, 0x003103CA, 0xC6C14A33, 0x45CAC0CF, 0x011E1FD3, 0x23D3C72B,
-0x2EB644C4, 0x484BD930, 0x3AC22E1A, 0x1AB6DD42, 0xCEDDE232, 0x3ACCCC31, 0xB830CA2D, 0xC930D2D7,
-0xD0E049BB, 0xE6243524, 0x3EF53914, 0xCB083BE3, 0x411EDBE9, 0x30C3C3E8, 0x3721F5E7, 0xBBDF3FD9,
-0x2AD21F33, 0xEE402858, 0xD3AFD237, 0x3D39401D, 0x30003623, 0x4734DC46, 0x192ACD32, 0x3324CAC2,
-0xD714D4B5, 0xDC2E21D0, 0x2327CDBA, 0x15B739C3, 0x31C9EEB8, 0xFAB5372E, 0xC239B5DA, 0xE628440F,
-0x34D425C6, 0x293BE6FD, 0xBDC04BBC, 0xE0DDB7CF, 0xD627BC34, 0xA5422FCB, 0x13211ABC, 0x1708E51C,
-0xCE33DAD1, 0x51AEC731, 0x2E383824, 0xC722D0D3, 0xCB32292B, 0xCECC402B, 0x1B312EF0, 0x34CF46CA,
-0xE3BD252C, 0x0C21EC36, 0x4ADFECBE, 0xC4D2E62C, 0xADE5BAD3, 0xDDCC1D18, 0x521AC135, 0x3F302D37,
-0x22CE2DCC, 0x262A1BCF, 0x4EE7D7CA, 0xD43D3526, 0x1840E020, 0xC3201F2F, 0x3ACB453E, 0x41EAD5B6,
-0xB6C4CF17, 0x243A55D4, 0xC7501E28, 0x351DCD1C, 0xE3A8D502, 0x3235271C, 0xAC342F00, 0x34B4E3D8,
-0x36473AE4, 0xAE403CEB, 0xBC3FDA3F, 0x552CDBEC, 0xE7C42B5C, 0xE743E13D, 0x18D44650, 0xBA2EDF31,
-0xB5C3EC42, 0x432EBE2E, 0xADDE4F2A, 0x401BCAD6, 0x03D6EAEB, 0xD0DEB133, 0x153FC4D4, 0x30DA2FD3,
-0xEE282FD9, 0x242ADC39, 0xD72B42D9, 0x44C7E0D5, 0xC72CB3C7, 0x27C9472B, 0x0036DFB6, 0xD9C53112,
-0xC0360E0E, 0x4EEA0E27, 0xEDCF27C1, 0x1739D5DC, 0x22DE2CE1, 0xDCCAF633, 0x31D02417, 0xD7DCD0DA,
-0xDE1DE0DC, 0xD827DD22, 0x1CDBD7EC, 0xCE171BCB, 0xEE2347CF, 0xC22C312D, 0xDBCC2A38, 0xBE0ADED4,
-0xDC20CC2D, 0xD5380DB2, 0x2A32C701, 0x3EC7D41E, 0xCDD7D74C, 0xE83E2A44, 0xC12B26E6, 0xE70046D7,
-0xD626D1EC, 0x35DDE41D, 0x303F27BD, 0xC94D4517, 0x31D1E229, 0xAD3529BF, 0x3AC5D21C, 0xCF1DB731,
-0x2738DBEB, 0x1F382B33, 0x1ED52213, 0xFCE22CD2, 0x1330331E, 0x4A30BA0F, 0x1F38B42A, 0x2E34CB1F,
-0xE3E125D5, 0x3AC72D17, 0xBD3C342C, 0x37272810, 0x1D34E4C7, 0xE5CC2EF8, 0x1E2FF1DF, 0xB9294236,
-0x26F10017, 0xBDE3FBD1, 0xB7DB52D0, 0x2E3CB8E9, 0xB3343D3C, 0x3E3BDFDD, 0x1F46393A, 0x25FA20C1,
-0x2D194CD1, 0xE9471D26, 0x34C3242E, 0xAE012034, 0xC8F3FED7, 0xB825362B, 0x322DC136, 0x42F41511,
-0x181855C2, 0x4937D5EB, 0xE13CDC23, 0x08242A28, 0x2DCCDFC0, 0x13CEC64F, 0xB3E6F7ED, 0xD93401EE,
-0x3D02DEE0, 0xCFC52300, 0xD2F1BE38, 0x2D092924, 0x253E2AF0, 0x37DACAD0, 0xDB1ECFE7, 0x40CED84D,
-0x3706C42A, 0x4231D91A, 0xDD30471D, 0xBD272DC8, 0xCB1941D9, 0xC22FC7C5, 0x333F3C0C, 0x3F3D2518,
-0xDDCCD143, 0xB3D834D5, 0xD231BEE4, 0x2BDB3B3D, 0x2F2754E7, 0xEAF3CE64, 0x3632E4C0, 0xD83324C2,
-0x11A4D5CC, 0x00D627D3, 0xD51F2731, 0x17C92BE2, 0x1AD62E1E, 0x16DB2418, 0x16B83823, 0x2711D54B,
-0xDFB02BDF, 0x28CDA600, 0x2AE9ED3E, 0xD314CD20, 0xD04F272D, 0xD0F9CD37, 0xCC1735E5, 0xD328EC37,
-0xA7D31A26, 0x214BD9A5, 0xCFCB4226, 0x233C4AD5, 0x26EF37D8, 0xD83E3230, 0x3EC8C93C, 0x07B9282B,
-0xD1E6DAF2, 0x31C52EDD, 0x3A0038A5, 0x56C1E0DF, 0x22E437C0, 0xDBC8143B, 0xCF1DB03F, 0x1D4BE636,
-0xB8D3C23A, 0xBCC3372E, 0xAF284228, 0xDCE02F1E, 0xB9D4E3D4, 0x56D3D0D8, 0x494816C1, 0xFB1240C3,
-0x23B1BDD2, 0x1236322E, 0xC2CBCB47, 0x102FE7C8, 0xBB0AE1D9, 0x3831BC29, 0x39AECBD9, 0xC7CF1ED2,
-0x0AE43913, 0xDDD62F2C, 0x4FD522E6, 0x3CB90A55, 0x2101C8EC, 0x432604BD, 0x29E3E31E, 0xC25B3C29,
-0x20E927D4, 0xD4300C41, 0xD9AECBD5, 0x48D8E143, 0x2CEE272F, 0xD2C11FBA, 0x2F2DB8D7, 0x1CF4DFE6,
-0xCCDCCEBF, 0xE052D0EA, 0xDADDEB1E, 0xC72ACB3A, 0x332E2B1B, 0x2D26E827, 0x2A29E6A6, 0xE614D6D5,
-0x221D1CC5, 0x51102031, 0x1735C248, 0x31D4DCD5, 0x3C20DC00, 0x2D231732, 0xE54AD9CD, 0x1D24D826,
-0xE936373A, 0x20C0D3C9, 0x2B231520, 0xD6CED133, 0xDFC8C7B5, 0xDC2FE8B8, 0x3332249B, 0xC6E6E11F,
-0xB7DA17AF, 0x1FD91321, 0xEE29CD41, 0xE1262FEF, 0xB6181DC6, 0x24F618C6, 0x3BE5DA2D, 0xFC2C35C8,
-0x51C232CC, 0x36183EDF, 0x2B2CD6EF, 0x2F2DBDB9, 0x00D03413, 0xCDC9CBC4, 0xDB3309CC, 0x264EB22C,
-0xCED1EAC9, 0x38D53F27, 0x2EE7D6F3, 0xC7232C23, 0xCCD42515, 0xC9C8C8E3, 0x231E3930, 0x5BBEDFCA,
-0x34D7E5D7, 0x25CCE9A7, 0xCD4BF1E8, 0x5E2542E6, 0x38DCE43E, 0xDA34F0CA, 0x2EBFF841, 0xDA422D3E,
-0x13CA2231, 0xD5C6DA27, 0xBAC0C6B6, 0xC82C49FF, 0x31312123, 0xBF00DFBF, 0xE8F23819, 0x2C34E81E,
-0xDC4C2B0C, 0x3A5650F2, 0x2CCB0FD0, 0xC42D4C28, 0x4F19DA4B, 0xF63DE630, 0x29F51C1F, 0xD6BE14C4,
-0xD2DDCDD6, 0xE0D02825, 0x2FE0E3D1, 0x41342FE8, 0x25D547ED, 0xC5A732B5, 0x19BD503F, 0x4CD9DA3D,
-0x24D013BF, 0x4FE93FCA, 0x12DBE8B9, 0x33DF151F, 0x1E24AECD, 0x2E2E3656, 0x133500AD, 0x3641403C,
-0xBDDF2BD4, 0xE33130E0, 0x3DC02726, 0x18390C3C, 0x26C04DC9, 0xDBF22D35, 0xC3E1EC45, 0xCED12623,
-0x1CE92E39, 0xCF2FD222, 0xD8DE31E6, 0x1EE916D1, 0x35DCB621, 0x19C2EB54, 0x41B34ED4, 0xD9373BDF,
-0x203ED6D8, 0x2CD4A8C8, 0x14E0C6C6, 0xDF242131, 0xCDD921CF, 0x33AACBCC, 0x2AD1A5C6, 0x3ED42B00,
-0xBF181FD0, 0xC0CC2329, 0x1BD1EDC9, 0x3A2D47CB, 0xDD27D8CB, 0xD8E8BAE6, 0xD5DE3FF5, 0x2C30D641,
-0xDCDCDF26, 0xC2C34433, 0x2837F53D, 0x29D8E12D, 0xBF3FEBD0, 0x34CACC45, 0x30E1DA21, 0x39DDDCB3,
-0x30193518, 0xC0132E19, 0x313D3736, 0xB2D4FF34, 0xF4D92945, 0xC70D3AEA, 0x3E3034F0, 0x00DA2F07,
-0x1DD415EB, 0xCC1AC4B2, 0x232EB21C, 0xD7431E16, 0x2FCE0835, 0xCF39242C, 0x1BCA2CD4, 0xD8B6D0FA,
-0x18C3262F, 0x2CE3BDCB, 0xD839DC38, 0x26161D24, 0x1223B3DC, 0xD6D63515, 0xCFBABFC6, 0xC1BF18C7,
-0x2637C715, 0x264020EA, 0xD024D3C4, 0x4126A11D, 0x2E34442D, 0x32BB1CC9, 0x36E7DD40, 0x3113C3C5,
-0xD100C8CE, 0xD21651E8, 0xC3CFCDD9, 0x403139F1, 0xD3D02119, 0x32171AC8, 0xD2F9B62E, 0xB5B335D4,
-0xC1462835, 0x1F1C2C35, 0xD8DDBF35, 0x422D2DDA, 0x38ED19D7, 0x3326BD2F, 0x4534DFCE, 0x46403132,
-0x19CDD51E, 0xCBC3CBC0, 0xE3CF2139, 0xC646ECD8, 0x29E7C7DD, 0xE94CCAF8, 0xB8C6EA37, 0xEC2B09DA,
-0xC8C82738, 0xC6CCDDFB, 0x3FCA3B4D, 0xC6482BD1, 0x2DE1D333, 0x3530BB3A, 0xBF4838EA, 0xE4411ACB,
-0x3514D939, 0xCD372B27, 0x4BEC1C39, 0xAB21C221, 0xD8D83F37, 0xCCE0512D, 0xDA4640C2, 0x36AE1CD6,
-0xBC2F303B, 0x20C3B8CD, 0xBFE6D4E0, 0xBECCC4EB, 0xC7CC1E4E, 0xCC2BD03C, 0x3738C518, 0x23B824CC,
-0x2BECD0BC, 0x2107B945, 0x2AC21B00, 0xBE49F2EB, 0x31D2E3DC, 0xDAD23F11, 0xCDED3137, 0x3ABADA3A,
-0xD9C0C12C, 0x36CEE8CF, 0xD0D5BDD3, 0x2AC9CFCC, 0xE61FD747, 0xC7B7B12A, 0x2BD520DF, 0xD5BC1D31,
-0xE6D8423B, 0xCC21EB43, 0x1F46292D, 0x171EE038, 0xDFA5E244, 0x1BD5C4AD, 0xC622C2B5, 0x4E33CFD3,
-0x3F263F30, 0x34E4CF15, 0x0041CC36, 0x4021DB29, 0xD62E2231, 0x2C22AE21, 0x1A201F44, 0xC6D7C100,
-0x3A335125, 0x42473A2A, 0xDF32DA1F, 0xE5D8B51F, 0x3049E832, 0xE6DED531, 0x315DD01E, 0xDDD92034,
-0x2EBF0AEB, 0x4B4639DD, 0xBED6C8DA, 0xDABA3714, 0xDD133BD7, 0xC934EACF, 0x0D35C3E2, 0xB4CCC213,
-0x37EE202B, 0x0AD21AD9, 0x28D2C9CD, 0xD800DB2D, 0xD34B274A, 0xBDD33644, 0x38EFF1CC, 0xBDABD734,
-0xB11E3E32, 0x2F1C23DC, 0xE80BD7DE, 0xDBE7D6F7, 0x240248BF, 0x23CEF1F6, 0x1F56E634, 0x33CD2230,
-0xB4DB182F, 0xD338BA36, 0x33392B24, 0xBB3B3649, 0x282F30E7, 0x45CC35B1, 0x46261B30, 0x1FD9A722,
-0x3BE3E1C3, 0x25334FF0, 0xB8BB28C0, 0xD751E2CC, 0x403600E1, 0x461FC3ED, 0xCB30C202, 0xD8D2B92A,
-0x2923D71B, 0xB9DDE6CC, 0xB935CB0A, 0xEF37D723, 0xD1DA06CD, 0x303CE928, 0xF8B9BA27, 0x37370A1F,
-0xD6C1DDD9, 0x18B6463F, 0x28C71FC3, 0x38D8B53A, 0xD22DE9A1, 0x18DDB236, 0x0A28D515, 0x363B263D,
-0x1F3A122D, 0x202AE323, 0xC72337E8, 0x32ED08CC, 0x2658C347, 0xC6F4E200, 0x45D1C2C3, 0xF92D343A,
-0x3EBE1E65, 0x10EB2FD3, 0xC64FD5E5, 0xC5D3F521, 0xE9CA1A37, 0xD736CDD6, 0xDCC7C233, 0xC9C8E2D4,
-0x2B99D60A, 0x1EE3DA0D, 0x30BDD8E1, 0x16D3BE1F, 0x1C4524D4, 0xC8D5D432, 0x19AEDA3D, 0xCDD4CAD5,
-0xD835332E, 0x2412DA1B, 0xD0CBEBD7, 0xC3CEF425, 0xD1D743E3, 0x000A163B, 0x23DC3129, 0x202332D1,
-0x322F2216, 0x28F5131A, 0xD316CF0D, 0xD0344C30, 0x423325D7, 0x37204237, 0xEEDDC721, 0x2038E805,
-0xD525C522, 0xBEDDE327, 0x3AC8BCC5, 0x45402E27, 0x34DFC1D9, 0x2DB0D049, 0x322F2ACF, 0xDB3AC3C5,
-0xD8D0EB4F, 0x2A1DCCCC, 0xD0D33DC2, 0x1349DC45, 0x39CBBC32, 0x30301EBF, 0x2C00DFC0, 0x5DD0CA11,
-0xD0220C3A, 0xC527CD1A, 0x31CD372C, 0x2E0ED7DC, 0xC6F92338, 0xF537E8D0, 0x3626DBBF, 0xC9C3C6C3,
-0x30DDBE17, 0x50394C39, 0x3A11343B, 0x27E8DC2E, 0x0DDB303F, 0x1818BCF0, 0xC5DC17DB, 0x24C53A26,
-0xECB0E7E2, 0xC21B1928, 0x15D7C920, 0x4126AACE, 0xE214D8C7, 0xD40BCD42, 0xB2CBD018, 0x554436DB,
-0x3C2D25D9, 0x21CEC0DC, 0xE9251919, 0xE41ACDC3, 0xDECF67C3, 0xEDDE3225, 0xCA30EEDD, 0xCFE01E37,
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-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
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-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x13000000, 0xC9112F26, 0xE3DF1FED, 0x284020CF, 0xC6ED13CA, 0x38B1E217, 0xD90FE8DB,
-0xD7C0C3B7, 0x341336CE, 0x45E2D239, 0x3E22F0D8, 0x461D2C29, 0x3825D628, 0xD733E5F1, 0xD7B6C532,
-0xC62B28C7, 0xD0BF3024, 0xF0BA3A26, 0x2D1D2836, 0x1BCF2DDE, 0xD02B251A, 0xB938CD2C, 0x34E220D9,
-0xC2BEC23B, 0xCC2908CD, 0x1D080039, 0x42BB25C5, 0x32EB3206, 0x36D3D1E0, 0xC32E10C3, 0x243B13E6,
-0xC02A1FF0, 0xC325D6DD, 0x23E33D2C, 0xDCD7DED5, 0x9C23C21D, 0x32E62056, 0x06314421, 0xE9E4ED24,
-0xC0C9C233, 0x44BE3FDD, 0xD25134E5, 0x292EE2E7, 0x4EE0D1DF, 0x29C82E3A, 0xF5392A22, 0x4BE2D133,
-0x58C2C4C8, 0xD2212920, 0x2935D4DB, 0xDECF4400, 0x31D7CCC9, 0x12DCFB2D, 0x2B2F0723, 0x2DE7B54E,
-0x2AD24ADA, 0x261E2931, 0xD538CEDF, 0xE12A1C2C, 0x33DDEDE9, 0x2FFC36C4, 0xE61823CE, 0xC225E1DF,
-0xC2102FEF, 0xCFD22617, 0x3EFBDA37, 0xDAD6BCD8, 0x110623E7, 0x3320E2D1, 0x1932B8D5, 0xCCEBBFC9,
-0x47234011, 0x0A2B45D8, 0x25C11244, 0x00EF3221, 0xC634CC38, 0x0F34D0E6, 0x1A3F40EA, 0x2DEDC82D,
-0xFFD2C8BD, 0x40E321CD, 0x24441BD3, 0xD932EDDD, 0x48362127, 0x1230EADE, 0x39E632F9, 0xD0D451DC,
-0x18DD2DC0, 0xC22AC72E, 0xD71E172E, 0xAFDED12B, 0x1DBAA948, 0xF927B647, 0xD7C31C23, 0x3328E73B,
-0xDBD72DD9, 0x3E23D424, 0xCB09E025, 0x16BA21CF, 0xDD00B9CB, 0x29E3CAD7, 0x3A19D011, 0xEA0EC4E0,
-0xD51CDDBF, 0x2AD1C640, 0x2CD6CBD3, 0x36D6D43C, 0xA72851C2, 0xE7EE3C3F, 0x432A4721, 0x46C726E5,
-0x253FD426, 0xD03B2C27, 0x1AEC343B, 0x5A2BC735, 0xCE31D2D2, 0xCFEDF30D, 0x492B4141, 0x20DC1BAD,
-0xDAF81CD9, 0xD6EAD21D, 0x2339CD25, 0xA31546BB, 0xD0C0F63F, 0x382BE719, 0xDA34BFDB, 0x1EDBBADF,
-0x5151E646, 0xC164D5E2, 0xD8292FCA, 0x33CF1F3B, 0x3FF531F4, 0xD3EB3453, 0xD433E236, 0x1B102B1C,
-0xC6C320E8, 0xD8393C2E, 0x17EAB7EB, 0xE0C42CE5, 0x313720CC, 0x3F39C42D, 0x33374AD5, 0xCE1ED41E,
-0xF7D2BE0D, 0xF114311E, 0xE22CD6EB, 0x4E23CA2A, 0xCDCF36D3, 0x463B1EC4, 0x312DE400, 0x1A1219CE,
-0x0CD1E2C3, 0x3850CBEA, 0x31D7CCCD, 0x3F2D3936, 0xC518E33E, 0xC31F31B7, 0xC0AED6C9, 0x2AC6E5D9,
-0xC334B8BF, 0x35EFD72E, 0xD72B3AD8, 0x31073AD7, 0x25E22D38, 0xF0CD4A64, 0x28DFDB2D, 0x22D9E714,
-0xB8E43935, 0x35FCBFEC, 0x1DC1391E, 0xD6E731A5, 0xBBC8B837, 0xBD3FBE3A, 0x00BADC53, 0x28C43F33,
-0x1CE0BAC2, 0xE0E125D9, 0x3BD6CB3D, 0x313230BE, 0xC4243D34, 0x1F24D2B1, 0x2058384C, 0x2AE9192D,
-0x302CCCEE, 0xD435C4C7, 0xB0D53217, 0xE52D32D9, 0xE0AF2127, 0x3E47D0CA, 0x4112BFCA, 0x27D0D0BD,
-0xE81E5CF9, 0xD50CBCE5, 0x2DC9B4F7, 0x3FBA33BC, 0xCBCC2821, 0xDFD51326, 0xD20ADA3A, 0x2000C3BB,
-0xC4DC4BE5, 0xCD39D7A7, 0xC40FF54F, 0xCC3BD1CC, 0x2C19EACC, 0xCD2E2129, 0x44D9F0DB, 0x2B40E11C,
-0x31343F4C, 0x0E142817, 0xD0104135, 0xE304CAC7, 0x259A1FD4, 0xC3EAED3C, 0x1A311AD7, 0xD8242BEE,
-0x20BF4EFD, 0x3FCA16C5, 0xDDEED03A, 0x0A22C52E, 0xD53B2D3A, 0xE22A2CB5, 0x291D3228, 0x2CCC2E45,
-0x48BA00D5, 0x4FE12D1D, 0xD8D91DD1, 0xCEDBEC31, 0xFBD526B9, 0x3C1DE845, 0xAFDCE91C, 0xD622D31E,
-0xCF2620D9, 0x28D63427, 0x362C3DDF, 0xD72C2530, 0xD6A7C203, 0x442C3233, 0x29B24E3F, 0xDD21412C,
-0x400BD6D0, 0xC8D4B831, 0x171EF12A, 0x34FFC9D0, 0x3B3ED02D, 0x0BC7E2CB, 0xC43D28C6, 0x42F6C948,
-0xD24AD429, 0xCB2C2A00, 0x43E2A236, 0xBC353312, 0xD91324B5, 0x30B4D013, 0xC92FDE2F, 0xBFD6D432,
-0xC82DCABC, 0xC032DC1D, 0x30C9D2CB, 0xE0341DC5, 0xDDCEBE39, 0x2CC41D58, 0xE213BF14, 0xDFCDCBD9,
-0x2E3C36DD, 0xE5262833, 0xF841291D, 0x15E324F5, 0x0315D732, 0xD1C5C5CA, 0xD73144D3, 0x2ABEBA1A,
-0xBCF42E2C, 0x00E1E53B, 0x4423AD2C, 0xB021CF20, 0xD8D5EEB6, 0xBD35BCCD, 0xE6D85334, 0xD549DF2D,
-0x35C74D19, 0x3F4BBE3D, 0x1F3FA3EB, 0xCEB2B335, 0x35D0BCBA, 0xD5D8CF27, 0xB11DCFC4, 0x24D3D408,
-0x183B35D0, 0x1C14D619, 0x35D445BB, 0xDE452444, 0xC83315C5, 0x3F2122D0, 0xB623C737, 0x33321DD0,
-0xD6DF33DE, 0xDE39AA20, 0xCF00F239, 0x412410D5, 0xC5DC2339, 0x1D3BD1B6, 0xC0E3481E, 0x1030451A,
-0x30EA30D1, 0xC6DCB9C7, 0x2C36DC17, 0xCBB0ED30, 0x26C20FBE, 0x35D6D528, 0xD6CC2242, 0xEDE4241E,
-0xC036DED9, 0x26303627, 0xB6B6371B, 0x26E3D6DF, 0x0D36C729, 0xBEEE4FD7, 0xE3C839D1, 0xC0313031,
-0xAEAD2828, 0x36323D23, 0x13342728, 0x2904EE20, 0x261DDCD6, 0x0CBCE1E1, 0xD2CBD5C3, 0xFD1C4B2C,
-0x1CD8CDDB, 0xD4BE53B1, 0x2BD6CDDE, 0xC61A01E1, 0x3D41BED3, 0xE0333BD0, 0x4040E821, 0xC4A32449,
-0xD3D3A8BF, 0x36E11C2C, 0x3CC1321B, 0xC5D03E1C, 0xB813D9DD, 0xD6C51838, 0xCEBED141, 0x1FEA3813,
-0x3611CAC0, 0xD12EE2C6, 0xE1BFD22D, 0xD0DAE9CC, 0x0E03DB00, 0xBC37393F, 0x422BC916, 0x49C4D72A,
-0xBFC0243B, 0xC1C2F1C3, 0xDF36CC32, 0x49E53EE4, 0xBFC02CDF, 0x2BEE2BE1, 0xC23224C5, 0xD63F16DA,
-0x15DBC21F, 0x49E4CC57, 0xBE272CC7, 0x274E0643, 0x5C1DDBE7, 0x34B73DF0, 0xCD2D2EB9, 0x1AD43BCD,
-0xFD3047D3, 0xDAC53936, 0x1328DCC8, 0xBC32331D, 0x001F2634, 0xC845410F, 0xDBDB1C2B, 0xD1D819D0,
-0xEBDDE12D, 0x37E335D7, 0xCDA84635, 0x0F362FBE, 0x30C229C4, 0xBC1DC43E, 0x3CD02F3D, 0x2EF5F5F4,
-0x462D15E6, 0x362F1FC5, 0xC0C9CD49, 0x14C92639, 0x2BD135D0, 0x49C6B8DA, 0xDBC7E1D9, 0xC6382328,
-0xEDC217BC, 0xE4D1331C, 0xDCC741CF, 0x283A341C, 0x38B93420, 0x46001BE7, 0x3E1030C4, 0x42A8C1CD,
-0xBB3339C5, 0xE538DD20, 0xDF3F2602, 0xE52BE5C1, 0xBE2B41BA, 0x3BD4D337, 0x2D39C3DB, 0xC3BB36F0,
-0xD12CCF17, 0x4130B93A, 0xE31DEAEC, 0xF9DEF52D, 0xADD35231, 0xD62ED0EF, 0xBE303521, 0x1E2ADB41,
-0x310AC62F, 0x22DA2DC5, 0x26E1D9D0, 0x1F4D2AC1, 0xC8E6DCE1, 0xC6B3D62E, 0xD6D20019, 0x4EDC2D39,
-0x342AE224, 0x07CBD4CB, 0xE43FB3BE, 0x1BE53748, 0xDD44C8A2, 0xBC34B7BA, 0xA1DD1D43, 0x23D31827,
-0x3519E93F, 0xC83B3720, 0x1BF0B72A, 0xEAC7DCC0, 0xCA4B28EC, 0xD54D242F, 0xF35435D1, 0x3DDEC824,
-0xC31128CE, 0x0B0FD136, 0x442D1E2B, 0xCBD1C3EC, 0xD635341B, 0xDD1F2931, 0x3442CDD0, 0xDADD3600,
-0xC31E40E3, 0xB0BD1B22, 0x38CA1F0D, 0xD42D3043, 0xE65127E4, 0x2F15C9D6, 0x3E360B30, 0xB2CB1524,
-0xC7BBC4DF, 0x38D244C7, 0x483B31C0, 0xDB43C8D1, 0x43DCDBBC, 0xDCC7571D, 0x24BAC2C6, 0x3B4ED6DC,
-0x3AE03245, 0x0C40E1E2, 0x493724C0, 0xD4ECC537, 0x36CC30BA, 0x1C303FC6, 0xD12F27D5, 0x00C4272F,
-0xFFFD061D, 0xC2D9251D, 0xC1D7D625, 0xBFCD3AD3, 0xB42E11D4, 0xC7230E1E, 0x24CD2C21, 0x0BD436F9,
-0xCECCD331, 0xE6BDE0D5, 0xD2C6C941, 0xE1D1D3EF, 0xEB4123CD, 0xDA1755E5, 0xCEE4C529, 0xDC43C5D1,
-0xD8FDDFEA, 0x1AC9C317, 0x22E13DCE, 0x01D7BA29, 0x1551E449, 0x43CD363E, 0xC6281B24, 0xCBD23725,
-0x3200D61C, 0x35D6CCBC, 0x262CB22C, 0xE2E43DB1, 0x26493335, 0x3AD72ACA, 0xC4244430, 0x3AD7C9C3,
-0xC91ED8D1, 0x40EAD2AC, 0x38C9CDAC, 0x413BC137, 0xCD304B1F, 0xEFCA2323, 0xAC3FE4CD, 0x3616F6E0,
-0x41C2272A, 0xDCD7B2E2, 0x27D9E018, 0xDEE2D943, 0xD5C01F22, 0xB0D93540, 0xB411C13D, 0xDE39CBE0,
-0xE2C6F126, 0x31450828, 0xD2BC2927, 0xBACA1DD1, 0x34DDCDC3, 0xD8302AD5, 0xE2D02824, 0x0B2BE03E,
-0x3BCAFD2C, 0x2E461D45, 0xBBF6F32E, 0x31E5DED2, 0x2ED4E847, 0x3BDDCD29, 0x231331D8, 0xF521CF2E,
-0xD024C718, 0x20D91011, 0xDB1E0F34, 0xD931C0BB, 0xBB310837, 0x29B7C5CB, 0x3B31DEE0, 0x0836B926,
-0x28CB1FD4, 0x31072A30, 0xEE41F300, 0x35CB501E, 0x603A2B47, 0x2C2739CE, 0xC0CFC4D9, 0xE0CED43C,
-0x22BDC9CA, 0xBAEC122D, 0x4D16F2C5, 0xB6E5C3DA, 0x19D5C9D0, 0x1D1DDFC2, 0x223A23FB, 0xCD382B09,
-0x3025C2E6, 0x3918BDD5, 0x33DFEF0E, 0x291A302B, 0x14184930, 0xD414D233, 0x473CCED7, 0xD2D318B7,
-0x3E2738D2, 0x2928D537, 0x002E14BB, 0xE2E03734, 0x1B1EDFD1, 0xCF483FD8, 0x3D043844, 0xD52E1C4C,
-0x2823EAD6, 0x1F2D241A, 0xBC4B22E6, 0x2EE7DFB8, 0x3424E2F0, 0xD41BD7CB, 0x2BBCDF1E, 0x155B5033,
-0xB527D543, 0xE3C5E9F4, 0xD9B5C92B, 0xD3CAE0DF, 0x31C4CED7, 0x0BD33B25, 0xCF3B111D, 0xE62F241F,
-0x22D93D22, 0xCF27EF43, 0xDAD2C5DD, 0xC60019BE, 0x2935D5C3, 0x2D0BCD22, 0x224714EA, 0xE7CAB817,
-0xD1282222, 0x3C25EBD0, 0x45F0A8DC, 0x3ACFB92D, 0x34B4E7E6, 0xE93523E0, 0x2C292FCA, 0x44D4C7AC,
-0xEA22C3FE, 0xEF37E524, 0x313ADCDA, 0x2212D846, 0x1BE0FF4B, 0x1CBC2E34, 0x174AF041, 0xD245223E,
-0xE1DB2BDC, 0xF2E9A515, 0xE3C33BCC, 0x43DBD5CE, 0xF11700DB, 0xDE44DD36, 0x26E1D604, 0xC2ACE419,
-0xB9D8C7D4, 0x37EFE21E, 0xE2BAC2D1, 0x3926E91A, 0xD013E8BC, 0x2C43ECD9, 0x232B30F8, 0xD6C9E0BD,
-0x26A718BC, 0xEFF6C840, 0xC13332C2, 0xC4B9BD36, 0x1B4921BD, 0xD0EBECE0, 0xBCE4D647, 0x35D4DCD5,
-0x1BBE4C27, 0xECC1B7CB, 0xD820284D, 0x0BC33DBF, 0x34D03140, 0x38EC3900, 0x29EBDBC9, 0xD43A3041,
-0x3AE0DD0C, 0x09CFCFDB, 0x44E0C7CE, 0x20DBC4E3, 0x26DC41DE, 0xBA3AD2E5, 0x2ABA34E1, 0xD70FBEB7,
-0x40E03FE2, 0xF8D62041, 0xBD47B7EA, 0xD2E03E34, 0x1FC6D2DE, 0xCF1CD155, 0x32D52630, 0x3C463D2C,
-0x253130E3, 0x1ED8BB4A, 0x411BDFDD, 0x3FD8EE35, 0x33D02BBB, 0x002ECAAE, 0xDF1FDFEB, 0x2CD8DA3C,
-0xB6352D59, 0xD5BDD3B9, 0x1946630D, 0xD9181731, 0xD419D31F, 0xCE2FB7D0, 0x32EFE3C3, 0xCDDB2FD3,
-0xD247BB3E, 0xBA41DECA, 0x23244AD2, 0xDEAAF2B2, 0xB8D525F2, 0xD327A4D0, 0x3718C0E2, 0x2D3E20D9,
-0x24CFDF12, 0x26D0BE1C, 0xC8D9282E, 0xEB54CADF, 0x44DB1AED, 0xC927BF29, 0x2E002B39, 0xBB2625E4,
-0xBB4421D2, 0x18CBAA3A, 0x213ECD37, 0x0F33163C, 0x3622E432, 0xE5C7C62B, 0xDE39E7C7, 0xF3151CCA,
-0x2ACED6D2, 0x2ADADFC4, 0xD6241ACC, 0xB92F0622, 0x1BC639E4, 0x33D92BC4, 0xAF14E0DD, 0xE6EEC2C9,
-0x16BDCAE3, 0x272E1AC3, 0x292E1EBE, 0xDCE439B1, 0x4225E1C6, 0xCD372420, 0x27D716B1, 0xD83EE339,
-0xDBCAD4B3, 0x26385033, 0xC5373528, 0x2DD2C936, 0xF9D5BAE6, 0x2E2DC7C2, 0xCD4BD045, 0x1DDF2DE8,
-0x0E3740CE, 0xE5D82C36, 0x29D1360A, 0xCD03C8C6, 0x37CCCCD8, 0xD83AD330, 0xBFD619CD, 0xDEDDC432,
-0xD0DADAEC, 0xD3E14F26, 0xA8CD35D9, 0xA3F325BD, 0xBC1626D7, 0x3AB81BD5, 0xBBFF1832, 0xC9DB2126,
-0x16250000, 0xE003BB39, 0x35D533CE, 0x1801C610, 0xD9D44644, 0x474BD3C3, 0x1C30C51E, 0x2E3342C6,
-0xB7D6B3E9, 0x5AE44BD2, 0x46D62830, 0xDBDD4B0C, 0x38CF2F1D, 0x2D331ACB, 0x36CCDED6, 0x10D7DA10,
-0xD42246E0, 0x0FC73FC0, 0x2C3E1E37, 0x2CF0D1B8, 0x17412EDD, 0x2630D0DD, 0xDBD535E4, 0xD927DA43,
-0xB636C11E, 0x25CBE2D8, 0x4711F64B, 0xBC2C2029, 0xD0E3F538, 0xB92C27DF, 0x272DE2D2, 0x0CC5BCEB,
-0xC0BC2EDF, 0x26D131C9, 0x1F092FEE, 0x2D342B34, 0x31B825D5, 0xC6BBC9C1, 0x38F1D0E4, 0xCBF7FDC7,
-0xC3CAC9B6, 0xDBC436C6, 0x19DC1FD8, 0x28CCAED1, 0x1921BDB4, 0x24BCBF33, 0x301EE244, 0x36BDBDE1,
-0x31C5B724, 0x00003ECD, 0x220B1EE7, 0xDEBAD3DC, 0x21CAB942, 0xC9193B33, 0xE3CD3A0A, 0x0DC22CC3,
-0x3EC0C7CB, 0x43F2BFE4, 0x0ECFE9C6, 0x3ECA2FD5, 0xCB492DD9, 0x23E7BDC9, 0xD33DC151, 0xFCBE2933,
-0x5ACEC51E, 0xF2172E1C, 0x3C24DE23, 0x3320D4D5, 0x2AB53C20, 0xC328323A, 0x45EA4133, 0x24391A32,
-0xC7D8DA2B, 0xF4EAAF39, 0xDFCA36E3, 0xDEBED5C8, 0x36252C36, 0x04D7DBC7, 0x30CAC23D, 0xB60BF73D,
-0xEACA2A30, 0x34C12ABE, 0xE2D747D8, 0x19D21FE3, 0x1DFD24EC, 0xB6B5D9C4, 0xBF2C1DD2, 0xD2B442E0,
-0x37CCE1BD, 0x2AD1E1CC, 0x18DAC6BD, 0x213AD93E, 0x2031D8CB, 0xD82F2D12, 0xD112D2F2, 0x19CD43F1,
-0x36BCB9CA, 0xD7C5DDFC, 0x34011D28, 0x3BDB0000, 0xCD00E1AA, 0x5228252C, 0x3512CA34, 0x0EE53A41,
-0x242CD2C2, 0xF425DD2A, 0xF02FDDF8, 0xD82026D3, 0x4ABEE7B8, 0x2DC9DDDC, 0x3BEECD3C, 0x2ED1442A,
-0xC713E92A, 0x310CC12B, 0xE128D520, 0x48E5C1CF, 0xC91CE3ED, 0xCCCBC72F, 0x0B23E3E9, 0xC1D2C8B6,
-0x511ED534, 0x2AC7D4C3, 0xCFDCE335, 0xD4C9F643, 0xD433EBF1, 0x1BF8DA31, 0x223FC515, 0xCC2F13C2,
-0xF825FFC8, 0x35E51633, 0x36293C4A, 0xC72ACA36, 0x4544E736, 0x1BD9315C, 0xCF16DFD4, 0xD0AFEFC3,
-0xCECBBDE2, 0x05D6AA32, 0xD851F045, 0x240FD948, 0x3D35B2E6, 0x17D7C7EE, 0x0B22DACE, 0xF53AD637,
-0xB2372DDB, 0xF6DF14CB, 0xBED95B24, 0xD4D5190B, 0x0000CB29, 0x3DC1ECF5, 0x30C6B34F, 0x1D2629B6,
-0xD429D1CC, 0xD50716E3, 0xD0C3C2CC, 0xC82CC7D4, 0x5F27C718, 0xE6201BE4, 0xDACFD42F, 0x2E2EE9D4,
-0x3AD036C0, 0x3828DB20, 0x27D63439, 0xD21026DE, 0xD60710BC, 0x13AEB9E9, 0x28C41944, 0x49D5E3D7,
-0x27163429, 0x1BBAD528, 0xB12A14BC, 0xC72FD9E2, 0x1F43213A, 0x133B3EE5, 0x3622FE21, 0xD438DCBE,
-0x41CB25E8, 0xD0D83E2C, 0x32BFC2CE, 0x362BE1DA, 0xC3CBCE24, 0x22DECDC2, 0x30CBD5CD, 0xD42DBC26,
-0xDDF6AAD0, 0xCADC0EC8, 0xDC333434, 0x333114F5, 0xCE24361A, 0xB1C5D123, 0x4B25380B, 0x2FEC3634,
-0x3EE2A610, 0xB4CEE72F, 0x29BCC721, 0xB23850CD, 0xA51AE4DD, 0xC81BBC2F, 0xD4DF0000, 0x2DE5D1E8,
-0x2E0A28D0, 0x29E3C1E1, 0x56F62DD6, 0x3828DD4B, 0xC41ACFDF, 0xD2390A3A, 0xDF3028CC, 0xE8C5E22B,
-0xD11CDCC1, 0x44D1CBEC, 0x33C73DDC, 0x1D25B7DC, 0xE7DD0525, 0x2743C41A, 0x2AE2D3DC, 0x21D6E82A,
-0x133CBAC7, 0x593F34B0, 0xDA5FE339, 0x5206252C, 0x394FD5BD, 0x21D2C92C, 0x292426E0, 0x48E0362B,
-0xCC272DE4, 0xC815C4DE, 0x49BD5D37, 0x1912342F, 0x2CE9E01B, 0x30D8D2D9, 0xDEBF46E8, 0x392F473A,
-0x3A18D324, 0x2FE31FD0, 0x2B2B2710, 0xB53B2AC7, 0xB3481CFF, 0x2DD7CFBC, 0x2232351A, 0xD7C91C16,
-0x1CB4DA16, 0x1BCBDF3C, 0xD2213822, 0x2121DB1F, 0xDBD1C02A, 0x27DA33C7, 0x351FC4CD, 0x0000B9D8,
-0xC2142C29, 0x38B9DD31, 0x54E60CDF, 0x2A4A42DB, 0x35CF2BB5, 0x0CEA3323, 0xC2D8BEE2, 0xC61F3B33,
-0x10CE11D0, 0x3336CE2E, 0x303ADD25, 0x3347B7D9, 0x33222C1A, 0x1A43E4C1, 0x4326E019, 0x2AE2E92E,
-0xD2C5DC40, 0xBA45D7D6, 0xDF341BDC, 0x3A361925, 0xD4FEF4D2, 0x3018DA31, 0xDDC12817, 0x3038DE24,
-0xEDC0292B, 0x3E3E3336, 0xCB1BEF17, 0xE10B2EBF, 0x2B20BABF, 0xC80C421B, 0xC2411D21, 0xECD8C7D6,
-0xC824E4AD, 0x65B53DD7, 0x304325D4, 0xDD1DEAE6, 0xD33131CF, 0x2F36452B, 0x23B219E9, 0xC1C23529,
-0x21DC3836, 0xD618E933, 0x393E2C14, 0x362ACA3A, 0xD6E2C237, 0xD6085111, 0xD721FCB1, 0xCCE6DEBC,
-0xD1DCD920, 0xC3320000, 0xEA26CB19, 0x18BB26B7, 0x233BDF4F, 0xDE23FD3F, 0x2ADA1ECB, 0x3122E839,
-0xEF42D7D7, 0xCAC7202D, 0xCD4CDED1, 0x2633C824, 0xD0123E4E, 0x104429B6, 0xC8CD4B00, 0x5136B738,
-0xCFC8202B, 0x163135DD, 0x2C3821E8, 0x29314CE0, 0x0F3CE4EC, 0xE5432DAF, 0xC63AE340, 0x4639DB18,
-0xDF282511, 0x25B5CBD3, 0xCAF50F37, 0x1E443B33, 0xE32CD32D, 0x10DA47B9, 0xDA410526, 0x34F0E4EA,
-0xCEED3134, 0xC0B31AA7, 0xD12B1AD3, 0xC722C743, 0xBFBEDD1F, 0xD328D52B, 0xCC384024, 0x18B43FB8,
-0x281742BB, 0xD8322FD2, 0xB5D628C6, 0xE420C0CB, 0xC9EB391D, 0x41E6B419, 0xBCC543E1, 0x2C37DDEF,
-0x1F2D41E9, 0xD0F0D205, 0x1FEAE5C5, 0x15DF14B8, 0x47E327D9, 0xD328CE25, 0x36DB2E24, 0xD92E1EBF,
-0x2B3230F4, 0xD1EAD5D9, 0xC7212ADA, 0xCD1235DC, 0xC519D5DB, 0xBFC631DF, 0xD5222B35, 0x35B6DEC6,
-0x153C4428, 0xC5C3E42F, 0x1B2E2D2A, 0x3CD422A6, 0xC22842CC, 0xCADAC43D, 0x2C10DAD2, 0x18C708B5,
-0x36D636BD, 0xCD29C5D3, 0xBFED433A, 0xE0384939, 0x005629F2, 0x36E2C425, 0x2830DF1C, 0xC9CB351C,
-0xB0D7D3E6, 0xF3CEC214, 0xDC25D1C7, 0x1BD5CBCC, 0x19DD21C9, 0xC854EE30, 0x4FE14EE3, 0x38D5D3E8,
-0xC9D126E4, 0x2FDD2130, 0xCE2130D1, 0xCFCAB0C9, 0xC71F0E1A, 0x2627D4DE, 0xCBE9DACD, 0xE7121F22,
-0x2CC8E435, 0x3838391D, 0xDD37242E, 0xEBBE2F10, 0x233C0000, 0xAFC91CE7, 0xCE3536F6, 0x0F25D248,
-0x2D04EBE4, 0x3FF634E5, 0xE929CE26, 0x24E0BABE, 0x302CD52B, 0xD1E2073F, 0x4333D11C, 0xDA48C2D1,
-0x2D33F315, 0x29B2C8C3, 0x3B26E3EB, 0x3821C6DA, 0x32163DD6, 0x1DC737BC, 0x463CCD24, 0x19D63DDD,
-0x200BDDB7, 0xBDD41E22, 0xC40A444F, 0x34BF49ED, 0xD4C0C0F4, 0xA41FB721, 0xBEDF51E8, 0x15D82A17,
-0x383FDF21, 0x2B2918D0, 0xE6EB4718, 0x244530DB, 0x25DD3919, 0x3BA819BE, 0xDAEFBE38, 0xEB3FCCD9,
-0xD1DF2E1C, 0x2520C3E3, 0x32D0BFD5, 0x37312BD5, 0xDC29D0C9, 0xBED02432, 0x310C3A18, 0x411ED8D7,
-0xA4E5CE22, 0x163CBD30, 0xC3E2BE45, 0xCFBBAAC3, 0xC8C0E4CF, 0x0000CEFC, 0xE8CC2433, 0x39ED223F,
-0x243AD83B, 0xD44D39C6, 0xCABF24DE, 0x252050EB, 0x29C73B40, 0xD4F434CF, 0xCAE4D5DF, 0xC5F2EEF1,
-0x2919C8D2, 0x2FC4D20B, 0x1CBF5528, 0x3DBBD52D, 0xE03AD031, 0x3D2CCA17, 0xBE23BDB8, 0xE7DA3B30,
-0xD1D2D331, 0xCC1825EA, 0x2F2D39D2, 0xF9313526, 0xCFBCC2E1, 0xE5BE3AD4, 0xBF59BE1C, 0x22FFC8B5,
-0x32B14015, 0x31D6BEE6, 0x46DF3843, 0xDCD1D8B2, 0xE728C8BE, 0xEA1E2A28, 0xD1D8C7D2, 0x30CAF134,
-0xEDD0EADA, 0x13C1E3D0, 0xB9D7DC29, 0xEAB93624, 0x24E49F38, 0x2E3FDEDC, 0xE6D0D23D, 0x1FBB3ED2,
-0x23D540DD, 0xD727D92B, 0x251E33E6, 0x4BA7EECE, 0xC1CD203C, 0xC5CFED32, 0xB9CF35C3, 0x29710000,
-0x29D7C636, 0x3A3ED1D0, 0xCC1B271F, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
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-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
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-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
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-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
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-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
-
-hard_output0 =
-0x42441F44, 0x006DFAE9, 0xDBB63AC2, 0xA3365CB3, 0xFA44372B, 0xC2603862, 0xA6C86E09, 0x416F0BF7,
-0x8E58011D, 0x47C54B99, 0x269AD14C, 0x0B286902, 0x093E4C64, 0x8D84D8E1, 0xB8AE0993, 0x49567118,
-0x8CEAABD2, 0x12D33409, 0xE3358237, 0x130176F6, 0x0986718F, 0xA18C83B5, 0x04EEF058, 0x59704040,
-0x7478FE81, 0x01D27193, 0xEA1AD7F3, 0x21E6C2B9, 0x6478A1FF, 0xED9959AD, 0xE39E57BE, 0x4D859105,
-0x056EF72D, 0xBD170BB7, 0xF01F9ADD, 0x99BF0C05, 0x44BAD09F, 0xF6ABDD61, 0xC0F8F116, 0x2972B53C,
-0x0FEC944B, 0xD1675432, 0x0025F563, 0xF42B2EA8, 0x808E5C37, 0xB6E79AD5, 0x3706284D, 0xB9C0AFA5,
-0xFF0E7E28, 0x5FA45C6F, 0x9CD5244E, 0xA013DDEA, 0x0D27D1A2, 0x2AE414AD, 0x41614379, 0xE6B68872,
-0x5585D926, 0x5098D45B, 0xF8980ABD, 0x65821418, 0xEF8968A3, 0x301DEC3A, 0x57EF2A7F, 0xC17BE446,
-0x94B65D62, 0xC9E6F350, 0x2E6130BC, 0x235F2E5E, 0xF1C13241, 0x94B291D6, 0x8C342458, 0x175B1FCA,
-0xE07310FD, 0xD24934DD, 0x3CE8D053, 0x5C8F243D, 0x945B0AB3, 0x50EB8CC1, 0x8EF499D4, 0xA67801BF,
-0x1680F061, 0x283FE705, 0xB8D7E773, 0x13AD3D2F, 0x4A6C305B, 0x1C1E5B12, 0x6F57D880, 0x8A666E5E,
-0x26511296, 0xFFC09750, 0xFF91760A, 0xAC26795C, 0x75F321FD, 0x4221B9CB, 0x2E119188, 0x0772A832,
-0x74D6036B, 0xA001B764, 0xF0D72816, 0xCBE119F5, 0xC5D6B248, 0x1BBAB091, 0x1BBE518E, 0xC647DCB1,
-0x240CE252, 0x3F8AAE65, 0xE0CDEAAB, 0xBE724062, 0x5720636C, 0xC816E67F, 0x8E5A6C7F, 0x9E2738B3,
-0x2419CBDF, 0xA6BF9B75, 0x48B21FC3, 0x8C4AED8D, 0xC1D8BCA8, 0x01353DE3, 0xA99D7D85, 0x9C6DDD20,
-0xA650398D, 0x4E7E5777, 0x623FA183, 0xF02B261F, 0xF0BBA66C, 0x35AC701F, 0xD818E590, 0x7CA713BE,
-0x01153743, 0xD1302B91, 0x55459E3C, 0x63FDA677, 0xECF93759, 0xBBE0E349, 0x73FD4FDE, 0x5C48C9E8,
-0x70F46F73, 0x0B15437C, 0x9F4159A0, 0x7C343E78, 0xB3D085E1, 0x04266351, 0x1933DAD9, 0x83AF8C77,
-0x2AC11BE1, 0x76C25CF6, 0x083E6CF7, 0x00DDBA22, 0x6AD2F284, 0xF87DBC6D, 0x7D40B45D, 0x6EBF21BD,
-0x972E8535, 0x632B51D8, 0x5BFBA23A, 0xCDF1D44D, 0x11749158, 0x06DC45D1, 0x93D63A59, 0x9D0552F7,
-0x61C8048F, 0xBFDE9FD2, 0x77827B70, 0xFFB130DC, 0xF18BBCE9, 0xD50C324F, 0x15521E17, 0x7D2470C3,
-0x5EE34C4C, 0x2AC0C8AB, 0xB2283269, 0x4107FE15, 0xE6DA1ED3, 0x66A2A3A7, 0xB204B429, 0x0E02F9D0,
-0xE5A45550, 0xEAF94102, 0x18F57A81, 0x8EEC9C68, 0xD575F397, 0xFC1BE8BF, 0x104E073F, 0xDF219F97,
-0x2EC93D4A, 0x6033EE18, 0xC1351A38, 0x420C6A87, 0x0B5DC831, 0xD90D23E2, 0x13B9E883, 0xCD65BE3C,
-0xDB17A9CC, 0xC73C2A7E, 0x3281
-
-c =
-2
-
-cab =
-1
-
-ea =
-4918
-
-eb =
-4920
-
-c_neg =
-0
-
-k_neg =
-3072
-
-k_pos =
-3136
-
-rv_index =
-0
-
-iter_max =
-8
-
-iter_min =
-4
-
-expected_iter_count =
-8
-
-ext_scale =
-15
-
-num_maps =
-0
-
-code_block_mode =
-0
-
-op_flags =
-RTE_BBDEV_TURBO_SUBBLOCK_DEINTERLEAVE, RTE_BBDEV_TURBO_NEG_LLR_1_BIT_IN
-
-expected_status =
-OK
\ No newline at end of file
diff --git a/app/test-bbdev/test_vectors/turbo_dec_c2_k3136_r0_e4920_sbd_negllr_crc24b.data b/app/test-bbdev/test_vectors/turbo_dec_c2_k3136_r0_e4920_sbd_negllr_crc24b.data
index a866878..cfff56a 100644
--- a/app/test-bbdev/test_vectors/turbo_dec_c2_k3136_r0_e4920_sbd_negllr_crc24b.data
+++ b/app/test-bbdev/test_vectors/turbo_dec_c2_k3136_r0_e4920_sbd_negllr_crc24b.data
@@ -666,12 +666,15 @@ ext_scale =
 num_maps =
 0
 
+r =
+0
+
 code_block_mode =
 0
 
 op_flags =
 RTE_BBDEV_TURBO_SUBBLOCK_DEINTERLEAVE, RTE_BBDEV_TURBO_NEG_LLR_1_BIT_IN,
-RTE_BBDEV_TURBO_DEC_TB_CRC_24B_KEEP
+RTE_BBDEV_TURBO_CRC_TYPE_24B, RTE_BBDEV_TURBO_DEC_TB_CRC_24B_KEEP
 
 expected_status =
 OK
\ No newline at end of file
diff --git a/app/test-bbdev/test_vectors/turbo_enc_c2_k5952_r0_e17868_crc24b.data b/app/test-bbdev/test_vectors/turbo_enc_c2_k5952_r0_e17868_crc24b.data
deleted file mode 100644
index 1300650..0000000
--- a/app/test-bbdev/test_vectors/turbo_enc_c2_k5952_r0_e17868_crc24b.data
+++ /dev/null
@@ -1,300 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-# Copyright(c) 2017 Intel Corporation
-
-op_type =
-RTE_BBDEV_OP_TURBO_ENC
-
-input0 =
-0x11d2bcac, 0x7715ae4d, 0xc9f4dbc6, 0x2fda3c1a, 0x09349b16, 0x2cd3c189,
-0xe5650429, 0xc73c42c1, 0xe7336bb7, 0xbb7de593, 0x83f986aa, 0xc0ade12e,
-0x6730b095, 0x78f7c059, 0xaa907199, 0x75c323d1, 0x7061f9ba, 0x97e067bf,
-0xc155cd55, 0x6a4cb08d, 0x4260e2fa, 0xff35e496, 0x37f251d3, 0x02fd9f9e,
-0x6f53345c, 0x790cda6d, 0x3b8549e4, 0x56d0c6ea, 0x70a38006, 0xfff18223,
-0x6f2035b5, 0x6cf508d3, 0x98a0a308, 0x432353fc, 0x0eb818eb, 0xdd9a128b,
-0xf92431b2, 0xad788286, 0xda07d5de, 0x44b4b3a8, 0xbe62fd67, 0x61a4eb54,
-0x90d7ac9f, 0xc4d9a930, 0xfddc3c24, 0xf5e3b1c8, 0x38143538, 0xcb1d3062,
-0xcae36df3, 0x50a73437, 0x542dcab7, 0x875973a0, 0x34690309, 0x49cb1ddb,
-0xf8a62b92, 0x82af6103, 0xc9f8c928, 0x3835b822, 0x16b044a6, 0xdae89096,
-0xa5be47d4, 0xaf61189e, 0x5cd70faf, 0x037331cf, 0xef7fa5f6, 0xb2f2b41a,
-0xa6f222c6, 0xdb60fe4c, 0x2a857a9a, 0x0b821f9d, 0x348afd17, 0x7eecbaeb,
-0x92bb9509, 0x8a3cec24, 0xd02549a2, 0x155ffa81, 0x2b7feac6, 0x3ee461e7,
-0xc981f936, 0x89b544c7, 0x9a431e36, 0x62511734, 0x769f9647, 0x211a747e,
-0x567abef4, 0xad87e2b4, 0xa3e0c3bf, 0x6d325dd5, 0xf561cc46, 0x39925735,
-0x3d8abbfd, 0xc3724c88, 0x8bdf03c9, 0x1b02a12a, 0x4f233a0c, 0x9ca9444a,
-0xc5d1f7e6, 0x4d995f37, 0xd9aefb32, 0xd0465248, 0x0f3a3b21, 0x62ea8c0c,
-0x91f8d54e, 0x5cf75514, 0x14618a01, 0x8fe9b87e, 0xf2b424f9, 0x49724ce2,
-0xa1464587, 0x5e00dc83, 0x59475455, 0x444119b1, 0x4fb9f036, 0x65fcbc1a,
-0x1c63a990, 0x767a6114, 0xb0ede06a, 0xcfb91ae3, 0x7874af5f, 0xf78772a3,
-0xa2932c81, 0x77f2759d, 0x930dc8f1, 0x95ce14a5, 0x134363ee, 0x61ee143f,
-0xf0034b35, 0xfdc75fce, 0x3be2dcf3, 0xff3a07eb, 0xdc43f0eb, 0x23ba73bb,
-0x45f7649e, 0xcacc297c, 0xa3dd98db, 0x058d46a9, 0x6bcfc154, 0x7be8e1e6,
-0x618a4754, 0x8d193c46, 0xba39e1ce, 0xc3b85cfc, 0xd80d853b, 0x38d6440d,
-0x9c1a6185, 0x90c9dfcb, 0x01c6e841, 0xeedfe6ac, 0x7b61a3ae, 0xad3924dd,
-0x514bc1a8, 0x6ed60d7e, 0x1b74b79b, 0xea295947, 0x5f9a5d33, 0xcd24311f,
-0x0bd3d10c, 0xd214ecfe, 0xcb37035d, 0x8ce95168, 0x7020cb52, 0xe432107d,
-0x042d63ac, 0x6201c8dd, 0x4bea65a2, 0x1a3cf453, 0x5b8e868d, 0x3d653bb0,
-0x24c1967e, 0x37f183a9, 0x3700e703, 0xb168a02b, 0x2592cd82, 0x5c0cdb66,
-0x70b64ebd, 0xf8dcb9a7, 0x634a8335, 0x06642398, 0xfe2f4497, 0x2e775256,
-0x30f85cbe, 0xf4d2fdaf, 0x46ca6c9d, 0x022097d6, 0xcedeb03e, 0xaf9437bc,
-0x341f8045, 0x93f6ff86, 0x2e019ec9, 0xc80116e8, 0xf984ff34, 0xe4f1be20,
-0xfe455510, 0xc561cdba, 0x2d6f560f, 0xb239fd9d, 0xd254e343, 0x8090448a,
-0xa724c4f1, 0xa00fe4f0, 0xf0379ac6, 0x0c61b383, 0x44b2228e, 0x9d223bc0,
-0xe7cfbc38, 0x62ae6a40, 0x6f8d445c, 0xc6045eaf, 0x8507df18, 0xe64c057e,
-0x4e589113, 0x3ba3bf55, 0x6a702b19, 0xea23af7d, 0xa1b98022, 0x7096c45c,
-0xace3b8c1, 0x47ed7bb4, 0x198a2b8f, 0x586b57db, 0xbf9d24d4, 0x96054c66,
-0x13f26306, 0x2a43524b, 0x1ecd419b, 0xb3a24852, 0x4ed7765f, 0x4c99fbe3,
-0x6c3b9ebb, 0x1ef7bfeb, 0x0daf1256, 0xe9c90c7f, 0xbe067ed7, 0x469102ba,
-0xedccc098, 0x96691fb1, 0x2a9b850f, 0x58aba5f2, 0x0bcad31d, 0x90b1f25b,
-0x78a55fe4, 0xdd41e626, 0xdcba3e83, 0x2209d8a9, 0x6ee2f76f, 0x55643570,
-0xd181a0ef, 0xd1b2790a, 0xc7793587, 0x3aebe10c, 0xbbde5fe0, 0x5c308948,
-0x01439ece, 0x5319fbef, 0x10b0de1b, 0x6595f4f3, 0xa3e6a7c9, 0xf97b2e10,
-0x4513cf3d, 0x8ded3394, 0x0949a772, 0x934f2269, 0x2b636628, 0x92101c68,
-0x804dfd94, 0x178315be, 0x384adf65, 0xe64d11d3, 0xc44881c0, 0x7a8e7886,
-0xb721c0c8, 0x6d0d0fc0, 0x97f0cc5a, 0x3c67c31f, 0x4906dd09, 0x6202c01a,
-0xad8d6c5b, 0x53158056, 0x13704ed5, 0xa1dfeaaa, 0xb35e4b40, 0xd9c3e6fa,
-0x0c9650ce, 0xbdfe5c22, 0x874bedb3, 0xbd07d0bd, 0x4eef4a4f, 0x2970d932,
-0xfdd003ac, 0x609fbea4, 0xad817794, 0xb4ee9f96, 0x559b3faa, 0x1edcf35f,
-0x8342e9fb, 0x69a73981, 0x5fc86a07, 0x929b45aa, 0x5c32e847, 0x43421484,
-0x9962abf5, 0x8cf07ae4, 0xba7b556d, 0x2da42ac1, 0xac0eef6f, 0xdc118ef8,
-0x6061597a, 0xc5f7a007, 0xb9b92c51, 0x87049008, 0x72c9da8a, 0x54dc48c6,
-0xb4c4b392, 0x50204c8d, 0x00b2ef59, 0xcdac687c, 0xb2158dc3, 0x4f1c65e3,
-0x8af22286, 0x4444ee49, 0x2d8921ce, 0x3c0a8d11, 0xb97325da, 0x056aec7b,
-0xa96ca31b, 0x71a5febb, 0xa3166c47, 0x5e920dcd, 0xa58b2e61, 0x4d3b392f,
-0x1b9b177b, 0x058b0dfa, 0x4bdc16ab, 0x8a4eeac3, 0xfbf2d2fc, 0x636f04a6,
-0x75a14bda, 0xa28f1947, 0xf2f248e4, 0x934e7dd6, 0xeb4401cb, 0x37f693a2,
-0xd1cb7e16, 0xbd5d9abb, 0x6f613f63, 0x9bfb5fd5, 0x6b70c5ea, 0xbdcc6c7a,
-0x41efaee1, 0xf45d3965, 0x0499b12b, 0x7820873a, 0xed53961f, 0x303c4f04,
-0x2e4bd363, 0x1bcdd589, 0xf7317de0, 0x7ba3d53a, 0x61fb36a8, 0x23e55b43,
-0x0ef838e9, 0x7b9d91a3, 0x3cd7d835, 0x5f28e517, 0xa100fad7, 0xff39800d,
-0xd7894433, 0xb61a62cd, 0xde618b70, 0x8560d770, 0xed02
-
-output0 =
-0x11d2bcac, 0x7715ae4d, 0xc9f4dbc6, 0x2fda3c1a, 0x09349b16, 0x2cd3c189,
-0xe5650429, 0xc73c42c1, 0xe7336bb7, 0xbb7de593, 0x83f986aa, 0xc0ade12e,
-0x6730b095, 0x78f7c059, 0xaa907199, 0x75c323d1, 0x7061f9ba, 0x97e067bf,
-0xc155cd55, 0x6a4cb08d, 0x4260e2fa, 0xff35e496, 0x37f251d3, 0x02fd9f9e,
-0x6f53345c, 0x790cda6d, 0x3b8549e4, 0x56d0c6ea, 0x70a38006, 0xfff18223,
-0x6f2035b5, 0x6cf508d3, 0x98a0a308, 0x432353fc, 0x0eb818eb, 0xdd9a128b,
-0xf92431b2, 0xad788286, 0xda07d5de, 0x44b4b3a8, 0xbe62fd67, 0x61a4eb54,
-0x90d7ac9f, 0xc4d9a930, 0xfddc3c24, 0xf5e3b1c8, 0x38143538, 0xcb1d3062,
-0xcae36df3, 0x50a73437, 0x542dcab7, 0x875973a0, 0x34690309, 0x49cb1ddb,
-0xf8a62b92, 0x82af6103, 0xc9f8c928, 0x3835b822, 0x16b044a6, 0xdae89096,
-0xa5be47d4, 0xaf61189e, 0x5cd70faf, 0x037331cf, 0xef7fa5f6, 0xb2f2b41a,
-0xa6f222c6, 0xdb60fe4c, 0x2a857a9a, 0x0b821f9d, 0x348afd17, 0x7eecbaeb,
-0x92bb9509, 0x8a3cec24, 0xd02549a2, 0x155ffa81, 0x2b7feac6, 0x3ee461e7,
-0xc981f936, 0x89b544c7, 0x9a431e36, 0x62511734, 0x769f9647, 0x211a747e,
-0x567abef4, 0xad87e2b4, 0xa3e0c3bf, 0x6d325dd5, 0xf561cc46, 0x39925735,
-0x3d8abbfd, 0xc3724c88, 0x8bdf03c9, 0x1b02a12a, 0x4f233a0c, 0x9ca9444a,
-0xc5d1f7e6, 0x4d995f37, 0xd9aefb32, 0xd0465248, 0x0f3a3b21, 0x62ea8c0c,
-0x91f8d54e, 0x5cf75514, 0x14618a01, 0x8fe9b87e, 0xf2b424f9, 0x49724ce2,
-0xa1464587, 0x5e00dc83, 0x59475455, 0x444119b1, 0x4fb9f036, 0x65fcbc1a,
-0x1c63a990, 0x767a6114, 0xb0ede06a, 0xcfb91ae3, 0x7874af5f, 0xf78772a3,
-0xa2932c81, 0x77f2759d, 0x930dc8f1, 0x95ce14a5, 0x134363ee, 0x61ee143f,
-0xf0034b35, 0xfdc75fce, 0x3be2dcf3, 0xff3a07eb, 0xdc43f0eb, 0x23ba73bb,
-0x45f7649e, 0xcacc297c, 0xa3dd98db, 0x058d46a9, 0x6bcfc154, 0x7be8e1e6,
-0x618a4754, 0x8d193c46, 0xba39e1ce, 0xc3b85cfc, 0xd80d853b, 0x38d6440d,
-0x9c1a6185, 0x90c9dfcb, 0x01c6e841, 0xeedfe6ac, 0x7b61a3ae, 0xad3924dd,
-0x514bc1a8, 0x6ed60d7e, 0x1b74b79b, 0xea295947, 0x5f9a5d33, 0xcd24311f,
-0x0bd3d10c, 0xd214ecfe, 0xcb37035d, 0x8ce95168, 0x7020cb52, 0xe432107d,
-0x042d63ac, 0x6201c8dd, 0x4bea65a2, 0x1a3cf453, 0x5b8e868d, 0x3d653bb0,
-0x24c1967e, 0x37f183a9, 0x3700e703, 0xb168a02b, 0x2592cd82, 0x5c0cdb66,
-0x70b64ebd, 0xf8dcb9a7, 0x634a8335, 0x06642398, 0xfe2f4497, 0x2e775256,
-0x30f85cbe, 0xf4d2fdaf, 0x46ca6c9d, 0x022097d6, 0xcedeb03e, 0xb4ca20bc,
-0x4fde636c, 0x10ea20a0, 0xe6da8721, 0xbfde5b08, 0x9c3739da, 0xb6dc015a,
-0x427db088, 0xdfdb8e6f, 0x756be6c1, 0x21f5297b, 0x06135665, 0xc1602b7d,
-0x049536c5, 0xbbb3b801, 0x0cdb0c19, 0x7b2ad622, 0xfee8218f, 0xc5c7f123,
-0x8abd3301, 0xa15b534d, 0x29dd2053, 0xd409abf9, 0x3ef19d6b, 0x70a3cbc2,
-0x7a51423a, 0x4505b2ad, 0xdc74c75e, 0x068751a9, 0xb0b56437, 0x14a10371,
-0x76af806f, 0xa8a47e19, 0x7c97a26e, 0x7998a3d6, 0xdc1ad1e2, 0xb532a301,
-0xca8a3e7d, 0xd0aef374, 0x204990c0, 0xc7011aec, 0xa69151ea, 0x53390026,
-0x7bf0d762, 0x735c2202, 0x64159e54, 0x5a3b1a56, 0x9ef1def2, 0x0ab8a961,
-0x587b0886, 0xb8cc5975, 0x2a5a0f23, 0x069d05be, 0x9cc3c207, 0x40ef1a02,
-0x4fae3f5b, 0x1f127aae, 0xd4e6d411, 0x17ac43ef, 0xe4bf891b, 0xfbb21765,
-0x2c560c7e, 0x8561988c, 0x73a01032, 0x0cfef73a, 0x694c4991, 0x885d7a3f,
-0x4218d1ff, 0xc2efaffb, 0xaf9d9715, 0xf76de6b2, 0xcce8e8ff, 0x370e3800,
-0x493675eb, 0xd8fbcbda, 0xa5b382c2, 0x86c8f1ea, 0x3d724ea4, 0xb067034c,
-0x6491d87e, 0x1a745ce4, 0xbb27180b, 0x1a2f0acc, 0xac4b7b3b, 0xe324578b,
-0xc87928df, 0x9c1de566, 0x0ce2a17d, 0xaf2e13ce, 0x146a8659, 0x8727f6ae,
-0xe2df7d03, 0x1a8e4cb4, 0xfa590976, 0x13a7c236, 0xc07489d0, 0xbe905e17,
-0xafeb3d4b, 0x201e73f2, 0x5bdca12e, 0x3e15a852, 0xbcfc3271, 0x5d398410,
-0x6bfacc15, 0x011fc61f, 0x43e43fd7, 0x0640717c, 0x96bfb3ff, 0x158eac19,
-0x3b852e91, 0x74f9ceda, 0xcac71326, 0xfc0e312a, 0x20e8137b, 0xa1162611,
-0x239ac7fe, 0xb9d00f8a, 0xea0b5241, 0x019f0d25, 0xc5153264, 0xb48a5547,
-0xe54e339f, 0x17a6cca5, 0x5065af0d, 0x5ce648b9, 0xb457b342, 0xc1cb3f0e,
-0x28d03c8b, 0x5144ed7a, 0xdb80779f, 0x53ce1b87, 0xbc071147, 0xbfe46c11,
-0x7296785e, 0x83e4a63e, 0xc58982e9, 0x9538c5b9, 0xf14abaaa, 0xd915124c,
-0x73540cd6, 0xe333696b, 0x58f9e00a, 0xd4dad10f, 0xc0de1420, 0x355e2bdc,
-0xb2faa8fd, 0xbe6a12f1, 0x45d415cc, 0x47f5aed9, 0x4754e770, 0x2bb07385,
-0x41374352, 0xf80beb47, 0xef02f35c, 0xc9c1b86e, 0x94b5785b, 0xba33123f,
-0x7e39f0c9, 0x028a9286, 0x7d52c9f1, 0x06f04da6, 0xbc6a68d1, 0xfc70bace,
-0x95b6a129, 0xfff224bb, 0x701ef3fb, 0x3309286f, 0x544ae8c1, 0xdca62c4a,
-0xf8862ee2, 0xf9e3cd29, 0x2c07cce2, 0x8d93652a, 0xf47e4611, 0x4635f586,
-0x1c03e0f4, 0x819724c7, 0x96b2a3f0, 0xeeb1ad95, 0xff08e517, 0xbd4ba6ed,
-0x49ddb12d, 0x365734b5, 0x5edf7459, 0x2ee117a9, 0x067b9462, 0x549f6d5f,
-0xe1dd8309, 0x12bb8e0a, 0x4382fe0f, 0x57fce11b, 0x1bc1c809, 0xd2741876,
-0xcffd36b9, 0x45a64a67, 0xb77955d5, 0xb5825f24, 0x86eef2a8, 0xb66cac3b,
-0xfec661f8, 0x531d5963, 0xa0a2f109, 0xe1795b68, 0x6bfd44e0, 0x0849af41,
-0xf56d7d73, 0x3eab025f, 0xd109b015, 0xec24d23b, 0x8b3f603c, 0x648f421f,
-0xc833f32a, 0x53cbda14, 0xb9b3fee4, 0xcf9ac8ab, 0x300f0548, 0xfe0bc595,
-0x4f437a1a, 0xdacfae1f, 0x284e4a6d, 0x57815e28, 0x15d32b39, 0x68f85b97,
-0x18b21602, 0x941259ef, 0x68598d90, 0x6dfd81db, 0xa8fc9a55, 0x60fef2b3,
-0xcf07961b, 0x11b96588, 0xd9928a88, 0x2bbc72fd, 0x025f81b4, 0x44794d6d,
-0x6a7420aa, 0xa73d4d89, 0x25b523ff, 0x521dbea3, 0xdacde374, 0xbf41776f,
-0x9c1e3cb6, 0xb7b3499b, 0x8e154ed3, 0x1ac8f8c8, 0x4f2cf203, 0xa293c979,
-0x2792a2e1, 0x329ca1dd, 0x01e1aa4a, 0x01a78d3e, 0x100c74ed, 0xb0db13c7,
-0x99d53541, 0xd435a3b9, 0x898bd713, 0x069287bd, 0xe3175d24, 0xb09dc7fb,
-0x7340d7d3, 0x81369cc3, 0x8f16a7a8, 0x43963d57, 0x58e0f6a3, 0x39803b6c,
-0xa419a5ac, 0xf45fd6fa, 0xec389d5b, 0x636ce34f, 0x71405df6, 0xfc504724,
-0xa3a3b192, 0x19df1379, 0xaf028f42, 0x3e1838e8, 0x6b7a64a9, 0xaa90ffee,
-0x238ee398, 0x67eae4bd, 0x0a549a15, 0x125873d3, 0x00ece005, 0x9f7b2b8f,
-0x7571f73c, 0x98940ab4, 0x192ed328, 0x8fae66da, 0x9063b323, 0x2542f666,
-0x07ac7c8e, 0xce92857a, 0x3ded4b69, 0x50204cb4, 0x2a81cd17, 0xfd6ac536,
-0xafb46424, 0xe802147b, 0x30a37858, 0x90697235, 0x1606e767, 0x26c1048e,
-0x3a20df7b, 0xe127de97, 0x481abd6c, 0xc3a61d15, 0xbb2e929c, 0xd2ec0d65,
-0xc0e53693, 0x500c2e9a, 0x316d0f4b, 0x18354452, 0xb2dd7728, 0x5a874b3e,
-0x6dcf6f9c, 0x9d7c15ce, 0x1b25566d, 0xe13d6e7a, 0x9d9d06ae, 0x4d0e7d23,
-0x33100e24, 0x7c20e0f8, 0x2cfc95bf, 0xb8e702a0, 0x5e60215b, 0xa516093e,
-0x4cf3bed7, 0x4a0d6f56, 0xaf4901cc, 0xaeb7137e, 0x07d3c34d, 0x38641bc6,
-0xf7366ca3, 0x6e01bd0d, 0x86818282, 0xf0f8712a, 0x431f57ad, 0x46b832c3,
-0xec1893b8, 0xfa43c94f, 0x8b4c382a, 0x84cc0cec, 0x3f1016f3, 0xdbc7b88d,
-0xa3c34e52, 0x50691492, 0x8b10e709, 0x5c5db670, 0xcda5888b, 0xa1ef2917,
-0x1d4689ba, 0xc6470dcc, 0x7010373d, 0x4f27b426, 0x06b0de9d, 0xba83e005,
-0x97cd5aad, 0xc1d0f41a, 0x01bae35a, 0xb30c805e, 0x8d7982eb, 0xe1a7b51d,
-0x88a9f4d2, 0x7a6742a8, 0x0d9cb569, 0x06e9bc87, 0xf8c93b93, 0x89f3e80a,
-0x96b971de, 0xcd548ef1, 0x5fbeb12a, 0x39c798e3, 0x90183352, 0x9b2476a7,
-0x9437b0ae, 0x1f8045af, 0xf6ff8634, 0x019ec993, 0x0116e82e, 0x84ff34c8,
-0xf1be20f9, 0x455510e4, 0x61cdbafe, 0x6f560fc5, 0x39fd9d2d, 0x54e343b2,
-0x90448ad2, 0x24c4f180, 0x0fe4f0a7, 0x379ac6a0, 0x61b383f0, 0xb2228e0c,
-0x223bc044, 0xcfbc389d, 0xae6a40e7, 0x8d445c62, 0x045eaf6f, 0x07df18c6,
-0x4c057e85, 0x589113e6, 0xa3bf554e, 0x702b193b, 0x23af7d6a, 0xb98022ea,
-0x96c45ca1, 0xe3b8c170, 0xed7bb4ac, 0x8a2b8f47, 0x6b57db19, 0x9d24d458,
-0x054c66bf, 0xf2630696, 0x43524b13, 0xcd419b2a, 0xa248521e, 0xd7765fb3,
-0x99fbe34e, 0x3b9ebb4c, 0xf7bfeb6c, 0xaf12561e, 0xc90c7f0d, 0x067ed7e9,
-0x9102babe, 0xccc09846, 0x691fb1ed, 0x9b850f96, 0xaba5f22a, 0xcad31d58,
-0xb1f25b0b, 0xa55fe490, 0x41e62678, 0xba3e83dd, 0x09d8a9dc, 0xe2f76f22,
-0x6435706e, 0x81a0ef55, 0xb2790ad1, 0x793587d1, 0xebe10cc7, 0xde5fe03a,
-0x308948bb, 0x439ece5c, 0x19fbef01, 0xb0de1b53, 0x95f4f310, 0xe6a7c965,
-0x7b2e10a3, 0x13cf3df9, 0xed339445, 0x49a7728d, 0x4f226909, 0x63662893,
-0x101c682b, 0x4dfd9492, 0x8315be80, 0x4adf6517, 0x4d11d338, 0x4881c0e6,
-0x8e7886c4, 0x21c0c87a, 0x0d0fc0b7, 0xf0cc5a6d, 0x67c31f97, 0x06dd093c,
-0x02c01a49, 0x8d6c5b62, 0x158056ad, 0x704ed553, 0xdfeaaa13, 0x5e4b40a1,
-0xc3e6fab3, 0x9650ced9, 0xfe5c220c, 0x4bedb3bd, 0x07d0bd87, 0xef4a4fbd,
-0x70d9324e, 0xd003ac29, 0x9fbea4fd, 0x81779460, 0xee9f96ad, 0x9b3faab4,
-0xdcf35f55, 0x42e9fb1e, 0xa7398183, 0xc86a0769, 0x9b45aa5f, 0x32e84792,
-0x4214845c, 0x62abf543, 0xf07ae499, 0x7b556d8c, 0xa42ac1ba, 0x0eef6f2d,
-0x118ef8ac, 0x61597adc, 0xf7a00760, 0xb92c51c5, 0x049008b9, 0xc9da8a87,
-0xdc48c672, 0xc4b39254, 0x204c8db4, 0xb2ef5950, 0xac687c00, 0x158dc3cd,
-0x1c65e3b2, 0xf222864f, 0x44ee498a, 0x8921ce44, 0x0a8d112d, 0x7325da3c,
-0x6aec7bb9, 0x6ca31b05, 0xa5febba9, 0x166c4771, 0x920dcda3, 0x8b2e615e,
-0x3b392fa5, 0x9b177b4d, 0x8b0dfa1b, 0xdc16ab05, 0x4eeac34b, 0xf2d2fc8a,
-0x6f04a6fb, 0xa14bda63, 0x8f194775, 0xf248e4a2, 0x4e7dd6f2, 0x4401cb93,
-0xf693a2eb, 0xcb7e1637, 0x5d9abbd1, 0x613f63bd, 0xfb5fd56f, 0x70c5ea9b,
-0xcc6c7a6b, 0xefaee1bd, 0x5d396541, 0x99b12bf4, 0x20873a04, 0x53961f78,
-0x3c4f04ed, 0x4bd36330, 0xcdd5892e, 0x317de01b, 0xa3d53af7, 0xfb36a87b,
-0xe55b4361, 0xf838e923, 0x9d91a30e, 0xd7d8357b, 0x28e5173c, 0x00fad75f,
-0x39800da1, 0x894433ff, 0x1a62cdd7, 0x618b70b6, 0x60d770de, 0xbaed0285,
-0x7bd24f54, 0x96a33975, 0x6884bd60, 0xeb75cf39, 0x19dd058a, 0xd4b8f064,
-0x045178ca, 0xd9e3c1de, 0x91b494a6, 0x3316ac81, 0xb926c7d8, 0xc190f058,
-0xce70a42c, 0x54f3b3c4, 0x79b20d90, 0x75177ad7, 0x9f010f51, 0x889a4fd5,
-0x8fbbc8f0, 0xf1340040, 0xc22acb69, 0xe1473a0a, 0x52ddd7e3, 0x4cd54494,
-0x4eb7a9ed, 0xd35e6a65, 0x3236b14c, 0x89786899, 0x3dc59704, 0x51d674be,
-0xbcf13659, 0x6ef6266e, 0xf50ef497, 0x141354bc, 0xc8a42e76, 0x59b14233,
-0x8b6cad7d, 0x061d8efe, 0xaca42513, 0x161cee21, 0xfeac5471, 0x4c499d31,
-0xac2892cb, 0x9bacf4c5, 0xfff36588, 0x898f7a06, 0xad87be87, 0xebe7cb95,
-0xa52b5fdf, 0x9f1f3945, 0xad435317, 0x1b316bcc, 0x8e6c0fd3, 0x767981d6,
-0x1f86412b, 0x32b457f5, 0x30ab14db, 0x7120e8ae, 0x3972f57e, 0x2268af9d,
-0xf45e5738, 0xc48bd523, 0x76726cae, 0x10bcdaa2, 0x49dcbe96, 0x8e28c545,
-0x25fd1cc8, 0xc272f106, 0x1a34497e, 0x5f850d98, 0x92e324e4, 0x7e59f811,
-0x0bba7ff0, 0x86b3b23f, 0x29558cee, 0xcbd55b0d, 0x15c10dc2, 0xd6617dd5,
-0x41168898, 0x920132eb, 0xd10f51c6, 0xdc6eba51, 0xa07f89cc, 0xfcea8627,
-0x44a52afa, 0x03d4230b, 0xdbb998d8, 0xf30d2a06, 0x08d35aeb, 0x9597f9bc,
-0x720d2689, 0xf64314dd, 0xcadd04c5, 0x9cab9213, 0x22205cca, 0xd6cc196e,
-0xa820e3c8, 0x7c262f92, 0xaf481f6b, 0xcecc0fe6, 0x2ec0b33a, 0x20aebc0a,
-0xb5699b4b, 0xe0a559ba, 0xb9cd5224, 0x9f7ceb48, 0x35807e3c, 0x30be0794,
-0x05463d41, 0x0e10046f, 0x776e71d6, 0xc6bac22d, 0xfee7f911, 0x3bc76715,
-0x5024f666, 0x88a07482, 0x7dc55ed7, 0x3ee1d3b6, 0xec419af3, 0x4cd0e39f,
-0x988f3802, 0x23baa080, 0xef9ce568, 0xf46ff60f, 0x2efcb093, 0x23b5b12a,
-0xd5fb68c7, 0x58d45968, 0x6dce76cd, 0xf82c5a91, 0xfe6a2bf7, 0x0303b383,
-0xf1b1196a, 0xa18d6d69, 0xb0025e33, 0x3f51e6c7, 0x0263bac1, 0x87743b29,
-0x8f62b573, 0x7a80ad05, 0x95869387, 0x33e6a0f5, 0x50950449, 0x5da456ad,
-0xb2ab1617, 0x7b345bf9, 0x7f923fd1, 0x4ca337fe, 0x95ccf61b, 0xfd8221ca,
-0x0f19808f, 0x80029266, 0x915a3c47, 0x415045d7, 0x92f91b36, 0xd23576e5,
-0x74a5652e, 0xe3d7288c, 0xba8213f7, 0x3a0ecd53, 0xa34fa01a, 0x62b4db3b,
-0x3a96a793, 0xcef7b0da, 0xb64b8d17, 0x8716c3ed, 0xbd0ab055, 0xa6896492,
-0x1250e75b, 0xb2bce1a7, 0x4100ca8f, 0x2e05625f, 0x8eb5bc83, 0x3dac8027,
-0x62b3376d, 0xd6b2cc64, 0x4c9502dc, 0x6c1cfcbe, 0x380c1dce, 0x2b238ea8,
-0x7051d59b, 0x580b122d, 0x6174b6e5, 0x4353d726, 0xba555765, 0xb645490f,
-0x58427e5f, 0x06fc96e1, 0xae8f4528, 0xab0fee5e, 0x5de960b3, 0x63e79c19,
-0x8552eeb8, 0x9344db26, 0x3326d17c, 0xa4174885, 0x6fe45472, 0x7bd20a9e,
-0xa5e4aba0, 0x77b509af, 0x22f64240, 0x40bc5144, 0x57ca1b2d, 0xc1260090,
-0x008997aa, 0xe8029716, 0x6efb01f3, 0xc73e1366, 0x9de737ff, 0x1b5fabe8,
-0x957bb682, 0x5e27f5a5, 0x7777491a, 0x9b6fc6c1, 0xb0802205, 0x16e94d46,
-0x58079aee, 0x2b24c4c4, 0xfffb2e7b, 0x7c5560e1, 0xe1ad3009, 0x6a0c0027,
-0x09aea741, 0x9af375a6, 0x7106b7bf, 0x1cdcff69, 0xa007f9c2, 0x6f7729c0,
-0xeac4297f, 0x8622ede7, 0x89346bfa, 0xc24674b5, 0xd1eabf00, 0xfa6b2d39,
-0x04b0c153, 0x6adf49dc, 0x48ea0937, 0xae771ea6, 0xd4208255, 0x4052586d,
-0x9c6aa640, 0x9adbb652, 0x017d8661, 0xb20855f0, 0x1e2ed7b6, 0x70af7f25,
-0x354df0de, 0xf2fdfde7, 0x0844478c, 0x63993fb2, 0xc49e71ae, 0x1e15ae81,
-0x932ad241, 0xba83cf8f, 0xc7e227f3, 0xd1171a85, 0x63ea34a0, 0xe74f042b,
-0xd88173d9, 0xba7d8443, 0x9d47c6c4, 0xbe282a93, 0x6142fbac, 0x69307e44,
-0xbb86a7f1, 0x9fa3418f, 0x3a3eadce, 0x9804167b, 0x2d5eb47a, 0x5aa2372d,
-0x66eb8e1c, 0xf56da1fd, 0x3753eee9, 0xac78c709, 0x787ae648, 0x42d4fa7f,
-0x5a036af5, 0xfc6dfa54, 0x269f1195, 0xef1c698d, 0x2932b2d6, 0xba10b26c,
-0xf9b58396, 0x8f04a38a, 0x31c1264d, 0xf11c5ac6, 0x693d8ef6, 0x25b1d015,
-0x01c06e8f, 0x9c250a6f, 0x4b8fffcd, 0x1eff0743, 0x5a4974ec, 0x9d2d24c1,
-0x5562b2ae, 0x2a5b2deb, 0xd4a32596, 0x8ec43665, 0xde3ae654, 0x99e979d0,
-0xb6250c7c, 0x478a2891, 0xe1d6c035, 0x1dc453e8, 0xc7490c8d, 0xd4e85297,
-0x8fa94952, 0xc863cde8, 0x724dbbc8, 0x89ba9607, 0x0144ba1b, 0x3fed833c,
-0xd16278d4, 0x0080f227, 0xfbe241c5, 0x61892e7f, 0x503dced0, 0xa54d6ea5,
-0xcb5024a3, 0x591e11d1, 0xabeb85db, 0xc8314e58, 0xfb7792cb, 0xc70e5ada,
-0xcc07e739, 0xdb3ad4d6, 0x7a2d24e8, 0x2a0e216a, 0xa04aa774, 0x1762ac59,
-0xed53f5f9, 0x261a791e, 0x7a4102ae, 0x4650dcc9, 0xffa48ffa, 0x35a8f4e1,
-0x98e0f041, 0x3e3a9a83, 0xfb43c8e9, 0x7e0e6a1e, 0x06f718e5, 0x6812c114,
-0xaf21e4a1, 0x10ce04ca, 0x6e465a05, 0x250758f2, 0xfdf02f68, 0x426ec74c,
-0x51e44567, 0x17e637cc, 0x9da657e4, 0x39ecef6e, 0xd31c4423, 0x12bc06b4,
-0x35af82e0, 0x76379d09, 0x7fb7aa1e, 0x0b73e469, 0x7b3697a4, 0x6bbbca38,
-0x018d2e07, 0x8d74a290, 0x02e00314, 0xdc9d1f4f, 0x62cbdd73, 0xd1173c86,
-0x62c1d5f2, 0xdfb16100, 0x37cc28e8, 0x43954e64, 0xeaa699d9, 0x0cd0a997,
-0xa0f26045
-
-ea =
-17868
-
-eb =
-17868
-
-cab =
-2
-
-c =
-2
-
-c_neg =
-0
-
-k_pos =
-5952
-
-k_neg =
-5888
-
-ncb_pos =
-17952
-
-ncb_neg =
-17760
-
-r =
-0
-
-rv_index =
-0
-
-code_block_mode =
-0
-
-op_flags =
-RTE_BBDEV_TURBO_CRC_24B_ATTACH
-
-expected_status =
-OK
diff --git a/app/test-bbdev/test_vectors/turbo_enc_c4_k4800_r2_e14412_crc24b.data b/app/test-bbdev/test_vectors/turbo_enc_c4_k4800_r2_e14412_crc24b.data
deleted file mode 100644
index ff95a3f..0000000
--- a/app/test-bbdev/test_vectors/turbo_enc_c4_k4800_r2_e14412_crc24b.data
+++ /dev/null
@@ -1,252 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-# Copyright(c) 2017 Intel Corporation
-
-op_type =
-RTE_BBDEV_OP_TURBO_ENC
-
-input0 =
-0xb0fe86aa, 0xffbf2968, 0x4f55a631, 0xf2152dbc, 0x195a49a5, 0xa4aa7c6c,
-0x48a7be38, 0xd32c84f2, 0xb040da60, 0xb39eb07c, 0x3443aad6, 0x19f52e13,
-0xb2914341, 0x0d5dfdb3, 0x1ba8aec0, 0x62d0c7be, 0x1d55475c, 0x10f7dd79,
-0x967e5333, 0xc0d524c1, 0xdca8da87, 0x1146ecf7, 0xfa09a85c, 0x83be800f,
-0x11b814cc, 0x362a4704, 0x4f22e7ce, 0x9985a0e2, 0x9de4be72, 0x488a45b3,
-0x6996ade2, 0xdb18c09a, 0x487d62a3, 0x94f82d13, 0xa0743f83, 0x75d2f5dd,
-0x0e470346, 0x6e2ec2e5, 0x1a67fe5f, 0xc369330d, 0x860e8766, 0x42c110f6,
-0x804a9985, 0x55db02b4, 0xb899fc5c, 0x57811d20, 0xda4f1f9d, 0x2a2efc30,
-0x953e7487, 0x4b0c3065, 0x247d5d47, 0xdde382e7, 0x1d6d2ad7, 0x4358ac24,
-0x2d0fd97f, 0x1483821e, 0xf6c74ee5, 0x23b5c2f4, 0x95d4a5fc, 0x486f370b,
-0x8dbae43d, 0x248f17d5, 0x2df76099, 0xd19ec872, 0xf592aa0e, 0x8de04c3c,
-0x3ada94fb, 0x9dd001a3, 0x2b4db6d1, 0x791cf495, 0x57dc764b, 0x21789f1f,
-0x0d38adf5, 0xd8cefdc2, 0xed98f8bf, 0x024bc4ed, 0x4f9d3062, 0x332d27c5,
-0xde70ad4e, 0xd85872d2, 0x5d0e29c0, 0xa4fd1887, 0x3fa67ba1, 0x46b9b008,
-0x055bbf61, 0xf78e59f0, 0x287d2e3b, 0x5b473fe7, 0xd7ad6e04, 0x9cdf4986,
-0x830432ae, 0xffded1ba, 0x35c00f77, 0xcf0a6648, 0x196c03aa, 0xba4e2dd3,
-0xdaf70fe4, 0x883de2cd, 0xedc3b52e, 0x14e638c1, 0xe607103a, 0xc4cfb700,
-0x4ed9843d, 0xc442a0cb, 0xc0d3bba2, 0x36789ba8, 0x9c9b7a24, 0xb943b6a4,
-0x8f2c6879, 0x0fb16a0c, 0x2677bada, 0xd14f2f7e, 0x662ec398, 0x1e37b7ae,
-0x8ad0312d, 0x21adb6a1, 0x072a11fd, 0x7ae828d1, 0xb510655f, 0x09f7b477,
-0x10a175fc, 0xb7086f51, 0x24546af3, 0xfae81b50, 0xcb328832, 0x63693615,
-0xa37c3678, 0x15fb6364, 0xb5f75a78, 0xfa9aa5f6, 0x03804a0e, 0x1d245890,
-0x06d6cdcd, 0x7485a3c7, 0x35a008ae, 0x1abeaf1c, 0xd9c55966, 0x2b694666,
-0x5341f2df, 0xcb647280, 0xfb88d81e, 0xf99a44d0, 0xb0585534, 0x0877b530,
-0x752ab39a, 0xd493d8bc, 0xfaa6a57a, 0xccb7c008, 0x9c35994b, 0x9cca47b8,
-0xff47dda2, 0xa557841a, 0x7459fb6a, 0x93ec6495, 0x0ef7e6d2, 0xa8a6e6d4,
-0x46364f91, 0xd52c5776, 0x4dfd0d25, 0xd458c769, 0x24864930, 0xf7789991,
-0xfcc231f2, 0xc8e4cfd0, 0x50975038, 0x989398d1, 0x04504b14, 0x5e529570,
-0xf8c17202, 0xaf459a8a, 0xac2fecb2, 0x0eb3a176, 0xf6bac24f, 0x6fbddade,
-0x42456542, 0x83c10198, 0xbea4efaf, 0xff2f2966, 0x5edae82b, 0x09c27f13,
-0xa094c3b4, 0xc53b810e, 0x7f1cc39d, 0x25731c8a, 0x8d34b6ee, 0x5fb78b80,
-0x2980eef8, 0x7b76a9fb, 0x37bfacb9, 0x80f7a0ea, 0xd1e3e69d, 0xcda19b8b,
-0x9af26246, 0xf55495cf, 0x6f45ad1b, 0xfe2cb329, 0xc33cb7e6, 0x67bbde4a,
-0x32310c7b, 0x80e6b00a, 0xdd4004d2, 0x0e0eb8b6, 0x6f8d951f, 0xb196cb40,
-0x6dbe29dd, 0xa138a375, 0xd4f5b058, 0x69ea638f, 0x50438a7a, 0xe5530eb3,
-0x527cb218, 0xbfa67b9d, 0x7efb86df, 0x724ed65b, 0x38006782, 0x6a9924a4,
-0x749955c2, 0x5cb82627, 0xa74ceecb, 0x89eb103d, 0x89a12973, 0x660613c4,
-0x8bdf96ae, 0xf08afcce, 0xa4023081, 0x79c6786c, 0x8026bdf0, 0x621f29a1,
-0xa8d8d3ec, 0x4ee5d537, 0xda83c99f, 0x9a69d0a8, 0xae027f9a, 0x639d9cc9,
-0xe80e2be1, 0x89d78cfb, 0x862fabb7, 0xb248c138, 0x3fe35f29, 0xf8b74cc6,
-0x27741dcf, 0xf9236485, 0x05225155, 0x4ed40ee6, 0xb30e4a95, 0x7d890ee0,
-0x0a97eb0d, 0xe7877652, 0x3de6fa67, 0xa3a5961e, 0x1bdf2af5, 0x5a7dcbbe,
-0x1641f1af, 0x4db5845b, 0x735761f2, 0x32a1431e, 0xab1e00b1, 0x495ddeb7,
-0xb480f29c, 0x47d83714, 0x8ba04129, 0x8c96062e, 0x657e7f7f, 0x30dfba23,
-0xfd4ee1bc, 0x9ffe10b1, 0xc917d2db, 0x18f0bd8d, 0x4b6c35d7, 0x54896222,
-0x7ce0f6c6, 0xb7813f4a, 0x71c52b4b, 0xac65da3a, 0x9aef9b4e, 0x85f9657e,
-0x62ba1965, 0xa1e39267, 0x40f66fb2, 0x10433b94, 0x851df333, 0xf0c6aa26,
-0xe0e19368, 0x5a706636, 0xf5de1e8c, 0x5ebc735a, 0x0967ef39, 0xf76c1fb7,
-0xe53f7f16, 0x51f2c4eb, 0x047dda3d, 0x73518b4a, 0x3ad90dd3, 0xaee51fc1,
-0x78f01060, 0x98d1502c, 0x990d5499, 0x7a19453c, 0x104c
-
-output0 =
-0xb0fe86aa, 0xffbf2968, 0x4f55a631, 0xf2152dbc, 0x195a49a5, 0xa4aa7c6c,
-0x48a7be38, 0xd32c84f2, 0xb040da60, 0xb39eb07c, 0x3443aad6, 0x19f52e13,
-0xb2914341, 0x0d5dfdb3, 0x1ba8aec0, 0x62d0c7be, 0x1d55475c, 0x10f7dd79,
-0x967e5333, 0xc0d524c1, 0xdca8da87, 0x1146ecf7, 0xfa09a85c, 0x83be800f,
-0x11b814cc, 0x362a4704, 0x4f22e7ce, 0x9985a0e2, 0x9de4be72, 0x488a45b3,
-0x6996ade2, 0xdb18c09a, 0x487d62a3, 0x94f82d13, 0xa0743f83, 0x75d2f5dd,
-0x0e470346, 0x6e2ec2e5, 0x1a67fe5f, 0xc369330d, 0x860e8766, 0x42c110f6,
-0x804a9985, 0x55db02b4, 0xb899fc5c, 0x57811d20, 0xda4f1f9d, 0x2a2efc30,
-0x953e7487, 0x4b0c3065, 0x247d5d47, 0xdde382e7, 0x1d6d2ad7, 0x4358ac24,
-0x2d0fd97f, 0x1483821e, 0xf6c74ee5, 0x23b5c2f4, 0x95d4a5fc, 0x486f370b,
-0x8dbae43d, 0x248f17d5, 0x2df76099, 0xd19ec872, 0xf592aa0e, 0x8de04c3c,
-0x3ada94fb, 0x9dd001a3, 0x2b4db6d1, 0x791cf495, 0x57dc764b, 0x21789f1f,
-0x0d38adf5, 0xd8cefdc2, 0xed98f8bf, 0x024bc4ed, 0x4f9d3062, 0x332d27c5,
-0xde70ad4e, 0xd85872d2, 0x5d0e29c0, 0xa4fd1887, 0x3fa67ba1, 0x46b9b008,
-0x055bbf61, 0xf78e59f0, 0x287d2e3b, 0x5b473fe7, 0xd7ad6e04, 0x9cdf4986,
-0x830432ae, 0xffded1ba, 0x35c00f77, 0xcf0a6648, 0x196c03aa, 0xba4e2dd3,
-0xdaf70fe4, 0x883de2cd, 0xedc3b52e, 0x14e638c1, 0xe607103a, 0xc4cfb700,
-0x4ed9843d, 0xc442a0cb, 0xc0d3bba2, 0x36789ba8, 0x9c9b7a24, 0xb943b6a4,
-0x8f2c6879, 0x0fb16a0c, 0x2677bada, 0xd14f2f7e, 0x662ec398, 0x1e37b7ae,
-0x8ad0312d, 0x21adb6a1, 0x072a11fd, 0x7ae828d1, 0xb510655f, 0x09f7b477,
-0x10a175fc, 0xb7086f51, 0x24546af3, 0xfae81b50, 0xcb328832, 0x63693615,
-0xa37c3678, 0x15fb6364, 0xb5f75a78, 0xfa9aa5f6, 0x03804a0e, 0x1d245890,
-0x06d6cdcd, 0x7485a3c7, 0x35a008ae, 0x1abeaf1c, 0xd9c55966, 0x2b694666,
-0x5341f2df, 0xcb647280, 0xfb88d81e, 0xf99a44d0, 0xb0585534, 0x0877b530,
-0x752ab39a, 0xd493d8bc, 0xfaa6a57a, 0xccb7c008, 0x9c35994b, 0x47ee26b8,
-0x94f624ac, 0xa3bd4876, 0xf7d4854e, 0x8871d433, 0x9321d942, 0x7b626be8,
-0x72c934b0, 0x3b7af8a4, 0x5102c29f, 0x710e4dbc, 0x99708292, 0x1458c4c1,
-0x61026bc5, 0xe776e388, 0x4a0222b3, 0x760e5aaf, 0x662f3583, 0x5ab1005b,
-0xe527ef70, 0x4170d611, 0x307bebc4, 0xfdd00caf, 0xbaae1044, 0xcab4d459,
-0x38281dcf, 0x90580c89, 0x49cf5986, 0xa27da769, 0xceced49b, 0x5ea37953,
-0x8a7e6c1c, 0x1e01b4e2, 0xe08026ae, 0x3754534a, 0x903b0ecf, 0x65f97a55,
-0x90798ed9, 0x9d1133bc, 0xe356a39f, 0xe47acbce, 0x01ccf326, 0x1954fd3d,
-0x240e69f8, 0x1da20bb4, 0xe1ab1684, 0x44c65d48, 0xd265e6c2, 0x51d4ef07,
-0x000970ef, 0xfeb939f4, 0x5dcc0132, 0x2bd27ae5, 0xba5dbd25, 0xa9d190e4,
-0x61556bec, 0x7fd6caba, 0x7fe312cb, 0xdd319413, 0x92a5dbbf, 0x17e61915,
-0x56067b67, 0x3dc348c0, 0x58c17fe0, 0xbe6bffcc, 0xd379026c, 0xc4174780,
-0xcce7f026, 0xb74b7eb0, 0xe4d5f625, 0x6bc16d3b, 0xff3e300e, 0x83f0d55a,
-0xf2e537df, 0x75c18f78, 0xa5458d1a, 0x47c778b0, 0x92eb8716, 0xcb5816fd,
-0xc2cc7079, 0xa7f1dc75, 0xed9e5ffa, 0xb7d6747f, 0xa2dc6907, 0x99b4d187,
-0x69f3138a, 0xbd285a1f, 0xb8ee18e0, 0x734b77a5, 0xc0700f69, 0x6c72a77a,
-0x76609ba9, 0xcfae9b73, 0x2cd329f0, 0x0d45aa12, 0x419fbcd7, 0x03e00f00,
-0x0effee99, 0x7f879eb4, 0x29a4c8df, 0x4432400a, 0x22b9cf55, 0xa1c4c645,
-0x200251b0, 0xff293906, 0xe11288e2, 0xde1e8ec7, 0x675752d1, 0x9630743e,
-0xd848c67e, 0x1eedfda9, 0x58b954fc, 0xa0dc7f1c, 0x0aea313e, 0x062b9449,
-0x0f17e57f, 0x96def6ec, 0x2ba45f14, 0xd9a5f8c5, 0x231483c8, 0x29b8783e,
-0xa6d24594, 0x1a62ffcd, 0x54c87a7f, 0x6fa9ca9a, 0xfff0f890, 0x51d6ae46,
-0xa96e82b0, 0x68cd9808, 0x56214df5, 0x2169defa, 0x72c1ecce, 0x2448e3c9,
-0x8eb2b3b3, 0x62c89c11, 0xbba20ee2, 0xea33f53a, 0x8b96a6b8, 0x9d33d551,
-0x363bd14e, 0x5fdd2b5f, 0xf8187546, 0xb692beab, 0x8df6b4c0, 0x753e2302,
-0xb90f7a37, 0x2b6bac6a, 0x13a07bc5, 0xb67f6d2b, 0x47b21569, 0xc2ab143f,
-0xf86ce30a, 0xde2dab70, 0x6f258860, 0x2878735c, 0x2aaeac20, 0xda80fb3e,
-0xe7a8ccf6, 0xbf011844, 0x40a610f8, 0x82f3fdf7, 0xadc4ec2c, 0xb8551030,
-0x76004380, 0xa384ff18, 0x080cf587, 0x6c4991d3, 0x2daea9aa, 0xa92d0c4f,
-0x4a9d117e, 0x2761f025, 0x96b40443, 0x57a82be4, 0x62374c44, 0x55dc64ae,
-0x28aa9f0c, 0x03a3b963, 0x41dbaa26, 0xb3c23735, 0x971cbd31, 0x939a9f80,
-0x76439fdc, 0xa9df79d6, 0x926ae3e2, 0x5ee75745, 0xf2396e52, 0xe18bd816,
-0x3f9834b9, 0x816a07bc, 0x8f873310, 0x45cf9b96, 0x0ce634dd, 0xe64a16d9,
-0x2733775a, 0x2b648c7e, 0xe600ee8e, 0xd99d8ae3, 0x10dadf2a, 0x904d3f87,
-0x3963e9e7, 0x47fcce89, 0xc256c898, 0x7db6cb66, 0xe1611a8b, 0xed81b10d,
-0x75eff974, 0x8a0a3d67, 0xa44311ff, 0x6f876783, 0x43dc93ce, 0x88616a33,
-0xa8706e8f, 0x33a2cbed, 0x3a6d20c3, 0x55175086, 0x39680945, 0x2d779a7b,
-0x0818a4ce, 0x55558918, 0xf7c08d35, 0x980a3038, 0x9cf068db, 0x3385d333,
-0xd81b33fb, 0x188018d5, 0x47c57bd3, 0x9ec2324f, 0x6901cd77, 0xc3bac44f,
-0x4d96aba8, 0x9094da5b, 0xa67a1353, 0x1fdfc4db, 0xa2fbeefa, 0xab4828e3,
-0x37d1db45, 0x0d33b3e9, 0x1ad72bb9, 0x7257bf9c, 0x2ec35167, 0xa4488b7f,
-0xf9dae588, 0x1038905a, 0x88ddf410, 0xaac11693, 0x24ac025d, 0x56cefbb5,
-0x6afe7f59, 0xc7f989e8, 0x15872570, 0x1bf16cdb, 0xfe9c93ce, 0x1fc9a076,
-0x85d37185, 0x1078cd31, 0xe1cd0327, 0x6d5315bc, 0x298cd836, 0xc8e21f06,
-0xe561c32d, 0x8ec404b4, 0x4d39bfbb, 0x24ede8c8, 0x451d6034, 0x3bafeea2,
-0x202f0ccf, 0x1fad37ce, 0xf04b5693, 0xeee57cd9, 0x5ef70007, 0x018e8a4f,
-0xfa61c9a9, 0x09989fcf, 0xe66b558b, 0x966efd48, 0x7525021d, 0xe7978b5e,
-0x7eb1d6dc, 0xa10c5e5b, 0xb7815e69, 0x7d486cfb, 0xcffdeb2a, 0x7375cb32,
-0x599008dc, 0xff91c796, 0x560ed4ad, 0x14e9a876, 0xfccf6a66, 0xa58be028,
-0xea9d408b, 0x3afc373b, 0xee008458, 0x19b6042e, 0x84806314, 0x431a4ba4,
-0x009ad6a1, 0xd7c62bf4, 0x1bebecba, 0x5c662f69, 0x83bfdea1, 0x45872a9a,
-0xca4700c9, 0x47dda29c, 0x57841aff, 0x59fb6aa5, 0xec649574, 0xf7e6d293,
-0xa6e6d40e, 0x364f91a8, 0x2c577646, 0xfd0d25d5, 0x58c7694d, 0x864930d4,
-0x78999124, 0xc231f2f7, 0xe4cfd0fc, 0x975038c8, 0x9398d150, 0x504b1498,
-0x52957004, 0xc172025e, 0x459a8af8, 0x2fecb2af, 0xb3a176ac, 0xbac24f0e,
-0xbddadef6, 0x4565426f, 0xc1019842, 0xa4efaf83, 0x2f2966be, 0xdae82bff,
-0xc27f135e, 0x94c3b409, 0x3b810ea0, 0x1cc39dc5, 0x731c8a7f, 0x34b6ee25,
-0xb78b808d, 0x80eef85f, 0x76a9fb29, 0xbfacb97b, 0xf7a0ea37, 0xe3e69d80,
-0xa19b8bd1, 0xf26246cd, 0x5495cf9a, 0x45ad1bf5, 0x2cb3296f, 0x3cb7e6fe,
-0xbbde4ac3, 0x310c7b67, 0xe6b00a32, 0x4004d280, 0x0eb8b6dd, 0x8d951f0e,
-0x96cb406f, 0xbe29ddb1, 0x38a3756d, 0xf5b058a1, 0xea638fd4, 0x438a7a69,
-0x530eb350, 0x7cb218e5, 0xa67b9d52, 0xfb86dfbf, 0x4ed65b7e, 0x00678272,
-0x9924a438, 0x9955c26a, 0xb8262774, 0x4ceecb5c, 0xeb103da7, 0xa1297389,
-0x0613c489, 0xdf96ae66, 0x8afcce8b, 0x023081f0, 0xc6786ca4, 0x26bdf079,
-0x1f29a180, 0xd8d3ec62, 0xe5d537a8, 0x83c99f4e, 0x69d0a8da, 0x027f9a9a,
-0x9d9cc9ae, 0x0e2be163, 0xd78cfbe8, 0x2fabb789, 0x48c13886, 0xe35f29b2,
-0xb74cc63f, 0x741dcff8, 0x23648527, 0x225155f9, 0xd40ee605, 0x0e4a954e,
-0x890ee0b3, 0x97eb0d7d, 0x8776520a, 0xe6fa67e7, 0xa5961e3d, 0xdf2af5a3,
-0x7dcbbe1b, 0x41f1af5a, 0xb5845b16, 0x5761f24d, 0xa1431e73, 0x1e00b132,
-0x5ddeb7ab, 0x80f29c49, 0xd83714b4, 0xa0412947, 0x96062e8b, 0x7e7f7f8c,
-0xdfba2365, 0x4ee1bc30, 0xfe10b1fd, 0x17d2db9f, 0xf0bd8dc9, 0x6c35d718,
-0x8962224b, 0xe0f6c654, 0x813f4a7c, 0xc52b4bb7, 0x65da3a71, 0xef9b4eac,
-0xf9657e9a, 0xba196585, 0xe3926762, 0xf66fb2a1, 0x433b9440, 0x1df33310,
-0xc6aa2685, 0xe19368f0, 0x706636e0, 0xde1e8c5a, 0xbc735af5, 0x67ef395e,
-0x6c1fb709, 0x3f7f16f7, 0xf2c4ebe5, 0x7dda3d51, 0x518b4a04, 0xd90dd373,
-0xe51fc13a, 0xf01060ae, 0xd1502c78, 0x0d549998, 0x19453c99, 0x52104c7a,
-0xc477d443, 0xce6910c0, 0x0dc163b4, 0x1dc4dab2, 0x5c4dbc0c, 0x6145ced9,
-0xf02e295b, 0x60196b15, 0x2aa68b89, 0x9ff0dd3b, 0xe4b874ce, 0x9175ec6c,
-0x9b629234, 0x644ce81d, 0x359fac36, 0x5211675f, 0xd24c092f, 0x1de9385e,
-0x1352b7e5, 0x8d650e83, 0x7057d366, 0x43371dd2, 0x61678e6e, 0xd436279b,
-0x267562b6, 0xabaf1706, 0x814bd74e, 0x3269cbda, 0x0a34b3cd, 0xa74c3d1a,
-0xd3b098c8, 0x02030412, 0xd75d7207, 0x519d1b3d, 0x1958436b, 0x69ba4221,
-0x81b6b4cf, 0xb83234e4, 0x7e652d03, 0x63bcf36e, 0xefecb5f7, 0x60550e08,
-0x394963ce, 0xfd6f2b38, 0x1342c68b, 0xbc39f1ca, 0x21bdd863, 0x59ade0af,
-0x2d0c793a, 0xa74702d4, 0xc00885f9, 0xc73c27af, 0x6566ea9e, 0xa31e0f7c,
-0x499f1706, 0xe19617ad, 0x0e19900a, 0x0a8d3669, 0xcc482af9, 0x5eb35096,
-0x269b51c1, 0x80d1145b, 0x4be232ff, 0x3d31fc83, 0x89127a6c, 0x90af3379,
-0x7726d002, 0x35f15151, 0x8393c3b5, 0x27a9ada8, 0x25940510, 0x05c49bf1,
-0xc7c1b886, 0xdb00826f, 0xf658f61f, 0xe5d77d98, 0xa637b6fb, 0x2f515fa5,
-0xb1f80c38, 0xe082d248, 0x4220acd0, 0x06360060, 0xcf42c277, 0xf5972529,
-0xf7e274fb, 0xfe41cc28, 0xde661de0, 0xa157bd26, 0x8e1f4788, 0x35c4111a,
-0x11a7360e, 0x751188e8, 0x544d9fc3, 0x33d853cd, 0x754542f7, 0x05d9979b,
-0x73e59071, 0x4909bb7e, 0x64ae94be, 0x0eb4c8e9, 0xacb903fe, 0xc716288e,
-0x1e914aa8, 0x19d127bd, 0x913a6dd4, 0x6af354d9, 0x72c29a95, 0x2fa731a5,
-0x9f206402, 0xa44abe92, 0xeb090ab4, 0x85b7584c, 0xf27cd398, 0x3b828e38,
-0x0cb8dd56, 0x37657f3c, 0x78fa0f2a, 0x3df7a0cb, 0x2621740f, 0x4d92422f,
-0x334a8fa2, 0x124f947d, 0x31be3505, 0xf6a1e561, 0x5d0c4087, 0x62971b45,
-0x312472a7, 0x933af4e3, 0x45c28196, 0x8ddd4f00, 0xa5ec20fb, 0x9acde751,
-0x23ac64e8, 0xbea00461, 0xf9d65eac, 0xe21db306, 0xcacb4f76, 0x83950ca3,
-0x66069329, 0xf7d72838, 0x5d13a747, 0x5c9ca583, 0x1d9d225e, 0xb2c705fe,
-0xd0fac625, 0x0a73b38e, 0xec8d6692, 0x0bb64587, 0xf147c00c, 0xcdd6020c,
-0x1608cede, 0xb531a423, 0x1c8b1b08, 0xdd74f03e, 0x6d3076fb, 0x2dcaaa44,
-0xe869582b, 0x0f19cde9, 0x44d15927, 0xee751f17, 0x655f24c4, 0x7508164e,
-0xab414b0d, 0x381d3525, 0x7a18cb74, 0xc91e435a, 0xb3397aa0, 0xa5567595,
-0x1da36e52, 0xb43ba598, 0x3ef0d4fd, 0x11d348c4, 0xfcb4cbfa, 0xa3dee1a7,
-0x8c6be341, 0xefafff59, 0xeaa95a58, 0x01ba74bb, 0x5b1d3193, 0x2ac942bb,
-0xbb5816ca, 0xe79720dd, 0x1683bbad, 0xea2f3992, 0xa89cdd39, 0x3a389386,
-0xc54d671f, 0xe8564365, 0x373196e0, 0xc08acfd2, 0x32f556b2, 0x15340220,
-0x817d0d1b, 0x4b9afaa3, 0xd3bbf932, 0x6c9ddf75, 0x0fca9bea, 0x2cd2d913,
-0x026e3647, 0x6e769b35, 0xdab34e6e, 0xc9b75a74, 0xfdc90304, 0xc6442959,
-0xa8f44fb4, 0x73fb26de, 0x833d2d60, 0x8cf7a461, 0xdc5c4bf9, 0x1bce371f,
-0xd1d6b743, 0xc1124cae, 0xf4d33161, 0x696956a5, 0xa5ce9c72, 0x5f84e109,
-0xa0dae0ff, 0xdfdf169e, 0xb734307c, 0x25843b5d, 0x0b710ae4, 0xafd25b2b,
-0xc013b89b, 0x5246e064, 0xeb28ab92, 0x4f92747c, 0x2f3c0c8b, 0x3268720d,
-0xef638533, 0xd0fc40ab, 0x5d29c943, 0x3fd9b311, 0x6833bf43, 0xa188ad03,
-0xacba3ad2, 0x9696f4da, 0x07b1b2fa, 0xb8f925f6, 0x082573f4, 0x506b5c0e,
-0xe290e707, 0x80933f06, 0x38dcad25, 0x276ab82f, 0x788f3a2c, 0x4b0e14bc,
-0xc1b38b43, 0x962a0efe, 0x77f19522, 0xd5bd951b, 0x90415ed2, 0x67a6a806,
-0x82d0503f, 0x814e505f, 0x6448341a, 0x2c88ba72, 0x1f783411, 0x5dcfc5d9,
-0x15cea1e2, 0x351ebdaa, 0xff083e5e, 0x173297d6, 0xbdadb9f2, 0xe82ebe50,
-0x33fff936, 0xaed0e402, 0xcd08e297, 0xeefee410, 0x023aedc0, 0x493fdd4c,
-0xd4454937, 0xa4c21893, 0xf9740292, 0x14308130, 0x2aa05568, 0xbd88a714,
-0x3f264976, 0x62203300, 0x5d9aa0bf, 0x3b9be4b0, 0xcb1c6dff, 0xe7f5ded8,
-0xb6ce0ec7, 0xdc1f094b, 0x0f93747c, 0x1768e49a, 0x1d7ebe93, 0x25d53887,
-0x144a1fe2, 0x32bc280c, 0x1d0b7884, 0x106b8928, 0x5aa38780, 0x87ca0d93,
-0x11a81f71, 0xe0957877, 0xb21fb0f7, 0x1e5a7ac0, 0x09db53a1, 0x5210dd59,
-0xa0566364
-
-ea =
-14412
-
-eb =
-14412
-
-cab =
-4
-
-c =
-4
-
-c_neg =
-0
-
-k_pos =
-4800
-
-k_neg =
-4736
-
-ncb_pos =
-14496
-
-ncb_neg =
-14304
-
-r =
-2
-
-rv_index =
-0
-
-code_block_mode =
-0
-
-op_flags =
-RTE_BBDEV_TURBO_CRC_24B_ATTACH
-
-expected_status =
-OK
\ No newline at end of file
-- 
1.8.3.1


^ permalink raw reply	[flat|nested] 115+ messages in thread

* [dpdk-dev] [PATCH v1 11/14] doc: update of testbbdev documentation
  2020-02-27  4:38 [dpdk-dev] [PATCH v1 00/14] bbdev new features Nicolas Chautru
                   ` (9 preceding siblings ...)
  2020-02-27  4:39 ` [dpdk-dev] [PATCH v1 10/14] test-bbdev: vectors update Nicolas Chautru
@ 2020-02-27  4:39 ` Nicolas Chautru
  2020-02-27  4:39 ` [dpdk-dev] [PATCH v1 12/14] drivers/baseband: add PMD for FPGA 5GNR FEC Nicolas Chautru
                   ` (3 subsequent siblings)
  14 siblings, 0 replies; 115+ messages in thread
From: Nicolas Chautru @ 2020-02-27  4:39 UTC (permalink / raw)
  To: thomas, akhil.goyal, dev; +Cc: ferruh.yigit, Nic Chautru

From: Nic Chautru <nicolas.chautru@intel.com>

Update related to the changes introduced by the
previous commits.

Signed-off-by: Nic Chautru <nicolas.chautru@intel.com>
---
 doc/guides/tools/testbbdev.rst | 337 +++++++++++++++++++++++++++++++++++------
 1 file changed, 291 insertions(+), 46 deletions(-)

diff --git a/doc/guides/tools/testbbdev.rst b/doc/guides/tools/testbbdev.rst
index 7e95696..016f3f9 100644
--- a/doc/guides/tools/testbbdev.rst
+++ b/doc/guides/tools/testbbdev.rst
@@ -6,9 +6,9 @@ dpdk-test-bbdev Application
 
 The ``dpdk-test-bbdev`` tool is a Data Plane Development Kit (DPDK) utility that
 allows measuring performance parameters of PMDs available in the bbdev framework.
-Available tests available for execution are: latency, throughput, validation and
-sanity tests. Execution of tests can be customized using various parameters
-passed to a python running script.
+Available tests available for execution are: latency, throughput, validation,
+bler and sanity tests. Execution of tests can be customized using various
+parameters passed to a python running script.
 
 Compiling the Application
 -------------------------
@@ -47,6 +47,8 @@ The tool application has a number of command line options:
                        [-c TEST_CASE [TEST_CASE ...]]
                        [-v TEST_VECTOR [TEST_VECTOR...]] [-n NUM_OPS]
                        [-b BURST_SIZE [BURST_SIZE ...]] [-l NUM_LCORES]
+                       [-t MAX_ITERS [MAX_ITERS ...]]
+                       [-s SNR [SNR ...]]
 
 command-line Options
 ~~~~~~~~~~~~~~~~~~~~
@@ -106,10 +108,18 @@ The following are the command-line options:
  Specifies operations enqueue/dequeue burst size. If not specified burst_size is
  set to 32. Maximum is 512.
 
+``-t MAX_ITERS [MAX_ITERS ...], --iter_max MAX_ITERS [MAX_ITERS ...]``
+ Specifies LDPC decoder operations maximum number of iterations for throughput
+ and bler tests. If not specified iter_max is set to 6.
+
+``-s SNR [SNR ...], --snr SNR [SNR ...]``
+ Specifies for LDPC decoder operations the SNR in dB used when generating LLRs
+ for bler tests. If not specified snr is set to 0 dB.
+
 Test Cases
 ~~~~~~~~~~
 
-There are 6 main test cases that can be executed using testbbdev tool:
+There are 7 main test cases that can be executed using testbbdev tool:
 
 * Sanity checks [-c unittest]
     - Performs sanity checks on BBDEV interface, validating basic functionality
@@ -149,6 +159,11 @@ There are 6 main test cases that can be executed using testbbdev tool:
     - Results are printed in million operations per second and million bits
       per second
 
+* BLER measurement [-c bler]
+    - Performs full operation of enqueue and dequeue
+    - Measures the achieved throughput on a subset or all available CPU cores
+    - Computed BLER in % based on the total number of operations.
+
 * Interrupt-mode Throughput [-c interrupt]
     - Similar to Throughput test case, but using interrupts. No polling.
 
@@ -159,7 +174,7 @@ Parameter Globbing
 Thanks to the globbing functionality in python test-bbdev.py script allows to
 run tests with different set of vector files without giving all of them explicitly.
 
-**Example usage:**
+**Example usage for 4G:**
 
 .. code-block:: console
 
@@ -221,6 +236,11 @@ It runs all tests with "default" vectors.
 * ``turbo_enc_default.data`` is a soft link to
   ``turbo_enc_c1_k6144_r0_e32256_crc24b_rm.data``
 
+* ``ldpc_dec_default.data`` is a soft link to
+  ``ldpc_dec_v6563.data``
+
+* ``ldpc_enc_default.data`` is a soft link to
+  ``ldpc_enc_c1_k8148_r0_e9372_rm.data``
 
 Running Tests
 -------------
@@ -254,6 +274,38 @@ x86_64-native-linux-icc target:
              |-- turbo_dec_c1_k6144_r0_e34560_posllr.data
              |-- turbo_enc_c1_k40_r0_e1194_rm.data
              |-- turbo_enc_c1_k6144_r0_e32256_crc24b_rm.data
+             |-- ldpc_enc_v9503.data
+             |-- ldpc_enc_v8568.data
+             |-- ldpc_enc_v7813.data
+             |-- ldpc_enc_v2342.data
+             |-- ldpc_enc_v11835.data
+             |-- ldpc_dec_v8568.data
+             |-- ldpc_dec_v8480.data
+             |-- ldpc_dec_v7813.data
+             |-- ldpc_dec_v2342_drop.data
+             |-- ldpc_dec_v11835.data
+             |-- ldpc_dec_HARQ_1_2.data
+             |-- ldpc_dec_HARQ_1_1.data
+             |-- ldpc_dec_HARQ_1_0.data
+             |-- ldpc_enc_v8568_crc24a.data
+             |-- ldpc_enc_v3964_rv1.data
+             |-- ldpc_enc_c1_k8148_r0_e9372_rm.data
+             |-- ldpc_enc_c1_k720_r0_e864_rm_crc24b.data
+             |-- ldpc_enc_c1_k720_r0_e832_rm.data
+             |-- ldpc_enc_c1_k330_r0_e360_rm.data
+             |-- ldpc_enc_c1_k1144_r0_e1380_rm_crc24b.data
+             |-- ldpc_enc_c1_k1144_r0_e1380_rm.data
+             |-- ldpc_dec_vcrc_fail.data
+             |-- ldpc_dec_v8568_low.data
+             |-- ldpc_dec_v14298.data
+             |-- ldpc_dec_HARQ_26449_1.loopback_w
+             |-- ldpc_dec_HARQ_1_3.data
+             |-- ldpc_enc_v2570_lbrm.data
+             |-- ldpc_dec_v9503.data
+             |-- ldpc_dec_v6563.data
+             |-- ldpc_dec_HARQ_3_1_harq_comp.data
+             |-- ldpc_dec_HARQ_2_1_llr_comp.data
+             |-- ldpc_dec_HARQ_26449_1.loopback_r
 
  |-- x86_64-native-linux-icc
      |-- app
@@ -280,7 +332,7 @@ baseband turbo_sw device
 
   ./test-bbdev.py -p ../../x86_64-native-linux-icc/app/testbbdev
   -e="--vdev=baseband_turbo_sw" -t 120 -c validation
-  -v ./test_vectors/turbo_* -n 64 -b 8 32
+  -v ./test_vectors/* -n 64 -b 8 32
 
 It runs **validation** test for each vector file that matches the given pattern.
 Number of operations to process on device is set to 64 and operations timeout is
@@ -342,8 +394,8 @@ Length of chain variable is calculated by parser. Can not be defined
 explicitly.
 
 Variable op_type has to be defined as a first variable in file. It specifies
-what type of operations will be executed. For decoder op_type has to be set to
-``RTE_BBDEV_OP_TURBO_DEC`` and for encoder to ``RTE_BBDEV_OP_TURBO_ENC``.
+what type of operations will be executed. For 4G decoder op_type has to be set to
+``RTE_BBDEV_OP_TURBO_DEC`` and for 4G encoder to ``RTE_BBDEV_OP_TURBO_ENC``.
 
 Full details of the meaning and valid values for the below fields are
 documented in *rte_bbdev_op.h*
@@ -469,35 +521,7 @@ uint8_t value
     num_maps =
     0
 
-Chain of flags for turbo decoder operation. Following flags can be used:
-
-- ``RTE_BBDEV_TURBO_SUBBLOCK_DEINTERLEAVE``
-
-- ``RTE_BBDEV_TURBO_CRC_TYPE_24B``
-
-- ``RTE_BBDEV_TURBO_EQUALIZER``
-
-- ``RTE_BBDEV_TURBO_SOFT_OUT_SATURATE``
-
-- ``RTE_BBDEV_TURBO_HALF_ITERATION_EVEN``
-
-- ``RTE_BBDEV_TURBO_CONTINUE_CRC_MATCH``
-
-- ``RTE_BBDEV_TURBO_SOFT_OUTPUT``
-
-- ``RTE_BBDEV_TURBO_EARLY_TERMINATION``
-
-- ``RTE_BBDEV_TURBO_DEC_INTERRUPTS``
-
-- ``RTE_BBDEV_TURBO_POS_LLR_1_BIT_IN``
-
-- ``RTE_BBDEV_TURBO_NEG_LLR_1_BIT_IN``
-
-- ``RTE_BBDEV_TURBO_POS_LLR_1_BIT_SOFT_OUT``
-
-- ``RTE_BBDEV_TURBO_NEG_LLR_1_BIT_SOFT_OUT``
-
-- ``RTE_BBDEV_TURBO_MAP_DEC``
+Chain of flags for LDPC decoder operation based on the rte_bbdev_op_td_flag_bitmasks:
 
 Example:
 
@@ -579,26 +603,247 @@ uint8_t value
     rv_index =
     0
 
-Chain of flags for turbo encoder operation. Following flags can be used:
+Chain of flags for LDPC decoder operation based on the rte_bbdev_op_te_flag_bitmasks:
+
+``RTE_BBDEV_TURBO_ENC_SCATTER_GATHER`` is used to indicate the parser to
+force the input data to be memory split and formed as a segmented mbuf.
+
+
+.. parsed-literal::
+
+    op_flags =
+    RTE_BBDEV_TURBO_RATE_MATCH
 
-- ``RTE_BBDEV_TURBO_RV_INDEX_BYPASS``
+Chain of operation statuses that are expected after operation is performed.
+Following statuses can be used:
 
-- ``RTE_BBDEV_TURBO_RATE_MATCH``
+- ``DMA``
 
-- ``RTE_BBDEV_TURBO_CRC_24B_ATTACH``
+- ``FCW``
 
-- ``RTE_BBDEV_TURBO_CRC_24A_ATTACH``
+- ``OK``
 
-- ``RTE_BBDEV_TURBO_ENC_SCATTER_GATHER``
+``OK`` means no errors are expected. Cannot be used with other values.
 
-``RTE_BBDEV_TURBO_ENC_SCATTER_GATHER`` is used to indicate the parser to
-force the input data to be memory split and formed as a segmented mbuf.
+.. parsed-literal::
+
+    expected_status =
+    OK
+
+LDPC decoder test vectors template
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+For LDPC decoder it has to be always set to ``RTE_BBDEV_OP_LDPC_DEC``
+
+.. parsed-literal::
+
+    op_type =
+    RTE_BBDEV_OP_LDPC_DEC
+
+Chain of uint32_t values. Note that it is possible to define more than one
+input/output entries which will result in chaining two or more data structures
+for *segmented Transport Blocks*
+
+.. parsed-literal::
+
+    input0 =
+    0x00000000, 0x7f817f00, 0x7f7f8100, 0x817f8100, 0x81008100, 0x7f818100, 0x81817f00, 0x7f818100,
+    0x81007f00, 0x7f818100, 0x817f8100, 0x81817f00, 0x81008100, 0x817f7f00, 0x7f7f8100, 0x81817f00
+
+.. parsed-literal::
+
+    output0 =
+    0xa7d6732e
+
+uint8_t value
+
+.. parsed-literal::
+
+    basegraph=
+    1
+
+uint16_t value
+
+.. parsed-literal::
+
+    z_c=
+    224
+
+uint16_t value
+
+.. parsed-literal::
+
+    n_cb=
+    14784
+
+uint8_t value
+
+.. parsed-literal::
+
+    q_m=
+    1
+
+uint16_t value
+
+.. parsed-literal::
+
+    n_filler=
+    40
+
+uint32_t value
+
+.. parsed-literal::
+
+    e=
+    13072
+
+uint8_t value
+
+.. parsed-literal::
+
+    rv_index=
+    2
+
+uint8_t value
+
+.. parsed-literal::
+    code_block_mode=
+    1
 
+uint8_t value
+
+.. parsed-literal::
+
+    iter_max=
+    20
+
+uint8_t value
+
+.. parsed-literal::
+
+    expected_iter_count=
+    8
+
+
+Chain of flags for LDPC decoder operation based on the rte_bbdev_op_ldpcdec_flag_bitmasks:
+
+Example:
+
+    .. parsed-literal::
+
+        op_flags =
+        RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE, RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE,
+        RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE, RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION
+
+Chain of operation statuses that are expected after operation is performed.
+Following statuses can be used:
+
+- ``SYNCRC``
+
+- ``SYN``
+
+- ``CRC``
+
+- ``OK``
+
+``OK`` means no errors are expected. Cannot be used with other values.
+
+.. parsed-literal::
+
+    expected_status =
+    CRC
+
+
+LDPC encoder test vectors template
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+For turbo encoder it has to be always set to ``RTE_BBDEV_OP_LDPC_ENC``
+
+.. parsed-literal::
+
+    op_type =
+    RTE_BBDEV_OP_LDPC_ENC
+
+Chain of uint32_t values
+
+.. parsed-literal::
+
+    input0 =
+    0x11d2bcac, 0x4d
+
+Chain of uint32_t values
+
+.. parsed-literal::
+
+    output0 =
+    0xd2399179, 0x640eb999, 0x2cbaf577, 0xaf224ae2, 0x9d139927, 0xe6909b29,
+    0xa25b7f47, 0x2aa224ce, 0x79f2
+
+
+uint8_t value
+
+.. parsed-literal::
+
+    basegraph=
+    1
+
+uint16_t value
+
+.. parsed-literal::
+
+    z_c=
+    52
+
+uint16_t value
+
+.. parsed-literal::
+
+    n_cb=
+    3432
+
+uint8_t value
+
+.. parsed-literal::
+
+    q_m=
+    6
+
+uint16_t value
+
+.. parsed-literal::
+
+    n_filler=
+    0
+
+uint32_t value
+
+.. parsed-literal::
+
+    e =
+    1380
+
+uint8_t value
+
+.. parsed-literal::
+
+    rv_index =
+    1
+
+uint8_t value
+
+.. parsed-literal::
+
+    code_block_mode =
+    1
+
+
+Chain of flags for LDPC encoder operation based on the
+rte_bbdev_op_ldpcenc_flag_bitmasks:
 
 .. parsed-literal::
 
     op_flags =
-    RTE_BBDEV_TURBO_RATE_MATCH
+    RTE_BBDEV_LDPC_RATE_MATCH
 
 Chain of operation statuses that are expected after operation is performed.
 Following statuses can be used:
-- 
1.8.3.1


^ permalink raw reply	[flat|nested] 115+ messages in thread

* [dpdk-dev] [PATCH v1 12/14] drivers/baseband: add PMD for FPGA 5GNR FEC
  2020-02-27  4:38 [dpdk-dev] [PATCH v1 00/14] bbdev new features Nicolas Chautru
                   ` (10 preceding siblings ...)
  2020-02-27  4:39 ` [dpdk-dev] [PATCH v1 11/14] doc: update of testbbdev documentation Nicolas Chautru
@ 2020-02-27  4:39 ` Nicolas Chautru
  2020-02-27  4:39 ` [dpdk-dev] [PATCH v1 13/14] test-bbdev: add support for FPGA driver initialization Nicolas Chautru
                   ` (2 subsequent siblings)
  14 siblings, 0 replies; 115+ messages in thread
From: Nicolas Chautru @ 2020-02-27  4:39 UTC (permalink / raw)
  To: thomas, akhil.goyal, dev; +Cc: ferruh.yigit, Nic Chautru

From: Nic Chautru <nicolas.chautru@intel.com>

Supports for FEC 5G PMD Driver on FPGA card PAC N3000

Signed-off-by: Nic Chautru <nicolas.chautru@intel.com>
---
 config/common_base                                 |    5 +
 doc/guides/bbdevs/fpga_5gnr_fec.rst                |  297 +++
 doc/guides/bbdevs/index.rst                        |    1 +
 drivers/baseband/Makefile                          |    2 +
 drivers/baseband/fpga_5gnr_fec/Makefile            |   29 +
 drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.c     | 2552 ++++++++++++++++++++
 drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h     |   74 +
 drivers/baseband/fpga_5gnr_fec/meson.build         |    6 +
 .../rte_pmd_bbdev_fpga_5gnr_fec_version.map        |   10 +
 drivers/baseband/meson.build                       |    2 +-
 mk/rte.app.mk                                      |    1 +
 11 files changed, 2978 insertions(+), 1 deletion(-)
 create mode 100644 doc/guides/bbdevs/fpga_5gnr_fec.rst
 create mode 100644 drivers/baseband/fpga_5gnr_fec/Makefile
 create mode 100644 drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.c
 create mode 100644 drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h
 create mode 100644 drivers/baseband/fpga_5gnr_fec/meson.build
 create mode 100644 drivers/baseband/fpga_5gnr_fec/rte_pmd_bbdev_fpga_5gnr_fec_version.map

diff --git a/config/common_base b/config/common_base
index 6ea9c63..f2cd338 100644
--- a/config/common_base
+++ b/config/common_base
@@ -578,6 +578,11 @@ CONFIG_RTE_LIBRTE_PMD_BBDEV_TURBO_SW=y
 CONFIG_RTE_LIBRTE_PMD_BBDEV_FPGA_LTE_FEC=y
 
 #
+# Compile PMD for Intel FPGA 5GNR FEC bbdev device
+#
+CONFIG_RTE_LIBRTE_PMD_BBDEV_FPGA_5GNR_FEC=y
+
+#
 # Compile generic crypto device library
 #
 CONFIG_RTE_LIBRTE_CRYPTODEV=y
diff --git a/doc/guides/bbdevs/fpga_5gnr_fec.rst b/doc/guides/bbdevs/fpga_5gnr_fec.rst
new file mode 100644
index 0000000..5641b1a
--- /dev/null
+++ b/doc/guides/bbdevs/fpga_5gnr_fec.rst
@@ -0,0 +1,297 @@
+..  SPDX-License-Identifier: BSD-3-Clause
+    Copyright(c) 2019 Intel Corporation
+
+Intel(R) FPGA 5GNR FEC Poll Mode Driver
+======================================
+
+The BBDEV FPGA 5GNR FEC poll mode driver (PMD) supports an FPGA implementation of a VRAN
+LDPC Encode / Decode 5GNR wireless acceleration function, using Intel's PCI-e and FPGA
+based Vista Creek device.
+
+Features
+--------
+
+FPGA 5GNR FEC PMD supports the following features:
+
+- LDPC Encode in the DL
+- LDPC Decode in the UL
+- 8 VFs per PF (physical device)
+- Maximum of 32 UL queues per VF
+- Maximum of 32 DL queues per VF
+- PCIe Gen-3 x8 Interface
+- MSI-X
+- SR-IOV
+
+FPGA 5GNR FEC PMD supports the following BBDEV capabilities:
+
+* For the LDPC encode operation:
+   - ``RTE_BBDEV_LDPC_CRC_24B_ATTACH`` :  set to attach CRC24B to CB(s)
+   - ``RTE_BBDEV_LDPC_RATE_MATCH`` :  if set then do not do Rate Match bypass
+
+* For the LDPC decode operation:
+   - ``RTE_BBDEV_LDPC_CRC_TYPE_24B_CHECK`` :  check CRC24B from CB(s)
+   - ``RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE`` :  disable early termination
+   - ``RTE_BBDEV_LDPC_CRC_TYPE_24B_DROP`` :  drops CRC24B bits appended while decoding
+   - ``RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE`` :  provides an input for HARQ combining
+   - ``RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE`` :  provides an input for HARQ combining
+   - ``RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_IN_ENABLE`` :  HARQ memory input is internal
+   - ``RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_OUT_ENABLE`` :  HARQ memory output is internal
+   - ``RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK`` :  loopback data to/from HARQ memory
+   - ``RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_FILLERS`` :  HARQ memory includes the fillers bits
+
+
+Limitations
+-----------
+
+FPGA 5GNR FEC does not support the following:
+
+- Scatter-Gather function
+
+
+Installation
+--------------
+
+Section 3 of the DPDK manual provides instuctions on installing and compiling DPDK. The
+default set of bbdev compile flags may be found in config/common_base, where for example
+the flag to build the FPGA 5GNR FEC device, ``CONFIG_RTE_LIBRTE_PMD_BBDEV_FPGA_5GNR_FEC``,
+is already set. It is assumed DPDK has been compiled using for instance:
+
+.. code-block:: console
+
+  make install T=x86_64-native-linuxapp-gcc
+
+
+DPDK requires hugepages to be configured as detailed in section 2 of the DPDK manual.
+The bbdev test application has been tested with a configuration 40 x 1GB hugepages. The
+hugepage configuration of a server may be examined using:
+
+.. code-block:: console
+
+   grep Huge* /proc/meminfo
+
+
+Initialization
+--------------
+
+When the device first powers up, its PCI Physical Functions (PF) can be listed through this command:
+
+.. code-block:: console
+
+  sudo lspci -vd8086:0d8f
+
+The physical and virtual functions are compatible with Linux UIO drivers:
+``vfio`` and ``igb_uio``. However, in order to work the FPGA 5GNR FEC device firstly needs
+to be bound to one of these linux drivers through DPDK.
+
+
+Bind PF UIO driver(s)
+~~~~~~~~~~~~~~~~~~~~~
+
+Install the DPDK igb_uio driver, bind it with the PF PCI device ID and use
+``lspci`` to confirm the PF device is under use by ``igb_uio`` DPDK UIO driver.
+
+The igb_uio driver may be bound to the PF PCI device using one of three methods:
+
+
+1. PCI functions (physical or virtual, depending on the use case) can be bound to
+the UIO driver by repeating this command for every function.
+
+.. code-block:: console
+
+  cd <dpdk-top-level-directory>
+  insmod ./build/kmod/igb_uio.ko
+  echo "8086 0d8f" > /sys/bus/pci/drivers/igb_uio/new_id
+  lspci -vd8086:0d8f
+
+
+2. Another way to bind PF with DPDK UIO driver is by using the ``dpdk-devbind.py`` tool
+
+.. code-block:: console
+
+  cd <dpdk-top-level-directory>
+  ./usertools/dpdk-devbind.py -b igb_uio 0000:06:00.0
+
+where the PCI device ID (example: 0000:06:00.0) is obtained using lspci -vd8086:0d8f
+
+
+3. A third way to bind is to use ``dpdk-setup.sh`` tool
+
+.. code-block:: console
+
+  cd <dpdk-top-level-directory>
+  ./usertools/dpdk-setup.sh
+
+  select 'Bind Ethernet/Crypto/Baseband device to IGB UIO module'
+  or
+  select 'Bind Ethernet/Crypto/Baseband device to VFIO module' depending on driver required
+  enter PCI device ID
+  select 'Display current Ethernet/Crypto/Baseband device settings' to confirm binding
+
+
+In the same way the FPGA 5GNR FEC PF can be bound with vfio, but vfio driver does not
+support SR-IOV configuration right out of the box, so it will need to be patched.
+
+
+Enable Virtual Functions
+~~~~~~~~~~~~~~~~~~~~~~~~
+
+Now, it should be visible in the printouts that PCI PF is under igb_uio control
+"``Kernel driver in use: igb_uio``"
+
+To show the number of available VFs on the device, read ``sriov_totalvfs`` file..
+
+.. code-block:: console
+
+  cat /sys/bus/pci/devices/0000\:<b>\:<d>.<f>/sriov_totalvfs
+
+  where 0000\:<b>\:<d>.<f> is the PCI device ID
+
+
+To enable VFs via igb_uio, echo the number of virtual functions intended to
+enable to ``max_vfs`` file..
+
+.. code-block:: console
+
+  echo <num-of-vfs> > /sys/bus/pci/devices/0000\:<b>\:<d>.<f>/max_vfs
+
+
+Afterwards, all VFs must be bound to appropriate UIO drivers as required, same
+way it was done with the physical function previously.
+
+Enabling SR-IOV via vfio driver is pretty much the same, except that the file
+name is different:
+
+.. code-block:: console
+
+  echo <num-of-vfs> > /sys/bus/pci/devices/0000\:<b>\:<d>.<f>/sriov_numvfs
+
+
+Configure the VFs through PF
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The PCI virtual functions must be configured before working or getting assigned
+to VMs/Containers. The configuration involves allocating the number of hardware
+queues, priorities, load balance, bandwidth and other settings necessary for the
+device to perform FEC functions.
+
+This configuration needs to be executed at least once after reboot or PCI FLR and can
+be achieved by using the function ``fpga_5gnr_fec_configure()``, which sets up the
+parameters defined in ``fpga_5gnr_fec_conf`` structure:
+
+.. code-block:: c
+
+  struct fpga_5gnr_fec_conf {
+      bool pf_mode_en;
+      uint8_t vf_ul_queues_number[FPGA_5GNR_FEC_NUM_VFS];
+      uint8_t vf_dl_queues_number[FPGA_5GNR_FEC_NUM_VFS];
+      uint8_t ul_bandwidth;
+      uint8_t dl_bandwidth;
+      uint8_t ul_load_balance;
+      uint8_t dl_load_balance;
+      uint16_t flr_time_out;
+  };
+
+- ``pf_mode_en``: identifies whether only PF is to be used, or the VFs. PF and
+  VFs are mutually exclusive and cannot run simultaneously.
+  Set to 1 for PF mode enabled.
+  If PF mode is enabled all queues available in the device are assigned
+  exclusively to PF and 0 queues given to VFs.
+
+- ``vf_*l_queues_number``: defines the hardware queue mapping for every VF.
+
+- ``*l_bandwidth``: in case of congestion on PCIe interface. The device
+  allocates different bandwidth to UL and DL. The weight is configured by this
+  setting. The unit of weight is 3 code blocks. For example, if the code block
+  cbps (code block per second) ratio between UL and DL is 12:1, then the
+  configuration value should be set to 36:3. The schedule algorithm is based
+  on code block regardless the length of each block.
+
+- ``*l_load_balance``: hardware queues are load-balanced in a round-robin
+  fashion. Queues get filled first-in first-out until they reach a pre-defined
+  watermark level, if exceeded, they won't get assigned new code blocks..
+  This watermark is defined by this setting.
+
+  If all hardware queues exceeds the watermark, no code blocks will be
+  streamed in from UL/DL code block FIFO.
+
+- ``flr_time_out``: specifies how many 16.384us to be FLR time out. The
+  time_out = flr_time_out x 16.384us. For instance, if you want to set 10ms for
+  the FLR time out then set this setting to 0x262=610.
+
+
+An example configuration code calling the function ``fpga_5gnr_fec_configure()`` is shown
+below:
+
+.. code-block:: c
+
+  struct fpga_5gnr_fec_conf conf;
+  unsigned int i;
+
+  memset(&conf, 0, sizeof(struct fpga_5gnr_fec_conf));
+  conf.pf_mode_en = 1;
+
+  for (i = 0; i < FPGA_5GNR_FEC_NUM_VFS; ++i) {
+      conf.vf_ul_queues_number[i] = 4;
+      conf.vf_dl_queues_number[i] = 4;
+  }
+  conf.ul_bandwidth = 12;
+  conf.dl_bandwidth = 5;
+  conf.dl_load_balance = 64;
+  conf.ul_load_balance = 64;
+
+  /* setup FPGA PF */
+  ret = fpga_5gnr_fec_configure(info->dev_name, &conf);
+  TEST_ASSERT_SUCCESS(ret,
+      "Failed to configure 4G FPGA PF for bbdev %s",
+      info->dev_name);
+
+
+Test Application
+----------------
+
+BBDEV provides a test application, ``test-bbdev.py`` and range of test data for testing
+the functionality of FPGA 5GNR FEC encode and decode, depending on the device's
+capabilities. The test application is located under app->test-bbdev folder and has the
+following options:
+
+.. code-block:: console
+
+  "-p", "--testapp-path": specifies path to the bbdev test app.
+  "-e", "--eal-params"	: EAL arguments which are passed to the test app.
+  "-t", "--timeout"	: Timeout in seconds (default=300).
+  "-c", "--test-cases"	: Defines test cases to run. Run all if not specified.
+  "-v", "--test-vector"	: Test vector path (default=dpdk_path+/app/test-bbdev/test_vectors/bbdev_null.data).
+  "-n", "--num-ops"	: Number of operations to process on device (default=32).
+  "-b", "--burst-size"	: Operations enqueue/dequeue burst size (default=32).
+  "-l", "--num-lcores"	: Number of lcores to run (default=16).
+  "-i", "--init-device" : Initialise PF device with default values.
+
+
+To execute the test application tool using simple decode or encode data,
+type one of the following:
+
+.. code-block:: console
+
+  ./test-bbdev.py -c validation -n 64 -b 1 -v ./ldpc_dec_default.data
+  ./test-bbdev.py -c validation -n 64 -b 1 -v ./ldpc_enc_default.data
+
+
+The test application ``test-bbdev.py``, supports the ability to configure the PF device with
+a default set of values, if the "-i" or "- -init-device" option is included. The default values
+are defined in test_bbdev_perf.c as:
+
+- VF_UL_QUEUE_VALUE 4
+- VF_DL_QUEUE_VALUE 4
+- UL_BANDWIDTH 3
+- DL_BANDWIDTH 3
+- UL_LOAD_BALANCE 128
+- DL_LOAD_BALANCE 128
+- FLR_TIMEOUT 610
+
+
+Test Vectors
+~~~~~~~~~~~~
+
+In addition to the simple LDPC decoder and LDPC encoder tests, bbdev also provides
+a range of additional tests under the test_vectors folder, which may be useful. The results
+of these tests will depend on the FPGA 5GNR FEC capabilities.
diff --git a/doc/guides/bbdevs/index.rst b/doc/guides/bbdevs/index.rst
index 005b95e..1a79343 100644
--- a/doc/guides/bbdevs/index.rst
+++ b/doc/guides/bbdevs/index.rst
@@ -11,3 +11,4 @@ Baseband Device Drivers
     null
     turbo_sw
     fpga_lte_fec
+    fpga_5gnr_fec
diff --git a/drivers/baseband/Makefile b/drivers/baseband/Makefile
index 91048be..762773c 100644
--- a/drivers/baseband/Makefile
+++ b/drivers/baseband/Makefile
@@ -12,5 +12,7 @@ DIRS-$(CONFIG_RTE_LIBRTE_PMD_BBDEV_TURBO_SW) += turbo_sw
 DEPDIRS-turbo_sw = $(core-libs)
 DIRS-$(CONFIG_RTE_LIBRTE_PMD_BBDEV_FPGA_LTE_FEC) += fpga_lte_fec
 DEPDIRS-fpga_lte_fec = $(core-libs)
+DIRS-$(CONFIG_RTE_LIBRTE_PMD_BBDEV_FPGA_LTE_FEC) += fpga_5gnr_fec
+DEPDIRS-fpga_5gnr_fec = $(core-libs)
 
 include $(RTE_SDK)/mk/rte.subdir.mk
diff --git a/drivers/baseband/fpga_5gnr_fec/Makefile b/drivers/baseband/fpga_5gnr_fec/Makefile
new file mode 100644
index 0000000..de80d67
--- /dev/null
+++ b/drivers/baseband/fpga_5gnr_fec/Makefile
@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2019 Intel Corporation
+
+include $(RTE_SDK)/mk/rte.vars.mk
+
+# library name
+LIB = librte_pmd_bbdev_fpga_5gnr_fec.a
+
+# build flags
+CFLAGS += -DALLOW_EXPERIMENTAL_API
+CFLAGS += -O3
+CFLAGS += $(WERROR_FLAGS)
+LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool -lrte_ring
+LDLIBS += -lrte_bbdev
+LDLIBS += -lrte_pci -lrte_bus_pci
+
+# versioning export map
+EXPORT_MAP := rte_pmd_bbdev_fpga_5gnr_fec_version.map
+
+# library version
+LIBABIVER := 1
+
+# library source files
+SRCS-$(CONFIG_RTE_LIBRTE_PMD_BBDEV_FPGA_5GNR_FEC) += fpga_5gnr_fec.c
+
+# export include files
+SYMLINK-$(CONFIG_RTE_LIBRTE_PMD_BBDEV_FPGA_5GNR_FEC)-include += fpga_5gnr_fec.h
+
+include $(RTE_SDK)/mk/rte.lib.mk
diff --git a/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.c b/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.c
new file mode 100644
index 0000000..5935e24
--- /dev/null
+++ b/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.c
@@ -0,0 +1,2552 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2020 Intel Corporation
+ */
+
+#include <unistd.h>
+
+#include <rte_common.h>
+#include <rte_log.h>
+#include <rte_dev.h>
+#include <rte_malloc.h>
+#include <rte_mempool.h>
+#include <rte_errno.h>
+#include <rte_pci.h>
+#include <rte_bus_pci.h>
+#include <rte_byteorder.h>
+#ifdef RTE_BBDEV_OFFLOAD_COST
+#include <rte_cycles.h>
+#endif
+
+#include <rte_bbdev.h>
+#include <rte_bbdev_pmd.h>
+
+#include "fpga_5gnr_fec.h"
+
+/* 5GNR SW PMD logging ID */
+static int fpga_5gnr_fec_logtype;
+
+/* Helper macro for logging */
+#define rte_bbdev_log(level, fmt, ...) \
+	rte_log(RTE_LOG_ ## level, fpga_5gnr_fec_logtype, fmt "\n", \
+		##__VA_ARGS__)
+
+#ifdef RTE_LIBRTE_BBDEV_DEBUG
+#define rte_bbdev_log_debug(fmt, ...) \
+		rte_bbdev_log(DEBUG, "fpga_5gnr_fec: " fmt, \
+		##__VA_ARGS__)
+#else
+#define rte_bbdev_log_debug(fmt, ...)
+#endif
+
+/* FPGA 5GNR FEC driver names */
+#define FPGA_5GNR_FEC_PF_DRIVER_NAME intel_fpga_5gnr_fec_pf
+#define FPGA_5GNR_FEC_VF_DRIVER_NAME intel_fpga_5gnr_fec_vf
+
+/* FPGA 5GNR FEC PCI vendor & device IDs */
+#define FPGA_5GNR_FEC_VENDOR_ID (0x8086)
+#define FPGA_5GNR_FEC_PF_DEVICE_ID (0x0D8F)
+#define FPGA_5GNR_FEC_VF_DEVICE_ID (0x0D90)
+
+/* Align DMA descriptors to 256 bytes - cache-aligned */
+#define FPGA_RING_DESC_ENTRY_LENGTH (8)
+/* Ring size is in 256 bits (32 bytes) units */
+#define FPGA_RING_DESC_LEN_UNIT_BYTES (32)
+/* Maximum size of queue */
+#define FPGA_RING_MAX_SIZE (1024)
+#define FPGA_FLR_TIMEOUT_UNIT (16.384)
+
+#define FPGA_NUM_UL_QUEUES (32)
+#define FPGA_NUM_DL_QUEUES (32)
+#define FPGA_TOTAL_NUM_QUEUES (FPGA_NUM_UL_QUEUES + FPGA_NUM_DL_QUEUES)
+#define FPGA_NUM_INTR_VEC (FPGA_TOTAL_NUM_QUEUES - RTE_INTR_VEC_RXTX_OFFSET)
+
+#define FPGA_INVALID_HW_QUEUE_ID (0xFFFFFFFF)
+
+#define FPGA_QUEUE_FLUSH_TIMEOUT_US (1000)
+#define FPGA_HARQ_RDY_TIMEOUT (10)
+#define FPGA_TIMEOUT_CHECK_INTERVAL (5)
+#define FPGA_DDR_OVERFLOW (0x10)
+
+#define FPGA_5GNR_FEC_DDR_WR_DATA_LEN_IN_BYTES 8
+#define FPGA_5GNR_FEC_DDR_RD_DATA_LEN_IN_BYTES 8
+
+
+/* FPGA 5GNR FEC Register mapping on BAR0 */
+enum {
+	FPGA_5GNR_FEC_VERSION_ID = 0x00000000, /* len: 4B */
+	FPGA_5GNR_FEC_CONFIGURATION = 0x00000004, /* len: 2B */
+	FPGA_5GNR_FEC_QUEUE_PF_VF_MAP_DONE = 0x00000008, /* len: 1B */
+	FPGA_5GNR_FEC_LOAD_BALANCE_FACTOR = 0x0000000a, /* len: 2B */
+	FPGA_5GNR_FEC_RING_DESC_LEN = 0x0000000c, /* len: 2B */
+	FPGA_5GNR_FEC_FLR_TIME_OUT = 0x0000000e, /* len: 2B */
+	FPGA_5GNR_FEC_VFQ_FLUSH_STATUS_LW = 0x00000018, /* len: 4B */
+	FPGA_5GNR_FEC_VFQ_FLUSH_STATUS_HI = 0x0000001c, /* len: 4B */
+	FPGA_5GNR_FEC_QUEUE_MAP = 0x00000040, /* len: 256B */
+	FPGA_5GNR_FEC_RING_CTRL_REGS = 0x00000200, /* len: 2048B */
+	FPGA_5GNR_FEC_DDR4_WR_ADDR_REGS = 0x00000A00, /* len: 4B */
+	FPGA_5GNR_FEC_DDR4_WR_DATA_REGS = 0x00000A08, /* len: 8B */
+	FPGA_5GNR_FEC_DDR4_WR_DONE_REGS = 0x00000A10, /* len: 1B */
+	FPGA_5GNR_FEC_DDR4_RD_ADDR_REGS = 0x00000A18, /* len: 4B */
+	FPGA_5GNR_FEC_DDR4_RD_DONE_REGS = 0x00000A20, /* len: 1B */
+	FPGA_5GNR_FEC_DDR4_RD_RDY_REGS = 0x00000A28, /* len: 1B */
+	FPGA_5GNR_FEC_DDR4_RD_DATA_REGS = 0x00000A30, /* len: 8B */
+	FPGA_5GNR_FEC_DDR4_ADDR_RDY_REGS = 0x00000A38, /* len: 1B */
+	FPGA_5GNR_FEC_HARQ_BUF_SIZE_RDY_REGS = 0x00000A40, /* len: 1B */
+	FPGA_5GNR_FEC_HARQ_BUF_SIZE_REGS = 0x00000A48  /* len: 4B */
+};
+
+/* FPGA 5GNR FEC Ring Control Registers */
+enum {
+	FPGA_5GNR_FEC_RING_HEAD_ADDR = 0x00000008,
+	FPGA_5GNR_FEC_RING_SIZE = 0x00000010,
+	FPGA_5GNR_FEC_RING_MISC = 0x00000014,
+	FPGA_5GNR_FEC_RING_ENABLE = 0x00000015,
+	FPGA_5GNR_FEC_RING_FLUSH_QUEUE_EN = 0x00000016,
+	FPGA_5GNR_FEC_RING_SHADOW_TAIL = 0x00000018,
+	FPGA_5GNR_FEC_RING_HEAD_POINT = 0x0000001C
+};
+
+/* FPGA 5GNR FEC DESCRIPTOR ERROR */
+enum {
+	DESC_ERR_NO_ERR = 0x0,
+	DESC_ERR_K_P_OUT_OF_RANGE = 0x1,
+	DESC_ERR_Z_C_NOT_LEGAL = 0x2,
+	DESC_ERR_DESC_OFFSET_ERR = 0x3,
+	DESC_ERR_DESC_READ_FAIL = 0x8,
+	DESC_ERR_DESC_READ_TIMEOUT = 0x9,
+	DESC_ERR_DESC_READ_TLP_POISONED = 0xA,
+	DESC_ERR_CB_READ_FAIL = 0xC,
+	DESC_ERR_CB_READ_TIMEOUT = 0xD,
+	DESC_ERR_CB_READ_TLP_POISONED = 0xE,
+	DESC_ERR_HBSTORE_ERR = 0xF
+};
+
+
+/* FPGA 5GNR FEC DMA Encoding Request Descriptor */
+struct __attribute__((__packed__)) fpga_dma_enc_desc {
+	uint32_t done:1,
+		rsrvd0:7,
+		error:4,
+		rsrvd1:4,
+		num_null:10,
+		rsrvd2:6;
+	uint32_t ncb:15,
+		rsrvd3:1,
+		k0:16;
+	uint32_t irq_en:1,
+		crc_en:1,
+		rsrvd4:1,
+		qm_idx:3,
+		bg_idx:1,
+		zc:9,
+		desc_idx:10,
+		rsrvd5:6;
+	uint16_t rm_e;
+	uint16_t k_;
+	uint32_t out_addr_lw;
+	uint32_t out_addr_hi;
+	uint32_t in_addr_lw;
+	uint32_t in_addr_hi;
+
+	union {
+		struct {
+			/* Virtual addresses used to retrieve SW context info */
+			void *op_addr;
+			/* Stores information about total number of Code Blocks
+			 * in currently processed Transport Block
+			 */
+			uint64_t cbs_in_op;
+		};
+
+		uint8_t sw_ctxt[FPGA_RING_DESC_LEN_UNIT_BYTES *
+					(FPGA_RING_DESC_ENTRY_LENGTH - 1)];
+	};
+};
+
+
+/* FPGA 5GNR DPC FEC DMA Decoding Request Descriptor */
+struct __attribute__((__packed__)) fpga_dma_dec_desc {
+	uint32_t done:1,
+		iter:5,
+		et_pass:1,
+		crcb_pass:1,
+		error:4,
+		qm_idx:3,
+		max_iter:5,
+		bg_idx:1,
+		rsrvd0:1,
+		harqin_en:1,
+		zc:9;
+	uint32_t hbstroe_offset:22,
+		num_null:10;
+	uint32_t irq_en:1,
+		ncb:15,
+		desc_idx:10,
+		drop_crc24b:1,
+		crc24b_ind:1,
+		rv:2,
+		et_dis:1,
+		rsrvd2:1;
+	uint32_t harq_input_length:16,
+		rm_e:16;/*the inbound data byte length*/
+	uint32_t out_addr_lw;
+	uint32_t out_addr_hi;
+	uint32_t in_addr_lw;
+	uint32_t in_addr_hi;
+
+	union {
+		struct {
+			/* Virtual addresses used to retrieve SW context info */
+			void *op_addr;
+			/* Stores information about total number of Code Blocks
+			 * in currently processed Transport Block
+			 */
+			uint8_t cbs_in_op;
+		};
+
+		uint32_t sw_ctxt[8 * (FPGA_RING_DESC_ENTRY_LENGTH - 1)];
+	};
+};
+
+/* FPGA 5GNR DMA Descriptor */
+union fpga_dma_desc {
+	struct fpga_dma_enc_desc enc_req;
+	struct fpga_dma_dec_desc dec_req;
+};
+
+/* FPGA 5GNR FEC Ring Control Register */
+struct __attribute__((__packed__)) fpga_ring_ctrl_reg {
+	uint64_t ring_base_addr;
+	uint64_t ring_head_addr;
+	uint16_t ring_size:11;
+	uint16_t rsrvd0;
+	union { /* Miscellaneous register */
+		uint8_t misc;
+		uint8_t max_ul_dec:5,
+			max_ul_dec_en:1,
+			rsrvd1:2;
+	};
+	uint8_t enable;
+	uint8_t flush_queue_en;
+	uint8_t rsrvd2;
+	uint16_t shadow_tail;
+	uint16_t rsrvd3;
+	uint16_t head_point;
+	uint16_t rsrvd4;
+
+};
+
+/* Private data structure for each FPGA FEC device */
+struct fpga_5gnr_fec_device {
+	/** Base address of MMIO registers (BAR0) */
+	void *mmio_base;
+	/** Base address of memory for sw rings */
+	void *sw_rings;
+	/** Physical address of sw_rings */
+	rte_iova_t sw_rings_phys;
+	/** Number of bytes available for each queue in device. */
+	uint32_t sw_ring_size;
+	/** Max number of entries available for each queue in device */
+	uint32_t sw_ring_max_depth;
+	/** Base address of response tail pointer buffer */
+	uint32_t *tail_ptrs;
+	/** Physical address of tail pointers */
+	rte_iova_t tail_ptr_phys;
+	/** Queues flush completion flag */
+	uint64_t *flush_queue_status;
+	/* Bitmap capturing which Queues are bound to the PF/VF */
+	uint64_t q_bound_bit_map;
+	/* Bitmap capturing which Queues have already been assigned */
+	uint64_t q_assigned_bit_map;
+	/** True if this is a PF FPGA FEC device */
+	bool pf_device;
+};
+
+/* Structure associated with each queue. */
+struct __rte_cache_aligned fpga_queue {
+	struct fpga_ring_ctrl_reg ring_ctrl_reg;  /* Ring Control Register */
+	union fpga_dma_desc *ring_addr;  /* Virtual address of software ring */
+	uint64_t *ring_head_addr;  /* Virtual address of completion_head */
+	uint64_t shadow_completion_head; /* Shadow completion head value */
+	uint16_t head_free_desc;  /* Ring head */
+	uint16_t tail;  /* Ring tail */
+	/* Mask used to wrap enqueued descriptors on the sw ring */
+	uint32_t sw_ring_wrap_mask;
+	uint32_t irq_enable;  /* Enable ops dequeue interrupts if set to 1 */
+	uint8_t q_idx;  /* Queue index */
+	struct fpga_5gnr_fec_device *d;
+	/* MMIO register of shadow_tail used to enqueue descriptors */
+	void *shadow_tail_addr;
+};
+
+/* Write to 16 bit MMIO register address */
+static inline void
+mmio_write_16(void *addr, uint16_t value)
+{
+	*((volatile uint16_t *)(addr)) = rte_cpu_to_le_16(value);
+}
+
+/* Write to 32 bit MMIO register address */
+static inline void
+mmio_write_32(void *addr, uint32_t value)
+{
+	*((volatile uint32_t *)(addr)) = rte_cpu_to_le_32(value);
+}
+
+/* Write to 64 bit MMIO register address */
+static inline void
+mmio_write_64(void *addr, uint64_t value)
+{
+	*((volatile uint64_t *)(addr)) = rte_cpu_to_le_64(value);
+}
+
+/* Write a 8 bit register of a FPGA 5GNR FEC device */
+static inline void
+fpga_reg_write_8(void *mmio_base, uint32_t offset, uint8_t payload)
+{
+	void *reg_addr = RTE_PTR_ADD(mmio_base, offset);
+	*((volatile uint8_t *)(reg_addr)) = payload;
+}
+
+/* Write a 16 bit register of a FPGA 5GNR FEC device */
+static inline void
+fpga_reg_write_16(void *mmio_base, uint32_t offset, uint16_t payload)
+{
+	void *reg_addr = RTE_PTR_ADD(mmio_base, offset);
+	mmio_write_16(reg_addr, payload);
+}
+
+/* Write a 32 bit register of a FPGA 5GNR FEC device */
+static inline void
+fpga_reg_write_32(void *mmio_base, uint32_t offset, uint32_t payload)
+{
+	void *reg_addr = RTE_PTR_ADD(mmio_base, offset);
+	mmio_write_32(reg_addr, payload);
+}
+
+/* Write a 64 bit register of a FPGA 5GNR FEC device */
+static inline void
+fpga_reg_write_64(void *mmio_base, uint32_t offset, uint64_t payload)
+{
+	void *reg_addr = RTE_PTR_ADD(mmio_base, offset);
+	mmio_write_64(reg_addr, payload);
+}
+
+/* Write a ring control register of a FPGA 5GNR FEC device */
+static inline void
+fpga_ring_reg_write(void *mmio_base, uint32_t offset,
+		struct fpga_ring_ctrl_reg payload)
+{
+	fpga_reg_write_64(mmio_base, offset, payload.ring_base_addr);
+	fpga_reg_write_64(mmio_base, offset + FPGA_5GNR_FEC_RING_HEAD_ADDR,
+			payload.ring_head_addr);
+	fpga_reg_write_16(mmio_base, offset + FPGA_5GNR_FEC_RING_SIZE,
+			payload.ring_size);
+	fpga_reg_write_16(mmio_base, offset + FPGA_5GNR_FEC_RING_HEAD_POINT,
+			payload.head_point);
+	fpga_reg_write_8(mmio_base, offset + FPGA_5GNR_FEC_RING_FLUSH_QUEUE_EN,
+			payload.flush_queue_en);
+	fpga_reg_write_16(mmio_base, offset + FPGA_5GNR_FEC_RING_SHADOW_TAIL,
+			payload.shadow_tail);
+	fpga_reg_write_8(mmio_base, offset + FPGA_5GNR_FEC_RING_MISC,
+			payload.misc);
+	fpga_reg_write_8(mmio_base, offset + FPGA_5GNR_FEC_RING_ENABLE,
+			payload.enable);
+}
+
+/* Read a register of FPGA 5GNR FEC device */
+static uint32_t
+fpga_reg_read_32(void *mmio_base, uint32_t offset)
+{
+	void *reg_addr = RTE_PTR_ADD(mmio_base, offset);
+	uint32_t ret = *((volatile uint32_t *)(reg_addr));
+	return rte_le_to_cpu_32(ret);
+}
+
+/* Read a register of FPGA 5GNR FEC device */
+static uint8_t
+fpga_reg_read_8(void *mmio_base, uint32_t offset)
+{
+	void *reg_addr = RTE_PTR_ADD(mmio_base, offset);
+	return *((volatile uint8_t *)(reg_addr));
+}
+
+/* Read a register of FPGA 5GNR FEC device */
+static uint64_t
+fpga_reg_read_64(void *mmio_base, uint32_t offset)
+{
+	void *reg_addr = RTE_PTR_ADD(mmio_base, offset);
+	uint64_t ret = *((volatile uint64_t *)(reg_addr));
+	return rte_le_to_cpu_64(ret);
+}
+
+#ifdef RTE_LIBRTE_BBDEV_DEBUG
+
+/* Read a register of FPGA 5GNR FEC device */
+static uint16_t
+fpga_reg_read_16(void *mmio_base, uint32_t offset)
+{
+	void *reg_addr = RTE_PTR_ADD(mmio_base, offset);
+	uint16_t ret = *((volatile uint16_t *)(reg_addr));
+	return rte_le_to_cpu_16(ret);
+}
+
+/* Read Ring Control Register of FPGA 5GNR FEC device */
+static inline void
+print_ring_reg_debug_info(void *mmio_base, uint32_t offset)
+{
+	rte_bbdev_log_debug(
+		"FPGA MMIO base address @ %p | Ring Control Register @ offset = 0x%08"
+		PRIx32, mmio_base, offset);
+	rte_bbdev_log_debug(
+		"RING_BASE_ADDR = 0x%016"PRIx64,
+		fpga_reg_read_64(mmio_base, offset));
+	rte_bbdev_log_debug(
+		"RING_HEAD_ADDR = 0x%016"PRIx64,
+		fpga_reg_read_64(mmio_base, offset +
+				FPGA_5GNR_FEC_RING_HEAD_ADDR));
+	rte_bbdev_log_debug(
+		"RING_SIZE = 0x%04"PRIx16,
+		fpga_reg_read_16(mmio_base, offset +
+				FPGA_5GNR_FEC_RING_SIZE));
+	rte_bbdev_log_debug(
+		"RING_MISC = 0x%02"PRIx8,
+		fpga_reg_read_8(mmio_base, offset +
+				FPGA_5GNR_FEC_RING_MISC));
+	rte_bbdev_log_debug(
+		"RING_ENABLE = 0x%02"PRIx8,
+		fpga_reg_read_8(mmio_base, offset +
+				FPGA_5GNR_FEC_RING_ENABLE));
+	rte_bbdev_log_debug(
+		"RING_FLUSH_QUEUE_EN = 0x%02"PRIx8,
+		fpga_reg_read_8(mmio_base, offset +
+				FPGA_5GNR_FEC_RING_FLUSH_QUEUE_EN));
+	rte_bbdev_log_debug(
+		"RING_SHADOW_TAIL = 0x%04"PRIx16,
+		fpga_reg_read_16(mmio_base, offset +
+				FPGA_5GNR_FEC_RING_SHADOW_TAIL));
+	rte_bbdev_log_debug(
+		"RING_HEAD_POINT = 0x%04"PRIx16,
+		fpga_reg_read_16(mmio_base, offset +
+				FPGA_5GNR_FEC_RING_HEAD_POINT));
+}
+
+/* Read Static Register of FPGA 5GNR FEC device */
+static inline void
+print_static_reg_debug_info(void *mmio_base)
+{
+	uint16_t config = fpga_reg_read_16(mmio_base,
+			FPGA_5GNR_FEC_CONFIGURATION);
+	uint8_t qmap_done = fpga_reg_read_8(mmio_base,
+			FPGA_5GNR_FEC_QUEUE_PF_VF_MAP_DONE);
+	uint16_t lb_factor = fpga_reg_read_16(mmio_base,
+			FPGA_5GNR_FEC_LOAD_BALANCE_FACTOR);
+	uint16_t ring_desc_len = fpga_reg_read_16(mmio_base,
+			FPGA_5GNR_FEC_RING_DESC_LEN);
+	uint16_t flr_time_out = fpga_reg_read_16(mmio_base,
+			FPGA_5GNR_FEC_FLR_TIME_OUT);
+
+	rte_bbdev_log_debug("UL.DL Weights = %u.%u",
+			((uint8_t)config), ((uint8_t)(config >> 8)));
+	rte_bbdev_log_debug("UL.DL Load Balance = %u.%u",
+			((uint8_t)lb_factor), ((uint8_t)(lb_factor >> 8)));
+	rte_bbdev_log_debug("Queue-PF/VF Mapping Table = %s",
+			(qmap_done > 0) ? "READY" : "NOT-READY");
+	rte_bbdev_log_debug("Ring Descriptor Size = %u bytes",
+			ring_desc_len*FPGA_RING_DESC_LEN_UNIT_BYTES);
+	rte_bbdev_log_debug("FLR Timeout = %f usec",
+			(float)flr_time_out*FPGA_FLR_TIMEOUT_UNIT);
+}
+
+/* Print decode DMA Descriptor of FPGA 5GNR Decoder device */
+static void
+print_dma_dec_desc_debug_info(union fpga_dma_desc *desc)
+{
+	rte_bbdev_log_debug("DMA response desc %p\n"
+		"\t-- done(%"PRIu32") | iter(%"PRIu32") | et_pass(%"PRIu32")"
+		" | crcb_pass (%"PRIu32") | error(%"PRIu32")\n"
+		"\t-- qm_idx(%"PRIu32") | max_iter(%"PRIu32") | "
+		"bg_idx (%"PRIu32") | harqin_en(%"PRIu32") | zc(%"PRIu32")\n"
+		"\t-- hbstroe_offset(%"PRIu32") | num_null (%"PRIu32") "
+		"| irq_en(%"PRIu32")\n"
+		"\t-- ncb(%"PRIu32") | desc_idx (%"PRIu32") | "
+		"drop_crc24b(%"PRIu32") | RV (%"PRIu32")\n"
+		"\t-- crc24b_ind(%"PRIu32") | et_dis (%"PRIu32")\n"
+		"\t-- harq_input_length(%"PRIu32") | rm_e(%"PRIu32")\n"
+		"\t-- cbs_in_op(%"PRIu32") | in_add (0x%08"PRIx32"%08"PRIx32")"
+		"| out_add (0x%08"PRIx32"%08"PRIx32")",
+		desc,
+		(uint32_t)desc->dec_req.done,
+		(uint32_t)desc->dec_req.iter,
+		(uint32_t)desc->dec_req.et_pass,
+		(uint32_t)desc->dec_req.crcb_pass,
+		(uint32_t)desc->dec_req.error,
+		(uint32_t)desc->dec_req.qm_idx,
+		(uint32_t)desc->dec_req.max_iter,
+		(uint32_t)desc->dec_req.bg_idx,
+		(uint32_t)desc->dec_req.harqin_en,
+		(uint32_t)desc->dec_req.zc,
+		(uint32_t)desc->dec_req.hbstroe_offset,
+		(uint32_t)desc->dec_req.num_null,
+		(uint32_t)desc->dec_req.irq_en,
+		(uint32_t)desc->dec_req.ncb,
+		(uint32_t)desc->dec_req.desc_idx,
+		(uint32_t)desc->dec_req.drop_crc24b,
+		(uint32_t)desc->dec_req.rv,
+		(uint32_t)desc->dec_req.crc24b_ind,
+		(uint32_t)desc->dec_req.et_dis,
+		(uint32_t)desc->dec_req.harq_input_length,
+		(uint32_t)desc->dec_req.rm_e,
+		(uint32_t)desc->dec_req.cbs_in_op,
+		(uint32_t)desc->dec_req.in_addr_hi,
+		(uint32_t)desc->dec_req.in_addr_lw,
+		(uint32_t)desc->dec_req.out_addr_hi,
+		(uint32_t)desc->dec_req.out_addr_lw);
+	uint32_t *word = (uint32_t *) desc;
+	rte_bbdev_log_debug("%08"PRIx32"\n%08"PRIx32"\n%08"PRIx32"\n%08"PRIx32"\n"
+			"%08"PRIx32"\n%08"PRIx32"\n%08"PRIx32"\n%08"PRIx32"\n",
+			word[0], word[1], word[2], word[3],
+			word[4], word[5], word[6], word[7]);
+}
+
+/* Print decode DMA Descriptor of FPGA 5GNR encoder device */
+static void
+print_dma_enc_desc_debug_info(union fpga_dma_desc *desc)
+{
+	rte_bbdev_log_debug("DMA response desc %p\n"
+			"%"PRIu32" %"PRIu32"\n"
+			"K' %"PRIu32" E %"PRIu32" desc %"PRIu32" Z %"PRIu32"\n"
+			"BG %"PRIu32" Qm %"PRIu32" CRC %"PRIu32" IRQ %"PRIu32"\n"
+			"k0 %"PRIu32" Ncb %"PRIu32" F %"PRIu32"\n",
+			desc,
+			(uint32_t)desc->enc_req.done,
+			(uint32_t)desc->enc_req.error,
+
+			(uint32_t)desc->enc_req.k_,
+			(uint32_t)desc->enc_req.rm_e,
+			(uint32_t)desc->enc_req.desc_idx,
+			(uint32_t)desc->enc_req.zc,
+
+			(uint32_t)desc->enc_req.bg_idx,
+			(uint32_t)desc->enc_req.qm_idx,
+			(uint32_t)desc->enc_req.crc_en,
+			(uint32_t)desc->enc_req.irq_en,
+
+			(uint32_t)desc->enc_req.k0,
+			(uint32_t)desc->enc_req.ncb,
+			(uint32_t)desc->enc_req.num_null);
+	uint32_t *word = (uint32_t *) desc;
+	rte_bbdev_log_debug("%08"PRIx32"\n%08"PRIx32"\n%08"PRIx32"\n%08"PRIx32"\n"
+			"%08"PRIx32"\n%08"PRIx32"\n%08"PRIx32"\n%08"PRIx32"\n",
+			word[0], word[1], word[2], word[3],
+			word[4], word[5], word[6], word[7]);
+}
+
+#endif
+
+static int
+fpga_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id)
+{
+	/* Number of queues bound to a PF/VF */
+	uint32_t hw_q_num = 0;
+	uint32_t ring_size, payload, address, q_id, offset;
+	rte_iova_t phys_addr;
+	struct fpga_ring_ctrl_reg ring_reg;
+	struct fpga_5gnr_fec_device *fpga_dev = dev->data->dev_private;
+
+	address = FPGA_5GNR_FEC_QUEUE_PF_VF_MAP_DONE;
+	if (!(fpga_reg_read_32(fpga_dev->mmio_base, address) & 0x1)) {
+		rte_bbdev_log(ERR,
+				"Queue-PF/VF mapping is not set! Was PF configured for device (%s) ?",
+				dev->data->name);
+		return -EPERM;
+	}
+
+	/* Clear queue registers structure */
+	memset(&ring_reg, 0, sizeof(struct fpga_ring_ctrl_reg));
+
+	/* Scan queue map.
+	 * If a queue is valid and mapped to a calling PF/VF the read value is
+	 * replaced with a queue ID and if it's not then
+	 * FPGA_INVALID_HW_QUEUE_ID is returned.
+	 */
+	for (q_id = 0; q_id < FPGA_TOTAL_NUM_QUEUES; ++q_id) {
+		uint32_t hw_q_id = fpga_reg_read_32(fpga_dev->mmio_base,
+				FPGA_5GNR_FEC_QUEUE_MAP + (q_id << 2));
+
+		rte_bbdev_log_debug("%s: queue ID: %u, registry queue ID: %u",
+				dev->device->name, q_id, hw_q_id);
+
+		if (hw_q_id != FPGA_INVALID_HW_QUEUE_ID) {
+			fpga_dev->q_bound_bit_map |= (1ULL << q_id);
+			/* Clear queue register of found queue */
+			offset = FPGA_5GNR_FEC_RING_CTRL_REGS +
+				(sizeof(struct fpga_ring_ctrl_reg) * q_id);
+			fpga_ring_reg_write(fpga_dev->mmio_base,
+					offset, ring_reg);
+			++hw_q_num;
+		}
+	}
+	if (hw_q_num == 0) {
+		rte_bbdev_log(ERR,
+			"No HW queues assigned to this device. Probably this is a VF configured for PF mode. Check device configuration!");
+		return -ENODEV;
+	}
+
+	if (num_queues > hw_q_num) {
+		rte_bbdev_log(ERR,
+			"Not enough queues for device %s! Requested: %u, available: %u",
+			dev->device->name, num_queues, hw_q_num);
+		return -EINVAL;
+	}
+
+	ring_size = FPGA_RING_MAX_SIZE * sizeof(struct fpga_dma_dec_desc);
+
+	/* Enforce 32 byte alignment */
+	RTE_BUILD_BUG_ON((RTE_CACHE_LINE_SIZE % 32) != 0);
+
+	/* Allocate memory for SW descriptor rings */
+	fpga_dev->sw_rings = rte_zmalloc_socket(dev->device->driver->name,
+			num_queues * ring_size, RTE_CACHE_LINE_SIZE,
+			socket_id);
+	if (fpga_dev->sw_rings == NULL) {
+		rte_bbdev_log(ERR,
+				"Failed to allocate memory for %s:%u sw_rings",
+				dev->device->driver->name, dev->data->dev_id);
+		return -ENOMEM;
+	}
+
+	fpga_dev->sw_rings_phys = rte_malloc_virt2iova(fpga_dev->sw_rings);
+	fpga_dev->sw_ring_size = ring_size;
+	fpga_dev->sw_ring_max_depth = FPGA_RING_MAX_SIZE;
+
+	/* Allocate memory for ring flush status */
+	fpga_dev->flush_queue_status = rte_zmalloc_socket(NULL,
+			sizeof(uint64_t), RTE_CACHE_LINE_SIZE, socket_id);
+	if (fpga_dev->flush_queue_status == NULL) {
+		rte_bbdev_log(ERR,
+				"Failed to allocate memory for %s:%u flush_queue_status",
+				dev->device->driver->name, dev->data->dev_id);
+		return -ENOMEM;
+	}
+
+	/* Set the flush status address registers */
+	phys_addr = rte_malloc_virt2iova(fpga_dev->flush_queue_status);
+
+	address = FPGA_5GNR_FEC_VFQ_FLUSH_STATUS_LW;
+	payload = (uint32_t)(phys_addr);
+	fpga_reg_write_32(fpga_dev->mmio_base, address, payload);
+
+	address = FPGA_5GNR_FEC_VFQ_FLUSH_STATUS_HI;
+	payload = (uint32_t)(phys_addr >> 32);
+	fpga_reg_write_32(fpga_dev->mmio_base, address, payload);
+
+	return 0;
+}
+
+static int
+fpga_dev_close(struct rte_bbdev *dev)
+{
+	struct fpga_5gnr_fec_device *fpga_dev = dev->data->dev_private;
+
+	rte_free(fpga_dev->sw_rings);
+	rte_free(fpga_dev->flush_queue_status);
+
+	return 0;
+}
+
+static void
+fpga_dev_info_get(struct rte_bbdev *dev,
+		struct rte_bbdev_driver_info *dev_info)
+{
+	struct fpga_5gnr_fec_device *d = dev->data->dev_private;
+	uint32_t q_id = 0;
+
+	static const struct rte_bbdev_op_cap bbdev_capabilities[] = {
+		{
+			.type   = RTE_BBDEV_OP_LDPC_ENC,
+			.cap.ldpc_enc = {
+				.capability_flags =
+						RTE_BBDEV_LDPC_RATE_MATCH |
+						RTE_BBDEV_LDPC_ENC_INTERRUPTS |
+						RTE_BBDEV_LDPC_CRC_24B_ATTACH,
+				.num_buffers_src =
+						RTE_BBDEV_LDPC_MAX_CODE_BLOCKS,
+				.num_buffers_dst =
+						RTE_BBDEV_LDPC_MAX_CODE_BLOCKS,
+			}
+		},
+		{
+		.type   = RTE_BBDEV_OP_LDPC_DEC,
+		.cap.ldpc_dec = {
+			.capability_flags =
+				RTE_BBDEV_LDPC_CRC_TYPE_24B_CHECK |
+				RTE_BBDEV_LDPC_CRC_TYPE_24B_DROP |
+				RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE |
+				RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE |
+				RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE |
+				RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_IN_ENABLE |
+				RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_OUT_ENABLE |
+				RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK |
+				RTE_BBDEV_LDPC_DEC_INTERRUPTS |
+				RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_FILLERS,
+			.llr_size = 6,
+			.llr_decimals = 2,
+			.num_buffers_src =
+					RTE_BBDEV_LDPC_MAX_CODE_BLOCKS,
+			.num_buffers_hard_out =
+					RTE_BBDEV_LDPC_MAX_CODE_BLOCKS,
+			.num_buffers_soft_out = 0,
+		}
+		},
+		RTE_BBDEV_END_OF_CAPABILITIES_LIST()
+	};
+
+	/* Check the HARQ DDR size available */
+	uint8_t timeout_counter = 0;
+	uint32_t harq_buf_ready = fpga_reg_read_32(d->mmio_base,
+			FPGA_5GNR_FEC_HARQ_BUF_SIZE_RDY_REGS);
+	while (harq_buf_ready != 1) {
+		usleep(FPGA_TIMEOUT_CHECK_INTERVAL);
+		timeout_counter++;
+		harq_buf_ready = fpga_reg_read_32(d->mmio_base,
+				FPGA_5GNR_FEC_HARQ_BUF_SIZE_RDY_REGS);
+		if (timeout_counter > FPGA_HARQ_RDY_TIMEOUT) {
+			rte_bbdev_log(ERR, "HARQ Buffer not ready %d",
+					harq_buf_ready);
+			harq_buf_ready = 1;
+		}
+	}
+	uint32_t harq_buf_size = fpga_reg_read_32(d->mmio_base,
+			FPGA_5GNR_FEC_HARQ_BUF_SIZE_REGS);
+
+	static struct rte_bbdev_queue_conf default_queue_conf;
+	default_queue_conf.socket = dev->data->socket_id;
+	default_queue_conf.queue_size = FPGA_RING_MAX_SIZE;
+
+	dev_info->driver_name = dev->device->driver->name;
+	dev_info->queue_size_lim = FPGA_RING_MAX_SIZE;
+	dev_info->hardware_accelerated = true;
+	dev_info->min_alignment = 64;
+	dev_info->harq_buffer_size = (harq_buf_size >> 10) + 1;
+	dev_info->default_queue_conf = default_queue_conf;
+	dev_info->capabilities = bbdev_capabilities;
+	dev_info->cpu_flag_reqs = NULL;
+
+	/* Calculates number of queues assigned to device */
+	dev_info->max_num_queues = 0;
+	for (q_id = 0; q_id < FPGA_TOTAL_NUM_QUEUES; ++q_id) {
+		uint32_t hw_q_id = fpga_reg_read_32(d->mmio_base,
+				FPGA_5GNR_FEC_QUEUE_MAP + (q_id << 2));
+		if (hw_q_id != FPGA_INVALID_HW_QUEUE_ID)
+			dev_info->max_num_queues++;
+	}
+}
+
+/**
+ * Find index of queue bound to current PF/VF which is unassigned. Return -1
+ * when there is no available queue
+ */
+static int
+fpga_find_free_queue_idx(struct rte_bbdev *dev,
+		const struct rte_bbdev_queue_conf *conf)
+{
+	struct fpga_5gnr_fec_device *d = dev->data->dev_private;
+	uint64_t q_idx;
+	uint8_t i = 0;
+	uint8_t range = FPGA_TOTAL_NUM_QUEUES >> 1;
+
+	if (conf->op_type == RTE_BBDEV_OP_LDPC_ENC) {
+		i = FPGA_NUM_DL_QUEUES;
+		range = FPGA_TOTAL_NUM_QUEUES;
+	}
+
+	for (; i < range; ++i) {
+		q_idx = 1ULL << i;
+		/* Check if index of queue is bound to current PF/VF */
+		if (d->q_bound_bit_map & q_idx)
+			/* Check if found queue was not already assigned */
+			if (!(d->q_assigned_bit_map & q_idx)) {
+				d->q_assigned_bit_map |= q_idx;
+				return i;
+			}
+	}
+
+	rte_bbdev_log(INFO, "Failed to find free queue on %s", dev->data->name);
+
+	return -1;
+}
+
+static int
+fpga_queue_setup(struct rte_bbdev *dev, uint16_t queue_id,
+		const struct rte_bbdev_queue_conf *conf)
+{
+	uint32_t address, ring_offset;
+	struct fpga_5gnr_fec_device *d = dev->data->dev_private;
+	struct fpga_queue *q;
+	int8_t q_idx;
+
+	/* Check if there is a free queue to assign */
+	q_idx = fpga_find_free_queue_idx(dev, conf);
+	if (q_idx == -1)
+		return -1;
+
+	/* Allocate the queue data structure. */
+	q = rte_zmalloc_socket(dev->device->driver->name, sizeof(*q),
+			RTE_CACHE_LINE_SIZE, conf->socket);
+	if (q == NULL) {
+		/* Mark queue as un-assigned */
+		d->q_assigned_bit_map &= (0xFFFFFFFF - (1ULL << q_idx));
+		rte_bbdev_log(ERR, "Failed to allocate queue memory");
+		return -ENOMEM;
+	}
+
+	q->d = d;
+	q->q_idx = q_idx;
+
+	/* Set ring_base_addr */
+	q->ring_addr = RTE_PTR_ADD(d->sw_rings, (d->sw_ring_size * queue_id));
+	q->ring_ctrl_reg.ring_base_addr = d->sw_rings_phys +
+			(d->sw_ring_size * queue_id);
+
+	/* Allocate memory for Completion Head variable*/
+	q->ring_head_addr = rte_zmalloc_socket(dev->device->driver->name,
+			sizeof(uint64_t), RTE_CACHE_LINE_SIZE, conf->socket);
+	if (q->ring_head_addr == NULL) {
+		/* Mark queue as un-assigned */
+		d->q_assigned_bit_map &= (0xFFFFFFFF - (1ULL << q_idx));
+		rte_free(q);
+		rte_bbdev_log(ERR,
+				"Failed to allocate memory for %s:%u completion_head",
+				dev->device->driver->name, dev->data->dev_id);
+		return -ENOMEM;
+	}
+	/* Set ring_head_addr */
+	q->ring_ctrl_reg.ring_head_addr =
+			rte_malloc_virt2iova(q->ring_head_addr);
+
+	/* Clear shadow_completion_head */
+	q->shadow_completion_head = 0;
+
+	/* Set ring_size */
+	if (conf->queue_size > FPGA_RING_MAX_SIZE) {
+		/* Mark queue as un-assigned */
+		d->q_assigned_bit_map &= (0xFFFFFFFF - (1ULL << q_idx));
+		rte_free(q->ring_head_addr);
+		rte_free(q);
+		rte_bbdev_log(ERR,
+				"Size of queue is too big %d (MAX: %d ) for %s:%u",
+				conf->queue_size, FPGA_RING_MAX_SIZE,
+				dev->device->driver->name, dev->data->dev_id);
+		return -EINVAL;
+	}
+	q->ring_ctrl_reg.ring_size = conf->queue_size;
+
+	/* Set Miscellaneous FPGA register*/
+	/* Max iteration number for TTI mitigation - todo */
+	q->ring_ctrl_reg.max_ul_dec = 0;
+	/* Enable max iteration number for TTI - todo */
+	q->ring_ctrl_reg.max_ul_dec_en = 0;
+
+	/* Enable the ring */
+	q->ring_ctrl_reg.enable = 1;
+
+	/* Set FPGA head_point and tail registers */
+	q->ring_ctrl_reg.head_point = q->tail = 0;
+
+	/* Set FPGA shadow_tail register */
+	q->ring_ctrl_reg.shadow_tail = q->tail;
+
+	/* Calculates the ring offset for found queue */
+	ring_offset = FPGA_5GNR_FEC_RING_CTRL_REGS +
+			(sizeof(struct fpga_ring_ctrl_reg) * q_idx);
+
+	/* Set FPGA Ring Control Registers */
+	fpga_ring_reg_write(d->mmio_base, ring_offset, q->ring_ctrl_reg);
+
+	/* Store MMIO register of shadow_tail */
+	address = ring_offset + FPGA_5GNR_FEC_RING_SHADOW_TAIL;
+	q->shadow_tail_addr = RTE_PTR_ADD(d->mmio_base, address);
+
+	q->head_free_desc = q->tail;
+
+	/* Set wrap mask */
+	q->sw_ring_wrap_mask = conf->queue_size - 1;
+
+	rte_bbdev_log_debug("Setup dev%u q%u: queue_idx=%u",
+			dev->data->dev_id, queue_id, q->q_idx);
+
+	dev->data->queues[queue_id].queue_private = q;
+
+	rte_bbdev_log_debug("BBDEV queue[%d] set up for FPGA queue[%d]",
+			queue_id, q_idx);
+
+#ifdef RTE_LIBRTE_BBDEV_DEBUG
+	/* Read FPGA Ring Control Registers after configuration*/
+	print_ring_reg_debug_info(d->mmio_base, ring_offset);
+#endif
+	return 0;
+}
+
+static int
+fpga_queue_release(struct rte_bbdev *dev, uint16_t queue_id)
+{
+	struct fpga_5gnr_fec_device *d = dev->data->dev_private;
+	struct fpga_queue *q = dev->data->queues[queue_id].queue_private;
+	struct fpga_ring_ctrl_reg ring_reg;
+	uint32_t offset;
+
+	rte_bbdev_log_debug("FPGA Queue[%d] released", queue_id);
+
+	if (q != NULL) {
+		memset(&ring_reg, 0, sizeof(struct fpga_ring_ctrl_reg));
+		offset = FPGA_5GNR_FEC_RING_CTRL_REGS +
+			(sizeof(struct fpga_ring_ctrl_reg) * q->q_idx);
+		/* Disable queue */
+		fpga_reg_write_8(d->mmio_base,
+				offset + FPGA_5GNR_FEC_RING_ENABLE, 0x00);
+		/* Clear queue registers */
+		fpga_ring_reg_write(d->mmio_base, offset, ring_reg);
+
+		/* Mark the Queue as un-assigned */
+		d->q_assigned_bit_map &= (0xFFFFFFFF - (1ULL << q->q_idx));
+		rte_free(q->ring_head_addr);
+		rte_free(q);
+		dev->data->queues[queue_id].queue_private = NULL;
+	}
+
+	return 0;
+}
+
+/* Function starts a device queue. */
+static int
+fpga_queue_start(struct rte_bbdev *dev, uint16_t queue_id)
+{
+	struct fpga_5gnr_fec_device *d = dev->data->dev_private;
+#ifdef RTE_LIBRTE_BBDEV_DEBUG
+	if (d == NULL) {
+		rte_bbdev_log(ERR, "Invalid device pointer");
+		return -1;
+	}
+#endif
+	struct fpga_queue *q = dev->data->queues[queue_id].queue_private;
+	uint32_t offset = FPGA_5GNR_FEC_RING_CTRL_REGS +
+			(sizeof(struct fpga_ring_ctrl_reg) * q->q_idx);
+	uint8_t enable = 0x01;
+	uint16_t zero = 0x0000;
+
+	/* Clear queue head and tail variables */
+	q->tail = q->head_free_desc = 0;
+
+	/* Clear FPGA head_point and tail registers */
+	fpga_reg_write_16(d->mmio_base, offset + FPGA_5GNR_FEC_RING_HEAD_POINT,
+			zero);
+	fpga_reg_write_16(d->mmio_base, offset + FPGA_5GNR_FEC_RING_SHADOW_TAIL,
+			zero);
+
+	/* Enable queue */
+	fpga_reg_write_8(d->mmio_base, offset + FPGA_5GNR_FEC_RING_ENABLE,
+			enable);
+
+	rte_bbdev_log_debug("FPGA Queue[%d] started", queue_id);
+	return 0;
+}
+
+/* Function stops a device queue. */
+static int
+fpga_queue_stop(struct rte_bbdev *dev, uint16_t queue_id)
+{
+	struct fpga_5gnr_fec_device *d = dev->data->dev_private;
+#ifdef RTE_LIBRTE_BBDEV_DEBUG
+	if (d == NULL) {
+		rte_bbdev_log(ERR, "Invalid device pointer");
+		return -1;
+	}
+#endif
+	struct fpga_queue *q = dev->data->queues[queue_id].queue_private;
+	uint32_t offset = FPGA_5GNR_FEC_RING_CTRL_REGS +
+			(sizeof(struct fpga_ring_ctrl_reg) * q->q_idx);
+	uint8_t payload = 0x01;
+	uint8_t counter = 0;
+	uint8_t timeout = FPGA_QUEUE_FLUSH_TIMEOUT_US /
+			FPGA_TIMEOUT_CHECK_INTERVAL;
+
+	/* Set flush_queue_en bit to trigger queue flushing */
+	fpga_reg_write_8(d->mmio_base,
+			offset + FPGA_5GNR_FEC_RING_FLUSH_QUEUE_EN, payload);
+
+	/** Check if queue flush is completed.
+	 * FPGA will update the completion flag after queue flushing is
+	 * completed. If completion flag is not updated within 1ms it is
+	 * considered as a failure.
+	 */
+	while (!(*((volatile uint8_t *)d->flush_queue_status + q->q_idx)
+			& payload)) {
+		if (counter > timeout) {
+			rte_bbdev_log(ERR, "FPGA Queue Flush failed for queue %d",
+					queue_id);
+			return -1;
+		}
+		usleep(FPGA_TIMEOUT_CHECK_INTERVAL);
+		counter++;
+	}
+
+	/* Disable queue */
+	payload = 0x00;
+	fpga_reg_write_8(d->mmio_base, offset + FPGA_5GNR_FEC_RING_ENABLE,
+			payload);
+
+	rte_bbdev_log_debug("FPGA Queue[%d] stopped", queue_id);
+	return 0;
+}
+
+static inline uint16_t
+get_queue_id(struct rte_bbdev_data *data, uint8_t q_idx)
+{
+	uint16_t queue_id;
+
+	for (queue_id = 0; queue_id < data->num_queues; ++queue_id) {
+		struct fpga_queue *q = data->queues[queue_id].queue_private;
+		if (q != NULL && q->q_idx == q_idx)
+			return queue_id;
+	}
+
+	return -1;
+}
+
+/* Interrupt handler triggered by FPGA dev for handling specific interrupt */
+static void
+fpga_dev_interrupt_handler(void *cb_arg)
+{
+	struct rte_bbdev *dev = cb_arg;
+	struct fpga_5gnr_fec_device *fpga_dev = dev->data->dev_private;
+	struct fpga_queue *q;
+	uint64_t ring_head;
+	uint64_t q_idx;
+	uint16_t queue_id;
+	uint8_t i;
+
+	/* Scan queue assigned to this device */
+	for (i = 0; i < FPGA_TOTAL_NUM_QUEUES; ++i) {
+		q_idx = 1ULL << i;
+		if (fpga_dev->q_bound_bit_map & q_idx) {
+			queue_id = get_queue_id(dev->data, i);
+			if (queue_id == (uint16_t) -1)
+				continue;
+
+			/* Check if completion head was changed */
+			q = dev->data->queues[queue_id].queue_private;
+			ring_head = *q->ring_head_addr;
+			if (q->shadow_completion_head != ring_head &&
+				q->irq_enable == 1) {
+				q->shadow_completion_head = ring_head;
+				rte_bbdev_pmd_callback_process(
+						dev,
+						RTE_BBDEV_EVENT_DEQUEUE,
+						&queue_id);
+			}
+		}
+	}
+}
+
+static int
+fpga_queue_intr_enable(struct rte_bbdev *dev, uint16_t queue_id)
+{
+	struct fpga_queue *q = dev->data->queues[queue_id].queue_private;
+
+	if (!rte_intr_cap_multiple(dev->intr_handle))
+		return -ENOTSUP;
+
+	q->irq_enable = 1;
+
+	return 0;
+}
+
+static int
+fpga_queue_intr_disable(struct rte_bbdev *dev, uint16_t queue_id)
+{
+	struct fpga_queue *q = dev->data->queues[queue_id].queue_private;
+	q->irq_enable = 0;
+
+	return 0;
+}
+
+static int
+fpga_intr_enable(struct rte_bbdev *dev)
+{
+	int ret;
+	uint8_t i;
+
+	if (!rte_intr_cap_multiple(dev->intr_handle)) {
+		rte_bbdev_log(ERR, "Multiple intr vector is not supported by FPGA (%s)",
+				dev->data->name);
+		return -ENOTSUP;
+	}
+
+	/* Create event file descriptors for each of 64 queue. Event fds will be
+	 * mapped to FPGA IRQs in rte_intr_enable(). This is a 1:1 mapping where
+	 * the IRQ number is a direct translation to the queue number.
+	 *
+	 * 63 (FPGA_NUM_INTR_VEC) event fds are created as rte_intr_enable()
+	 * mapped the first IRQ to already created interrupt event file
+	 * descriptor (intr_handle->fd).
+	 */
+	if (rte_intr_efd_enable(dev->intr_handle, FPGA_NUM_INTR_VEC)) {
+		rte_bbdev_log(ERR, "Failed to create fds for %u queues",
+				dev->data->num_queues);
+		return -1;
+	}
+
+	/* TODO Each event file descriptor is overwritten by interrupt event
+	 * file descriptor. That descriptor is added to epoll observed list.
+	 * It ensures that callback function assigned to that descriptor will
+	 * invoked when any FPGA queue issues interrupt.
+	 */
+	for (i = 0; i < FPGA_NUM_INTR_VEC; ++i)
+		dev->intr_handle->efds[i] = dev->intr_handle->fd;
+
+	if (!dev->intr_handle->intr_vec) {
+		dev->intr_handle->intr_vec = rte_zmalloc("intr_vec",
+				dev->data->num_queues * sizeof(int), 0);
+		if (!dev->intr_handle->intr_vec) {
+			rte_bbdev_log(ERR, "Failed to allocate %u vectors",
+					dev->data->num_queues);
+			return -ENOMEM;
+		}
+	}
+
+	ret = rte_intr_enable(dev->intr_handle);
+	if (ret < 0) {
+		rte_bbdev_log(ERR,
+				"Couldn't enable interrupts for device: %s",
+				dev->data->name);
+		return ret;
+	}
+
+	ret = rte_intr_callback_register(dev->intr_handle,
+			fpga_dev_interrupt_handler, dev);
+	if (ret < 0) {
+		rte_bbdev_log(ERR,
+				"Couldn't register interrupt callback for device: %s",
+				dev->data->name);
+		return ret;
+	}
+
+	return 0;
+}
+
+static const struct rte_bbdev_ops fpga_ops = {
+	.setup_queues = fpga_setup_queues,
+	.intr_enable = fpga_intr_enable,
+	.close = fpga_dev_close,
+	.info_get = fpga_dev_info_get,
+	.queue_setup = fpga_queue_setup,
+	.queue_stop = fpga_queue_stop,
+	.queue_start = fpga_queue_start,
+	.queue_release = fpga_queue_release,
+	.queue_intr_enable = fpga_queue_intr_enable,
+	.queue_intr_disable = fpga_queue_intr_disable
+};
+
+static inline void
+fpga_dma_enqueue(struct fpga_queue *q, uint16_t num_desc,
+		struct rte_bbdev_stats *queue_stats)
+{
+#ifdef RTE_BBDEV_OFFLOAD_COST
+	uint64_t start_time = 0;
+	queue_stats->acc_offload_cycles = 0;
+#else
+	RTE_SET_USED(queue_stats);
+#endif
+
+	/* Update tail and shadow_tail register */
+	q->tail = (q->tail + num_desc) & q->sw_ring_wrap_mask;
+
+	rte_wmb();
+
+#ifdef RTE_BBDEV_OFFLOAD_COST
+	/* Start time measurement for enqueue function offload. */
+	start_time = rte_rdtsc_precise();
+#endif
+	mmio_write_16(q->shadow_tail_addr, q->tail);
+
+#ifdef RTE_BBDEV_OFFLOAD_COST
+	rte_wmb();
+	queue_stats->acc_offload_cycles += rte_rdtsc_precise() - start_time;
+#endif
+}
+
+/* Read flag value 0/1/ from bitmap */
+static inline bool
+check_bit(uint32_t bitmap, uint32_t bitmask)
+{
+	return bitmap & bitmask;
+}
+
+/* Print an error if a descriptor error has occurred.
+ *  Return 0 on success, 1 on failure
+ */
+static inline int
+check_desc_error(uint32_t error_code) {
+	switch (error_code) {
+	case DESC_ERR_NO_ERR:
+		return 0;
+	case DESC_ERR_K_P_OUT_OF_RANGE:
+		rte_bbdev_log(ERR, "Encode block size K' is out of range");
+		break;
+	case DESC_ERR_Z_C_NOT_LEGAL:
+		rte_bbdev_log(ERR, "Zc is illegal");
+		break;
+	case DESC_ERR_DESC_OFFSET_ERR:
+		rte_bbdev_log(ERR,
+				"Queue offset does not meet the expectation in the FPGA"
+				);
+		break;
+	case DESC_ERR_DESC_READ_FAIL:
+		rte_bbdev_log(ERR, "Unsuccessful completion for descriptor read");
+		break;
+	case DESC_ERR_DESC_READ_TIMEOUT:
+		rte_bbdev_log(ERR, "Descriptor read time-out");
+		break;
+	case DESC_ERR_DESC_READ_TLP_POISONED:
+		rte_bbdev_log(ERR, "Descriptor read TLP poisoned");
+		break;
+	case DESC_ERR_CB_READ_FAIL:
+		rte_bbdev_log(ERR, "Unsuccessful completion for code block");
+		break;
+	case DESC_ERR_CB_READ_TIMEOUT:
+		rte_bbdev_log(ERR, "Code block read time-out");
+		break;
+	case DESC_ERR_CB_READ_TLP_POISONED:
+		rte_bbdev_log(ERR, "Code block read TLP poisoned");
+		break;
+	case DESC_ERR_HBSTORE_ERR:
+		rte_bbdev_log(ERR, "Hbstroe exceeds HARQ buffer size.");
+		break;
+	default:
+		rte_bbdev_log(ERR, "Descriptor error unknown error code %u",
+				error_code);
+		break;
+	}
+	return 1;
+}
+
+/* Compute value of k0.
+ * Based on 3GPP 38.212 Table 5.4.2.1-2
+ * Starting position of different redundancy versions, k0
+ */
+static inline uint16_t
+get_k0(uint16_t n_cb, uint16_t z_c, uint8_t basegraph, uint8_t rv_index)
+{
+	if (rv_index == 0)
+		return 0;
+	uint16_t n = (basegraph == 1 ? 66 : 50) * z_c;
+	if (n_cb == n) {
+		if (rv_index == 1)
+			return (basegraph == 1 ? 17 : 13) * z_c;
+		else if (rv_index == 2)
+			return (basegraph == 1 ? 33 : 25) * z_c;
+		else
+			return (basegraph == 1 ? 56 : 43) * z_c;
+	} else {
+		/* LBRM case - includes a division by N */
+		if (rv_index == 1)
+			return (((basegraph == 1 ? 17 : 13) * n_cb)
+					/ n) * z_c;
+		else if (rv_index == 2)
+			return (((basegraph == 1 ? 33 : 25) * n_cb)
+					/ n) * z_c;
+		else
+			return (((basegraph == 1 ? 56 : 43) * n_cb)
+					/ n) * z_c;
+	}
+}
+
+
+/**
+ * Set DMA descriptor for encode operation (1 Code Block)
+ *
+ * @param op
+ *   Pointer to a single encode operation.
+ * @param desc
+ *   Pointer to DMA descriptor.
+ * @param input
+ *   Pointer to pointer to input data which will be decoded.
+ * @param e
+ *   E value (length of output in bits).
+ * @param ncb
+ *   Ncb value (size of the soft buffer).
+ * @param out_length
+ *   Length of output buffer
+ * @param in_offset
+ *   Input offset in rte_mbuf structure. It is used for calculating the point
+ *   where data is starting.
+ * @param out_offset
+ *   Output offset in rte_mbuf structure. It is used for calculating the point
+ *   where hard output data will be stored.
+ * @param cbs_in_op
+ *   Number of CBs contained in one operation.
+ */
+static inline int
+fpga_dma_desc_te_fill(struct rte_bbdev_enc_op *op,
+		struct fpga_dma_enc_desc *desc, struct rte_mbuf *input,
+		struct rte_mbuf *output, uint16_t k_,  uint16_t e,
+		uint32_t in_offset, uint32_t out_offset, uint16_t desc_offset,
+		uint8_t cbs_in_op)
+{
+	/* reset */
+	desc->done = 0;
+	desc->error = 0;
+	desc->k_ = k_;
+	desc->rm_e = e;
+	desc->desc_idx = desc_offset;
+	desc->zc = op->ldpc_enc.z_c;
+	desc->bg_idx = op->ldpc_enc.basegraph - 1;
+	desc->qm_idx = op->ldpc_enc.q_m / 2;
+	desc->crc_en = check_bit(op->ldpc_enc.op_flags,
+			RTE_BBDEV_LDPC_CRC_24B_ATTACH);
+	desc->irq_en = 0;
+	desc->k0 = get_k0(op->ldpc_enc.n_cb, op->ldpc_enc.z_c,
+			op->ldpc_enc.basegraph, op->ldpc_enc.rv_index);
+	desc->ncb = op->ldpc_enc.n_cb;
+	desc->num_null = op->ldpc_enc.n_filler;
+	/* Set inbound data buffer address */
+	desc->in_addr_hi = (uint32_t)(
+			rte_pktmbuf_mtophys_offset(input, in_offset) >> 32);
+	desc->in_addr_lw = (uint32_t)(
+			rte_pktmbuf_mtophys_offset(input, in_offset));
+
+	desc->out_addr_hi = (uint32_t)(
+			rte_pktmbuf_mtophys_offset(output, out_offset) >> 32);
+	desc->out_addr_lw = (uint32_t)(
+			rte_pktmbuf_mtophys_offset(output, out_offset));
+	/* Save software context needed for dequeue */
+	desc->op_addr = op;
+	/* Set total number of CBs in an op */
+	desc->cbs_in_op = cbs_in_op;
+	return 0;
+}
+
+/**
+ * Set DMA descriptor for decode operation (1 Code Block)
+ *
+ * @param op
+ *   Pointer to a single encode operation.
+ * @param desc
+ *   Pointer to DMA descriptor.
+ * @param input
+ *   Pointer to pointer to input data which will be decoded.
+ * @param in_offset
+ *   Input offset in rte_mbuf structure. It is used for calculating the point
+ *   where data is starting.
+ * @param out_offset
+ *   Output offset in rte_mbuf structure. It is used for calculating the point
+ *   where hard output data will be stored.
+ * @param cbs_in_op
+ *   Number of CBs contained in one operation.
+ */
+static inline int
+fpga_dma_desc_ld_fill(struct rte_bbdev_dec_op *op,
+		struct fpga_dma_dec_desc *desc,
+		struct rte_mbuf *input,	struct rte_mbuf *output,
+		uint16_t harq_in_length,
+		uint32_t in_offset, uint32_t out_offset,
+		uint32_t harq_offset,
+		uint16_t desc_offset,
+		uint8_t cbs_in_op)
+{
+	/* reset */
+	desc->done = 0;
+	desc->error = 0;
+	/* Set inbound data buffer address */
+	desc->in_addr_hi = (uint32_t)(
+			rte_pktmbuf_mtophys_offset(input, in_offset) >> 32);
+	desc->in_addr_lw = (uint32_t)(
+			rte_pktmbuf_mtophys_offset(input, in_offset));
+	desc->rm_e = op->ldpc_dec.cb_params.e;
+	desc->harq_input_length = harq_in_length;
+	desc->et_dis = !check_bit(op->ldpc_dec.op_flags,
+			RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE);
+	desc->rv = op->ldpc_dec.rv_index;
+	desc->crc24b_ind = check_bit(op->ldpc_dec.op_flags,
+			RTE_BBDEV_LDPC_CRC_TYPE_24B_CHECK);
+	desc->drop_crc24b = check_bit(op->ldpc_dec.op_flags,
+			RTE_BBDEV_LDPC_CRC_TYPE_24B_DROP);
+	desc->desc_idx = desc_offset;
+	desc->ncb = op->ldpc_dec.n_cb;
+	desc->num_null = op->ldpc_dec.n_filler;
+	desc->hbstroe_offset = harq_offset >> 10;
+	desc->zc = op->ldpc_dec.z_c;
+	desc->harqin_en = check_bit(op->ldpc_dec.op_flags,
+			RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE);
+	desc->bg_idx = op->ldpc_dec.basegraph - 1;
+	desc->max_iter = op->ldpc_dec.iter_max;
+	desc->qm_idx = op->ldpc_dec.q_m / 2;
+	desc->out_addr_hi = (uint32_t)(
+			rte_pktmbuf_mtophys_offset(output, out_offset) >> 32);
+	desc->out_addr_lw = (uint32_t)(
+			rte_pktmbuf_mtophys_offset(output, out_offset));
+	/* Save software context needed for dequeue */
+	desc->op_addr = op;
+	/* Set total number of CBs in an op */
+	desc->cbs_in_op = cbs_in_op;
+
+	return 0;
+}
+
+#ifdef RTE_LIBRTE_BBDEV_DEBUG
+/* Validates LDPC encoder parameters */
+static int
+validate_enc_op(struct rte_bbdev_enc_op *op __rte_unused)
+{
+	struct rte_bbdev_op_ldpc_enc *ldpc_enc = &op->ldpc_enc;
+	struct rte_bbdev_op_enc_ldpc_cb_params *cb = NULL;
+	struct rte_bbdev_op_enc_ldpc_tb_params *tb = NULL;
+
+
+	if (ldpc_enc->input.length >
+			RTE_BBDEV_LDPC_MAX_CB_SIZE >> 3) {
+		rte_bbdev_log(ERR, "CB size (%u) is too big, max: %d",
+				ldpc_enc->input.length,
+				RTE_BBDEV_LDPC_MAX_CB_SIZE);
+		return -1;
+	}
+
+	if (op->mempool == NULL) {
+		rte_bbdev_log(ERR, "Invalid mempool pointer");
+		return -1;
+	}
+	if (ldpc_enc->input.data == NULL) {
+		rte_bbdev_log(ERR, "Invalid input pointer");
+		return -1;
+	}
+	if (ldpc_enc->output.data == NULL) {
+		rte_bbdev_log(ERR, "Invalid output pointer");
+		return -1;
+	}
+	if ((ldpc_enc->basegraph > 2) || (ldpc_enc->basegraph == 0)) {
+		rte_bbdev_log(ERR,
+				"basegraph (%u) is out of range 1 <= value <= 2",
+				ldpc_enc->basegraph);
+		return -1;
+	}
+	if (ldpc_enc->code_block_mode > 1) {
+		rte_bbdev_log(ERR,
+				"code_block_mode (%u) is out of range 0:Tb 1:CB",
+				ldpc_enc->code_block_mode);
+		return -1;
+	}
+
+	if (ldpc_enc->code_block_mode == 0) {
+		tb = &ldpc_enc->tb_params;
+		if (tb->c == 0) {
+			rte_bbdev_log(ERR,
+					"c (%u) is out of range 1 <= value <= %u",
+					tb->c, RTE_BBDEV_LDPC_MAX_CODE_BLOCKS);
+			return -1;
+		}
+		if (tb->cab > tb->c) {
+			rte_bbdev_log(ERR,
+					"cab (%u) is greater than c (%u)",
+					tb->cab, tb->c);
+			return -1;
+		}
+		if ((tb->ea < RTE_BBDEV_LDPC_MIN_CB_SIZE)
+				&& tb->r < tb->cab) {
+			rte_bbdev_log(ERR,
+					"ea (%u) is less than %u or it is not even",
+					tb->ea, RTE_BBDEV_LDPC_MIN_CB_SIZE);
+			return -1;
+		}
+		if ((tb->eb < RTE_BBDEV_LDPC_MIN_CB_SIZE)
+				&& tb->c > tb->cab) {
+			rte_bbdev_log(ERR,
+					"eb (%u) is less than %u",
+					tb->eb, RTE_BBDEV_LDPC_MIN_CB_SIZE);
+			return -1;
+		}
+		if (tb->r > (tb->c - 1)) {
+			rte_bbdev_log(ERR,
+					"r (%u) is greater than c - 1 (%u)",
+					tb->r, tb->c - 1);
+			return -1;
+		}
+	} else {
+		cb = &ldpc_enc->cb_params;
+		if (cb->e < RTE_BBDEV_LDPC_MIN_CB_SIZE) {
+			rte_bbdev_log(ERR,
+					"e (%u) is less than %u or it is not even",
+					cb->e, RTE_BBDEV_LDPC_MIN_CB_SIZE);
+			return -1;
+		}
+	}
+	return 0;
+}
+#endif
+
+static inline char *
+mbuf_append(struct rte_mbuf *m_head, struct rte_mbuf *m, uint16_t len)
+{
+	if (unlikely(len > rte_pktmbuf_tailroom(m)))
+		return NULL;
+
+	char *tail = (char *)m->buf_addr + m->data_off + m->data_len;
+	m->data_len = (uint16_t)(m->data_len + len);
+	m_head->pkt_len  = (m_head->pkt_len + len);
+	return tail;
+}
+
+#ifdef RTE_LIBRTE_BBDEV_DEBUG
+/* Validates LDPC decoder parameters */
+static int
+validate_dec_op(struct rte_bbdev_dec_op *op __rte_unused)
+{
+	struct rte_bbdev_op_ldpc_dec *ldpc_dec = &op->ldpc_dec;
+	struct rte_bbdev_op_dec_ldpc_cb_params *cb = NULL;
+	struct rte_bbdev_op_dec_ldpc_tb_params *tb = NULL;
+
+	if (op->mempool == NULL) {
+		rte_bbdev_log(ERR, "Invalid mempool pointer");
+		return -1;
+	}
+	if (ldpc_dec->rv_index > 3) {
+		rte_bbdev_log(ERR,
+				"rv_index (%u) is out of range 0 <= value <= 3",
+				ldpc_dec->rv_index);
+		return -1;
+	}
+
+	if (ldpc_dec->iter_max == 0) {
+		rte_bbdev_log(ERR,
+				"iter_max (%u) is equal to 0",
+				ldpc_dec->iter_max);
+		return -1;
+	}
+
+	if (ldpc_dec->code_block_mode > 1) {
+		rte_bbdev_log(ERR,
+				"code_block_mode (%u) is out of range 0 <= value <= 1",
+				ldpc_dec->code_block_mode);
+		return -1;
+	}
+
+	if (ldpc_dec->code_block_mode == 0) {
+		tb = &ldpc_dec->tb_params;
+		if (tb->c < 1) {
+			rte_bbdev_log(ERR,
+					"c (%u) is out of range 1 <= value <= %u",
+					tb->c, RTE_BBDEV_LDPC_MAX_CODE_BLOCKS);
+			return -1;
+		}
+		if (tb->cab > tb->c) {
+			rte_bbdev_log(ERR,
+					"cab (%u) is greater than c (%u)",
+					tb->cab, tb->c);
+			return -1;
+		}
+	} else {
+		cb = &ldpc_dec->cb_params;
+		if (cb->e < RTE_BBDEV_LDPC_MIN_CB_SIZE) {
+			rte_bbdev_log(ERR,
+					"e (%u) is out of range %u <= value <= %u",
+					cb->e, RTE_BBDEV_LDPC_MIN_CB_SIZE,
+					RTE_BBDEV_LDPC_MAX_CB_SIZE);
+			return -1;
+		}
+	}
+
+	return 0;
+}
+#endif
+
+static inline int
+fpga_harq_write_loopback(struct fpga_5gnr_fec_device *fpga_dev,
+		struct rte_mbuf *harq_input, uint16_t harq_in_length,
+		uint32_t harq_in_offset, uint32_t harq_out_offset)
+{
+	uint32_t out_offset = harq_out_offset;
+	uint32_t in_offset = harq_in_offset;
+	uint32_t left_length = harq_in_length;
+	uint32_t reg_32, increment = 0;
+	uint64_t *input = NULL;
+	uint32_t last_transaction = left_length
+			% FPGA_5GNR_FEC_DDR_WR_DATA_LEN_IN_BYTES;
+	uint64_t last_word;
+
+	if (last_transaction > 0)
+		left_length -= last_transaction;
+
+	/*
+	 * Get HARQ buffer size for each VF/PF: When 0x00, there is no
+	 * available DDR space for the corresponding VF/PF.
+	 */
+	reg_32 = fpga_reg_read_32(fpga_dev->mmio_base,
+			FPGA_5GNR_FEC_HARQ_BUF_SIZE_REGS);
+	if (reg_32 < harq_in_length) {
+		left_length = reg_32;
+		rte_bbdev_log(ERR, "HARQ in length > HARQ buffer size\n");
+	}
+
+	input = (uint64_t *)rte_pktmbuf_mtod_offset(harq_input,
+			uint8_t *, in_offset);
+
+	while (left_length > 0) {
+		if (fpga_reg_read_8(fpga_dev->mmio_base,
+				FPGA_5GNR_FEC_DDR4_ADDR_RDY_REGS) ==  1) {
+			fpga_reg_write_32(fpga_dev->mmio_base,
+					FPGA_5GNR_FEC_DDR4_WR_ADDR_REGS,
+					out_offset);
+			fpga_reg_write_64(fpga_dev->mmio_base,
+					FPGA_5GNR_FEC_DDR4_WR_DATA_REGS,
+					input[increment]);
+			left_length -= FPGA_5GNR_FEC_DDR_WR_DATA_LEN_IN_BYTES;
+			out_offset += FPGA_5GNR_FEC_DDR_WR_DATA_LEN_IN_BYTES;
+			increment++;
+			fpga_reg_write_8(fpga_dev->mmio_base,
+					FPGA_5GNR_FEC_DDR4_WR_DONE_REGS, 1);
+		}
+	}
+	while (last_transaction > 0) {
+		if (fpga_reg_read_8(fpga_dev->mmio_base,
+				FPGA_5GNR_FEC_DDR4_ADDR_RDY_REGS) ==  1) {
+			fpga_reg_write_32(fpga_dev->mmio_base,
+					FPGA_5GNR_FEC_DDR4_WR_ADDR_REGS,
+					out_offset);
+			last_word = input[increment];
+			last_word &= (uint64_t)(1 << (last_transaction * 4))
+					- 1;
+			fpga_reg_write_64(fpga_dev->mmio_base,
+					FPGA_5GNR_FEC_DDR4_WR_DATA_REGS,
+					last_word);
+			fpga_reg_write_8(fpga_dev->mmio_base,
+					FPGA_5GNR_FEC_DDR4_WR_DONE_REGS, 1);
+			last_transaction = 0;
+		}
+	}
+	return 1;
+}
+
+static inline int
+fpga_harq_read_loopback(struct fpga_5gnr_fec_device *fpga_dev,
+		struct rte_mbuf *harq_output, uint16_t harq_in_length,
+		uint32_t harq_in_offset, uint32_t harq_out_offset)
+{
+	uint32_t left_length, in_offset = harq_in_offset;
+	uint64_t reg;
+	uint32_t increment = 0;
+	uint64_t *input = NULL;
+	uint32_t last_transaction = harq_in_length
+			% FPGA_5GNR_FEC_DDR_WR_DATA_LEN_IN_BYTES;
+
+	if (last_transaction > 0)
+		harq_in_length += (8 - last_transaction);
+
+	reg = fpga_reg_read_32(fpga_dev->mmio_base,
+			FPGA_5GNR_FEC_HARQ_BUF_SIZE_REGS);
+	if (reg < harq_in_length) {
+		harq_in_length = reg;
+		rte_bbdev_log(ERR, "HARQ in length > HARQ buffer size\n");
+	}
+
+	if (!mbuf_append(harq_output, harq_output, harq_in_length)) {
+		rte_bbdev_log(ERR, "HARQ output buffer warning %d %d\n",
+				harq_output->buf_len -
+				rte_pktmbuf_headroom(harq_output),
+				harq_in_length);
+		harq_in_length = harq_output->buf_len -
+				rte_pktmbuf_headroom(harq_output);
+		if (!mbuf_append(harq_output, harq_output, harq_in_length)) {
+			rte_bbdev_log(ERR, "HARQ output buffer issue %d %d\n",
+					harq_output->buf_len, harq_in_length);
+			return -1;
+		}
+	}
+	left_length = harq_in_length;
+
+	input = (uint64_t *)rte_pktmbuf_mtod_offset(harq_output,
+			uint8_t *, harq_out_offset);
+
+	while (left_length > 0) {
+		fpga_reg_write_32(fpga_dev->mmio_base,
+			FPGA_5GNR_FEC_DDR4_RD_ADDR_REGS, in_offset);
+		fpga_reg_write_8(fpga_dev->mmio_base,
+				FPGA_5GNR_FEC_DDR4_RD_DONE_REGS, 1);
+		reg = fpga_reg_read_8(fpga_dev->mmio_base,
+			FPGA_5GNR_FEC_DDR4_RD_RDY_REGS);
+		while (reg != 1) {
+			reg = fpga_reg_read_8(fpga_dev->mmio_base,
+				FPGA_5GNR_FEC_DDR4_RD_RDY_REGS);
+			if (reg == FPGA_DDR_OVERFLOW) {
+				rte_bbdev_log(ERR,
+						"Read address is overflow!\n");
+				return -1;
+			}
+		}
+		input[increment] = fpga_reg_read_64(fpga_dev->mmio_base,
+			FPGA_5GNR_FEC_DDR4_RD_DATA_REGS);
+		left_length -= FPGA_5GNR_FEC_DDR_RD_DATA_LEN_IN_BYTES;
+		in_offset += FPGA_5GNR_FEC_DDR_WR_DATA_LEN_IN_BYTES;
+		increment++;
+		fpga_reg_write_8(fpga_dev->mmio_base,
+				FPGA_5GNR_FEC_DDR4_RD_DONE_REGS, 0);
+	}
+	return 1;
+}
+
+static inline int
+enqueue_ldpc_enc_one_op_cb(struct fpga_queue *q, struct rte_bbdev_enc_op *op,
+		uint16_t desc_offset)
+{
+	union fpga_dma_desc *desc;
+	int ret;
+	uint8_t c, crc24_bits = 0;
+	struct rte_bbdev_op_ldpc_enc *enc = &op->ldpc_enc;
+	uint16_t in_offset = enc->input.offset;
+	uint16_t out_offset = enc->output.offset;
+	struct rte_mbuf *m_in = enc->input.data;
+	struct rte_mbuf *m_out = enc->output.data;
+	struct rte_mbuf *m_out_head = enc->output.data;
+	uint32_t in_length, out_length, e;
+	uint16_t total_left = enc->input.length;
+	uint16_t ring_offset;
+	uint16_t K, k_;
+
+#ifdef RTE_LIBRTE_BBDEV_DEBUG
+	/* Validate op structure */
+	/* FIXME */
+	if (validate_enc_op(op) == -1) {
+		rte_bbdev_log(ERR, "LDPC encoder validation failed");
+		return -EINVAL;
+	}
+#endif
+
+	/* Clear op status */
+	op->status = 0;
+
+	if (m_in == NULL || m_out == NULL) {
+		rte_bbdev_log(ERR, "Invalid mbuf pointer");
+		op->status = 1 << RTE_BBDEV_DATA_ERROR;
+		return -EINVAL;
+	}
+
+	if (enc->op_flags & RTE_BBDEV_LDPC_CRC_24B_ATTACH)
+		crc24_bits = 24;
+
+	if (enc->code_block_mode == 0) {
+		/* For Transport Block mode */
+		/* FIXME */
+		c = enc->tb_params.c;
+		e = enc->tb_params.ea;
+	} else { /* For Code Block mode */
+		c = 1;
+		e = enc->cb_params.e;
+	}
+
+	/* Update total_left */
+	K = (enc->basegraph == 1 ? 22 : 10) * enc->z_c;
+	k_ = K - enc->n_filler;
+	in_length = (k_ - crc24_bits) >> 3;
+	out_length = (e + 7) >> 3;
+
+	total_left = rte_pktmbuf_data_len(m_in) - in_offset;
+
+	/* Update offsets */
+	if (total_left != in_length) {
+		op->status |= 1 << RTE_BBDEV_DATA_ERROR;
+		rte_bbdev_log(ERR,
+				"Mismatch between mbuf length and included CBs sizes %d",
+				total_left);
+	}
+
+	mbuf_append(m_out_head, m_out, out_length);
+
+	/* Offset into the ring */
+	ring_offset = ((q->tail + desc_offset) & q->sw_ring_wrap_mask);
+	/* Setup DMA Descriptor */
+	desc = q->ring_addr + ring_offset;
+
+	ret = fpga_dma_desc_te_fill(op, &desc->enc_req, m_in, m_out,
+			k_, e, in_offset, out_offset, ring_offset, c);
+	if (unlikely(ret < 0))
+		return ret;
+
+	/* Update lengths */
+	total_left -= in_length;
+	op->ldpc_enc.output.length += out_length;
+
+	if (total_left > 0) {
+		rte_bbdev_log(ERR,
+			"Mismatch between mbuf length and included CB sizes: mbuf len %u, cb len %u",
+				total_left, in_length);
+		return -1;
+	}
+
+#ifdef RTE_LIBRTE_BBDEV_DEBUG
+	print_dma_enc_desc_debug_info(desc);
+#endif
+	return 1;
+}
+
+static inline int
+enqueue_ldpc_dec_one_op_cb(struct fpga_queue *q, struct rte_bbdev_dec_op *op,
+		uint16_t desc_offset)
+{
+	union fpga_dma_desc *desc;
+	int ret;
+	uint16_t ring_offset;
+	uint8_t c;
+	uint16_t e, in_length, out_length, k0, l, seg_total_left, sys_cols;
+	uint16_t K, parity_offset, harq_in_length = 0, harq_out_length = 0;
+	uint16_t crc24_overlap = 0;
+	struct rte_bbdev_op_ldpc_dec *dec = &op->ldpc_dec;
+	struct rte_mbuf *m_in = dec->input.data;
+	struct rte_mbuf *m_out = dec->hard_output.data;
+	struct rte_mbuf *m_out_head = dec->hard_output.data;
+	uint16_t in_offset = dec->input.offset;
+	uint16_t out_offset = dec->hard_output.offset;
+	uint32_t harq_offset = 0;
+
+#ifdef RTE_LIBRTE_BBDEV_DEBUG
+		/* Validate op structure */
+		if (validate_dec_op(op) == -1) {
+			rte_bbdev_log(ERR, "LDPC decoder validation failed");
+			return -EINVAL;
+		}
+#endif
+
+	/* Clear op status */
+	op->status = 0;
+
+	/* Setup DMA Descriptor */
+	ring_offset = ((q->tail + desc_offset) & q->sw_ring_wrap_mask);
+	desc = q->ring_addr + ring_offset;
+
+	if (check_bit(dec->op_flags,
+			RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK)) {
+		struct rte_mbuf *harq_in = dec->harq_combined_input.data;
+		struct rte_mbuf *harq_out = dec->harq_combined_output.data;
+		harq_in_length = dec->harq_combined_input.length;
+		uint32_t harq_in_offset = dec->harq_combined_input.offset;
+		uint32_t harq_out_offset = dec->harq_combined_output.offset;
+
+		if (check_bit(dec->op_flags,
+				RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_OUT_ENABLE
+				)) {
+			ret = fpga_harq_write_loopback(q->d, harq_in,
+					harq_in_length, harq_in_offset,
+					harq_out_offset);
+		} else if (check_bit(dec->op_flags,
+				RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_IN_ENABLE
+				)) {
+			ret = fpga_harq_read_loopback(q->d, harq_out,
+				harq_in_length, harq_in_offset,
+				harq_out_offset);
+			dec->harq_combined_output.length = harq_in_length;
+		} else {
+			rte_bbdev_log(ERR, "OP flag Err!");
+			ret = -1;
+		}
+		/* Set descriptor for dequeue */
+		desc->dec_req.done = 1;
+		desc->dec_req.error = 0;
+		desc->dec_req.op_addr = op;
+		desc->dec_req.cbs_in_op = 1;
+		/* Mark this dummy descriptor to be dropped by HW */
+		desc->dec_req.desc_idx = (ring_offset + 1)
+				& q->sw_ring_wrap_mask;
+		return ret; /* Error or number of CB */
+	}
+
+	if (m_in == NULL || m_out == NULL) {
+		rte_bbdev_log(ERR, "Invalid mbuf pointer");
+		op->status = 1 << RTE_BBDEV_DATA_ERROR;
+		return -1;
+	}
+
+	c = 1;
+	e = dec->cb_params.e;
+
+	if (check_bit(dec->op_flags, RTE_BBDEV_LDPC_CRC_TYPE_24B_DROP))
+		crc24_overlap = 24;
+
+	sys_cols = (dec->basegraph == 1) ? 22 : 10;
+	K = sys_cols * dec->z_c;
+	parity_offset = K - 2 * dec->z_c;
+
+	out_length = ((K - crc24_overlap - dec->n_filler) >> 3);
+	in_length = e;
+	seg_total_left = dec->input.length;
+
+	if (check_bit(dec->op_flags, RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE)) {
+		harq_in_length = RTE_MIN(dec->harq_combined_input.length,
+				(uint32_t)dec->n_cb);
+	}
+
+	if (check_bit(dec->op_flags, RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE)) {
+		k0 = get_k0(dec->n_cb, dec->z_c,
+				dec->basegraph, dec->rv_index);
+		if (k0 > parity_offset)
+			l = k0 + e;
+		else
+			l = k0 + e + dec->n_filler;
+		harq_out_length = RTE_MIN(RTE_MAX(harq_in_length, l),
+				dec->n_cb - dec->n_filler);
+		dec->harq_combined_output.length = harq_out_length;
+	}
+
+	mbuf_append(m_out_head, m_out, out_length);
+	if (check_bit(dec->op_flags, RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE))
+		harq_offset = dec->harq_combined_input.offset;
+	else if (check_bit(dec->op_flags, RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE))
+		harq_offset = dec->harq_combined_output.offset;
+
+	if ((harq_offset & 0x3FF) > 0) {
+		rte_bbdev_log(ERR, "Invalid HARQ offset %d", harq_offset);
+		op->status = 1 << RTE_BBDEV_DATA_ERROR;
+		return -1;
+	}
+
+	ret = fpga_dma_desc_ld_fill(op, &desc->dec_req, m_in, m_out,
+		harq_in_length, in_offset, out_offset, harq_offset,
+		ring_offset, c);
+	if (unlikely(ret < 0))
+		return ret;
+	/* Update lengths */
+	seg_total_left -= in_length;
+	op->ldpc_dec.hard_output.length += out_length;
+	if (seg_total_left > 0) {
+		rte_bbdev_log(ERR,
+				"Mismatch between mbuf length and included CB sizes: mbuf len %u, cb len %u",
+				seg_total_left, in_length);
+		return -1;
+	}
+
+#ifdef RTE_LIBRTE_BBDEV_DEBUG
+	print_dma_dec_desc_debug_info(desc);
+#endif
+
+	return 1;
+}
+
+static uint16_t
+fpga_enqueue_ldpc_enc(struct rte_bbdev_queue_data *q_data,
+		struct rte_bbdev_enc_op **ops, uint16_t num)
+{
+	uint16_t i, total_enqueued_cbs = 0;
+	int32_t avail;
+	int enqueued_cbs;
+	struct fpga_queue *q = q_data->queue_private;
+	union fpga_dma_desc *desc;
+
+	/* Check if queue is not full */
+	if (unlikely(((q->tail + 1) & q->sw_ring_wrap_mask) ==
+			q->head_free_desc))
+		return 0;
+
+	/* Calculates available space */
+	avail = (q->head_free_desc > q->tail) ?
+		q->head_free_desc - q->tail - 1 :
+		q->ring_ctrl_reg.ring_size + q->head_free_desc - q->tail - 1;
+
+	for (i = 0; i < num; ++i) {
+
+		/* Check if there is available space for further
+		 * processing
+		 */
+		if (unlikely(avail - 1 < 0))
+			break;
+		avail -= 1;
+		enqueued_cbs = enqueue_ldpc_enc_one_op_cb(q, ops[i],
+				total_enqueued_cbs);
+
+		if (enqueued_cbs < 0)
+			break;
+
+		total_enqueued_cbs += enqueued_cbs;
+
+		rte_bbdev_log_debug("enqueuing enc ops [%d/%d] | head %d | tail %d",
+				total_enqueued_cbs, num,
+				q->head_free_desc, q->tail);
+	}
+
+	/* Set interrupt bit for last CB in enqueued ops. FPGA issues interrupt
+	 * only when all previous CBs were already processed.
+	 */
+	desc = q->ring_addr + ((q->tail + total_enqueued_cbs - 1)
+			& q->sw_ring_wrap_mask);
+	desc->enc_req.irq_en = q->irq_enable;
+
+	fpga_dma_enqueue(q, total_enqueued_cbs, &q_data->queue_stats);
+
+	/* Update stats */
+	q_data->queue_stats.enqueued_count += i;
+	q_data->queue_stats.enqueue_err_count += num - i;
+
+	return i;
+}
+
+static uint16_t
+fpga_enqueue_ldpc_dec(struct rte_bbdev_queue_data *q_data,
+		struct rte_bbdev_dec_op **ops, uint16_t num)
+{
+	uint16_t i, total_enqueued_cbs = 0;
+	int32_t avail;
+	int enqueued_cbs;
+	struct fpga_queue *q = q_data->queue_private;
+	union fpga_dma_desc *desc;
+
+	/* Check if queue is not full */
+	if (unlikely(((q->tail + 1) & q->sw_ring_wrap_mask) ==
+			q->head_free_desc))
+		return 0;
+
+	/* Calculates available space */
+	avail = (q->head_free_desc > q->tail) ?
+		q->head_free_desc - q->tail - 1 :
+		q->ring_ctrl_reg.ring_size + q->head_free_desc - q->tail - 1;
+
+	for (i = 0; i < num; ++i) {
+
+		/* Check if there is available space for further
+		 * processing
+		 */
+		if (unlikely(avail - 1 < 0))
+			break;
+		avail -= 1;
+		enqueued_cbs = enqueue_ldpc_dec_one_op_cb(q, ops[i],
+				total_enqueued_cbs);
+
+		if (enqueued_cbs < 0)
+			break;
+
+		total_enqueued_cbs += enqueued_cbs;
+
+		rte_bbdev_log_debug("enqueuing dec ops [%d/%d] | head %d | tail %d",
+				total_enqueued_cbs, num,
+				q->head_free_desc, q->tail);
+	}
+
+	/* Update stats */
+	q_data->queue_stats.enqueued_count += i;
+	q_data->queue_stats.enqueue_err_count += num - i;
+
+	/* Set interrupt bit for last CB in enqueued ops. FPGA issues interrupt
+	 * only when all previous CBs were already processed.
+	 */
+	desc = q->ring_addr + ((q->tail + total_enqueued_cbs - 1)
+			& q->sw_ring_wrap_mask);
+	desc->enc_req.irq_en = q->irq_enable;
+	fpga_dma_enqueue(q, total_enqueued_cbs, &q_data->queue_stats);
+	return i;
+}
+
+
+static inline int
+dequeue_ldpc_enc_one_op_cb(struct fpga_queue *q, struct rte_bbdev_enc_op **op,
+		uint16_t desc_offset)
+{
+	union fpga_dma_desc *desc;
+	int desc_error = 0;
+
+	/* Set current desc */
+	desc = q->ring_addr + ((q->head_free_desc + desc_offset)
+			& q->sw_ring_wrap_mask);
+
+	/*check if done */
+	if (desc->enc_req.done == 0)
+		return -1;
+
+	/* make sure the response is read atomically */
+	rte_smp_rmb();
+
+	rte_bbdev_log_debug("DMA response desc %p", desc);
+
+#ifdef RTE_LIBRTE_BBDEV_DEBUG
+	print_dma_enc_desc_debug_info(desc);
+#endif
+
+	*op = desc->enc_req.op_addr;
+	/* Check the descriptor error field, return 1 on error */
+	desc_error = check_desc_error(desc->enc_req.error);
+	(*op)->status = desc_error << RTE_BBDEV_DATA_ERROR;
+
+	return 1;
+}
+
+
+static inline int
+dequeue_ldpc_dec_one_op_cb(struct fpga_queue *q, struct rte_bbdev_dec_op **op,
+		uint16_t desc_offset)
+{
+	union fpga_dma_desc *desc;
+	int desc_error = 0;
+	/* Set descriptor */
+	desc = q->ring_addr + ((q->head_free_desc + desc_offset)
+			& q->sw_ring_wrap_mask);
+
+	/* Verify done bit is set */
+	if (desc->dec_req.done == 0)
+		return -1;
+
+	/* make sure the response is read atomically */
+	rte_smp_rmb();
+
+#ifdef RTE_LIBRTE_BBDEV_DEBUG
+	print_dma_dec_desc_debug_info(desc);
+#endif
+
+	*op = desc->dec_req.op_addr;
+
+	if (check_bit((*op)->ldpc_dec.op_flags,
+			RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK)) {
+		(*op)->status = 0;
+		return 1;
+	}
+
+	/* FPGA reports iterations based on round-up minus 1 */
+	(*op)->ldpc_dec.iter_count = desc->dec_req.iter + 1;
+	/* CRC Check criteria */
+	if (desc->dec_req.crc24b_ind && !(desc->dec_req.crcb_pass))
+		(*op)->status = 1 << RTE_BBDEV_CRC_ERROR;
+	/* et_pass = 0 when decoder fails */
+	(*op)->status |= !(desc->dec_req.et_pass) << RTE_BBDEV_SYNDROME_ERROR;
+	/* Check the descriptor error field, return 1 on error */
+	desc_error = check_desc_error(desc->dec_req.error);
+	(*op)->status |= desc_error << RTE_BBDEV_DATA_ERROR;
+	return 1;
+}
+
+static uint16_t
+fpga_dequeue_ldpc_enc(struct rte_bbdev_queue_data *q_data,
+		struct rte_bbdev_enc_op **ops, uint16_t num)
+{
+	struct fpga_queue *q = q_data->queue_private;
+	uint32_t avail = (q->tail - q->head_free_desc) & q->sw_ring_wrap_mask;
+	uint16_t i;
+	uint16_t dequeued_cbs = 0;
+	int ret;
+
+	for (i = 0; (i < num) && (dequeued_cbs < avail); ++i) {
+		ret = dequeue_ldpc_enc_one_op_cb(q, &ops[i], dequeued_cbs);
+
+		if (ret < 0)
+			break;
+
+		dequeued_cbs += ret;
+
+		rte_bbdev_log_debug("dequeuing enc ops [%d/%d] | head %d | tail %d",
+				dequeued_cbs, num, q->head_free_desc, q->tail);
+	}
+
+	/* Update head */
+	q->head_free_desc = (q->head_free_desc + dequeued_cbs) &
+			q->sw_ring_wrap_mask;
+
+	/* Update stats */
+	q_data->queue_stats.dequeued_count += i;
+
+	return i;
+}
+
+static uint16_t
+fpga_dequeue_ldpc_dec(struct rte_bbdev_queue_data *q_data,
+		struct rte_bbdev_dec_op **ops, uint16_t num)
+{
+	struct fpga_queue *q = q_data->queue_private;
+	uint32_t avail = (q->tail - q->head_free_desc) & q->sw_ring_wrap_mask;
+	uint16_t i;
+	uint16_t dequeued_cbs = 0;
+	int ret;
+
+	for (i = 0; (i < num) && (dequeued_cbs < avail); ++i) {
+		ret = dequeue_ldpc_dec_one_op_cb(q, &ops[i], dequeued_cbs);
+
+		if (ret < 0)
+			break;
+
+		dequeued_cbs += ret;
+
+		rte_bbdev_log_debug("dequeuing dec ops [%d/%d] | head %d | tail %d",
+				dequeued_cbs, num, q->head_free_desc, q->tail);
+	}
+
+	/* Update head */
+	q->head_free_desc = (q->head_free_desc + dequeued_cbs) &
+			q->sw_ring_wrap_mask;
+
+	/* Update stats */
+	q_data->queue_stats.dequeued_count += i;
+
+	return i;
+}
+
+
+/* Initialization Function */
+static void
+fpga_5gnr_fec_init(struct rte_bbdev *dev, struct rte_pci_driver *drv)
+{
+	struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
+
+	dev->dev_ops = &fpga_ops;
+	dev->enqueue_ldpc_enc_ops = fpga_enqueue_ldpc_enc;
+	dev->enqueue_ldpc_dec_ops = fpga_enqueue_ldpc_dec;
+	dev->dequeue_ldpc_enc_ops = fpga_dequeue_ldpc_enc;
+	dev->dequeue_ldpc_dec_ops = fpga_dequeue_ldpc_dec;
+
+	((struct fpga_5gnr_fec_device *) dev->data->dev_private)->pf_device =
+			!strcmp(drv->driver.name,
+					RTE_STR(FPGA_5GNR_FEC_PF_DRIVER_NAME));
+	((struct fpga_5gnr_fec_device *) dev->data->dev_private)->mmio_base =
+			pci_dev->mem_resource[0].addr;
+
+	rte_bbdev_log_debug(
+			"Init device %s [%s] @ virtaddr %p phyaddr %#"PRIx64,
+			dev->device->driver->name, dev->data->name,
+			(void *)pci_dev->mem_resource[0].addr,
+			pci_dev->mem_resource[0].phys_addr);
+}
+
+static int
+fpga_5gnr_fec_probe(struct rte_pci_driver *pci_drv,
+	struct rte_pci_device *pci_dev)
+{
+	struct rte_bbdev *bbdev = NULL;
+	char dev_name[RTE_BBDEV_NAME_MAX_LEN];
+
+	if (pci_dev == NULL) {
+		rte_bbdev_log(ERR, "NULL PCI device");
+		return -EINVAL;
+	}
+
+	rte_pci_device_name(&pci_dev->addr, dev_name, sizeof(dev_name));
+
+	/* Allocate memory to be used privately by drivers */
+	bbdev = rte_bbdev_allocate(pci_dev->device.name);
+	if (bbdev == NULL)
+		return -ENODEV;
+
+	/* allocate device private memory */
+	bbdev->data->dev_private = rte_zmalloc_socket(dev_name,
+			sizeof(struct fpga_5gnr_fec_device),
+			RTE_CACHE_LINE_SIZE,
+			pci_dev->device.numa_node);
+
+	if (bbdev->data->dev_private == NULL) {
+		rte_bbdev_log(CRIT,
+				"Allocate of %zu bytes for device \"%s\" failed",
+				sizeof(struct fpga_5gnr_fec_device), dev_name);
+				rte_bbdev_release(bbdev);
+			return -ENOMEM;
+	}
+
+	/* Fill HW specific part of device structure */
+	bbdev->device = &pci_dev->device;
+	bbdev->intr_handle = &pci_dev->intr_handle;
+	bbdev->data->socket_id = pci_dev->device.numa_node;
+
+	/* Invoke FEC FPGA device initialization function */
+	fpga_5gnr_fec_init(bbdev, pci_drv);
+
+	rte_bbdev_log_debug("bbdev id = %u [%s]",
+			bbdev->data->dev_id, dev_name);
+
+	struct fpga_5gnr_fec_device *d = bbdev->data->dev_private;
+	uint32_t version_id = fpga_reg_read_32(d->mmio_base,
+			FPGA_5GNR_FEC_VERSION_ID);
+	rte_bbdev_log(INFO, "FEC FPGA RTL v%u.%u",
+		((uint16_t)(version_id >> 16)), ((uint16_t)version_id));
+
+#ifdef RTE_LIBRTE_BBDEV_DEBUG
+	if (!strcmp(bbdev->device->driver->name,
+			RTE_STR(FPGA_5GNR_FEC_PF_DRIVER_NAME)))
+		print_static_reg_debug_info(d->mmio_base);
+#endif
+	return 0;
+}
+
+static int
+fpga_5gnr_fec_remove(struct rte_pci_device *pci_dev)
+{
+	struct rte_bbdev *bbdev;
+	int ret;
+	uint8_t dev_id;
+
+	if (pci_dev == NULL)
+		return -EINVAL;
+
+	/* Find device */
+	bbdev = rte_bbdev_get_named_dev(pci_dev->device.name);
+	if (bbdev == NULL) {
+		rte_bbdev_log(CRIT,
+				"Couldn't find HW dev \"%s\" to uninitialise it",
+				pci_dev->device.name);
+		return -ENODEV;
+	}
+	dev_id = bbdev->data->dev_id;
+
+	/* free device private memory before close */
+	rte_free(bbdev->data->dev_private);
+
+	/* Close device */
+	ret = rte_bbdev_close(dev_id);
+	if (ret < 0)
+		rte_bbdev_log(ERR,
+				"Device %i failed to close during uninit: %i",
+				dev_id, ret);
+
+	/* release bbdev from library */
+	ret = rte_bbdev_release(bbdev);
+	if (ret)
+		rte_bbdev_log(ERR, "Device %i failed to uninit: %i", dev_id,
+				ret);
+
+	rte_bbdev_log_debug("Destroyed bbdev = %u", dev_id);
+
+	return 0;
+}
+
+static inline void
+set_default_fpga_conf(struct fpga_5gnr_fec_conf *def_conf)
+{
+	/* clear default configuration before initialization */
+	memset(def_conf, 0, sizeof(struct fpga_5gnr_fec_conf));
+	/* Set pf mode to true */
+	def_conf->pf_mode_en = true;
+
+	/* Set ratio between UL and DL to 1:1 (unit of weight is 3 CBs) */
+	def_conf->ul_bandwidth = 3;
+	def_conf->dl_bandwidth = 3;
+
+	/* Set Load Balance Factor to 64 */
+	def_conf->dl_load_balance = 64;
+	def_conf->ul_load_balance = 64;
+}
+
+/* Initial configuration of FPGA 5GNR FEC device */
+int
+fpga_5gnr_fec_configure(const char *dev_name,
+		const struct fpga_5gnr_fec_conf *conf)
+{
+	uint32_t payload_32, address;
+	uint16_t payload_16;
+	uint8_t payload_8;
+	uint16_t q_id, vf_id, total_q_id, total_ul_q_id, total_dl_q_id;
+	struct rte_bbdev *bbdev = rte_bbdev_get_named_dev(dev_name);
+	struct fpga_5gnr_fec_conf def_conf;
+
+	if (bbdev == NULL) {
+		rte_bbdev_log(ERR,
+				"Invalid dev_name (%s), or device is not yet initialised",
+				dev_name);
+		return -ENODEV;
+	}
+
+	struct fpga_5gnr_fec_device *d = bbdev->data->dev_private;
+
+	if (conf == NULL) {
+		rte_bbdev_log(ERR,
+				"FPGA Configuration was not provided. Default configuration will be loaded.");
+		set_default_fpga_conf(&def_conf);
+		conf = &def_conf;
+	}
+
+	/*
+	 * Configure UL:DL ratio.
+	 * [7:0]: UL weight
+	 * [15:8]: DL weight
+	 */
+	payload_16 = (conf->dl_bandwidth << 8) | conf->ul_bandwidth;
+	address = FPGA_5GNR_FEC_CONFIGURATION;
+	fpga_reg_write_16(d->mmio_base, address, payload_16);
+
+	/* Clear all queues registers */
+	payload_32 = FPGA_INVALID_HW_QUEUE_ID;
+	for (q_id = 0; q_id < FPGA_TOTAL_NUM_QUEUES; ++q_id) {
+		address = (q_id << 2) + FPGA_5GNR_FEC_QUEUE_MAP;
+		fpga_reg_write_32(d->mmio_base, address, payload_32);
+	}
+
+	/*
+	 * If PF mode is enabled allocate all queues for PF only.
+	 *
+	 * For VF mode each VF can have different number of UL and DL queues.
+	 * Total number of queues to configure cannot exceed FPGA
+	 * capabilities - 64 queues - 32 queues for UL and 32 queues for DL.
+	 * Queues mapping is done according to configuration:
+	 *
+	 * UL queues:
+	 * |                Q_ID              | VF_ID |
+	 * |                 0                |   0   |
+	 * |                ...               |   0   |
+	 * | conf->vf_dl_queues_number[0] - 1 |   0   |
+	 * | conf->vf_dl_queues_number[0]     |   1   |
+	 * |                ...               |   1   |
+	 * | conf->vf_dl_queues_number[1] - 1 |   1   |
+	 * |                ...               |  ...  |
+	 * | conf->vf_dl_queues_number[7] - 1 |   7   |
+	 *
+	 * DL queues:
+	 * |                Q_ID              | VF_ID |
+	 * |                 32               |   0   |
+	 * |                ...               |   0   |
+	 * | conf->vf_ul_queues_number[0] - 1 |   0   |
+	 * | conf->vf_ul_queues_number[0]     |   1   |
+	 * |                ...               |   1   |
+	 * | conf->vf_ul_queues_number[1] - 1 |   1   |
+	 * |                ...               |  ...  |
+	 * | conf->vf_ul_queues_number[7] - 1 |   7   |
+	 *
+	 * Example of configuration:
+	 * conf->vf_ul_queues_number[0] = 4;  -> 4 UL queues for VF0
+	 * conf->vf_dl_queues_number[0] = 4;  -> 4 DL queues for VF0
+	 * conf->vf_ul_queues_number[1] = 2;  -> 2 UL queues for VF1
+	 * conf->vf_dl_queues_number[1] = 2;  -> 2 DL queues for VF1
+	 *
+	 * UL:
+	 * | Q_ID | VF_ID |
+	 * |   0  |   0   |
+	 * |   1  |   0   |
+	 * |   2  |   0   |
+	 * |   3  |   0   |
+	 * |   4  |   1   |
+	 * |   5  |   1   |
+	 *
+	 * DL:
+	 * | Q_ID | VF_ID |
+	 * |  32  |   0   |
+	 * |  33  |   0   |
+	 * |  34  |   0   |
+	 * |  35  |   0   |
+	 * |  36  |   1   |
+	 * |  37  |   1   |
+	 */
+	if (conf->pf_mode_en) {
+		payload_32 = 0x1;
+		for (q_id = 0; q_id < FPGA_TOTAL_NUM_QUEUES; ++q_id) {
+			address = (q_id << 2) + FPGA_5GNR_FEC_QUEUE_MAP;
+			fpga_reg_write_32(d->mmio_base, address, payload_32);
+		}
+	} else {
+		/* Calculate total number of UL and DL queues to configure */
+		total_ul_q_id = total_dl_q_id = 0;
+		for (vf_id = 0; vf_id < FPGA_5GNR_FEC_NUM_VFS; ++vf_id) {
+			total_ul_q_id += conf->vf_ul_queues_number[vf_id];
+			total_dl_q_id += conf->vf_dl_queues_number[vf_id];
+		}
+		total_q_id = total_dl_q_id + total_ul_q_id;
+		/*
+		 * Check if total number of queues to configure does not exceed
+		 * FPGA capabilities (64 queues - 32 UL and 32 DL queues)
+		 */
+		if ((total_ul_q_id > FPGA_NUM_UL_QUEUES) ||
+			(total_dl_q_id > FPGA_NUM_DL_QUEUES) ||
+			(total_q_id > FPGA_TOTAL_NUM_QUEUES)) {
+			rte_bbdev_log(ERR,
+					"FPGA Configuration failed. Too many queues to configure: UL_Q %u, DL_Q %u, FPGA_Q %u",
+					total_ul_q_id, total_dl_q_id,
+					FPGA_TOTAL_NUM_QUEUES);
+			return -EINVAL;
+		}
+		total_ul_q_id = 0;
+		for (vf_id = 0; vf_id < FPGA_5GNR_FEC_NUM_VFS; ++vf_id) {
+			for (q_id = 0; q_id < conf->vf_ul_queues_number[vf_id];
+					++q_id, ++total_ul_q_id) {
+				address = (total_ul_q_id << 2) +
+						FPGA_5GNR_FEC_QUEUE_MAP;
+				payload_32 = ((0x80 + vf_id) << 16) | 0x1;
+				fpga_reg_write_32(d->mmio_base, address,
+						payload_32);
+			}
+		}
+		total_dl_q_id = 0;
+		for (vf_id = 0; vf_id < FPGA_5GNR_FEC_NUM_VFS; ++vf_id) {
+			for (q_id = 0; q_id < conf->vf_dl_queues_number[vf_id];
+					++q_id, ++total_dl_q_id) {
+				address = ((total_dl_q_id + FPGA_NUM_UL_QUEUES)
+						<< 2) + FPGA_5GNR_FEC_QUEUE_MAP;
+				payload_32 = ((0x80 + vf_id) << 16) | 0x1;
+				fpga_reg_write_32(d->mmio_base, address,
+						payload_32);
+			}
+		}
+	}
+
+	/* Setting Load Balance Factor */
+	payload_16 = (conf->dl_load_balance << 8) | (conf->ul_load_balance);
+	address = FPGA_5GNR_FEC_LOAD_BALANCE_FACTOR;
+	fpga_reg_write_16(d->mmio_base, address, payload_16);
+
+	/* Setting length of ring descriptor entry */
+	payload_16 = FPGA_RING_DESC_ENTRY_LENGTH;
+	address = FPGA_5GNR_FEC_RING_DESC_LEN;
+	fpga_reg_write_16(d->mmio_base, address, payload_16);
+
+	/* Setting FLR timeout value */
+	payload_16 = conf->flr_time_out;
+	address = FPGA_5GNR_FEC_FLR_TIME_OUT;
+	fpga_reg_write_16(d->mmio_base, address, payload_16);
+
+	/* Queue PF/VF mapping table is ready */
+	payload_8 = 0x1;
+	address = FPGA_5GNR_FEC_QUEUE_PF_VF_MAP_DONE;
+	fpga_reg_write_8(d->mmio_base, address, payload_8);
+
+	rte_bbdev_log_debug("PF FPGA 5GNR FEC configuration complete for %s",
+			dev_name);
+
+#ifdef RTE_LIBRTE_BBDEV_DEBUG
+	print_static_reg_debug_info(d->mmio_base);
+#endif
+	return 0;
+}
+
+/* FPGA 5GNR FEC PCI PF address map */
+static struct rte_pci_id pci_id_fpga_5gnr_fec_pf_map[] = {
+	{
+		RTE_PCI_DEVICE(FPGA_5GNR_FEC_VENDOR_ID,
+				FPGA_5GNR_FEC_PF_DEVICE_ID)
+	},
+	{.device_id = 0},
+};
+
+static struct rte_pci_driver fpga_5gnr_fec_pci_pf_driver = {
+	.probe = fpga_5gnr_fec_probe,
+	.remove = fpga_5gnr_fec_remove,
+	.id_table = pci_id_fpga_5gnr_fec_pf_map,
+	.drv_flags = RTE_PCI_DRV_NEED_MAPPING
+};
+
+/* FPGA 5GNR FEC PCI VF address map */
+static struct rte_pci_id pci_id_fpga_5gnr_fec_vf_map[] = {
+	{
+		RTE_PCI_DEVICE(FPGA_5GNR_FEC_VENDOR_ID,
+				FPGA_5GNR_FEC_VF_DEVICE_ID)
+	},
+	{.device_id = 0},
+};
+
+static struct rte_pci_driver fpga_5gnr_fec_pci_vf_driver = {
+	.probe = fpga_5gnr_fec_probe,
+	.remove = fpga_5gnr_fec_remove,
+	.id_table = pci_id_fpga_5gnr_fec_vf_map,
+	.drv_flags = RTE_PCI_DRV_NEED_MAPPING
+};
+
+
+RTE_PMD_REGISTER_PCI(FPGA_5GNR_FEC_PF_DRIVER_NAME, fpga_5gnr_fec_pci_pf_driver);
+RTE_PMD_REGISTER_PCI_TABLE(FPGA_5GNR_FEC_PF_DRIVER_NAME,
+		pci_id_fpga_5gnr_fec_pf_map);
+RTE_PMD_REGISTER_PCI(FPGA_5GNR_FEC_VF_DRIVER_NAME, fpga_5gnr_fec_pci_vf_driver);
+RTE_PMD_REGISTER_PCI_TABLE(FPGA_5GNR_FEC_VF_DRIVER_NAME,
+		pci_id_fpga_5gnr_fec_vf_map);
+
+RTE_INIT(fpga_5gnr_fec_init_log)
+{
+	fpga_5gnr_fec_logtype = rte_log_register("pmd.bb.fpga_5gnr_fec");
+	if (fpga_5gnr_fec_logtype >= 0)
+#ifdef RTE_LIBRTE_BBDEV_DEBUG
+		rte_log_set_level(fpga_5gnr_fec_logtype, RTE_LOG_DEBUG);
+#else
+		rte_log_set_level(fpga_5gnr_fec_logtype, RTE_LOG_NOTICE);
+#endif
+}
diff --git a/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h b/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h
new file mode 100644
index 0000000..7eebc7d
--- /dev/null
+++ b/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h
@@ -0,0 +1,74 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2020 Intel Corporation
+ */
+
+#ifndef _FPGA_5GNR_FEC_H_
+#define _FPGA_5GNR_FEC_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+
+/**
+ * @file fpga_5gnr_fec.h
+ *
+ * Interface for Intel(R) FGPA 5GNR FEC device configuration at the host level,
+ * directly accessible by the application.
+ * Configuration related to 5GNR functionality is done through
+ * librte_bbdev library.
+ *
+ * @warning
+ * @b EXPERIMENTAL: this API may change without prior notice
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**< Number of Virtual Functions FGPA 4G FEC supports */
+#define FPGA_5GNR_FEC_NUM_VFS 8
+
+/**
+ * Structure to pass FPGA 4G FEC configuration.
+ */
+struct fpga_5gnr_fec_conf {
+	/**< 1 if PF is used for dataplane, 0 for VFs */
+	bool pf_mode_en;
+	/**< Number of UL queues per VF */
+	uint8_t vf_ul_queues_number[FPGA_5GNR_FEC_NUM_VFS];
+	/**< Number of DL queues per VF */
+	uint8_t vf_dl_queues_number[FPGA_5GNR_FEC_NUM_VFS];
+	/**< UL bandwidth. Needed for schedule algorithm */
+	uint8_t ul_bandwidth;
+	/**< DL bandwidth. Needed for schedule algorithm */
+	uint8_t dl_bandwidth;
+	/**< UL Load Balance */
+	uint8_t ul_load_balance;
+	/**< DL Load Balance */
+	uint8_t dl_load_balance;
+	/**< FLR timeout value */
+	uint16_t flr_time_out;
+};
+
+/**
+ * Configure Intel(R) FPGA 5GNR FEC device
+ *
+ * @param dev_name
+ *   The name of the device. This is the short form of PCI BDF, e.g. 00:01.0.
+ *   It can also be retrieved for a bbdev device from the dev_name field in the
+ *   rte_bbdev_info structure returned by rte_bbdev_info_get().
+ * @param conf
+ *   Configuration to apply to FPGA 4G FEC.
+ *
+ * @return
+ *   Zero on success, negative value on failure.
+ */
+__rte_experimental
+int
+fpga_5gnr_fec_configure(const char *dev_name,
+		const struct fpga_5gnr_fec_conf *conf);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _FPGA_5GNR_FEC_H_ */
diff --git a/drivers/baseband/fpga_5gnr_fec/meson.build b/drivers/baseband/fpga_5gnr_fec/meson.build
new file mode 100644
index 0000000..86121d8
--- /dev/null
+++ b/drivers/baseband/fpga_5gnr_fec/meson.build
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2020 Intel Corporation
+
+deps += ['bbdev', 'bus_vdev', 'ring', 'pci', 'bus_pci']
+allow_experimental_apis = true
+sources = files('fpga_5gnr_fec.c')
diff --git a/drivers/baseband/fpga_5gnr_fec/rte_pmd_bbdev_fpga_5gnr_fec_version.map b/drivers/baseband/fpga_5gnr_fec/rte_pmd_bbdev_fpga_5gnr_fec_version.map
new file mode 100644
index 0000000..b0fb971
--- /dev/null
+++ b/drivers/baseband/fpga_5gnr_fec/rte_pmd_bbdev_fpga_5gnr_fec_version.map
@@ -0,0 +1,10 @@
+DPDK_20.0 {
+	local: *;
+};
+
+EXPERIMENTAL {
+	global:
+
+	fpga_5gnr_fec_configure;
+
+};
diff --git a/drivers/baseband/meson.build b/drivers/baseband/meson.build
index be7677f..4d909f9 100644
--- a/drivers/baseband/meson.build
+++ b/drivers/baseband/meson.build
@@ -1,7 +1,7 @@
 # SPDX-License-Identifier: BSD-3-Clause
 # Copyright(c) 2018 Luca Boccassi <bluca@debian.org>
 
-drivers = ['null', 'turbo_sw', 'fpga_lte_fec']
+drivers = ['null', 'turbo_sw', 'fpga_lte_fec', 'fpga_5gnr_fec']
 
 config_flag_fmt = 'RTE_LIBRTE_PMD_BBDEV_@0@'
 driver_name_fmt = 'rte_pmd_bbdev_@0@'
diff --git a/mk/rte.app.mk b/mk/rte.app.mk
index d295ca0..da12b9e 100644
--- a/mk/rte.app.mk
+++ b/mk/rte.app.mk
@@ -246,6 +246,7 @@ _LDLIBS-$(CONFIG_RTE_LIBRTE_NETVSC_PMD)     += -lrte_pmd_netvsc
 ifeq ($(CONFIG_RTE_LIBRTE_BBDEV),y)
 _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_BBDEV_NULL)     += -lrte_pmd_bbdev_null
 _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_BBDEV_FPGA_LTE_FEC) += -lrte_pmd_bbdev_fpga_lte_fec
+_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_BBDEV_FPGA_5GNR_FEC) += -lrte_pmd_bbdev_fpga_5gnr_fec
 
 # TURBO SOFTWARE PMD is dependent on the FLEXRAN library
 _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_BBDEV_TURBO_SW) += -lrte_pmd_bbdev_turbo_sw
-- 
1.8.3.1


^ permalink raw reply	[flat|nested] 115+ messages in thread

* [dpdk-dev] [PATCH v1 13/14] test-bbdev: add support for FPGA driver initialization
  2020-02-27  4:38 [dpdk-dev] [PATCH v1 00/14] bbdev new features Nicolas Chautru
                   ` (11 preceding siblings ...)
  2020-02-27  4:39 ` [dpdk-dev] [PATCH v1 12/14] drivers/baseband: add PMD for FPGA 5GNR FEC Nicolas Chautru
@ 2020-02-27  4:39 ` Nicolas Chautru
  2020-02-27  4:39 ` [dpdk-dev] [PATCH v1 14/14] doc: add feature matrix table for bbdev devices Nicolas Chautru
  2020-03-03 18:08 ` [dpdk-dev] [PATCH v1 00/14] " Chautru, Nicolas
  14 siblings, 0 replies; 115+ messages in thread
From: Nicolas Chautru @ 2020-02-27  4:39 UTC (permalink / raw)
  To: thomas, akhil.goyal, dev; +Cc: ferruh.yigit, Nic Chautru

From: Nic Chautru <nicolas.chautru@intel.com>

Adding capacity to initialize the device driver from
the test-bbdev environment for the new device
FPGA for 5GNR FEC.

Signed-off-by: Nic Chautru <nicolas.chautru@intel.com>
---
 app/test-bbdev/Makefile          |  3 +++
 app/test-bbdev/meson.build       |  3 +++
 app/test-bbdev/test_bbdev_perf.c | 58 ++++++++++++++++++++++++++++++++++++++++
 3 files changed, 64 insertions(+)

diff --git a/app/test-bbdev/Makefile b/app/test-bbdev/Makefile
index c53982f..e951302 100644
--- a/app/test-bbdev/Makefile
+++ b/app/test-bbdev/Makefile
@@ -24,5 +24,8 @@ LDLIBS += -lm
 ifeq ($(CONFIG_RTE_LIBRTE_PMD_BBDEV_FPGA_LTE_FEC),y)
 LDLIBS += -lrte_pmd_bbdev_fpga_lte_fec
 endif
+ifeq ($(CONFIG_RTE_LIBRTE_PMD_BBDEV_FPGA_5GNR_FEC),y)
+LDLIBS += -lrte_pmd_bbdev_fpga_5gnr_fec
+endif
 
 include $(RTE_SDK)/mk/rte.app.mk
diff --git a/app/test-bbdev/meson.build b/app/test-bbdev/meson.build
index 4f53a2e..e57e019 100644
--- a/app/test-bbdev/meson.build
+++ b/app/test-bbdev/meson.build
@@ -10,3 +10,6 @@ deps += ['bbdev', 'bus_vdev']
 if dpdk_conf.has('RTE_LIBRTE_PMD_BBDEV_FPGA_LTE_FEC')
 	deps += ['pmd_bbdev_fpga_lte_fec']
 endif
+if dpdk_conf.has('RTE_LIBRTE_PMD_BBDEV_FPGA_5GNR_FEC')
+	deps += ['pmd_bbdev_fpga_5gnr_fec']
+endif
\ No newline at end of file
diff --git a/app/test-bbdev/test_bbdev_perf.c b/app/test-bbdev/test_bbdev_perf.c
index 1017b97..50ffee0 100644
--- a/app/test-bbdev/test_bbdev_perf.c
+++ b/app/test-bbdev/test_bbdev_perf.c
@@ -39,6 +39,19 @@
 #define FLR_4G_TIMEOUT 610
 #endif
 
+#ifdef RTE_LIBRTE_PMD_BBDEV_FPGA_5GNR_FEC
+#include <fpga_5gnr_fec.h>
+#define FPGA_5GNR_PF_DRIVER_NAME ("intel_fpga_5gnr_fec_pf")
+#define FPGA_5GNR_VF_DRIVER_NAME ("intel_fpga_5gnr_fec_vf")
+#define VF_UL_5G_QUEUE_VALUE 4
+#define VF_DL_5G_QUEUE_VALUE 4
+#define UL_5G_BANDWIDTH 3
+#define DL_5G_BANDWIDTH 3
+#define UL_5G_LOAD_BALANCE 128
+#define DL_5G_LOAD_BALANCE 128
+#define FLR_5G_TIMEOUT 610
+#endif
+
 #define OPS_CACHE_SIZE 256U
 #define OPS_POOL_SIZE_MIN 511U /* 0.5K per queue */
 
@@ -587,6 +600,51 @@ typedef int (test_case_function)(struct active_device *ad,
 				info->dev_name);
 	}
 #endif
+#ifdef RTE_LIBRTE_PMD_BBDEV_FPGA_5GNR_FEC
+	if ((get_init_device() == true) &&
+		(!strcmp(info->drv.driver_name, FPGA_5GNR_PF_DRIVER_NAME))) {
+		struct fpga_5gnr_fec_conf conf;
+		unsigned int i;
+
+		printf("Configure FPGA 5GNR FEC Driver %s with default values\n",
+				info->drv.driver_name);
+
+		/* clear default configuration before initialization */
+		memset(&conf, 0, sizeof(struct fpga_5gnr_fec_conf));
+
+		/* Set PF mode :
+		 * true if PF is used for data plane
+		 * false for VFs
+		 */
+		conf.pf_mode_en = true;
+
+		for (i = 0; i < FPGA_5GNR_FEC_NUM_VFS; ++i) {
+			/* Number of UL queues per VF (fpga supports 8 VFs) */
+			conf.vf_ul_queues_number[i] = VF_UL_5G_QUEUE_VALUE;
+			/* Number of DL queues per VF (fpga supports 8 VFs) */
+			conf.vf_dl_queues_number[i] = VF_DL_5G_QUEUE_VALUE;
+		}
+
+		/* UL bandwidth. Needed for schedule algorithm */
+		conf.ul_bandwidth = UL_5G_BANDWIDTH;
+		/* DL bandwidth */
+		conf.dl_bandwidth = DL_5G_BANDWIDTH;
+
+		/* UL & DL load Balance Factor to 64 */
+		conf.ul_load_balance = UL_5G_LOAD_BALANCE;
+		conf.dl_load_balance = DL_5G_LOAD_BALANCE;
+
+		/**< FLR timeout value */
+		conf.flr_time_out = FLR_5G_TIMEOUT;
+
+		/* setup FPGA PF with configuration information */
+		ret = fpga_5gnr_fec_configure(info->dev_name, &conf);
+		TEST_ASSERT_SUCCESS(ret,
+				"Failed to configure 5G FPGA PF for bbdev %s",
+				info->dev_name);
+	}
+#endif
+
 	nb_queues = RTE_MIN(rte_lcore_count(), info->drv.max_num_queues);
 	nb_queues = RTE_MIN(nb_queues, (unsigned int) MAX_QUEUES);
 
-- 
1.8.3.1


^ permalink raw reply	[flat|nested] 115+ messages in thread

* [dpdk-dev] [PATCH v1 14/14] doc: add feature matrix table for bbdev devices
  2020-02-27  4:38 [dpdk-dev] [PATCH v1 00/14] bbdev new features Nicolas Chautru
                   ` (12 preceding siblings ...)
  2020-02-27  4:39 ` [dpdk-dev] [PATCH v1 13/14] test-bbdev: add support for FPGA driver initialization Nicolas Chautru
@ 2020-02-27  4:39 ` Nicolas Chautru
  2020-03-04 18:22   ` [dpdk-dev] [PATCH v2 00/15] bbdev new features Nicolas Chautru
                     ` (3 more replies)
  2020-03-03 18:08 ` [dpdk-dev] [PATCH v1 00/14] " Chautru, Nicolas
  14 siblings, 4 replies; 115+ messages in thread
From: Nicolas Chautru @ 2020-02-27  4:39 UTC (permalink / raw)
  To: thomas, akhil.goyal, dev; +Cc: ferruh.yigit, Nic Chautru

From: Nic Chautru <nicolas.chautru@intel.com>

Adding missing overview page in documentation with
comparison of feature set by PMD implementation.

Signed-off-by: Nic Chautru <nicolas.chautru@intel.com>
---
 .gitignore                                   |  1 +
 doc/guides/bbdevs/features/default.ini       | 16 ++++++++++++++++
 doc/guides/bbdevs/features/fpga_5gnr_fec.ini | 11 +++++++++++
 doc/guides/bbdevs/features/fpga_lte_fec.ini  | 10 ++++++++++
 doc/guides/bbdevs/features/mbc.ini           | 14 ++++++++++++++
 doc/guides/bbdevs/features/null.ini          |  7 +++++++
 doc/guides/bbdevs/features/turbo_sw.ini      | 11 +++++++++++
 doc/guides/bbdevs/index.rst                  |  1 +
 doc/guides/bbdevs/overview.rst               | 15 +++++++++++++++
 doc/guides/conf.py                           |  5 +++++
 10 files changed, 91 insertions(+)
 create mode 100644 doc/guides/bbdevs/features/default.ini
 create mode 100644 doc/guides/bbdevs/features/fpga_5gnr_fec.ini
 create mode 100644 doc/guides/bbdevs/features/fpga_lte_fec.ini
 create mode 100644 doc/guides/bbdevs/features/mbc.ini
 create mode 100644 doc/guides/bbdevs/features/null.ini
 create mode 100644 doc/guides/bbdevs/features/turbo_sw.ini
 create mode 100644 doc/guides/bbdevs/overview.rst

diff --git a/.gitignore b/.gitignore
index 2acb459..f2f8892 100644
--- a/.gitignore
+++ b/.gitignore
@@ -10,6 +10,7 @@ doc/guides/cryptodevs/overview_aead_table.txt
 doc/guides/cryptodevs/overview_asym_table.txt
 doc/guides/compressdevs/overview_feature_table.txt
 doc/guides/vdpadevs/overview_feature_table.txt
+doc/guides/bbdevs/overview_feature_table.txt
 
 # ignore generated ctags/cscope files
 cscope.out.po
diff --git a/doc/guides/bbdevs/features/default.ini b/doc/guides/bbdevs/features/default.ini
new file mode 100644
index 0000000..5fe267a
--- /dev/null
+++ b/doc/guides/bbdevs/features/default.ini
@@ -0,0 +1,16 @@
+;
+; Features of a default bbdev driver.
+;
+; This file defines the features that are valid for inclusion in
+; the other driver files and also the order that they appear in
+; the features table in the documentation.
+;
+[Features]
+Turbo Decoder (4G)     =
+Turbo Encoder (4G)     =
+LDPC Decoder (5G)      =
+LDPC Encoder (5G)      =
+LLR/HARQ Compression   =
+External DDR Access    =
+HW Accelerated         =
+BBDEV API              =
diff --git a/doc/guides/bbdevs/features/fpga_5gnr_fec.ini b/doc/guides/bbdevs/features/fpga_5gnr_fec.ini
new file mode 100644
index 0000000..7a0b8d4
--- /dev/null
+++ b/doc/guides/bbdevs/features/fpga_5gnr_fec.ini
@@ -0,0 +1,11 @@
+;
+; Supported features of the 'fpga_5ngr_fec' bbdev driver.
+;
+; Refer to default.ini for the full list of available PMD features.
+;
+[Features]
+LDPC Decoder (5G)      = Y
+LDPC Encoder (5G)      = Y
+External DDR Access    = Y
+HW Accelerated         = Y
+BBDEV API              = Y
diff --git a/doc/guides/bbdevs/features/fpga_lte_fec.ini b/doc/guides/bbdevs/features/fpga_lte_fec.ini
new file mode 100644
index 0000000..f1cfb92
--- /dev/null
+++ b/doc/guides/bbdevs/features/fpga_lte_fec.ini
@@ -0,0 +1,10 @@
+;
+; Supported features of the 'fpga_lte_fec' bbdev driver.
+;
+; Refer to default.ini for the full list of available PMD features.
+;
+[Features]
+Turbo Decoder (4G)     = Y
+Turbo Encoder (4G)     = Y
+HW Accelerated         = Y
+BBDEV API              = Y
diff --git a/doc/guides/bbdevs/features/mbc.ini b/doc/guides/bbdevs/features/mbc.ini
new file mode 100644
index 0000000..78a7b95
--- /dev/null
+++ b/doc/guides/bbdevs/features/mbc.ini
@@ -0,0 +1,14 @@
+;
+; Supported features of the 'mbc' bbdev driver.
+;
+; Refer to default.ini for the full list of available PMD features.
+;
+[Features]
+Turbo Decoder (4G)     = Y
+Turbo Encoder (4G)     = Y
+LDPC Decoder (5G)      = Y
+LDPC Encoder (5G)      = Y
+LLR/HARQ Compression   = Y
+External DDR Access    = Y
+HW Accelerated         = Y
+BBDEV API              = Y
diff --git a/doc/guides/bbdevs/features/null.ini b/doc/guides/bbdevs/features/null.ini
new file mode 100644
index 0000000..d9bbda9
--- /dev/null
+++ b/doc/guides/bbdevs/features/null.ini
@@ -0,0 +1,7 @@
+;
+; Supported features of the 'null' bbdev driver.
+;
+; Refer to default.ini for the full list of available PMD features.
+;
+[Features]
+BBDEV API              = Y
diff --git a/doc/guides/bbdevs/features/turbo_sw.ini b/doc/guides/bbdevs/features/turbo_sw.ini
new file mode 100644
index 0000000..2c7075e
--- /dev/null
+++ b/doc/guides/bbdevs/features/turbo_sw.ini
@@ -0,0 +1,11 @@
+;
+; Supported features of the 'turbo_sw' bbdev driver.
+;
+; Refer to default.ini for the full list of available PMD features.
+;
+[Features]
+Turbo Decoder (4G)     = Y
+Turbo Encoder (4G)     = Y
+LDPC Decoder (5G)      = Y
+LDPC Encoder (5G)      = Y
+BBDEV API              = Y
diff --git a/doc/guides/bbdevs/index.rst b/doc/guides/bbdevs/index.rst
index 1a79343..a8092dd 100644
--- a/doc/guides/bbdevs/index.rst
+++ b/doc/guides/bbdevs/index.rst
@@ -8,6 +8,7 @@ Baseband Device Drivers
     :maxdepth: 2
     :numbered:
 
+    overview
     null
     turbo_sw
     fpga_lte_fec
diff --git a/doc/guides/bbdevs/overview.rst b/doc/guides/bbdevs/overview.rst
new file mode 100644
index 0000000..ace4e67
--- /dev/null
+++ b/doc/guides/bbdevs/overview.rst
@@ -0,0 +1,15 @@
+..  SPDX-License-Identifier: BSD-3-Clause
+    Copyright(c) 2020 Intel Corporation.
+
+Baseband Device Supported Functionality Matrices
+==============================================
+
+Supported Feature Flags
+-----------------------
+
+.. _table_bbdev_pmd_features:
+
+.. include:: overview_feature_table.txt
+
+
+
diff --git a/doc/guides/conf.py b/doc/guides/conf.py
index c368fa5..d52b584 100644
--- a/doc/guides/conf.py
+++ b/doc/guides/conf.py
@@ -406,6 +406,11 @@ def setup(app):
                             'Features',
                             'Features availability in vDPA drivers',
                             'Feature')
+    table_file = dirname(__file__) + '/bbdevs/overview_feature_table.txt'
+    generate_overview_table(table_file, 1,
+                            'Features',
+                            'Features availability in bbdev drivers',
+                            'Feature')
 
     if LooseVersion(sphinx_version) < LooseVersion('1.3.1'):
         print('Upgrade sphinx to version >= 1.3.1 for '
-- 
1.8.3.1


^ permalink raw reply	[flat|nested] 115+ messages in thread

* Re: [dpdk-dev] [PATCH v1 00/14] bbdev new features
  2020-02-27  4:38 [dpdk-dev] [PATCH v1 00/14] bbdev new features Nicolas Chautru
                   ` (13 preceding siblings ...)
  2020-02-27  4:39 ` [dpdk-dev] [PATCH v1 14/14] doc: add feature matrix table for bbdev devices Nicolas Chautru
@ 2020-03-03 18:08 ` " Chautru, Nicolas
  2020-03-04  8:23   ` Thomas Monjalon
  14 siblings, 1 reply; 115+ messages in thread
From: Chautru, Nicolas @ 2020-03-03 18:08 UTC (permalink / raw)
  To: thomas, akhil.goyal, dev; +Cc: Yigit, Ferruh

Hi Akhil, Thomas, 

Checking whether there is anything on your end or can we have these patches merged? 

I did not include the release note update in that serie but will push a trivial patchset for this later on if that's okay. 

Thanks, 
Nic


-----Original Message-----
From: Chautru, Nicolas <nicolas.chautru@intel.com> 
Sent: Wednesday, February 26, 2020 8:39 PM
To: thomas@monjalon.net; akhil.goyal@nxp.com; dev@dpdk.org
Cc: Yigit, Ferruh <ferruh.yigit@intel.com>; Chautru, Nicolas <nicolas.chautru@intel.com>
Subject: [PATCH v1 00/14] bbdev new features

This set includes extending support for the bbdev device drivers for 20.05 and notably add a new baseband PMD for FPGA 5GNR FEC implementation. 
Documentation is updated as well accordingly. 

Nic Chautru (14):
  bbdev: add capability flag for filler bits inclusion in HARQ
  bbdev: expose device HARQ buffer size at device level
  baseband/turbo_sw: fix the exposed LLR decimals assumption
  baseband/turbo_sw: support large size code block
  test-bbdev: rename FPGA LTE macros to be more explicit
  test-bbdev: support HARQ validation
  test-bbdev: support for performance tests
  test-bbdev: support for LDPC interrupt test
  test-bbdev: support for offload test for LDPC
  test-bbdev: vectors update
  doc: update of testbbdev documentation
  drivers/baseband: add PMD for FPGA 5GNR FEC
  test-bbdev: add support for FPGA driver initialization
  doc: add feature matrix table for bbdev devices

 .gitignore                                         |    1 +
 app/test-bbdev/Makefile                            |    3 +
 app/test-bbdev/ldpc_dec_default.data               |    2 +-
 app/test-bbdev/main.c                              |   29 +-
 app/test-bbdev/main.h                              |    9 +-
 app/test-bbdev/meson.build                         |    3 +
 app/test-bbdev/test_bbdev_perf.c                   | 1468 ++++++++++-
 app/test-bbdev/test_bbdev_vector.c                 |    9 +-
 app/test-bbdev/test_vectors/ldpc_dec_v2342.data    |  745 ------
 app/test-bbdev/test_vectors/ldpc_dec_v9503.data    |    4 +-
 .../turbo_dec_c1_k6144_r0_e34560_negllr.data       |  645 -----
 .../turbo_dec_c2_k3136_r0_e4920_sbd_negllr.data    |  676 ------
 ...bo_dec_c2_k3136_r0_e4920_sbd_negllr_crc24b.data |    5 +-
 .../turbo_enc_c2_k5952_r0_e17868_crc24b.data       |  300 ---
 .../turbo_enc_c4_k4800_r2_e14412_crc24b.data       |  252 --
 config/common_base                                 |    5 +
 doc/guides/bbdevs/features/default.ini             |   16 +
 doc/guides/bbdevs/features/fpga_5gnr_fec.ini       |   11 +
 doc/guides/bbdevs/features/fpga_lte_fec.ini        |   10 +
 doc/guides/bbdevs/features/mbc.ini                 |   14 +
 doc/guides/bbdevs/features/null.ini                |    7 +
 doc/guides/bbdevs/features/turbo_sw.ini            |   11 +
 doc/guides/bbdevs/fpga_5gnr_fec.rst                |  297 +++
 doc/guides/bbdevs/index.rst                        |    2 +
 doc/guides/bbdevs/overview.rst                     |   15 +
 doc/guides/conf.py                                 |    5 +
 doc/guides/tools/testbbdev.rst                     |  337 ++-
 drivers/baseband/Makefile                          |    2 +
 drivers/baseband/fpga_5gnr_fec/Makefile            |   29 +
 drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.c     | 2552 ++++++++++++++++++++
 drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h     |   74 +
 drivers/baseband/fpga_5gnr_fec/meson.build         |    6 +
 .../rte_pmd_bbdev_fpga_5gnr_fec_version.map        |   10 +
 drivers/baseband/meson.build                       |    2 +-
 drivers/baseband/turbo_sw/bbdev_turbo_software.c   |   15 +-
 lib/librte_bbdev/rte_bbdev.h                       |    4 +
 lib/librte_bbdev/rte_bbdev_op.h                    |   14 +-
 mk/rte.app.mk                                      |    1 +
 38 files changed, 4772 insertions(+), 2818 deletions(-)  delete mode 100644 app/test-bbdev/test_vectors/ldpc_dec_v2342.data
 delete mode 100644 app/test-bbdev/test_vectors/turbo_dec_c1_k6144_r0_e34560_negllr.data
 delete mode 100644 app/test-bbdev/test_vectors/turbo_dec_c2_k3136_r0_e4920_sbd_negllr.data
 delete mode 100644 app/test-bbdev/test_vectors/turbo_enc_c2_k5952_r0_e17868_crc24b.data
 delete mode 100644 app/test-bbdev/test_vectors/turbo_enc_c4_k4800_r2_e14412_crc24b.data
 create mode 100644 doc/guides/bbdevs/features/default.ini
 create mode 100644 doc/guides/bbdevs/features/fpga_5gnr_fec.ini
 create mode 100644 doc/guides/bbdevs/features/fpga_lte_fec.ini
 create mode 100644 doc/guides/bbdevs/features/mbc.ini
 create mode 100644 doc/guides/bbdevs/features/null.ini
 create mode 100644 doc/guides/bbdevs/features/turbo_sw.ini
 create mode 100644 doc/guides/bbdevs/fpga_5gnr_fec.rst
 create mode 100644 doc/guides/bbdevs/overview.rst  create mode 100644 drivers/baseband/fpga_5gnr_fec/Makefile
 create mode 100644 drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.c
 create mode 100644 drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h
 create mode 100644 drivers/baseband/fpga_5gnr_fec/meson.build
 create mode 100644 drivers/baseband/fpga_5gnr_fec/rte_pmd_bbdev_fpga_5gnr_fec_version.map

--
1.8.3.1


^ permalink raw reply	[flat|nested] 115+ messages in thread

* Re: [dpdk-dev] [PATCH v1 00/14] bbdev new features
  2020-03-03 18:08 ` [dpdk-dev] [PATCH v1 00/14] " Chautru, Nicolas
@ 2020-03-04  8:23   ` Thomas Monjalon
  2020-03-04 18:28     ` Chautru, Nicolas
  0 siblings, 1 reply; 115+ messages in thread
From: Thomas Monjalon @ 2020-03-04  8:23 UTC (permalink / raw)
  To: Chautru, Nicolas; +Cc: akhil.goyal, dev, Yigit, Ferruh

03/03/2020 19:08, Chautru, Nicolas:
> Hi Akhil, Thomas, 
> 
> Checking whether there is anything on your end or can we have these patches merged? 
> 
> I did not include the release note update in that serie but will push a trivial patchset for this later on if that's okay. 

Why not including the release notes in the patches?
We prefer not having separate commits for documentation and release notes.




^ permalink raw reply	[flat|nested] 115+ messages in thread

* [dpdk-dev] [PATCH v2 00/15] bbdev new features
  2020-02-27  4:39 ` [dpdk-dev] [PATCH v1 14/14] doc: add feature matrix table for bbdev devices Nicolas Chautru
@ 2020-03-04 18:22   ` Nicolas Chautru
  2020-03-04 18:22     ` [dpdk-dev] [PATCH v2 01/15] bbdev: add capability flag for filler bits inclusion in HARQ Nicolas Chautru
                       ` (14 more replies)
  2020-03-04 18:54   ` [dpdk-dev] [PATCH v3 00/14] bbdev new features Nicolas Chautru
                     ` (2 subsequent siblings)
  3 siblings, 15 replies; 115+ messages in thread
From: Nicolas Chautru @ 2020-03-04 18:22 UTC (permalink / raw)
  To: thomas, akhil.goyal, dev; +Cc: ferruh.yigit, Nicolas Chautru

v2: including release note update + fix for typo in commit message reported by DPDK CI. 

This set includes extending support for the bbdev device drivers for 20.05 and notably add a new baseband PMD for FPGA 5GNR FEC implementation. 
Documentation is updated as well accordingly. 


Nic Chautru (14):
  bbdev: add capability flag for filler bits inclusion in HARQ
  bbdev: expose device HARQ buffer size at device level
  baseband/turbo_sw: fix the exposed LLR decimals assumption
  baseband/turbo_sw: support large size code block
  test-bbdev: rename FPGA LTE macros to be more explicit
  test-bbdev: support HARQ validation
  test-bbdev: support for performance tests
  test-bbdev: support for LDPC interrupt test
  test-bbdev: support for offload test for LDPC
  test-bbdev: vectors update
  doc: update of testbbdev documentation
  drivers/baseband: add PMD for FPGA 5GNR FEC
  test-bbdev: add support for FPGA driver initialization
  doc: add feature matrix table for bbdev devices

Nicolas Chautru (1):
  doc: add release note for bbdev PMD update

 .gitignore                                         |    1 +
 app/test-bbdev/Makefile                            |    3 +
 app/test-bbdev/ldpc_dec_default.data               |    2 +-
 app/test-bbdev/main.c                              |   29 +-
 app/test-bbdev/main.h                              |    9 +-
 app/test-bbdev/meson.build                         |    3 +
 app/test-bbdev/test_bbdev_perf.c                   | 1468 ++++++++++-
 app/test-bbdev/test_bbdev_vector.c                 |    9 +-
 app/test-bbdev/test_vectors/ldpc_dec_v2342.data    |  745 ------
 app/test-bbdev/test_vectors/ldpc_dec_v9503.data    |    4 +-
 .../turbo_dec_c1_k6144_r0_e34560_negllr.data       |  645 -----
 .../turbo_dec_c2_k3136_r0_e4920_sbd_negllr.data    |  676 ------
 ...bo_dec_c2_k3136_r0_e4920_sbd_negllr_crc24b.data |    5 +-
 .../turbo_enc_c2_k5952_r0_e17868_crc24b.data       |  300 ---
 .../turbo_enc_c4_k4800_r2_e14412_crc24b.data       |  252 --
 config/common_base                                 |    5 +
 doc/guides/bbdevs/features/default.ini             |   16 +
 doc/guides/bbdevs/features/fpga_5gnr_fec.ini       |   11 +
 doc/guides/bbdevs/features/fpga_lte_fec.ini        |   10 +
 doc/guides/bbdevs/features/mbc.ini                 |   14 +
 doc/guides/bbdevs/features/null.ini                |    7 +
 doc/guides/bbdevs/features/turbo_sw.ini            |   11 +
 doc/guides/bbdevs/fpga_5gnr_fec.rst                |  297 +++
 doc/guides/bbdevs/index.rst                        |    2 +
 doc/guides/bbdevs/overview.rst                     |   15 +
 doc/guides/conf.py                                 |    5 +
 doc/guides/rel_notes/release_20_05.rst             |   12 +
 doc/guides/tools/testbbdev.rst                     |  337 ++-
 drivers/baseband/Makefile                          |    2 +
 drivers/baseband/fpga_5gnr_fec/Makefile            |   29 +
 drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.c     | 2552 ++++++++++++++++++++
 drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h     |   74 +
 drivers/baseband/fpga_5gnr_fec/meson.build         |    6 +
 .../rte_pmd_bbdev_fpga_5gnr_fec_version.map        |   10 +
 drivers/baseband/meson.build                       |    2 +-
 drivers/baseband/turbo_sw/bbdev_turbo_software.c   |   15 +-
 lib/librte_bbdev/rte_bbdev.h                       |    4 +
 lib/librte_bbdev/rte_bbdev_op.h                    |   14 +-
 mk/rte.app.mk                                      |    1 +
 39 files changed, 4784 insertions(+), 2818 deletions(-)
 delete mode 100644 app/test-bbdev/test_vectors/ldpc_dec_v2342.data
 delete mode 100644 app/test-bbdev/test_vectors/turbo_dec_c1_k6144_r0_e34560_negllr.data
 delete mode 100644 app/test-bbdev/test_vectors/turbo_dec_c2_k3136_r0_e4920_sbd_negllr.data
 delete mode 100644 app/test-bbdev/test_vectors/turbo_enc_c2_k5952_r0_e17868_crc24b.data
 delete mode 100644 app/test-bbdev/test_vectors/turbo_enc_c4_k4800_r2_e14412_crc24b.data
 create mode 100644 doc/guides/bbdevs/features/default.ini
 create mode 100644 doc/guides/bbdevs/features/fpga_5gnr_fec.ini
 create mode 100644 doc/guides/bbdevs/features/fpga_lte_fec.ini
 create mode 100644 doc/guides/bbdevs/features/mbc.ini
 create mode 100644 doc/guides/bbdevs/features/null.ini
 create mode 100644 doc/guides/bbdevs/features/turbo_sw.ini
 create mode 100644 doc/guides/bbdevs/fpga_5gnr_fec.rst
 create mode 100644 doc/guides/bbdevs/overview.rst
 create mode 100644 drivers/baseband/fpga_5gnr_fec/Makefile
 create mode 100644 drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.c
 create mode 100644 drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h
 create mode 100644 drivers/baseband/fpga_5gnr_fec/meson.build
 create mode 100644 drivers/baseband/fpga_5gnr_fec/rte_pmd_bbdev_fpga_5gnr_fec_version.map

-- 
1.8.3.1


^ permalink raw reply	[flat|nested] 115+ messages in thread

* [dpdk-dev] [PATCH v2 01/15] bbdev: add capability flag for filler bits inclusion in HARQ
  2020-03-04 18:22   ` [dpdk-dev] [PATCH v2 00/15] bbdev new features Nicolas Chautru
@ 2020-03-04 18:22     ` Nicolas Chautru
  2020-03-04 18:22     ` [dpdk-dev] [PATCH v2 02/15] bbdev: expose device HARQ buffer size at device level Nicolas Chautru
                       ` (13 subsequent siblings)
  14 siblings, 0 replies; 115+ messages in thread
From: Nicolas Chautru @ 2020-03-04 18:22 UTC (permalink / raw)
  To: thomas, akhil.goyal, dev; +Cc: ferruh.yigit, Nic Chautru

From: Nic Chautru <nicolas.chautru@intel.com>

Adding capability flag for device variants when HARQ buffer
may or may not include the filler bits.
Minor cosmetic changes in same file.

Signed-off-by: Nic Chautru <nicolas.chautru@intel.com>
---
 lib/librte_bbdev/rte_bbdev.h    |  2 ++
 lib/librte_bbdev/rte_bbdev_op.h | 12 ++++++++++--
 2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/lib/librte_bbdev/rte_bbdev.h b/lib/librte_bbdev/rte_bbdev.h
index 591fb79..b2da190 100644
--- a/lib/librte_bbdev/rte_bbdev.h
+++ b/lib/librte_bbdev/rte_bbdev.h
@@ -607,6 +607,7 @@ struct __rte_cache_aligned rte_bbdev {
  * @param ops
  *   Pointer array where operations will be dequeued to. Must have at least
  *   @p num_ops entries
+ *   ie. A pointer to a table of void * pointers (ops) that will be filled.
  * @param num_ops
  *   The maximum number of operations to dequeue.
  *
@@ -638,6 +639,7 @@ struct __rte_cache_aligned rte_bbdev {
  * @param ops
  *   Pointer array where operations will be dequeued to. Must have at least
  *   @p num_ops entries
+ *   ie. A pointer to a table of void * pointers (ops) that will be filled.
  * @param num_ops
  *   The maximum number of operations to dequeue.
  *
diff --git a/lib/librte_bbdev/rte_bbdev_op.h b/lib/librte_bbdev/rte_bbdev_op.h
index 1e119a7..062f9ff 100644
--- a/lib/librte_bbdev/rte_bbdev_op.h
+++ b/lib/librte_bbdev/rte_bbdev_op.h
@@ -31,8 +31,11 @@
 #define RTE_BBDEV_TURBO_MAX_TB_SIZE (391656)
 /* Maximum size of Code Block (36.212, Table 5.1.3-3) */
 #define RTE_BBDEV_TURBO_MAX_CB_SIZE (6144)
-/* Maximum size of Code Block  */
+/* Maximum size of Code Block */
 #define RTE_BBDEV_LDPC_MAX_CB_SIZE (8448)
+/* Minimum size of Code Block */
+#define RTE_BBDEV_LDPC_MIN_CB_SIZE (40)
+
 /* Minimum size of Code Block (36.212, Table 5.1.3-3) */
 #define RTE_BBDEV_TURBO_MIN_CB_SIZE (40)
 /* Maximum size of circular buffer */
@@ -177,7 +180,12 @@ enum rte_bbdev_op_ldpcdec_flag_bitmasks {
 	/** Set if a device supports loop-back access to
 	 *  HARQ internal memory. Intended for troubleshooting.
 	 */
-	RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK = (1ULL << 17)
+	RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK = (1ULL << 17),
+	/** Set if a device includes LLR filler bits in the circular buffer
+	 *  for HARQ memory. If not set, it is assumed the filler are not in
+	 *  HARQ memory and handled directory by the LDPC decoder.
+	 */
+	RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_FILLERS = (1ULL << 18)
 };
 
 /** Flags for LDPC encoder operation and capability structure */
-- 
1.8.3.1


^ permalink raw reply	[flat|nested] 115+ messages in thread

* [dpdk-dev] [PATCH v2 02/15] bbdev: expose device HARQ buffer size at device level
  2020-03-04 18:22   ` [dpdk-dev] [PATCH v2 00/15] bbdev new features Nicolas Chautru
  2020-03-04 18:22     ` [dpdk-dev] [PATCH v2 01/15] bbdev: add capability flag for filler bits inclusion in HARQ Nicolas Chautru
@ 2020-03-04 18:22     ` Nicolas Chautru
  2020-03-04 18:22     ` [dpdk-dev] [PATCH v2 03/15] baseband/turbo_sw: fix the exposed LLR decimals assumption Nicolas Chautru
                       ` (12 subsequent siblings)
  14 siblings, 0 replies; 115+ messages in thread
From: Nicolas Chautru @ 2020-03-04 18:22 UTC (permalink / raw)
  To: thomas, akhil.goyal, dev; +Cc: ferruh.yigit, Nic Chautru

From: Nic Chautru <nicolas.chautru@intel.com>

This exposes the HARQ buffer size at the device driver level
instead of using the capability of a specific operation.

This is currently not yet used by a device until
future commit.

Signed-off-by: Nic Chautru <nicolas.chautru@intel.com>
---
 drivers/baseband/turbo_sw/bbdev_turbo_software.c | 2 +-
 lib/librte_bbdev/rte_bbdev.h                     | 2 ++
 lib/librte_bbdev/rte_bbdev_op.h                  | 2 --
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/baseband/turbo_sw/bbdev_turbo_software.c b/drivers/baseband/turbo_sw/bbdev_turbo_software.c
index f2fe7a2..6d5e080 100644
--- a/drivers/baseband/turbo_sw/bbdev_turbo_software.c
+++ b/drivers/baseband/turbo_sw/bbdev_turbo_software.c
@@ -219,7 +219,6 @@ struct turbo_sw_queue {
 					RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE,
 			.llr_size = 8,
 			.llr_decimals = 2,
-			.harq_memory_size = 0,
 			.num_buffers_src =
 					RTE_BBDEV_LDPC_MAX_CODE_BLOCKS,
 			.num_buffers_hard_out =
@@ -251,6 +250,7 @@ struct turbo_sw_queue {
 	dev_info->default_queue_conf = default_queue_conf;
 	dev_info->capabilities = bbdev_capabilities;
 	dev_info->min_alignment = 64;
+	dev_info->harq_buffer_size = 0;
 
 	rte_bbdev_log_debug("got device info from %u\n", dev->data->dev_id);
 }
diff --git a/lib/librte_bbdev/rte_bbdev.h b/lib/librte_bbdev/rte_bbdev.h
index b2da190..38d9d50 100644
--- a/lib/librte_bbdev/rte_bbdev.h
+++ b/lib/librte_bbdev/rte_bbdev.h
@@ -307,6 +307,8 @@ struct rte_bbdev_driver_info {
 	bool queue_intr_supported;
 	/** Minimum alignment of buffers, in bytes */
 	uint16_t min_alignment;
+	/** HARQ memory available in kB */
+	uint32_t harq_buffer_size;
 	/** Default queue configuration used if none is supplied  */
 	struct rte_bbdev_queue_conf default_queue_conf;
 	/** Device operation capabilities */
diff --git a/lib/librte_bbdev/rte_bbdev_op.h b/lib/librte_bbdev/rte_bbdev_op.h
index 062f9ff..8122089 100644
--- a/lib/librte_bbdev/rte_bbdev_op.h
+++ b/lib/librte_bbdev/rte_bbdev_op.h
@@ -712,8 +712,6 @@ struct rte_bbdev_op_cap_ldpc_dec {
 	int8_t llr_size;
 	/** LLR numbers of decimals bit for arithmetic representation */
 	int8_t llr_decimals;
-	/** Amount of memory for HARQ in external DDR in MB */
-	uint16_t harq_memory_size;
 	/** Num input code block buffers */
 	uint16_t num_buffers_src;
 	/** Num hard output code block buffers */
-- 
1.8.3.1


^ permalink raw reply	[flat|nested] 115+ messages in thread

* [dpdk-dev] [PATCH v2 03/15] baseband/turbo_sw: fix the exposed LLR decimals assumption
  2020-03-04 18:22   ` [dpdk-dev] [PATCH v2 00/15] bbdev new features Nicolas Chautru
  2020-03-04 18:22     ` [dpdk-dev] [PATCH v2 01/15] bbdev: add capability flag for filler bits inclusion in HARQ Nicolas Chautru
  2020-03-04 18:22     ` [dpdk-dev] [PATCH v2 02/15] bbdev: expose device HARQ buffer size at device level Nicolas Chautru
@ 2020-03-04 18:22     ` Nicolas Chautru
  2020-03-04 18:22     ` [dpdk-dev] [PATCH v2 04/15] baseband/turbo_sw: support large size code block Nicolas Chautru
                       ` (11 subsequent siblings)
  14 siblings, 0 replies; 115+ messages in thread
From: Nicolas Chautru @ 2020-03-04 18:22 UTC (permalink / raw)
  To: thomas, akhil.goyal, dev; +Cc: ferruh.yigit, Nic Chautru

From: Nic Chautru <nicolas.chautru@intel.com>

The actual LLR representation was incorrectly assumed to be 2
instead of 4. This would impact wireless performance but is not
critical to be back ported on LTS branches.

Fixes: c769c711757a ("baseband/turbo_sw: extend for 5G")

Signed-off-by: Nic Chautru <nicolas.chautru@intel.com>
---
 drivers/baseband/turbo_sw/bbdev_turbo_software.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/baseband/turbo_sw/bbdev_turbo_software.c b/drivers/baseband/turbo_sw/bbdev_turbo_software.c
index 6d5e080..5ca8ca1 100644
--- a/drivers/baseband/turbo_sw/bbdev_turbo_software.c
+++ b/drivers/baseband/turbo_sw/bbdev_turbo_software.c
@@ -218,7 +218,7 @@ struct turbo_sw_queue {
 					RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE |
 					RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE,
 			.llr_size = 8,
-			.llr_decimals = 2,
+			.llr_decimals = 4,
 			.num_buffers_src =
 					RTE_BBDEV_LDPC_MAX_CODE_BLOCKS,
 			.num_buffers_hard_out =
-- 
1.8.3.1


^ permalink raw reply	[flat|nested] 115+ messages in thread

* [dpdk-dev] [PATCH v2 04/15] baseband/turbo_sw: support large size code block
  2020-03-04 18:22   ` [dpdk-dev] [PATCH v2 00/15] bbdev new features Nicolas Chautru
                       ` (2 preceding siblings ...)
  2020-03-04 18:22     ` [dpdk-dev] [PATCH v2 03/15] baseband/turbo_sw: fix the exposed LLR decimals assumption Nicolas Chautru
@ 2020-03-04 18:22     ` Nicolas Chautru
  2020-03-04 18:22     ` [dpdk-dev] [PATCH v2 05/15] test-bbdev: rename FPGA LTE macros to be more explicit Nicolas Chautru
                       ` (10 subsequent siblings)
  14 siblings, 0 replies; 115+ messages in thread
From: Nicolas Chautru @ 2020-03-04 18:22 UTC (permalink / raw)
  To: thomas, akhil.goyal, dev; +Cc: ferruh.yigit, Nic Chautru

From: Nic Chautru <nicolas.chautru@intel.com>

This is to support cases when the input data for
decoding a code block is larger than 64kB and would
not fit as a contiguous block of data into one
mbuf. In that case the length from the opearation
supersedes the mbug default structure.

Signed-off-by: Nic Chautru <nicolas.chautru@intel.com>
---
 app/test-bbdev/test_bbdev_perf.c                 | 40 +++++++++++++++++++-----
 drivers/baseband/turbo_sw/bbdev_turbo_software.c | 11 ++++---
 2 files changed, 39 insertions(+), 12 deletions(-)

diff --git a/app/test-bbdev/test_bbdev_perf.c b/app/test-bbdev/test_bbdev_perf.c
index d8db58e..d46966d 100644
--- a/app/test-bbdev/test_bbdev_perf.c
+++ b/app/test-bbdev/test_bbdev_perf.c
@@ -764,6 +764,7 @@ typedef int (test_case_function)(struct active_device *ad,
 {
 	int ret;
 	unsigned int i, j;
+	bool large_input = false;
 
 	for (i = 0; i < n; ++i) {
 		char *data;
@@ -774,24 +775,47 @@ typedef int (test_case_function)(struct active_device *ad,
 				op_type, n * ref_entries->nb_segments,
 				mbuf_pool->size);
 
-		TEST_ASSERT_SUCCESS(((seg->length + RTE_PKTMBUF_HEADROOM) >
-				(uint32_t)UINT16_MAX),
-				"Given data is bigger than allowed mbuf segment size");
-
+		if (seg->length > 64000) {
+			/*
+			 * Special case when DPDK mbuf cannot handle
+			 * the required input size
+			 */
+			printf("Warning: Larger input size than DPDK mbuf %d\n",
+					seg->length);
+			large_input = true;
+		} else {
+			TEST_ASSERT_SUCCESS(
+					((seg->length + RTE_PKTMBUF_HEADROOM)
+					> (uint32_t)UINT16_MAX),
+					"Given data is bigger than allowed mbuf segment size"
+					);
+		}
 		bufs[i].data = m_head;
 		bufs[i].offset = 0;
 		bufs[i].length = 0;
 
 		if ((op_type == DATA_INPUT) || (op_type == DATA_HARQ_INPUT)) {
-			data = rte_pktmbuf_append(m_head, seg->length);
-			TEST_ASSERT_NOT_NULL(data,
+			if ((op_type == DATA_INPUT) && large_input) {
+				/* Allocate a fake overused mbuf */
+				data = rte_malloc(NULL, 128 * 1024, 0);
+				memcpy(data, seg->addr, seg->length);
+				m_head->buf_addr = data;
+				m_head->buf_iova = rte_mem_virt2phy(data);
+				m_head->data_off = 0;
+				m_head->data_len = seg->length;
+			} else {
+				data = rte_pktmbuf_append(m_head, seg->length);
+				TEST_ASSERT_NOT_NULL(data,
 					"Couldn't append %u bytes to mbuf from %d data type mbuf pool",
 					seg->length, op_type);
 
-			TEST_ASSERT(data == RTE_PTR_ALIGN(data, min_alignment),
+				TEST_ASSERT(data == RTE_PTR_ALIGN(
+						data, min_alignment),
 					"Data addr in mbuf (%p) is not aligned to device min alignment (%u)",
 					data, min_alignment);
-			rte_memcpy(data, seg->addr, seg->length);
+				rte_memcpy(data, seg->addr, seg->length);
+			}
+
 			bufs[i].length += seg->length;
 
 			for (j = 1; j < ref_entries->nb_segments; ++j) {
diff --git a/drivers/baseband/turbo_sw/bbdev_turbo_software.c b/drivers/baseband/turbo_sw/bbdev_turbo_software.c
index 5ca8ca1..ea3fecb 100644
--- a/drivers/baseband/turbo_sw/bbdev_turbo_software.c
+++ b/drivers/baseband/turbo_sw/bbdev_turbo_software.c
@@ -1335,7 +1335,7 @@ struct turbo_sw_queue {
 
 static inline void
 process_ldpc_dec_cb(struct turbo_sw_queue *q, struct rte_bbdev_dec_op *op,
-		uint8_t c, uint16_t out_length, uint16_t e,
+		uint8_t c, uint16_t out_length, uint32_t e,
 		struct rte_mbuf *m_in,
 		struct rte_mbuf *m_out_head, struct rte_mbuf *m_out,
 		struct rte_mbuf *m_harq_in,
@@ -1617,8 +1617,8 @@ struct turbo_sw_queue {
 		struct rte_bbdev_stats *queue_stats)
 {
 	uint8_t c, r = 0;
-	uint16_t e, out_length;
-	uint16_t crc24_overlap = 0;
+	uint32_t e;
+	uint16_t out_length, crc24_overlap = 0;
 	struct rte_bbdev_op_ldpc_dec *dec = &op->ldpc_dec;
 	struct rte_mbuf *m_in = dec->input.data;
 	struct rte_mbuf *m_harq_in = dec->harq_combined_input.data;
@@ -1661,7 +1661,10 @@ struct turbo_sw_queue {
 			e = (r < dec->tb_params.cab) ?
 				dec->tb_params.ea : dec->tb_params.eb;
 
-		seg_total_left = rte_pktmbuf_data_len(m_in) - in_offset;
+		if (e < 64000) /* Special case handling when overusing mbuf */
+			seg_total_left = rte_pktmbuf_data_len(m_in) - in_offset;
+		else
+			seg_total_left = e;
 
 		process_ldpc_dec_cb(q, op, c, out_length, e,
 				m_in, m_out_head, m_out,
-- 
1.8.3.1


^ permalink raw reply	[flat|nested] 115+ messages in thread

* [dpdk-dev] [PATCH v2 05/15] test-bbdev: rename FPGA LTE macros to be more explicit
  2020-03-04 18:22   ` [dpdk-dev] [PATCH v2 00/15] bbdev new features Nicolas Chautru
                       ` (3 preceding siblings ...)
  2020-03-04 18:22     ` [dpdk-dev] [PATCH v2 04/15] baseband/turbo_sw: support large size code block Nicolas Chautru
@ 2020-03-04 18:22     ` Nicolas Chautru
  2020-03-04 18:22     ` [dpdk-dev] [PATCH v2 06/15] test-bbdev: support HARQ validation Nicolas Chautru
                       ` (9 subsequent siblings)
  14 siblings, 0 replies; 115+ messages in thread
From: Nicolas Chautru @ 2020-03-04 18:22 UTC (permalink / raw)
  To: thomas, akhil.goyal, dev; +Cc: ferruh.yigit, Nic Chautru

From: Nic Chautru <nicolas.chautru@intel.com>

Self-contained and cosmetic renaming of macro
so that to be more explict for future extension.

Signed-off-by: Nic Chautru <nicolas.chautru@intel.com>
---
 app/test-bbdev/test_bbdev_perf.c | 51 +++++++++++++++-------------------------
 1 file changed, 19 insertions(+), 32 deletions(-)

diff --git a/app/test-bbdev/test_bbdev_perf.c b/app/test-bbdev/test_bbdev_perf.c
index d46966d..aa8bb71 100644
--- a/app/test-bbdev/test_bbdev_perf.c
+++ b/app/test-bbdev/test_bbdev_perf.c
@@ -18,10 +18,6 @@
 #include <rte_hexdump.h>
 #include <rte_interrupts.h>
 
-#ifdef RTE_LIBRTE_PMD_BBDEV_FPGA_LTE_FEC
-#include <fpga_lte_fec.h>
-#endif
-
 #include "main.h"
 #include "test_bbdev_vector.h"
 
@@ -31,15 +27,16 @@
 #define TEST_REPETITIONS 1000
 
 #ifdef RTE_LIBRTE_PMD_BBDEV_FPGA_LTE_FEC
-#define FPGA_PF_DRIVER_NAME ("intel_fpga_lte_fec_pf")
-#define FPGA_VF_DRIVER_NAME ("intel_fpga_lte_fec_vf")
-#define VF_UL_QUEUE_VALUE 4
-#define VF_DL_QUEUE_VALUE 4
-#define UL_BANDWIDTH 3
-#define DL_BANDWIDTH 3
-#define UL_LOAD_BALANCE 128
-#define DL_LOAD_BALANCE 128
-#define FLR_TIMEOUT 610
+#include <fpga_lte_fec.h>
+#define FPGA_LTE_PF_DRIVER_NAME ("intel_fpga_lte_fec_pf")
+#define FPGA_LTE_VF_DRIVER_NAME ("intel_fpga_lte_fec_vf")
+#define VF_UL_4G_QUEUE_VALUE 4
+#define VF_DL_4G_QUEUE_VALUE 4
+#define UL_4G_BANDWIDTH 3
+#define DL_4G_BANDWIDTH 3
+#define UL_4G_LOAD_BALANCE 128
+#define DL_4G_LOAD_BALANCE 128
+#define FLR_4G_TIMEOUT 610
 #endif
 
 #define OPS_CACHE_SIZE 256U
@@ -521,11 +518,11 @@ typedef int (test_case_function)(struct active_device *ad,
  */
 #ifdef RTE_LIBRTE_PMD_BBDEV_FPGA_LTE_FEC
 	if ((get_init_device() == true) &&
-		(!strcmp(info->drv.driver_name, FPGA_PF_DRIVER_NAME))) {
+		(!strcmp(info->drv.driver_name, FPGA_LTE_PF_DRIVER_NAME))) {
 		struct fpga_lte_fec_conf conf;
 		unsigned int i;
 
-		printf("Configure FPGA FEC Driver %s with default values\n",
+		printf("Configure FPGA LTE FEC Driver %s with default values\n",
 				info->drv.driver_name);
 
 		/* clear default configuration before initialization */
@@ -539,22 +536,22 @@ typedef int (test_case_function)(struct active_device *ad,
 
 		for (i = 0; i < FPGA_LTE_FEC_NUM_VFS; ++i) {
 			/* Number of UL queues per VF (fpga supports 8 VFs) */
-			conf.vf_ul_queues_number[i] = VF_UL_QUEUE_VALUE;
+			conf.vf_ul_queues_number[i] = VF_UL_4G_QUEUE_VALUE;
 			/* Number of DL queues per VF (fpga supports 8 VFs) */
-			conf.vf_dl_queues_number[i] = VF_DL_QUEUE_VALUE;
+			conf.vf_dl_queues_number[i] = VF_DL_4G_QUEUE_VALUE;
 		}
 
 		/* UL bandwidth. Needed for schedule algorithm */
-		conf.ul_bandwidth = UL_BANDWIDTH;
+		conf.ul_bandwidth = UL_4G_BANDWIDTH;
 		/* DL bandwidth */
-		conf.dl_bandwidth = DL_BANDWIDTH;
+		conf.dl_bandwidth = DL_4G_BANDWIDTH;
 
 		/* UL & DL load Balance Factor to 64 */
-		conf.ul_load_balance = UL_LOAD_BALANCE;
-		conf.dl_load_balance = DL_LOAD_BALANCE;
+		conf.ul_load_balance = UL_4G_LOAD_BALANCE;
+		conf.dl_load_balance = DL_4G_LOAD_BALANCE;
 
 		/**< FLR timeout value */
-		conf.flr_time_out = FLR_TIMEOUT;
+		conf.flr_time_out = FLR_4G_TIMEOUT;
 
 		/* setup FPGA PF with configuration information */
 		ret = fpga_lte_fec_configure(info->dev_name, &conf);
@@ -2862,11 +2859,6 @@ typedef int (test_case_function)(struct active_device *ad,
 
 		start_time = rte_rdtsc_precise();
 
-		/*
-		 * printf("Latency Debug %d\n",
-		 * ops_enq[0]->ldpc_enc.cb_params.z_c); REMOVEME
-		 */
-
 		enq = rte_bbdev_enqueue_ldpc_enc_ops(dev_id, queue_id,
 				&ops_enq[enq], burst_sz);
 		TEST_ASSERT(enq == burst_sz,
@@ -2892,11 +2884,6 @@ typedef int (test_case_function)(struct active_device *ad,
 			TEST_ASSERT_SUCCESS(ret, "Validation failed!");
 		}
 
-		/*
-		 * printf("Ready to free - deq %d num_to_process %d\n", FIXME
-		 *		deq, num_to_process);
-		 * printf("cache %d\n", ops_enq[0]->mempool->cache_size);
-		 */
 		rte_bbdev_enc_op_free_bulk(ops_enq, deq);
 		dequeued += deq;
 	}
-- 
1.8.3.1


^ permalink raw reply	[flat|nested] 115+ messages in thread

* [dpdk-dev] [PATCH v2 06/15] test-bbdev: support HARQ validation
  2020-03-04 18:22   ` [dpdk-dev] [PATCH v2 00/15] bbdev new features Nicolas Chautru
                       ` (4 preceding siblings ...)
  2020-03-04 18:22     ` [dpdk-dev] [PATCH v2 05/15] test-bbdev: rename FPGA LTE macros to be more explicit Nicolas Chautru
@ 2020-03-04 18:22     ` Nicolas Chautru
  2020-03-04 18:22     ` [dpdk-dev] [PATCH v2 07/15] test-bbdev: support for performance tests Nicolas Chautru
                       ` (8 subsequent siblings)
  14 siblings, 0 replies; 115+ messages in thread
From: Nicolas Chautru @ 2020-03-04 18:22 UTC (permalink / raw)
  To: thomas, akhil.goyal, dev; +Cc: ferruh.yigit, Nic Chautru

From: Nic Chautru <nicolas.chautru@intel.com>

Adding functionality to validate HARQ for different
devices implementation.
Adding capacity to fetch HARQ data when required as
part of this validation.

Signed-off-by: Nic Chautru <nicolas.chautru@intel.com>
---
 app/test-bbdev/test_bbdev_perf.c   | 552 ++++++++++++++++++++++++++++++++-----
 app/test-bbdev/test_bbdev_vector.c |   9 +-
 2 files changed, 492 insertions(+), 69 deletions(-)

diff --git a/app/test-bbdev/test_bbdev_perf.c b/app/test-bbdev/test_bbdev_perf.c
index aa8bb71..978ccd6 100644
--- a/app/test-bbdev/test_bbdev_perf.c
+++ b/app/test-bbdev/test_bbdev_perf.c
@@ -44,14 +44,25 @@
 
 #define SYNC_WAIT 0
 #define SYNC_START 1
+#define INVALID_OPAQUE -1
 
 #define INVALID_QUEUE_ID -1
+/* Increment for next code block in external HARQ memory */
+#define HARQ_INCR 32768
+/* Headroom for filler LLRs insertion in HARQ buffer */
+#define FILLER_HEADROOM 1024
 
 static struct test_bbdev_vector test_vector;
 
 /* Switch between PMD and Interrupt for throughput TC */
 static bool intr_enabled;
 
+/* LLR arithmetic representation for numerical conversion */
+static int ldpc_llr_decimals;
+static int ldpc_llr_size;
+/* Keep track of the LDPC decoder device capability flag */
+static uint32_t ldpc_cap_flags;
+
 /* Represents tested active devices */
 static struct active_device {
 	const char *driver_name;
@@ -293,7 +304,7 @@ typedef int (test_case_function)(struct active_device *ad,
 				return TEST_FAILED;
 			}
 			if (intr_enabled && !(cap->capability_flags &
-					RTE_BBDEV_TURBO_ENC_INTERRUPTS)) {
+					RTE_BBDEV_LDPC_ENC_INTERRUPTS)) {
 				printf(
 					"Dequeue interrupts are not supported!\n");
 				return TEST_FAILED;
@@ -336,12 +347,19 @@ typedef int (test_case_function)(struct active_device *ad,
 				return TEST_FAILED;
 			}
 			if (intr_enabled && !(cap->capability_flags &
-					RTE_BBDEV_TURBO_DEC_INTERRUPTS)) {
+					RTE_BBDEV_LDPC_DEC_INTERRUPTS)) {
 				printf(
 					"Dequeue interrupts are not supported!\n");
 				return TEST_FAILED;
 			}
-
+			if (intr_enabled && (test_vector.ldpc_dec.op_flags &
+				(RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE |
+				RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE |
+				RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK
+					))) {
+				printf("Skip loop-back with interrupt\n");
+				return TEST_FAILED;
+			}
 			return TEST_SUCCESS;
 		}
 	}
@@ -377,7 +395,8 @@ typedef int (test_case_function)(struct active_device *ad,
 	snprintf(pool_name, sizeof(pool_name), "%s_pool_%u", op_type_str,
 			dev_id);
 	return rte_pktmbuf_pool_create(pool_name, mbuf_pool_size, 0, 0,
-			RTE_MAX(max_seg_sz + RTE_PKTMBUF_HEADROOM,
+			RTE_MAX(max_seg_sz + RTE_PKTMBUF_HEADROOM
+					+ FILLER_HEADROOM,
 			(unsigned int)RTE_MBUF_DEFAULT_BUF_SIZE), socket_id);
 }
 
@@ -432,27 +451,33 @@ typedef int (test_case_function)(struct active_device *ad,
 		return TEST_SUCCESS;
 
 	/* Inputs */
-	mbuf_pool_size = optimal_mempool_size(ops_pool_size * in->nb_segments);
-	mp = create_mbuf_pool(in, ad->dev_id, socket_id, mbuf_pool_size, "in");
-	TEST_ASSERT_NOT_NULL(mp,
-			"ERROR Failed to create %u items input pktmbuf pool for dev %u on socket %u.",
-			mbuf_pool_size,
-			ad->dev_id,
-			socket_id);
-	ad->in_mbuf_pool = mp;
+	if (in->nb_segments > 0) {
+		mbuf_pool_size = optimal_mempool_size(ops_pool_size *
+				in->nb_segments);
+		mp = create_mbuf_pool(in, ad->dev_id, socket_id,
+				mbuf_pool_size, "in");
+		TEST_ASSERT_NOT_NULL(mp,
+				"ERROR Failed to create %u items input pktmbuf pool for dev %u on socket %u.",
+				mbuf_pool_size,
+				ad->dev_id,
+				socket_id);
+		ad->in_mbuf_pool = mp;
+	}
 
 	/* Hard outputs */
-	mbuf_pool_size = optimal_mempool_size(ops_pool_size *
-			hard_out->nb_segments);
-	mp = create_mbuf_pool(hard_out, ad->dev_id, socket_id, mbuf_pool_size,
-			"hard_out");
-	TEST_ASSERT_NOT_NULL(mp,
-			"ERROR Failed to create %u items hard output pktmbuf pool for dev %u on socket %u.",
-			mbuf_pool_size,
-			ad->dev_id,
-			socket_id);
-	ad->hard_out_mbuf_pool = mp;
-
+	if (hard_out->nb_segments > 0) {
+		mbuf_pool_size = optimal_mempool_size(ops_pool_size *
+				hard_out->nb_segments);
+		mp = create_mbuf_pool(hard_out, ad->dev_id, socket_id,
+				mbuf_pool_size,
+				"hard_out");
+		TEST_ASSERT_NOT_NULL(mp,
+				"ERROR Failed to create %u items hard output pktmbuf pool for dev %u on socket %u.",
+				mbuf_pool_size,
+				ad->dev_id,
+				socket_id);
+		ad->hard_out_mbuf_pool = mp;
+	}
 
 	/* Soft outputs */
 	if (soft_out->nb_segments > 0) {
@@ -907,6 +932,45 @@ typedef int (test_case_function)(struct active_device *ad,
 	}
 }
 
+/*
+ * We may have to insert filler bits
+ * when they are required by the HARQ assumption
+ */
+static void
+ldpc_add_filler(struct rte_bbdev_op_data *input_ops,
+		const uint16_t n, struct test_op_params *op_params)
+{
+	struct rte_bbdev_op_ldpc_dec dec = op_params->ref_dec_op->ldpc_dec;
+
+	if (input_ops == NULL)
+		return;
+	/* No need to add filler if not required by device */
+	if (!(ldpc_cap_flags &
+			RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_FILLERS))
+		return;
+	/* No need to add filler for loopback operation */
+	if (dec.op_flags & RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK)
+		return;
+
+	uint16_t i, j, parity_offset;
+	for (i = 0; i < n; ++i) {
+		struct rte_mbuf *m = input_ops[i].data;
+		int8_t *llr = rte_pktmbuf_mtod_offset(m, int8_t *,
+				input_ops[i].offset);
+		parity_offset = (dec.basegraph == 1 ? 20 : 8)
+				* dec.z_c - dec.n_filler;
+		uint16_t new_hin_size = input_ops[i].length + dec.n_filler;
+		m->data_len = new_hin_size;
+		input_ops[i].length = new_hin_size;
+		for (j = new_hin_size - 1; j >= parity_offset + dec.n_filler;
+				j--)
+			llr[j] = llr[j - dec.n_filler];
+		uint16_t llr_max_pre_scaling = (1 << (ldpc_llr_size - 1)) - 1;
+		for (j = 0; j < dec.n_filler; j++)
+			llr[parity_offset + j] = llr_max_pre_scaling;
+	}
+}
+
 static void
 ldpc_input_llr_scaling(struct rte_bbdev_op_data *input_ops,
 		const uint16_t n, const int8_t llr_size,
@@ -929,7 +993,9 @@ typedef int (test_case_function)(struct active_device *ad,
 					++byte_idx) {
 
 				llr_tmp = llr[byte_idx];
-				if (llr_decimals == 2)
+				if (llr_decimals == 4)
+					llr_tmp *= 8;
+				else if (llr_decimals == 2)
 					llr_tmp *= 2;
 				else if (llr_decimals == 0)
 					llr_tmp /= 2;
@@ -997,12 +1063,24 @@ typedef int (test_case_function)(struct active_device *ad,
 			capabilities->cap.turbo_dec.max_llr_modulus);
 
 	if (test_vector.op_type == RTE_BBDEV_OP_LDPC_DEC) {
-		ldpc_input_llr_scaling(*queue_ops[DATA_INPUT], n,
-			capabilities->cap.ldpc_dec.llr_size,
-			capabilities->cap.ldpc_dec.llr_decimals);
-		ldpc_input_llr_scaling(*queue_ops[DATA_HARQ_INPUT], n,
-				capabilities->cap.ldpc_dec.llr_size,
-				capabilities->cap.ldpc_dec.llr_decimals);
+		bool loopback = op_params->ref_dec_op->ldpc_dec.op_flags &
+				RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK;
+		bool llr_comp = op_params->ref_dec_op->ldpc_dec.op_flags &
+				RTE_BBDEV_LDPC_LLR_COMPRESSION;
+		bool harq_comp = op_params->ref_dec_op->ldpc_dec.op_flags &
+				RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION;
+		ldpc_llr_decimals = capabilities->cap.ldpc_dec.llr_decimals;
+		ldpc_llr_size = capabilities->cap.ldpc_dec.llr_size;
+		ldpc_cap_flags = capabilities->cap.ldpc_dec.capability_flags;
+		if (!loopback && !llr_comp)
+			ldpc_input_llr_scaling(*queue_ops[DATA_INPUT], n,
+					ldpc_llr_size, ldpc_llr_decimals);
+		if (!loopback && !harq_comp)
+			ldpc_input_llr_scaling(*queue_ops[DATA_HARQ_INPUT], n,
+					ldpc_llr_size, ldpc_llr_decimals);
+		if (!loopback)
+			ldpc_add_filler(*queue_ops[DATA_HARQ_INPUT], n,
+					op_params);
 	}
 
 	return 0;
@@ -1165,17 +1243,21 @@ typedef int (test_case_function)(struct active_device *ad,
 		ops[i]->ldpc_dec.op_flags = ldpc_dec->op_flags;
 		ops[i]->ldpc_dec.code_block_mode = ldpc_dec->code_block_mode;
 
-		ops[i]->ldpc_dec.hard_output = hard_outputs[start_idx + i];
-		ops[i]->ldpc_dec.input = inputs[start_idx + i];
+		if (hard_outputs != NULL)
+			ops[i]->ldpc_dec.hard_output =
+					hard_outputs[start_idx + i];
+		if (inputs != NULL)
+			ops[i]->ldpc_dec.input =
+					inputs[start_idx + i];
 		if (soft_outputs != NULL)
 			ops[i]->ldpc_dec.soft_output =
-				soft_outputs[start_idx + i];
+					soft_outputs[start_idx + i];
 		if (harq_inputs != NULL)
 			ops[i]->ldpc_dec.harq_combined_input =
 					harq_inputs[start_idx + i];
 		if (harq_outputs != NULL)
 			ops[i]->ldpc_dec.harq_combined_output =
-				harq_outputs[start_idx + i];
+					harq_outputs[start_idx + i];
 	}
 }
 
@@ -1217,7 +1299,22 @@ typedef int (test_case_function)(struct active_device *ad,
 check_dec_status_and_ordering(struct rte_bbdev_dec_op *op,
 		unsigned int order_idx, const int expected_status)
 {
-	TEST_ASSERT(op->status == expected_status,
+	int status = op->status;
+	/* ignore parity mismatch false alarms for long iterations */
+	{
+		if (!(expected_status & (1 << RTE_BBDEV_SYNDROME_ERROR)) &&
+				(status & (1 << RTE_BBDEV_SYNDROME_ERROR))) {
+			printf("WARNING: Ignore Syndrome Check mismatch\n");
+			status -= (1 << RTE_BBDEV_SYNDROME_ERROR);
+		}
+		if ((expected_status & (1 << RTE_BBDEV_SYNDROME_ERROR)) &&
+				!(status & (1 << RTE_BBDEV_SYNDROME_ERROR))) {
+			printf("WARNING: Ignore Syndrome Check mismatch\n");
+			status += (1 << RTE_BBDEV_SYNDROME_ERROR);
+		}
+	}
+
+	TEST_ASSERT(status == expected_status,
 			"op_status (%d) != expected_status (%d)",
 			op->status, expected_status);
 
@@ -1236,9 +1333,10 @@ typedef int (test_case_function)(struct active_device *ad,
 			"op_status (%d) != expected_status (%d)",
 			op->status, expected_status);
 
-	TEST_ASSERT((void *)(uintptr_t)order_idx == op->opaque_data,
-			"Ordering error, expected %p, got %p",
-			(void *)(uintptr_t)order_idx, op->opaque_data);
+	if (op->opaque_data != (void *)(uintptr_t)INVALID_OPAQUE)
+		TEST_ASSERT((void *)(uintptr_t)order_idx == op->opaque_data,
+				"Ordering error, expected %p, got %p",
+				(void *)(uintptr_t)order_idx, op->opaque_data);
 
 	return TEST_SUCCESS;
 }
@@ -1282,6 +1380,170 @@ typedef int (test_case_function)(struct active_device *ad,
 	return TEST_SUCCESS;
 }
 
+
+/* Compute K0 for a given configuration for HARQ output length computation */
+static inline uint16_t
+get_k0(uint16_t n_cb, uint16_t z_c, uint8_t basegraph, uint8_t rv_index)
+{
+	if (rv_index == 0)
+		return 0;
+	uint16_t n = (basegraph == 1 ? 66 : 50) * z_c;
+	if (n_cb == n) {
+		if (rv_index == 1)
+			return (basegraph == 1 ? 17 : 13) * z_c;
+		else if (rv_index == 2)
+			return (basegraph == 1 ? 33 : 25) * z_c;
+		else
+			return (basegraph == 1 ? 56 : 43) * z_c;
+	}
+	/* LBRM case - includes a division by N */
+	if (rv_index == 1)
+		return (((basegraph == 1 ? 17 : 13) * n_cb)
+				/ n) * z_c;
+	else if (rv_index == 2)
+		return (((basegraph == 1 ? 33 : 25) * n_cb)
+				/ n) * z_c;
+	else
+		return (((basegraph == 1 ? 56 : 43) * n_cb)
+				/ n) * z_c;
+}
+
+/* HARQ output length including the Filler bits */
+static inline uint16_t
+compute_Harq_Len(struct rte_bbdev_op_ldpc_dec *ops_ld) {
+	uint16_t k0 = 0;
+	uint8_t max_rv = (ops_ld->rv_index == 1) ? 3 : ops_ld->rv_index;
+	k0 = get_k0(ops_ld->n_cb, ops_ld->z_c, ops_ld->basegraph, max_rv);
+	/* Compute RM out size and number of rows */
+	uint16_t parity_offset = (ops_ld->basegraph == 1 ? 20 : 8)
+			* ops_ld->z_c - ops_ld->n_filler;
+	uint16_t deRmOutSize = RTE_MIN(
+			k0 + ops_ld->cb_params.e +
+			((k0 > parity_offset) ?
+					0 : ops_ld->n_filler),
+					ops_ld->n_cb);
+	uint16_t numRows = ((deRmOutSize + ops_ld->z_c - 1)
+			/ ops_ld->z_c);
+	uint16_t harq_output_len = numRows * ops_ld->z_c;
+	return harq_output_len;
+}
+
+static inline int
+validate_op_harq_chain(struct rte_bbdev_op_data *op,
+		struct op_data_entries *orig_op,
+		struct rte_bbdev_op_ldpc_dec *ops_ld)
+{
+	uint8_t i;
+	uint32_t j, jj, k;
+	struct rte_mbuf *m = op->data;
+	uint8_t nb_dst_segments = orig_op->nb_segments;
+	uint32_t total_data_size = 0;
+	int8_t *harq_orig, *harq_out, abs_harq_origin;
+	uint32_t byte_error = 0, cum_error = 0, error;
+	int16_t llr_max = (1 << (ldpc_llr_size - ldpc_llr_decimals)) - 1;
+	int16_t llr_max_pre_scaling = (1 << (ldpc_llr_size - 1)) - 1;
+	uint16_t parity_offset;
+
+	TEST_ASSERT(nb_dst_segments == m->nb_segs,
+			"Number of segments differ in original (%u) and filled (%u) op",
+			nb_dst_segments, m->nb_segs);
+
+	/* Validate each mbuf segment length */
+	for (i = 0; i < nb_dst_segments; ++i) {
+		/* Apply offset to the first mbuf segment */
+		uint16_t offset = (i == 0) ? op->offset : 0;
+		uint16_t data_len = rte_pktmbuf_data_len(m) - offset;
+		total_data_size += orig_op->segments[i].length;
+
+		TEST_ASSERT(orig_op->segments[i].length <
+				(uint32_t)(data_len + 64),
+				"Length of segment differ in original (%u) and filled (%u) op",
+				orig_op->segments[i].length, data_len);
+		harq_orig = (int8_t *) orig_op->segments[i].addr;
+		harq_out = rte_pktmbuf_mtod_offset(m, int8_t *, offset);
+
+		if (!(ldpc_cap_flags &
+				RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_FILLERS
+				) || (ops_ld->op_flags &
+				RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK)) {
+			data_len -= ops_ld->z_c;
+			parity_offset = data_len;
+		} else {
+			/* Compute RM out size and number of rows */
+			parity_offset = (ops_ld->basegraph == 1 ? 20 : 8)
+					* ops_ld->z_c - ops_ld->n_filler;
+			uint16_t deRmOutSize = compute_Harq_Len(ops_ld) -
+					ops_ld->n_filler;
+			if (data_len > deRmOutSize)
+				data_len = deRmOutSize;
+			if (data_len > orig_op->segments[i].length)
+				data_len = orig_op->segments[i].length;
+		}
+		/*
+		 * HARQ output can have minor differences
+		 * due to integer representation and related scaling
+		 */
+		for (j = 0, jj = 0; j < data_len; j++, jj++) {
+			if (j == parity_offset) {
+				/* Special Handling of the filler bits */
+				for (k = 0; k < ops_ld->n_filler; k++) {
+					if (harq_out[jj] !=
+							llr_max_pre_scaling) {
+						printf("HARQ Filler issue %d: %d %d\n",
+							jj, harq_out[jj],
+							llr_max);
+						byte_error++;
+					}
+					jj++;
+				}
+			}
+			if (!(ops_ld->op_flags &
+				RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK)) {
+				if (ldpc_llr_decimals > 1)
+					harq_out[jj] = (harq_out[jj] + 1)
+						>> (ldpc_llr_decimals - 1);
+				/* Saturated to S7 */
+				if (harq_orig[j] > llr_max)
+					harq_orig[j] = llr_max;
+				if (harq_orig[j] < -llr_max)
+					harq_orig[j] = -llr_max;
+			}
+			if (harq_orig[j] != harq_out[jj]) {
+				error = (harq_orig[j] > harq_out[jj]) ?
+						harq_orig[j] - harq_out[jj] :
+						harq_out[jj] - harq_orig[j];
+				abs_harq_origin = harq_orig[j] > 0 ?
+							harq_orig[j] :
+							-harq_orig[j];
+				/* Residual quantization error */
+				if ((error > 8 && (abs_harq_origin <
+						(llr_max - 16))) ||
+						(error > 16)) {
+					printf("HARQ mismatch %d: exp %d act %d => %d\n",
+							j, harq_orig[j],
+							harq_out[jj], error);
+					byte_error++;
+					cum_error += error;
+				}
+			}
+		}
+		m = m->next;
+	}
+
+	if (byte_error)
+		TEST_ASSERT(byte_error <= 1,
+				"HARQ output mismatch (%d) %d",
+				byte_error, cum_error);
+
+	/* Validate total mbuf pkt length */
+	uint32_t pkt_len = rte_pktmbuf_pkt_len(op->data) - op->offset;
+	TEST_ASSERT(total_data_size < pkt_len + 64,
+			"Length of data differ in original (%u) and filled (%u) op",
+			total_data_size, pkt_len);
+
+	return TEST_SUCCESS;
+}
+
 static int
 validate_dec_op(struct rte_bbdev_dec_op **ops, const uint16_t n,
 		struct rte_bbdev_dec_op *ref_op, const int vector_mask)
@@ -1325,7 +1587,6 @@ typedef int (test_case_function)(struct active_device *ad,
 	return TEST_SUCCESS;
 }
 
-
 static int
 validate_ldpc_dec_op(struct rte_bbdev_dec_op **ops, const uint16_t n,
 		struct rte_bbdev_dec_op *ref_op, const int vector_mask)
@@ -1357,8 +1618,15 @@ typedef int (test_case_function)(struct active_device *ad,
 			TEST_ASSERT(ops_td->iter_count <= ref_td->iter_count,
 					"Returned iter_count (%d) > expected iter_count (%d)",
 					ops_td->iter_count, ref_td->iter_count);
-		/* We can ignore data when the decoding failed to converge */
-		if ((ops[i]->status &  (1 << RTE_BBDEV_SYNDROME_ERROR)) == 0)
+		/*
+		 * We can ignore output data when the decoding failed to
+		 * converge or for loop-back cases
+		 */
+		if (!check_bit(ops[i]->ldpc_dec.op_flags,
+				RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK
+				) && (
+				ops[i]->status & (1 << RTE_BBDEV_SYNDROME_ERROR
+						)) == 0)
 			TEST_ASSERT_SUCCESS(validate_op_chain(hard_output,
 					hard_data_orig),
 					"Hard output buffers (CB=%u) are not equal",
@@ -1371,12 +1639,18 @@ typedef int (test_case_function)(struct active_device *ad,
 					i);
 		if (ref_op->ldpc_dec.op_flags &
 				RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE) {
-			ldpc_input_llr_scaling(harq_output, 1, 8, 0);
-			TEST_ASSERT_SUCCESS(validate_op_chain(harq_output,
-					harq_data_orig),
+			TEST_ASSERT_SUCCESS(validate_op_harq_chain(harq_output,
+					harq_data_orig, ops_td),
 					"HARQ output buffers (CB=%u) are not equal",
 					i);
 		}
+		if (ref_op->ldpc_dec.op_flags &
+				RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK)
+			TEST_ASSERT_SUCCESS(validate_op_harq_chain(harq_output,
+					harq_data_orig, ops_td),
+					"HARQ output buffers (CB=%u) are not equal",
+					i);
+
 	}
 
 	return TEST_SUCCESS;
@@ -1715,6 +1989,105 @@ typedef int (test_case_function)(struct active_device *ad,
 	return ret;
 }
 
+
+/* Push back the HARQ output from DDR to host */
+static void
+retrieve_harq_ddr(uint16_t dev_id, uint16_t queue_id,
+		struct rte_bbdev_dec_op **ops,
+		const uint16_t n)
+{
+	uint16_t j;
+	int save_status, ret;
+	uint32_t harq_offset = (uint32_t) queue_id * HARQ_INCR * 1024;
+	struct rte_bbdev_dec_op *ops_deq[MAX_BURST];
+	uint32_t flags = ops[0]->ldpc_dec.op_flags;
+	bool loopback = flags & RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK;
+	bool mem_out = flags & RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_OUT_ENABLE;
+	bool hc_out = flags & RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE;
+	bool h_comp = flags & RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION;
+	for (j = 0; j < n; ++j) {
+		if ((loopback && mem_out) || hc_out) {
+			save_status = ops[j]->status;
+			ops[j]->ldpc_dec.op_flags =
+				RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK +
+				RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_IN_ENABLE;
+			if (h_comp)
+				ops[j]->ldpc_dec.op_flags +=
+					RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION;
+			ops[j]->ldpc_dec.harq_combined_input.offset =
+					harq_offset;
+			ops[j]->ldpc_dec.harq_combined_output.offset = 0;
+			harq_offset += HARQ_INCR;
+			if (!loopback)
+				ops[j]->ldpc_dec.harq_combined_input.length =
+				ops[j]->ldpc_dec.harq_combined_output.length;
+			rte_bbdev_enqueue_ldpc_dec_ops(dev_id, queue_id,
+					&ops[j], 1);
+			ret = 0;
+			while (ret == 0)
+				ret = rte_bbdev_dequeue_ldpc_dec_ops(
+						dev_id, queue_id,
+						&ops_deq[j], 1);
+			ops[j]->ldpc_dec.op_flags = flags;
+			ops[j]->status = save_status;
+		}
+	}
+}
+
+/*
+ * Push back the HARQ output from HW DDR to Host
+ * Preload HARQ memory input and adjust HARQ offset
+ */
+static void
+preload_harq_ddr(uint16_t dev_id, uint16_t queue_id,
+		struct rte_bbdev_dec_op **ops, const uint16_t n,
+		bool preload)
+{
+	uint16_t j;
+	int ret;
+	uint32_t harq_offset = (uint32_t) queue_id * HARQ_INCR * 1024;
+	struct rte_bbdev_op_data save_hc_in, save_hc_out;
+	struct rte_bbdev_dec_op *ops_deq[MAX_BURST];
+	uint32_t flags = ops[0]->ldpc_dec.op_flags;
+	bool mem_in = flags & RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_IN_ENABLE;
+	bool hc_in = flags & RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE;
+	bool mem_out = flags & RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_OUT_ENABLE;
+	bool hc_out = flags & RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE;
+	bool h_comp = flags & RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION;
+	for (j = 0; j < n; ++j) {
+		if ((mem_in || hc_in) && preload) {
+			save_hc_in = ops[j]->ldpc_dec.harq_combined_input;
+			save_hc_out = ops[j]->ldpc_dec.harq_combined_output;
+			ops[j]->ldpc_dec.op_flags =
+				RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK +
+				RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_OUT_ENABLE;
+			if (h_comp)
+				ops[j]->ldpc_dec.op_flags +=
+					RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION;
+			ops[j]->ldpc_dec.harq_combined_output.offset =
+					harq_offset;
+			ops[j]->ldpc_dec.harq_combined_input.offset = 0;
+			rte_bbdev_enqueue_ldpc_dec_ops(dev_id, queue_id,
+					&ops[j], 1);
+			ret = 0;
+			while (ret == 0)
+				ret = rte_bbdev_dequeue_ldpc_dec_ops(
+					dev_id, queue_id, &ops_deq[j], 1);
+			ops[j]->ldpc_dec.op_flags = flags;
+			ops[j]->ldpc_dec.harq_combined_input = save_hc_in;
+			ops[j]->ldpc_dec.harq_combined_output = save_hc_out;
+		}
+		/* Adjust HARQ offset when we reach external DDR */
+		if (mem_in || hc_in)
+			ops[j]->ldpc_dec.harq_combined_input.offset
+				= harq_offset;
+		if (mem_out || hc_out)
+			ops[j]->ldpc_dec.harq_combined_output.offset
+				= harq_offset;
+		harq_offset += HARQ_INCR;
+	}
+}
+
 static void
 dequeue_event_callback(uint16_t dev_id,
 		enum rte_bbdev_event_type event, void *cb_arg,
@@ -1750,13 +2123,22 @@ typedef int (test_case_function)(struct active_device *ad,
 	burst_sz = rte_atomic16_read(&tp->burst_sz);
 	num_ops = tp->op_params->num_to_process;
 
-	if (test_vector.op_type == RTE_BBDEV_OP_TURBO_DEC ||
-			test_vector.op_type == RTE_BBDEV_OP_LDPC_DEC)
+	if (test_vector.op_type == RTE_BBDEV_OP_TURBO_DEC)
 		deq = rte_bbdev_dequeue_dec_ops(dev_id, queue_id,
 				&tp->dec_ops[
 					rte_atomic16_read(&tp->nb_dequeued)],
 				burst_sz);
-	else
+	else if (test_vector.op_type == RTE_BBDEV_OP_LDPC_DEC)
+		deq = rte_bbdev_dequeue_ldpc_dec_ops(dev_id, queue_id,
+				&tp->dec_ops[
+					rte_atomic16_read(&tp->nb_dequeued)],
+				burst_sz);
+	else if (test_vector.op_type == RTE_BBDEV_OP_LDPC_ENC)
+		deq = rte_bbdev_dequeue_ldpc_enc_ops(dev_id, queue_id,
+				&tp->enc_ops[
+					rte_atomic16_read(&tp->nb_dequeued)],
+				burst_sz);
+	else /*RTE_BBDEV_OP_TURBO_ENC*/
 		deq = rte_bbdev_dequeue_enc_ops(dev_id, queue_id,
 				&tp->enc_ops[
 					rte_atomic16_read(&tp->nb_dequeued)],
@@ -2133,6 +2515,12 @@ typedef int (test_case_function)(struct active_device *ad,
 	int i, j, ret;
 	struct rte_bbdev_info info;
 	uint16_t num_to_enq;
+	bool extDdr = check_bit(ldpc_cap_flags,
+			RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_OUT_ENABLE);
+	bool loopback = check_bit(ref_op->ldpc_dec.op_flags,
+			RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK);
+	bool hc_out = check_bit(ref_op->ldpc_dec.op_flags,
+			RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE);
 
 	TEST_ASSERT_SUCCESS((burst_sz > MAX_BURST),
 			"BURST_SIZE should be <= %u", MAX_BURST);
@@ -2170,13 +2558,18 @@ typedef int (test_case_function)(struct active_device *ad,
 
 	for (i = 0; i < TEST_REPETITIONS; ++i) {
 		for (j = 0; j < num_ops; ++j) {
-			mbuf_reset(ops_enq[j]->ldpc_dec.hard_output.data);
-			if (check_bit(ref_op->ldpc_dec.op_flags,
-					RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE))
+			if (!loopback)
+				mbuf_reset(
+				ops_enq[j]->ldpc_dec.hard_output.data);
+			if (hc_out || loopback)
 				mbuf_reset(
 				ops_enq[j]->ldpc_dec.harq_combined_output.data);
 		}
-
+		if (extDdr) {
+			bool preload = i == (TEST_REPETITIONS - 1);
+			preload_harq_ddr(tp->dev_id, queue_id, ops_enq,
+					num_ops, preload);
+		}
 		start_time = rte_rdtsc_precise();
 
 		for (enq = 0, deq = 0; enq < num_ops;) {
@@ -2207,6 +2600,10 @@ typedef int (test_case_function)(struct active_device *ad,
 		tp->iter_count = RTE_MAX(ops_enq[i]->ldpc_dec.iter_count,
 				tp->iter_count);
 	}
+	if (extDdr) {
+		/* Read loopback is not thread safe */
+		retrieve_harq_ddr(tp->dev_id, queue_id, ops_enq, num_ops);
+	}
 
 	if (test_vector.op_type != RTE_BBDEV_OP_NONE) {
 		ret = validate_ldpc_dec_op(ops_deq, num_ops, ref_op,
@@ -2696,6 +3093,8 @@ typedef int (test_case_function)(struct active_device *ad,
 	uint16_t i, j, dequeued;
 	struct rte_bbdev_dec_op *ops_enq[MAX_BURST], *ops_deq[MAX_BURST];
 	uint64_t start_time = 0, last_time = 0;
+	bool extDdr = ldpc_cap_flags &
+			RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_OUT_ENABLE;
 
 	for (i = 0, dequeued = 0; dequeued < num_to_process; ++i) {
 		uint16_t enq = 0, deq = 0;
@@ -2708,6 +3107,15 @@ typedef int (test_case_function)(struct active_device *ad,
 		ret = rte_bbdev_dec_op_alloc_bulk(mempool, ops_enq, burst_sz);
 		TEST_ASSERT_SUCCESS(ret,
 				"rte_bbdev_dec_op_alloc_bulk() failed");
+
+		/* For latency tests we need to disable early termination */
+		if (check_bit(ref_op->ldpc_dec.op_flags,
+				RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE))
+			ref_op->ldpc_dec.op_flags -=
+					RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE;
+		ref_op->ldpc_dec.iter_max = 6;
+		ref_op->ldpc_dec.iter_count = ref_op->ldpc_dec.iter_max;
+
 		if (test_vector.op_type != RTE_BBDEV_OP_NONE)
 			copy_reference_ldpc_dec_op(ops_enq, burst_sz, dequeued,
 					bufs->inputs,
@@ -2717,6 +3125,10 @@ typedef int (test_case_function)(struct active_device *ad,
 					bufs->harq_outputs,
 					ref_op);
 
+		if (extDdr)
+			preload_harq_ddr(dev_id, queue_id, ops_enq,
+					burst_sz, true);
+
 		/* Set counter to validate the ordering */
 		for (j = 0; j < burst_sz; ++j)
 			ops_enq[j]->opaque_data = (void *)(uintptr_t)j;
@@ -2743,6 +3155,9 @@ typedef int (test_case_function)(struct active_device *ad,
 		*min_time = RTE_MIN(*min_time, last_time);
 		*total_time += last_time;
 
+		if (extDdr)
+			retrieve_harq_ddr(dev_id, queue_id, ops_enq, burst_sz);
+
 		if (test_vector.op_type != RTE_BBDEV_OP_NONE) {
 			ret = validate_ldpc_dec_op(ops_deq, burst_sz, ref_op,
 					vector_mask);
@@ -2752,7 +3167,6 @@ typedef int (test_case_function)(struct active_device *ad,
 		rte_bbdev_dec_op_free_bulk(ops_enq, deq);
 		dequeued += deq;
 	}
-
 	return i;
 }
 
@@ -2844,7 +3258,6 @@ typedef int (test_case_function)(struct active_device *ad,
 			burst_sz = num_to_process - dequeued;
 
 		ret = rte_bbdev_enc_op_alloc_bulk(mempool, ops_enq, burst_sz);
-
 		TEST_ASSERT_SUCCESS(ret,
 				"rte_bbdev_enc_op_alloc_bulk() failed");
 		if (test_vector.op_type != RTE_BBDEV_OP_NONE)
@@ -3081,6 +3494,8 @@ typedef int (test_case_function)(struct active_device *ad,
 	uint64_t enq_start_time, deq_start_time;
 	uint64_t enq_sw_last_time, deq_last_time;
 	struct rte_bbdev_stats stats;
+	bool extDdr = ldpc_cap_flags &
+			RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_OUT_ENABLE;
 
 	for (i = 0, dequeued = 0; dequeued < num_to_process; ++i) {
 		uint16_t enq = 0, deq = 0;
@@ -3098,6 +3513,10 @@ typedef int (test_case_function)(struct active_device *ad,
 					bufs->harq_outputs,
 					ref_op);
 
+		if (extDdr)
+			preload_harq_ddr(dev_id, queue_id, ops_enq,
+					burst_sz, true);
+
 		/* Start time meas for enqueue function offload latency */
 		enq_start_time = rte_rdtsc_precise();
 		do {
@@ -3105,13 +3524,13 @@ typedef int (test_case_function)(struct active_device *ad,
 					&ops_enq[enq], burst_sz - enq);
 		} while (unlikely(burst_sz != enq));
 
+		enq_sw_last_time = rte_rdtsc_precise() - enq_start_time;
 		ret = get_bbdev_queue_stats(dev_id, queue_id, &stats);
 		TEST_ASSERT_SUCCESS(ret,
 				"Failed to get stats for queue (%u) of device (%u)",
 				queue_id, dev_id);
 
-		enq_sw_last_time = rte_rdtsc_precise() - enq_start_time -
-				stats.acc_offload_cycles;
+		enq_sw_last_time -= stats.acc_offload_cycles;
 		time_st->enq_sw_max_time = RTE_MAX(time_st->enq_sw_max_time,
 				enq_sw_last_time);
 		time_st->enq_sw_min_time = RTE_MIN(time_st->enq_sw_min_time,
@@ -3144,9 +3563,14 @@ typedef int (test_case_function)(struct active_device *ad,
 
 		/* Dequeue remaining operations if needed*/
 		while (burst_sz != deq)
-			deq += rte_bbdev_dequeue_dec_ops(dev_id, queue_id,
+			deq += rte_bbdev_dequeue_ldpc_dec_ops(dev_id, queue_id,
 					&ops_deq[deq], burst_sz - deq);
 
+		if (extDdr) {
+			/* Read loopback is not thread safe */
+			retrieve_harq_ddr(dev_id, queue_id, ops_enq, burst_sz);
+		}
+
 		rte_bbdev_dec_op_free_bulk(ops_enq, deq);
 		dequeued += deq;
 	}
@@ -3173,7 +3597,8 @@ typedef int (test_case_function)(struct active_device *ad,
 			burst_sz = num_to_process - dequeued;
 
 		ret = rte_bbdev_enc_op_alloc_bulk(mempool, ops_enq, burst_sz);
-		TEST_ASSERT_SUCCESS(ret, "rte_bbdev_op_alloc_bulk() failed");
+		TEST_ASSERT_SUCCESS(ret,
+				"rte_bbdev_enc_op_alloc_bulk() failed");
 		if (test_vector.op_type != RTE_BBDEV_OP_NONE)
 			copy_reference_enc_op(ops_enq, burst_sz, dequeued,
 					bufs->inputs,
@@ -3187,13 +3612,13 @@ typedef int (test_case_function)(struct active_device *ad,
 					&ops_enq[enq], burst_sz - enq);
 		} while (unlikely(burst_sz != enq));
 
+		enq_sw_last_time = rte_rdtsc_precise() - enq_start_time;
+
 		ret = get_bbdev_queue_stats(dev_id, queue_id, &stats);
 		TEST_ASSERT_SUCCESS(ret,
 				"Failed to get stats for queue (%u) of device (%u)",
 				queue_id, dev_id);
-
-		enq_sw_last_time = rte_rdtsc_precise() - enq_start_time -
-				stats.acc_offload_cycles;
+		enq_sw_last_time -= stats.acc_offload_cycles;
 		time_st->enq_sw_max_time = RTE_MAX(time_st->enq_sw_max_time,
 				enq_sw_last_time);
 		time_st->enq_sw_min_time = RTE_MIN(time_st->enq_sw_min_time,
@@ -3255,7 +3680,8 @@ typedef int (test_case_function)(struct active_device *ad,
 			burst_sz = num_to_process - dequeued;
 
 		ret = rte_bbdev_enc_op_alloc_bulk(mempool, ops_enq, burst_sz);
-		TEST_ASSERT_SUCCESS(ret, "rte_bbdev_op_alloc_bulk() failed");
+		TEST_ASSERT_SUCCESS(ret,
+				"rte_bbdev_enc_op_alloc_bulk() failed");
 		if (test_vector.op_type != RTE_BBDEV_OP_NONE)
 			copy_reference_ldpc_enc_op(ops_enq, burst_sz, dequeued,
 					bufs->inputs,
@@ -3269,13 +3695,13 @@ typedef int (test_case_function)(struct active_device *ad,
 					&ops_enq[enq], burst_sz - enq);
 		} while (unlikely(burst_sz != enq));
 
+		enq_sw_last_time = rte_rdtsc_precise() - enq_start_time;
 		ret = get_bbdev_queue_stats(dev_id, queue_id, &stats);
 		TEST_ASSERT_SUCCESS(ret,
 				"Failed to get stats for queue (%u) of device (%u)",
 				queue_id, dev_id);
 
-		enq_sw_last_time = rte_rdtsc_precise() - enq_start_time -
-				stats.acc_offload_cycles;
+		enq_sw_last_time -= stats.acc_offload_cycles;
 		time_st->enq_sw_max_time = RTE_MAX(time_st->enq_sw_max_time,
 				enq_sw_last_time);
 		time_st->enq_sw_min_time = RTE_MIN(time_st->enq_sw_min_time,
diff --git a/app/test-bbdev/test_bbdev_vector.c b/app/test-bbdev/test_bbdev_vector.c
index 77356cb..50d1da0 100644
--- a/app/test-bbdev/test_bbdev_vector.c
+++ b/app/test-bbdev/test_bbdev_vector.c
@@ -197,6 +197,9 @@
 	else if (!strcmp(token,
 			"RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_OUT_ENABLE"))
 		*op_flag_value = RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_OUT_ENABLE;
+	else if (!strcmp(token,
+			"RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK"))
+		*op_flag_value = RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK;
 	else {
 		printf("The given value is not a LDPC decoder flag\n");
 		return -1;
@@ -943,16 +946,10 @@
 	unsigned char i;
 	struct rte_bbdev_op_ldpc_dec *ldpc_dec = &vector->ldpc_dec;
 
-	if (vector->entries[DATA_INPUT].nb_segments == 0)
-		return -1;
-
 	for (i = 0; i < vector->entries[DATA_INPUT].nb_segments; i++)
 		if (vector->entries[DATA_INPUT].segments[i].addr == NULL)
 			return -1;
 
-	if (vector->entries[DATA_HARD_OUTPUT].nb_segments == 0)
-		return -1;
-
 	for (i = 0; i < vector->entries[DATA_HARD_OUTPUT].nb_segments; i++)
 		if (vector->entries[DATA_HARD_OUTPUT].segments[i].addr == NULL)
 			return -1;
-- 
1.8.3.1


^ permalink raw reply	[flat|nested] 115+ messages in thread

* [dpdk-dev] [PATCH v2 07/15] test-bbdev: support for performance tests
  2020-03-04 18:22   ` [dpdk-dev] [PATCH v2 00/15] bbdev new features Nicolas Chautru
                       ` (5 preceding siblings ...)
  2020-03-04 18:22     ` [dpdk-dev] [PATCH v2 06/15] test-bbdev: support HARQ validation Nicolas Chautru
@ 2020-03-04 18:22     ` Nicolas Chautru
  2020-03-04 18:22     ` [dpdk-dev] [PATCH v2 08/15] test-bbdev: support for LDPC interrupt test Nicolas Chautru
                       ` (7 subsequent siblings)
  14 siblings, 0 replies; 115+ messages in thread
From: Nicolas Chautru @ 2020-03-04 18:22 UTC (permalink / raw)
  To: thomas, akhil.goyal, dev; +Cc: ferruh.yigit, Nic Chautru

From: Nic Chautru <nicolas.chautru@intel.com>

Includes support for BLER wireless performance test with
new arguments for SNR and number of iterations for 5G.

Signed-off-by: Nic Chautru <nicolas.chautru@intel.com>
---
 app/test-bbdev/main.c            |  29 ++-
 app/test-bbdev/main.h            |   9 +-
 app/test-bbdev/test_bbdev_perf.c | 523 ++++++++++++++++++++++++++++++++++++++-
 3 files changed, 548 insertions(+), 13 deletions(-)

diff --git a/app/test-bbdev/main.c b/app/test-bbdev/main.c
index 8a42115..ff65173 100644
--- a/app/test-bbdev/main.c
+++ b/app/test-bbdev/main.c
@@ -29,6 +29,8 @@
 	unsigned int num_ops;
 	unsigned int burst_sz;
 	unsigned int num_lcores;
+	double snr;
+	unsigned int iter_max;
 	char test_vector_filename[PATH_MAX];
 	bool init_device;
 } test_params;
@@ -140,6 +142,18 @@
 	return test_params.num_lcores;
 }
 
+double
+get_snr(void)
+{
+	return test_params.snr;
+}
+
+unsigned int
+get_iter_max(void)
+{
+	return test_params.iter_max;
+}
+
 bool
 get_init_device(void)
 {
@@ -180,12 +194,15 @@
 		{ "test-cases", 1, 0, 'c' },
 		{ "test-vector", 1, 0, 'v' },
 		{ "lcores", 1, 0, 'l' },
+		{ "snr", 1, 0, 's' },
+		{ "iter_max", 6, 0, 't' },
 		{ "init-device", 0, 0, 'i'},
 		{ "help", 0, 0, 'h' },
 		{ NULL,  0, 0, 0 }
 	};
+	tp->iter_max = DEFAULT_ITER;
 
-	while ((opt = getopt_long(argc, argv, "hin:b:c:v:l:", lgopts,
+	while ((opt = getopt_long(argc, argv, "hin:b:c:v:l:s:t:", lgopts,
 			&option_index)) != EOF)
 		switch (opt) {
 		case 'n':
@@ -237,6 +254,16 @@
 					sizeof(tp->test_vector_filename),
 					"%s", optarg);
 			break;
+		case 's':
+			TEST_ASSERT(strlen(optarg) > 0,
+					"SNR is not provided");
+			tp->snr = strtod(optarg, NULL);
+			break;
+		case 't':
+			TEST_ASSERT(strlen(optarg) > 0,
+					"Iter_max is not provided");
+			tp->iter_max = strtol(optarg, NULL, 10);
+			break;
 		case 'l':
 			TEST_ASSERT(strlen(optarg) > 0,
 					"Num of lcores is not provided");
diff --git a/app/test-bbdev/main.h b/app/test-bbdev/main.h
index 23b4d58..fb3dec8 100644
--- a/app/test-bbdev/main.h
+++ b/app/test-bbdev/main.h
@@ -19,6 +19,8 @@
 #define MAX_BURST 512U
 #define DEFAULT_BURST 32U
 #define DEFAULT_OPS 64U
+#define DEFAULT_ITER 6U
+
 
 
 #define TEST_ASSERT(cond, msg, ...) do {  \
@@ -104,8 +106,7 @@ struct test_command {
 		.command = RTE_STR(name), \
 		.callback = test_func_##name, \
 	}; \
-	static void __attribute__((constructor, used)) \
-	test_register_##name(void) \
+	RTE_INIT(test_register_##name) \
 	{ \
 		add_test_command(&test_struct_##name); \
 	}
@@ -118,6 +119,10 @@ struct test_command {
 
 unsigned int get_num_lcores(void);
 
+double get_snr(void);
+
+unsigned int get_iter_max(void);
+
 bool get_init_device(void);
 
 #endif
diff --git a/app/test-bbdev/test_bbdev_perf.c b/app/test-bbdev/test_bbdev_perf.c
index 978ccd6..7bc824b 100644
--- a/app/test-bbdev/test_bbdev_perf.c
+++ b/app/test-bbdev/test_bbdev_perf.c
@@ -111,6 +111,8 @@ struct thread_params {
 	double ops_per_sec;
 	double mbps;
 	uint8_t iter_count;
+	double iter_average;
+	double bler;
 	rte_atomic16_t nb_dequeued;
 	rte_atomic16_t processing_status;
 	rte_atomic16_t burst_sz;
@@ -1204,6 +1206,213 @@ typedef int (test_case_function)(struct active_device *ad,
 	}
 }
 
+
+/* Returns a random number drawn from a normal distribution
+ * with mean of 0 and variance of 1
+ * Marsaglia algorithm
+ */
+static double
+randn(int n)
+{
+	double S, Z, U1, U2, u, v, fac;
+
+	do {
+		U1 = (double)rand() / RAND_MAX;
+		U2 = (double)rand() / RAND_MAX;
+		u = 2. * U1 - 1.;
+		v = 2. * U2 - 1.;
+		S = u * u + v * v;
+	} while (S >= 1 || S == 0);
+	fac = sqrt(-2. * log(S) / S);
+	Z = (n % 2) ? u * fac : v * fac;
+	return Z;
+}
+
+static inline double
+maxstar(double A, double B)
+{
+	if (fabs(A - B) > 5)
+		return fmax(A, B);
+	else
+		return fmax(A, B) + log1p(exp(-fabs(A - B)));
+}
+
+
+/*
+ * Generate Qm LLRS for Qm==6
+ * Modulation, AWGN and LLR estimation from max log development
+ */
+static void
+gen_qm6_llr(int8_t *llrs, uint32_t i, double N0, double llr_max)
+{
+	int qm = 6;
+	int qam = 64;
+	int m, k;
+	double I, Q, p0, p1, llr_, b[qm], log_syml_prob[qam];
+	/* 5.1.4 of TS38.211 */
+	const double symbols_I[64] = {
+			3, 3, 1, 1, 3, 3, 1, 1, 5, 5, 7, 7, 5, 5, 7, 7,
+			3, 3, 1, 1, 3, 3, 1, 1, 5, 5, 7, 7, 5, 5, 7, 7,
+			-3, -3, -1, -1, -3, -3, -1, -1, -5, -5, -7, -7,
+			-5, -5, -7, -7, -3, -3, -1, -1, -3, -3, -1, -1,
+			-5, -5, -7, -7, -5, -5, -7, -7};
+	const double symbols_Q[64] = {
+			3, 1, 3, 1, 5, 7, 5, 7, 3, 1, 3, 1, 5, 7, 5, 7,
+			-3, -1, -3, -1, -5, -7, -5, -7, -3, -1, -3, -1,
+			-5, -7, -5, -7, 3, 1, 3, 1, 5, 7, 5, 7, 3, 1, 3, 1,
+			5, 7, 5, 7, -3, -1, -3, -1, -5, -7, -5, -7,
+			-3, -1, -3, -1, -5, -7, -5, -7};
+	/* Average constellation point energy */
+	N0 *= 42.0;
+	for (k = 0; k < qm; k++)
+		b[k] = llrs[qm * i + k] < 0 ? 1.0 : 0.0;
+	/* 5.1.4 of TS38.211 */
+	I = (1 - 2 * b[0])*(4 - (1 - 2 * b[2]) * (2 - (1 - 2 * b[4])));
+	Q = (1 - 2 * b[1])*(4 - (1 - 2 * b[3]) * (2 - (1 - 2 * b[5])));
+	/* AWGN channel */
+	I += sqrt(N0 / 2) * randn(0);
+	Q += sqrt(N0 / 2) * randn(1);
+	/*
+	 * Calculate the log of the probability that each of
+	 * the constellation points was transmitted
+	 */
+	for (m = 0; m < qam; m++)
+		log_syml_prob[m] = -(pow(I - symbols_I[m], 2.0)
+				+ pow(Q - symbols_Q[m], 2.0)) / N0;
+	/* Calculate an LLR for each of the k_64QAM bits in the set */
+	for (k = 0; k < qm; k++) {
+		p0 = -999999;
+		p1 = -999999;
+		/* For each constellation point */
+		for (m = 0; m < qam; m++) {
+			if ((m >> (qm - k - 1)) & 1)
+				p1 = maxstar(p1, log_syml_prob[m]);
+			else
+				p0 = maxstar(p0, log_syml_prob[m]);
+		}
+		/* Calculate the LLR */
+		llr_ = p0 - p1;
+		llr_ *= (1 << ldpc_llr_decimals);
+		llr_ = round(llr_);
+		if (llr_ > llr_max)
+			llr_ = llr_max;
+		if (llr_ < -llr_max)
+			llr_ = -llr_max;
+		llrs[qm * i + k] = (int8_t) llr_;
+	}
+}
+
+/*
+ * Generate Qm LLRS for Qm==4
+ * Modulation, AWGN and LLR estimation from max log development
+ */
+static void
+gen_qm4_llr(int8_t *llrs, uint32_t i, double N0, double llr_max)
+{
+	int qm = 4;
+	int qam = 16;
+	int m, k;
+	double I, Q, p0, p1, llr_, b[qm], log_syml_prob[qam];
+	/* 5.1.4 of TS38.211 */
+	const double symbols_I[16] = {1, 1, 3, 3, 1, 1, 3, 3,
+			-1, -1, -3, -3, -1, -1, -3, -3};
+	const double symbols_Q[16] = {1, 3, 1, 3, -1, -3, -1, -3,
+			1, 3, 1, 3, -1, -3, -1, -3};
+	/* Average constellation point energy */
+	N0 *= 10.0;
+	for (k = 0; k < qm; k++)
+		b[k] = llrs[qm * i + k] < 0 ? 1.0 : 0.0;
+	/* 5.1.4 of TS38.211 */
+	I = (1 - 2 * b[0]) * (2 - (1 - 2 * b[2]));
+	Q = (1 - 2 * b[1]) * (2 - (1 - 2 * b[3]));
+	/* AWGN channel */
+	I += sqrt(N0 / 2) * randn(0);
+	Q += sqrt(N0 / 2) * randn(1);
+	/*
+	 * Calculate the log of the probability that each of
+	 * the constellation points was transmitted
+	 */
+	for (m = 0; m < qam; m++)
+		log_syml_prob[m] = -(pow(I - symbols_I[m], 2.0)
+				+ pow(Q - symbols_Q[m], 2.0)) / N0;
+	/* Calculate an LLR for each of the k_64QAM bits in the set */
+	for (k = 0; k < qm; k++) {
+		p0 = -999999;
+		p1 = -999999;
+		/* For each constellation point */
+		for (m = 0; m < qam; m++) {
+			if ((m >> (qm - k - 1)) & 1)
+				p1 = maxstar(p1, log_syml_prob[m]);
+			else
+				p0 = maxstar(p0, log_syml_prob[m]);
+		}
+		/* Calculate the LLR */
+		llr_ = p0 - p1;
+		llr_ *= (1 << ldpc_llr_decimals);
+		llr_ = round(llr_);
+		if (llr_ > llr_max)
+			llr_ = llr_max;
+		if (llr_ < -llr_max)
+			llr_ = -llr_max;
+		llrs[qm * i + k] = (int8_t) llr_;
+	}
+}
+
+static void
+gen_qm2_llr(int8_t *llrs, uint32_t j, double N0, double llr_max)
+{
+	double b, b1, n;
+	double coeff = 2.0 * sqrt(N0);
+
+	/* Ignore in vectors rare quasi null LLRs not to be saturated */
+	if (llrs[j] < 8 && llrs[j] > -8)
+		return;
+
+	/* Note don't change sign here */
+	n = randn(j % 2);
+	b1 = ((llrs[j] > 0 ? 2.0 : -2.0)
+			+ coeff * n) / N0;
+	b = b1 * (1 << ldpc_llr_decimals);
+	b = round(b);
+	if (b > llr_max)
+		b = llr_max;
+	if (b < -llr_max)
+		b = -llr_max;
+	llrs[j] = (int8_t) b;
+}
+
+/* Generate LLR for a given SNR */
+static void
+generate_llr_input(uint16_t n, struct rte_bbdev_op_data *inputs,
+		struct rte_bbdev_dec_op *ref_op)
+{
+	struct rte_mbuf *m;
+	uint16_t qm;
+	uint32_t i, j, e, range;
+	double N0, llr_max;
+
+	e = ref_op->ldpc_dec.cb_params.e;
+	qm = ref_op->ldpc_dec.q_m;
+	llr_max = (1 << (ldpc_llr_size - 1)) - 1;
+	range = e / qm;
+	N0 = 1.0 / pow(10.0, get_snr() / 10.0);
+
+	for (i = 0; i < n; ++i) {
+		m = inputs[i].data;
+		int8_t *llrs = rte_pktmbuf_mtod_offset(m, int8_t *, 0);
+		if (qm == 6) {
+			for (j = 0; j < range; ++j)
+				gen_qm6_llr(llrs, j, N0, llr_max);
+		} else if (qm == 4) {
+			for (j = 0; j < range; ++j)
+				gen_qm4_llr(llrs, j, N0, llr_max);
+		} else {
+			for (j = 0; j < e; ++j)
+				gen_qm2_llr(llrs, j, N0, llr_max);
+		}
+	}
+}
+
 static void
 copy_reference_ldpc_dec_op(struct rte_bbdev_dec_op **ops, unsigned int n,
 		unsigned int start_idx,
@@ -1301,7 +1510,7 @@ typedef int (test_case_function)(struct active_device *ad,
 {
 	int status = op->status;
 	/* ignore parity mismatch false alarms for long iterations */
-	{
+	if (get_iter_max() >= 10) {
 		if (!(expected_status & (1 << RTE_BBDEV_SYNDROME_ERROR)) &&
 				(status & (1 << RTE_BBDEV_SYNDROME_ERROR))) {
 			printf("WARNING: Ignore Syndrome Check mismatch\n");
@@ -1587,6 +1796,30 @@ typedef int (test_case_function)(struct active_device *ad,
 	return TEST_SUCCESS;
 }
 
+/* Check Number of code blocks errors */
+static int
+validate_ldpc_bler(struct rte_bbdev_dec_op **ops, const uint16_t n)
+{
+	unsigned int i;
+	struct op_data_entries *hard_data_orig =
+			&test_vector.entries[DATA_HARD_OUTPUT];
+	struct rte_bbdev_op_ldpc_dec *ops_td;
+	struct rte_bbdev_op_data *hard_output;
+	int errors = 0;
+	struct rte_mbuf *m;
+
+	for (i = 0; i < n; ++i) {
+		ops_td = &ops[i]->ldpc_dec;
+		hard_output = &ops_td->hard_output;
+		m = hard_output->data;
+		if (memcmp(rte_pktmbuf_mtod_offset(m, uint32_t *, 0),
+				hard_data_orig->segments[0].addr,
+				hard_data_orig->segments[0].length))
+			errors++;
+	}
+	return errors;
+}
+
 static int
 validate_ldpc_dec_op(struct rte_bbdev_dec_op **ops, const uint16_t n,
 		struct rte_bbdev_dec_op *ref_op, const int vector_mask)
@@ -2500,6 +2733,139 @@ typedef int (test_case_function)(struct active_device *ad,
 }
 
 static int
+bler_pmd_lcore_ldpc_dec(void *arg)
+{
+	struct thread_params *tp = arg;
+	uint16_t enq, deq;
+	uint64_t total_time = 0, start_time;
+	const uint16_t queue_id = tp->queue_id;
+	const uint16_t burst_sz = tp->op_params->burst_sz;
+	const uint16_t num_ops = tp->op_params->num_to_process;
+	struct rte_bbdev_dec_op *ops_enq[num_ops];
+	struct rte_bbdev_dec_op *ops_deq[num_ops];
+	struct rte_bbdev_dec_op *ref_op = tp->op_params->ref_dec_op;
+	struct test_buffers *bufs = NULL;
+	int i, j, ret;
+	float parity_bler = 0;
+	struct rte_bbdev_info info;
+	uint16_t num_to_enq;
+	bool extDdr = check_bit(ldpc_cap_flags,
+			RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_OUT_ENABLE);
+	bool loopback = check_bit(ref_op->ldpc_dec.op_flags,
+			RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK);
+	bool hc_out = check_bit(ref_op->ldpc_dec.op_flags,
+			RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE);
+
+	TEST_ASSERT_SUCCESS((burst_sz > MAX_BURST),
+			"BURST_SIZE should be <= %u", MAX_BURST);
+
+	rte_bbdev_info_get(tp->dev_id, &info);
+
+	TEST_ASSERT_SUCCESS((num_ops > info.drv.queue_size_lim),
+			"NUM_OPS cannot exceed %u for this device",
+			info.drv.queue_size_lim);
+
+	bufs = &tp->op_params->q_bufs[GET_SOCKET(info.socket_id)][queue_id];
+
+	while (rte_atomic16_read(&tp->op_params->sync) == SYNC_WAIT)
+		rte_pause();
+
+	ret = rte_bbdev_dec_op_alloc_bulk(tp->op_params->mp, ops_enq, num_ops);
+	TEST_ASSERT_SUCCESS(ret, "Allocation failed for %d ops", num_ops);
+
+	/* For BLER tests we need to enable early termination */
+	if (!check_bit(ref_op->ldpc_dec.op_flags,
+			RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE))
+		ref_op->ldpc_dec.op_flags +=
+				RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE;
+	ref_op->ldpc_dec.iter_max = get_iter_max();
+	ref_op->ldpc_dec.iter_count = ref_op->ldpc_dec.iter_max;
+
+	if (test_vector.op_type != RTE_BBDEV_OP_NONE)
+		copy_reference_ldpc_dec_op(ops_enq, num_ops, 0, bufs->inputs,
+				bufs->hard_outputs, bufs->soft_outputs,
+				bufs->harq_inputs, bufs->harq_outputs, ref_op);
+	generate_llr_input(num_ops, bufs->inputs, ref_op);
+
+	/* Set counter to validate the ordering */
+	for (j = 0; j < num_ops; ++j)
+		ops_enq[j]->opaque_data = (void *)(uintptr_t)j;
+
+	for (i = 0; i < 1; ++i) { /* Could add more iterations */
+		for (j = 0; j < num_ops; ++j) {
+			if (!loopback)
+				mbuf_reset(
+				ops_enq[j]->ldpc_dec.hard_output.data);
+			if (hc_out || loopback)
+				mbuf_reset(
+				ops_enq[j]->ldpc_dec.harq_combined_output.data);
+		}
+		if (extDdr) {
+			bool preload = i == (TEST_REPETITIONS - 1);
+			preload_harq_ddr(tp->dev_id, queue_id, ops_enq,
+					num_ops, preload);
+		}
+		start_time = rte_rdtsc_precise();
+
+		for (enq = 0, deq = 0; enq < num_ops;) {
+			num_to_enq = burst_sz;
+
+			if (unlikely(num_ops - enq < num_to_enq))
+				num_to_enq = num_ops - enq;
+
+			enq += rte_bbdev_enqueue_ldpc_dec_ops(tp->dev_id,
+					queue_id, &ops_enq[enq], num_to_enq);
+
+			deq += rte_bbdev_dequeue_ldpc_dec_ops(tp->dev_id,
+					queue_id, &ops_deq[deq], enq - deq);
+		}
+
+		/* dequeue the remaining */
+		while (deq < enq) {
+			deq += rte_bbdev_dequeue_ldpc_dec_ops(tp->dev_id,
+					queue_id, &ops_deq[deq], enq - deq);
+		}
+
+		total_time += rte_rdtsc_precise() - start_time;
+	}
+
+	tp->iter_count = 0;
+	tp->iter_average = 0;
+	/* get the max of iter_count for all dequeued ops */
+	for (i = 0; i < num_ops; ++i) {
+		tp->iter_count = RTE_MAX(ops_enq[i]->ldpc_dec.iter_count,
+				tp->iter_count);
+		tp->iter_average += (double) ops_enq[i]->ldpc_dec.iter_count;
+		if (ops_enq[i]->status & (1 << RTE_BBDEV_SYNDROME_ERROR))
+			parity_bler += 1.0;
+	}
+
+	parity_bler /= num_ops; /* This one is based on SYND */
+	tp->iter_average /= num_ops;
+	tp->bler = (double) validate_ldpc_bler(ops_deq, num_ops) / num_ops;
+
+	if (test_vector.op_type != RTE_BBDEV_OP_NONE
+			&& tp->bler == 0
+			&& parity_bler == 0
+			&& !hc_out) {
+		ret = validate_ldpc_dec_op(ops_deq, num_ops, ref_op,
+				tp->op_params->vector_mask);
+		TEST_ASSERT_SUCCESS(ret, "Validation failed!");
+	}
+
+	rte_bbdev_dec_op_free_bulk(ops_enq, num_ops);
+
+	double tb_len_bits = calc_ldpc_dec_TB_size(ref_op);
+	tp->ops_per_sec = ((double)num_ops * 1) /
+			((double)total_time / (double)rte_get_tsc_hz());
+	tp->mbps = (((double)(num_ops * 1 * tb_len_bits)) /
+			1000000.0) / ((double)total_time /
+			(double)rte_get_tsc_hz());
+
+	return TEST_SUCCESS;
+}
+
+static int
 throughput_pmd_lcore_ldpc_dec(void *arg)
 {
 	struct thread_params *tp = arg;
@@ -2544,7 +2910,7 @@ typedef int (test_case_function)(struct active_device *ad,
 			RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE))
 		ref_op->ldpc_dec.op_flags -=
 				RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE;
-	ref_op->ldpc_dec.iter_max = 6;
+	ref_op->ldpc_dec.iter_max = get_iter_max();
 	ref_op->ldpc_dec.iter_count = ref_op->ldpc_dec.iter_max;
 
 	if (test_vector.op_type != RTE_BBDEV_OP_NONE)
@@ -2825,27 +3191,147 @@ typedef int (test_case_function)(struct active_device *ad,
 		used_cores, total_mops, total_mbps);
 }
 
+/* Aggregate the performance results over the number of cores used */
 static void
 print_dec_throughput(struct thread_params *t_params, unsigned int used_cores)
 {
-	unsigned int iter = 0;
+	unsigned int core_idx = 0;
 	double total_mops = 0, total_mbps = 0;
 	uint8_t iter_count = 0;
 
-	for (iter = 0; iter < used_cores; iter++) {
+	for (core_idx = 0; core_idx < used_cores; core_idx++) {
 		printf(
 			"Throughput for core (%u): %.8lg Ops/s, %.8lg Mbps @ max %u iterations\n",
-			t_params[iter].lcore_id, t_params[iter].ops_per_sec,
-			t_params[iter].mbps, t_params[iter].iter_count);
-		total_mops += t_params[iter].ops_per_sec;
-		total_mbps += t_params[iter].mbps;
-		iter_count = RTE_MAX(iter_count, t_params[iter].iter_count);
+			t_params[core_idx].lcore_id,
+			t_params[core_idx].ops_per_sec,
+			t_params[core_idx].mbps,
+			t_params[core_idx].iter_count);
+		total_mops += t_params[core_idx].ops_per_sec;
+		total_mbps += t_params[core_idx].mbps;
+		iter_count = RTE_MAX(iter_count,
+				t_params[core_idx].iter_count);
 	}
 	printf(
 		"\nTotal throughput for %u cores: %.8lg MOPS, %.8lg Mbps @ max %u iterations\n",
 		used_cores, total_mops, total_mbps, iter_count);
 }
 
+/* Aggregate the performance results over the number of cores used */
+static void
+print_dec_bler(struct thread_params *t_params, unsigned int used_cores)
+{
+	unsigned int core_idx = 0;
+	double total_mbps = 0, total_bler = 0, total_iter = 0;
+	double snr = get_snr();
+
+	for (core_idx = 0; core_idx < used_cores; core_idx++) {
+		printf("Core%u BLER %.1f %% - Iters %.1f - Tp %.1f Mbps %s\n",
+				t_params[core_idx].lcore_id,
+				t_params[core_idx].bler * 100,
+				t_params[core_idx].iter_average,
+				t_params[core_idx].mbps,
+				get_vector_filename());
+		total_mbps += t_params[core_idx].mbps;
+		total_bler += t_params[core_idx].bler;
+		total_iter += t_params[core_idx].iter_average;
+	}
+	total_bler /= used_cores;
+	total_iter /= used_cores;
+
+	printf("SNR %.2f BLER %.1f %% - Iterations %.1f %d - Tp %.1f Mbps %s\n",
+			snr, total_bler * 100, total_iter, get_iter_max(),
+			total_mbps, get_vector_filename());
+}
+
+/*
+ * Test function that determines BLER wireless performance
+ */
+static int
+bler_test(struct active_device *ad,
+		struct test_op_params *op_params)
+{
+	int ret;
+	unsigned int lcore_id, used_cores = 0;
+	struct thread_params *t_params;
+	struct rte_bbdev_info info;
+	lcore_function_t *bler_function;
+	uint16_t num_lcores;
+	const char *op_type_str;
+
+	rte_bbdev_info_get(ad->dev_id, &info);
+
+	op_type_str = rte_bbdev_op_type_str(test_vector.op_type);
+	TEST_ASSERT_NOT_NULL(op_type_str, "Invalid op type: %u",
+			test_vector.op_type);
+
+	printf("+ ------------------------------------------------------- +\n");
+	printf("== test: bler\ndev: %s, nb_queues: %u, burst size: %u, num ops: %u, num_lcores: %u, op type: %s, itr mode: %s, GHz: %lg\n",
+			info.dev_name, ad->nb_queues, op_params->burst_sz,
+			op_params->num_to_process, op_params->num_lcores,
+			op_type_str,
+			intr_enabled ? "Interrupt mode" : "PMD mode",
+			(double)rte_get_tsc_hz() / 1000000000.0);
+
+	/* Set number of lcores */
+	num_lcores = (ad->nb_queues < (op_params->num_lcores))
+			? ad->nb_queues
+			: op_params->num_lcores;
+
+	/* Allocate memory for thread parameters structure */
+	t_params = rte_zmalloc(NULL, num_lcores * sizeof(struct thread_params),
+			RTE_CACHE_LINE_SIZE);
+	TEST_ASSERT_NOT_NULL(t_params, "Failed to alloc %zuB for t_params",
+			RTE_ALIGN(sizeof(struct thread_params) * num_lcores,
+				RTE_CACHE_LINE_SIZE));
+
+	if (test_vector.op_type == RTE_BBDEV_OP_LDPC_DEC)
+		bler_function = bler_pmd_lcore_ldpc_dec;
+	else
+		return TEST_SKIPPED;
+
+	rte_atomic16_set(&op_params->sync, SYNC_WAIT);
+
+	/* Master core is set at first entry */
+	t_params[0].dev_id = ad->dev_id;
+	t_params[0].lcore_id = rte_lcore_id();
+	t_params[0].op_params = op_params;
+	t_params[0].queue_id = ad->queue_ids[used_cores++];
+	t_params[0].iter_count = 0;
+
+	RTE_LCORE_FOREACH_SLAVE(lcore_id) {
+		if (used_cores >= num_lcores)
+			break;
+
+		t_params[used_cores].dev_id = ad->dev_id;
+		t_params[used_cores].lcore_id = lcore_id;
+		t_params[used_cores].op_params = op_params;
+		t_params[used_cores].queue_id = ad->queue_ids[used_cores];
+		t_params[used_cores].iter_count = 0;
+
+		rte_eal_remote_launch(bler_function,
+				&t_params[used_cores++], lcore_id);
+	}
+
+	rte_atomic16_set(&op_params->sync, SYNC_START);
+	ret = bler_function(&t_params[0]);
+
+	/* Master core is always used */
+	for (used_cores = 1; used_cores < num_lcores; used_cores++)
+		ret |= rte_eal_wait_lcore(t_params[used_cores].lcore_id);
+
+	print_dec_bler(t_params, num_lcores);
+
+	/* Return if test failed */
+	if (ret) {
+		rte_free(t_params);
+		return ret;
+	}
+
+	/* Function to print something  here*/
+	rte_free(t_params);
+	return ret;
+}
+
 /*
  * Test function that determines how long an enqueue + dequeue of a burst
  * takes on available lcores.
@@ -3113,7 +3599,7 @@ typedef int (test_case_function)(struct active_device *ad,
 				RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE))
 			ref_op->ldpc_dec.op_flags -=
 					RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE;
-		ref_op->ldpc_dec.iter_max = 6;
+		ref_op->ldpc_dec.iter_max = get_iter_max();
 		ref_op->ldpc_dec.iter_count = ref_op->ldpc_dec.iter_max;
 
 		if (test_vector.op_type != RTE_BBDEV_OP_NONE)
@@ -3971,6 +4457,12 @@ typedef int (test_case_function)(struct active_device *ad,
 }
 
 static int
+bler_tc(void)
+{
+	return run_test_case(bler_test);
+}
+
+static int
 throughput_tc(void)
 {
 	return run_test_case(throughput_test);
@@ -4000,6 +4492,16 @@ typedef int (test_case_function)(struct active_device *ad,
 	return run_test_case(throughput_test);
 }
 
+static struct unit_test_suite bbdev_bler_testsuite = {
+	.suite_name = "BBdev BLER Tests",
+	.setup = testsuite_setup,
+	.teardown = testsuite_teardown,
+	.unit_test_cases = {
+		TEST_CASE_ST(ut_setup, ut_teardown, bler_tc),
+		TEST_CASES_END() /**< NULL terminate unit test array */
+	}
+};
+
 static struct unit_test_suite bbdev_throughput_testsuite = {
 	.suite_name = "BBdev Throughput Tests",
 	.setup = testsuite_setup,
@@ -4051,6 +4553,7 @@ typedef int (test_case_function)(struct active_device *ad,
 	}
 };
 
+REGISTER_TEST_COMMAND(bler, bbdev_bler_testsuite);
 REGISTER_TEST_COMMAND(throughput, bbdev_throughput_testsuite);
 REGISTER_TEST_COMMAND(validation, bbdev_validation_testsuite);
 REGISTER_TEST_COMMAND(latency, bbdev_latency_testsuite);
-- 
1.8.3.1


^ permalink raw reply	[flat|nested] 115+ messages in thread

* [dpdk-dev] [PATCH v2 08/15] test-bbdev: support for LDPC interrupt test
  2020-03-04 18:22   ` [dpdk-dev] [PATCH v2 00/15] bbdev new features Nicolas Chautru
                       ` (6 preceding siblings ...)
  2020-03-04 18:22     ` [dpdk-dev] [PATCH v2 07/15] test-bbdev: support for performance tests Nicolas Chautru
@ 2020-03-04 18:22     ` Nicolas Chautru
  2020-03-04 18:22     ` [dpdk-dev] [PATCH v2 09/15] test-bbdev: support for offload test for LDPC Nicolas Chautru
                       ` (6 subsequent siblings)
  14 siblings, 0 replies; 115+ messages in thread
From: Nicolas Chautru @ 2020-03-04 18:22 UTC (permalink / raw)
  To: thomas, akhil.goyal, dev; +Cc: ferruh.yigit, Nic Chautru

From: Nic Chautru <nicolas.chautru@intel.com>

Adding missing implementation for the interrupt tests
for LDPC encoder and decoders.

Signed-off-by: Nic Chautru <nicolas.chautru@intel.com>
---
 app/test-bbdev/test_bbdev_perf.c | 202 ++++++++++++++++++++++++++++++++++++++-
 1 file changed, 200 insertions(+), 2 deletions(-)

diff --git a/app/test-bbdev/test_bbdev_perf.c b/app/test-bbdev/test_bbdev_perf.c
index 7bc824b..8fcdda0 100644
--- a/app/test-bbdev/test_bbdev_perf.c
+++ b/app/test-bbdev/test_bbdev_perf.c
@@ -745,6 +745,9 @@ typedef int (test_case_function)(struct active_device *ad,
 	/* Clear active devices structs. */
 	memset(active_devs, 0, sizeof(active_devs));
 	nb_active_devs = 0;
+
+	/* Disable interrupts */
+	intr_enabled = false;
 }
 
 static int
@@ -2457,6 +2460,109 @@ typedef int (test_case_function)(struct active_device *ad,
 }
 
 static int
+throughput_intr_lcore_ldpc_dec(void *arg)
+{
+	struct thread_params *tp = arg;
+	unsigned int enqueued;
+	const uint16_t queue_id = tp->queue_id;
+	const uint16_t burst_sz = tp->op_params->burst_sz;
+	const uint16_t num_to_process = tp->op_params->num_to_process;
+	struct rte_bbdev_dec_op *ops[num_to_process];
+	struct test_buffers *bufs = NULL;
+	struct rte_bbdev_info info;
+	int ret, i, j;
+	struct rte_bbdev_dec_op *ref_op = tp->op_params->ref_dec_op;
+	uint16_t num_to_enq, enq;
+
+	bool loopback = check_bit(ref_op->ldpc_dec.op_flags,
+			RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK);
+	bool hc_out = check_bit(ref_op->ldpc_dec.op_flags,
+			RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE);
+
+	TEST_ASSERT_SUCCESS((burst_sz > MAX_BURST),
+			"BURST_SIZE should be <= %u", MAX_BURST);
+
+	TEST_ASSERT_SUCCESS(rte_bbdev_queue_intr_enable(tp->dev_id, queue_id),
+			"Failed to enable interrupts for dev: %u, queue_id: %u",
+			tp->dev_id, queue_id);
+
+	rte_bbdev_info_get(tp->dev_id, &info);
+
+	TEST_ASSERT_SUCCESS((num_to_process > info.drv.queue_size_lim),
+			"NUM_OPS cannot exceed %u for this device",
+			info.drv.queue_size_lim);
+
+	bufs = &tp->op_params->q_bufs[GET_SOCKET(info.socket_id)][queue_id];
+
+	rte_atomic16_clear(&tp->processing_status);
+	rte_atomic16_clear(&tp->nb_dequeued);
+
+	while (rte_atomic16_read(&tp->op_params->sync) == SYNC_WAIT)
+		rte_pause();
+
+	ret = rte_bbdev_dec_op_alloc_bulk(tp->op_params->mp, ops,
+				num_to_process);
+	TEST_ASSERT_SUCCESS(ret, "Allocation failed for %d ops",
+			num_to_process);
+	if (test_vector.op_type != RTE_BBDEV_OP_NONE)
+		copy_reference_ldpc_dec_op(ops, num_to_process, 0, bufs->inputs,
+				bufs->hard_outputs, bufs->soft_outputs,
+				bufs->harq_inputs, bufs->harq_outputs, ref_op);
+
+	/* Set counter to validate the ordering */
+	for (j = 0; j < num_to_process; ++j)
+		ops[j]->opaque_data = (void *)(uintptr_t)j;
+
+	for (j = 0; j < TEST_REPETITIONS; ++j) {
+		for (i = 0; i < num_to_process; ++i) {
+			if (!loopback)
+				rte_pktmbuf_reset(
+					ops[i]->ldpc_dec.hard_output.data);
+			if (hc_out || loopback)
+				mbuf_reset(
+				ops[i]->ldpc_dec.harq_combined_output.data);
+		}
+
+		tp->start_time = rte_rdtsc_precise();
+		for (enqueued = 0; enqueued < num_to_process;) {
+			num_to_enq = burst_sz;
+
+			if (unlikely(num_to_process - enqueued < num_to_enq))
+				num_to_enq = num_to_process - enqueued;
+
+			enq = 0;
+			do {
+				enq += rte_bbdev_enqueue_ldpc_dec_ops(
+						tp->dev_id,
+						queue_id, &ops[enqueued],
+						num_to_enq);
+			} while (unlikely(num_to_enq != enq));
+			enqueued += enq;
+
+			/* Write to thread burst_sz current number of enqueued
+			 * descriptors. It ensures that proper number of
+			 * descriptors will be dequeued in callback
+			 * function - needed for last batch in case where
+			 * the number of operations is not a multiple of
+			 * burst size.
+			 */
+			rte_atomic16_set(&tp->burst_sz, num_to_enq);
+
+			/* Wait until processing of previous batch is
+			 * completed
+			 */
+			while (rte_atomic16_read(&tp->nb_dequeued) !=
+					(int16_t) enqueued)
+				rte_pause();
+		}
+		if (j != TEST_REPETITIONS - 1)
+			rte_atomic16_clear(&tp->nb_dequeued);
+	}
+
+	return TEST_SUCCESS;
+}
+
+static int
 throughput_intr_lcore_dec(void *arg)
 {
 	struct thread_params *tp = arg;
@@ -2635,6 +2741,98 @@ typedef int (test_case_function)(struct active_device *ad,
 	return TEST_SUCCESS;
 }
 
+
+static int
+throughput_intr_lcore_ldpc_enc(void *arg)
+{
+	struct thread_params *tp = arg;
+	unsigned int enqueued;
+	const uint16_t queue_id = tp->queue_id;
+	const uint16_t burst_sz = tp->op_params->burst_sz;
+	const uint16_t num_to_process = tp->op_params->num_to_process;
+	struct rte_bbdev_enc_op *ops[num_to_process];
+	struct test_buffers *bufs = NULL;
+	struct rte_bbdev_info info;
+	int ret, i, j;
+	uint16_t num_to_enq, enq;
+
+	TEST_ASSERT_SUCCESS((burst_sz > MAX_BURST),
+			"BURST_SIZE should be <= %u", MAX_BURST);
+
+	TEST_ASSERT_SUCCESS(rte_bbdev_queue_intr_enable(tp->dev_id, queue_id),
+			"Failed to enable interrupts for dev: %u, queue_id: %u",
+			tp->dev_id, queue_id);
+
+	rte_bbdev_info_get(tp->dev_id, &info);
+
+	TEST_ASSERT_SUCCESS((num_to_process > info.drv.queue_size_lim),
+			"NUM_OPS cannot exceed %u for this device",
+			info.drv.queue_size_lim);
+
+	bufs = &tp->op_params->q_bufs[GET_SOCKET(info.socket_id)][queue_id];
+
+	rte_atomic16_clear(&tp->processing_status);
+	rte_atomic16_clear(&tp->nb_dequeued);
+
+	while (rte_atomic16_read(&tp->op_params->sync) == SYNC_WAIT)
+		rte_pause();
+
+	ret = rte_bbdev_enc_op_alloc_bulk(tp->op_params->mp, ops,
+			num_to_process);
+	TEST_ASSERT_SUCCESS(ret, "Allocation failed for %d ops",
+			num_to_process);
+	if (test_vector.op_type != RTE_BBDEV_OP_NONE)
+		copy_reference_ldpc_enc_op(ops, num_to_process, 0,
+				bufs->inputs, bufs->hard_outputs,
+				tp->op_params->ref_enc_op);
+
+	/* Set counter to validate the ordering */
+	for (j = 0; j < num_to_process; ++j)
+		ops[j]->opaque_data = (void *)(uintptr_t)j;
+
+	for (j = 0; j < TEST_REPETITIONS; ++j) {
+		for (i = 0; i < num_to_process; ++i)
+			rte_pktmbuf_reset(ops[i]->turbo_enc.output.data);
+
+		tp->start_time = rte_rdtsc_precise();
+		for (enqueued = 0; enqueued < num_to_process;) {
+			num_to_enq = burst_sz;
+
+			if (unlikely(num_to_process - enqueued < num_to_enq))
+				num_to_enq = num_to_process - enqueued;
+
+			enq = 0;
+			do {
+				enq += rte_bbdev_enqueue_ldpc_enc_ops(
+						tp->dev_id,
+						queue_id, &ops[enqueued],
+						num_to_enq);
+			} while (unlikely(enq != num_to_enq));
+			enqueued += enq;
+
+			/* Write to thread burst_sz current number of enqueued
+			 * descriptors. It ensures that proper number of
+			 * descriptors will be dequeued in callback
+			 * function - needed for last batch in case where
+			 * the number of operations is not a multiple of
+			 * burst size.
+			 */
+			rte_atomic16_set(&tp->burst_sz, num_to_enq);
+
+			/* Wait until processing of previous batch is
+			 * completed
+			 */
+			while (rte_atomic16_read(&tp->nb_dequeued) !=
+					(int16_t) enqueued)
+				rte_pause();
+		}
+		if (j != TEST_REPETITIONS - 1)
+			rte_atomic16_clear(&tp->nb_dequeued);
+	}
+
+	return TEST_SUCCESS;
+}
+
 static int
 throughput_pmd_lcore_dec(void *arg)
 {
@@ -3378,11 +3576,11 @@ typedef int (test_case_function)(struct active_device *ad,
 		if (test_vector.op_type == RTE_BBDEV_OP_TURBO_DEC)
 			throughput_function = throughput_intr_lcore_dec;
 		else if (test_vector.op_type == RTE_BBDEV_OP_LDPC_DEC)
-			throughput_function = throughput_intr_lcore_dec;
+			throughput_function = throughput_intr_lcore_ldpc_dec;
 		else if (test_vector.op_type == RTE_BBDEV_OP_TURBO_ENC)
 			throughput_function = throughput_intr_lcore_enc;
 		else if (test_vector.op_type == RTE_BBDEV_OP_LDPC_ENC)
-			throughput_function = throughput_intr_lcore_enc;
+			throughput_function = throughput_intr_lcore_ldpc_enc;
 		else
 			throughput_function = throughput_intr_lcore_enc;
 
-- 
1.8.3.1


^ permalink raw reply	[flat|nested] 115+ messages in thread

* [dpdk-dev] [PATCH v2 09/15] test-bbdev: support for offload test for LDPC
  2020-03-04 18:22   ` [dpdk-dev] [PATCH v2 00/15] bbdev new features Nicolas Chautru
                       ` (7 preceding siblings ...)
  2020-03-04 18:22     ` [dpdk-dev] [PATCH v2 08/15] test-bbdev: support for LDPC interrupt test Nicolas Chautru
@ 2020-03-04 18:22     ` Nicolas Chautru
  2020-03-04 18:22     ` [dpdk-dev] [PATCH v2 10/15] test-bbdev: vectors update Nicolas Chautru
                       ` (5 subsequent siblings)
  14 siblings, 0 replies; 115+ messages in thread
From: Nicolas Chautru @ 2020-03-04 18:22 UTC (permalink / raw)
  To: thomas, akhil.goyal, dev; +Cc: ferruh.yigit, Nic Chautru

From: Nic Chautru <nicolas.chautru@intel.com>

Adding support for the offload latency tests when
using the LDPC encoder and decoder operations.

Signed-off-by: Nic Chautru <nicolas.chautru@intel.com>
---
 app/test-bbdev/test_bbdev_perf.c | 26 +++++++++++++++++++-------
 1 file changed, 19 insertions(+), 7 deletions(-)

diff --git a/app/test-bbdev/test_bbdev_perf.c b/app/test-bbdev/test_bbdev_perf.c
index 8fcdda0..1017b97 100644
--- a/app/test-bbdev/test_bbdev_perf.c
+++ b/app/test-bbdev/test_bbdev_perf.c
@@ -4538,7 +4538,7 @@ typedef int (test_case_function)(struct active_device *ad,
 offload_latency_empty_q_test_dec(uint16_t dev_id, uint16_t queue_id,
 		const uint16_t num_to_process, uint16_t burst_sz,
 		uint64_t *deq_total_time, uint64_t *deq_min_time,
-		uint64_t *deq_max_time)
+		uint64_t *deq_max_time, const enum rte_bbdev_op_type op_type)
 {
 	int i, deq_total;
 	struct rte_bbdev_dec_op *ops[MAX_BURST];
@@ -4552,7 +4552,12 @@ typedef int (test_case_function)(struct active_device *ad,
 
 		if (unlikely(num_to_process - deq_total < burst_sz))
 			burst_sz = num_to_process - deq_total;
-		rte_bbdev_dequeue_dec_ops(dev_id, queue_id, ops, burst_sz);
+		if (op_type == RTE_BBDEV_OP_TURBO_DEC)
+			rte_bbdev_dequeue_dec_ops(dev_id, queue_id, ops,
+					burst_sz);
+		else
+			rte_bbdev_dequeue_ldpc_dec_ops(dev_id, queue_id, ops,
+								burst_sz);
 
 		deq_last_time = rte_rdtsc_precise() - deq_start_time;
 		*deq_max_time = RTE_MAX(*deq_max_time, deq_last_time);
@@ -4567,7 +4572,7 @@ typedef int (test_case_function)(struct active_device *ad,
 offload_latency_empty_q_test_enc(uint16_t dev_id, uint16_t queue_id,
 		const uint16_t num_to_process, uint16_t burst_sz,
 		uint64_t *deq_total_time, uint64_t *deq_min_time,
-		uint64_t *deq_max_time)
+		uint64_t *deq_max_time, const enum rte_bbdev_op_type op_type)
 {
 	int i, deq_total;
 	struct rte_bbdev_enc_op *ops[MAX_BURST];
@@ -4580,7 +4585,12 @@ typedef int (test_case_function)(struct active_device *ad,
 
 		if (unlikely(num_to_process - deq_total < burst_sz))
 			burst_sz = num_to_process - deq_total;
-		rte_bbdev_dequeue_enc_ops(dev_id, queue_id, ops, burst_sz);
+		if (op_type == RTE_BBDEV_OP_LDPC_ENC)
+			rte_bbdev_dequeue_ldpc_enc_ops(dev_id, queue_id, ops,
+					burst_sz);
+		else
+			rte_bbdev_dequeue_enc_ops(dev_id, queue_id, ops,
+								burst_sz);
 
 		deq_last_time = rte_rdtsc_precise() - deq_start_time;
 		*deq_max_time = RTE_MAX(*deq_max_time, deq_last_time);
@@ -4590,6 +4600,7 @@ typedef int (test_case_function)(struct active_device *ad,
 
 	return i;
 }
+
 #endif
 
 static int
@@ -4627,14 +4638,15 @@ typedef int (test_case_function)(struct active_device *ad,
 	printf("== test: offload latency empty dequeue\ndev: %s, burst size: %u, num ops: %u, op type: %s\n",
 			info.dev_name, burst_sz, num_to_process, op_type_str);
 
-	if (op_type == RTE_BBDEV_OP_TURBO_DEC)
+	if (op_type == RTE_BBDEV_OP_TURBO_DEC ||
+			op_type == RTE_BBDEV_OP_LDPC_DEC)
 		iter = offload_latency_empty_q_test_dec(ad->dev_id, queue_id,
 				num_to_process, burst_sz, &deq_total_time,
-				&deq_min_time, &deq_max_time);
+				&deq_min_time, &deq_max_time, op_type);
 	else
 		iter = offload_latency_empty_q_test_enc(ad->dev_id, queue_id,
 				num_to_process, burst_sz, &deq_total_time,
-				&deq_min_time, &deq_max_time);
+				&deq_min_time, &deq_max_time, op_type);
 
 	if (iter <= 0)
 		return TEST_FAILED;
-- 
1.8.3.1


^ permalink raw reply	[flat|nested] 115+ messages in thread

* [dpdk-dev] [PATCH v2 10/15] test-bbdev: vectors update
  2020-03-04 18:22   ` [dpdk-dev] [PATCH v2 00/15] bbdev new features Nicolas Chautru
                       ` (8 preceding siblings ...)
  2020-03-04 18:22     ` [dpdk-dev] [PATCH v2 09/15] test-bbdev: support for offload test for LDPC Nicolas Chautru
@ 2020-03-04 18:22     ` Nicolas Chautru
  2020-03-04 18:22     ` [dpdk-dev] [PATCH v2 11/15] doc: update of testbbdev documentation Nicolas Chautru
                       ` (4 subsequent siblings)
  14 siblings, 0 replies; 115+ messages in thread
From: Nicolas Chautru @ 2020-03-04 18:22 UTC (permalink / raw)
  To: thomas, akhil.goyal, dev; +Cc: ferruh.yigit, Nic Chautru

From: Nic Chautru <nicolas.chautru@intel.com>

Modification to vectors parameters used for unit test
for coverage and performance test of bbdev drivers
across all devices.
Reducing list for focused coverage when required.

Signed-off-by: Nic Chautru <nicolas.chautru@intel.com>
---
 app/test-bbdev/ldpc_dec_default.data               |   2 +-
 app/test-bbdev/test_vectors/ldpc_dec_v2342.data    | 745 ---------------------
 app/test-bbdev/test_vectors/ldpc_dec_v9503.data    |   4 +-
 .../turbo_dec_c1_k6144_r0_e34560_negllr.data       | 645 ------------------
 .../turbo_dec_c2_k3136_r0_e4920_sbd_negllr.data    | 676 -------------------
 ...bo_dec_c2_k3136_r0_e4920_sbd_negllr_crc24b.data |   5 +-
 .../turbo_enc_c2_k5952_r0_e17868_crc24b.data       | 300 ---------
 .../turbo_enc_c4_k4800_r2_e14412_crc24b.data       | 252 -------
 8 files changed, 7 insertions(+), 2622 deletions(-)
 delete mode 100644 app/test-bbdev/test_vectors/ldpc_dec_v2342.data
 delete mode 100644 app/test-bbdev/test_vectors/turbo_dec_c1_k6144_r0_e34560_negllr.data
 delete mode 100644 app/test-bbdev/test_vectors/turbo_dec_c2_k3136_r0_e4920_sbd_negllr.data
 delete mode 100644 app/test-bbdev/test_vectors/turbo_enc_c2_k5952_r0_e17868_crc24b.data
 delete mode 100644 app/test-bbdev/test_vectors/turbo_enc_c4_k4800_r2_e14412_crc24b.data

diff --git a/app/test-bbdev/ldpc_dec_default.data b/app/test-bbdev/ldpc_dec_default.data
index 3058cc0..e53aa1b 120000
--- a/app/test-bbdev/ldpc_dec_default.data
+++ b/app/test-bbdev/ldpc_dec_default.data
@@ -1 +1 @@
-test_vectors/ldpc_dec_v2342.data
\ No newline at end of file
+test_vectors/ldpc_dec_v2342_drop.data
\ No newline at end of file
diff --git a/app/test-bbdev/test_vectors/ldpc_dec_v2342.data b/app/test-bbdev/test_vectors/ldpc_dec_v2342.data
deleted file mode 100644
index eca4131..0000000
--- a/app/test-bbdev/test_vectors/ldpc_dec_v2342.data
+++ /dev/null
@@ -1,745 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-# Copyright(c) 2019 Intel Corporation
-
-op_type =
-RTE_BBDEV_OP_LDPC_DEC
-
-input0 =
-0x7F817F81, 0x817F7F81, 0x8181817F, 0x7F817F81, 0x7F818181, 0x7F81817F, 0x7F817F81, 0x817F8181,
-0x817F8181, 0x817F8181, 0x7F818181, 0x81817F81, 0x81817F81, 0x7F7F817F, 0x817F7F7F, 0x7F7F8181,
-0x7F7F7F81, 0x7F7F817F, 0x7F81817F, 0x7F81817F, 0x7F818181, 0x8181817F, 0x8181817F, 0x7F7F817F,
-0x7F7F8181, 0x8181817F, 0x817F7F7F, 0x81818181, 0x817F7F81, 0x7F7F817F, 0x7F818181, 0x81817F7F,
-0x7F7F7F7F, 0x7F7F817F, 0x7F7F8181, 0x81817F7F, 0x817F8181, 0x7F817F81, 0x7F7F817F, 0x7F7F7F81,
-0x7F7F7F81, 0x817F8181, 0x817F7F7F, 0x817F7F81, 0x7F817F7F, 0x7F7F8181, 0x817F7F7F, 0x7F818181,
-0x7F7F7F7F, 0x7F7F7F81, 0x81817F81, 0x817F7F81, 0x7F7F7F81, 0x7F7F7F81, 0x81818181, 0x7F818181,
-0x817F8181, 0x7F818181, 0x7F817F81, 0x81817F7F, 0x7F817F7F, 0x817F7F7F, 0x7F818181, 0x7F7F8181,
-0x81817F81, 0x8181817F, 0x7F7F817F, 0x7F817F81, 0x81817F7F, 0x817F7F7F, 0x81817F81, 0x81818181,
-0x7F7F8181, 0x81817F81, 0x81817F7F, 0x817F8181, 0x7F7F817F, 0x7F818181, 0x7F81817F, 0x81817F7F,
-0x7F817F7F, 0x81817F7F, 0x7F7F817F, 0x7F818181, 0x7F817F81, 0x7F7F7F81, 0x7F7F7F7F, 0x817F8181,
-0x7F817F7F, 0x81817F81, 0x81817F81, 0x7F817F7F, 0x81817F81, 0x817F7F7F, 0x817F817F, 0x7F7F7F81,
-0x7F817F81, 0x7F7F7F7F, 0x81817F7F, 0x8181817F, 0x81817F81, 0x7F7F7F81, 0x7F7F7F7F, 0x7F817F7F,
-0x81817F7F, 0x7F7F7F81, 0x81817F81, 0x81818181, 0x7F7F7F7F, 0x7F7F817F, 0x7F7F7F81, 0x81817F81,
-0x7F817F7F, 0x7F81817F, 0x81817F81, 0x817F817F, 0x7F7F7F81, 0x817F8181, 0x81818181, 0x81817F81,
-0x7F818181, 0x817F7F81, 0x7F7F7F81, 0x7F817F7F, 0x81818181, 0x81818181, 0x817F7F7F, 0x81817F81,
-0x817F8181, 0x7F7F7F7F, 0x7F7F8181, 0x7F7F817F, 0x7F817F7F, 0x7F81817F, 0x7F7F817F, 0x7F817F7F,
-0x7F7F7F7F, 0x7F818181, 0x817F7F81, 0x817F817F, 0x7F817F81, 0x817F7F81, 0x81818181, 0x8181817F,
-0x81817F81, 0x7F817F7F, 0x817F8181, 0x7F7F7F7F, 0x7F817F81, 0x7F7F817F, 0x7F81817F, 0x817F8181,
-0x817F7F81, 0x817F817F, 0x817F817F, 0x81817F7F, 0x7F818181, 0x817F7F7F, 0x81817F7F, 0x7F7F7F81,
-0x8181817F, 0x817F7F81, 0x7F817F81, 0x81817F7F, 0x7F7F8181, 0x817F7F7F, 0x817F7F81, 0x7F7F817F,
-0x7F81817F, 0x7F81817F, 0x817F8181, 0x7F81817F, 0x81817F7F, 0x7F818181, 0x7F817F7F, 0x7F7F817F,
-0x81817F81, 0x81817F7F, 0x817F817F, 0x817F817F, 0x8181817F, 0x7F817F7F, 0x81817F7F, 0x7F818181,
-0x817F8181, 0x81817F81, 0x8181817F, 0x7F7F7F81, 0x81817F81, 0x81817F7F, 0x8181817F, 0x817F8181,
-0x8181817F, 0x8181817F, 0x817F7F7F, 0x81817F7F, 0x7F7F8181, 0x7F818181, 0x7F817F81, 0x81817F7F,
-0x817F7F81, 0x817F7F7F, 0x8181817F, 0x7F817F7F, 0x817F7F7F, 0x81817F7F, 0x7F818181, 0x7F7F7F7F,
-0x7F817F81, 0x7F7F8181, 0x817F817F, 0x7F7F7F7F, 0x817F8181, 0x81817F81, 0x7F7F817F, 0x7F817F7F,
-0x817F7F7F, 0x81817F7F, 0x7F7F7F7F, 0x7F817F81, 0x7F817F7F, 0x817F8181, 0x7F818181, 0x81817F81,
-0x7F7F817F, 0x7F817F81, 0x817F7F81, 0x7F7F817F, 0x817F817F, 0x817F817F, 0x7F7F8181, 0x7F817F81,
-0x7F818181, 0x7F7F7F7F, 0x81818181, 0x7F7F7F81, 0x81817F7F, 0x817F8181, 0x7F817F7F, 0x7F817F7F,
-0x7F7F8181, 0x81818181, 0x817F8181, 0x817F7F7F, 0x7F7F7F7F, 0x7F7F7F7F, 0x81817F81, 0x7F7F7F81,
-0x8181817F, 0x8181817F, 0x8181817F, 0x817F817F, 0x7F817F7F, 0x7F818181, 0x7F817F81, 0x7F817F81,
-0x7F7F8181, 0x817F817F, 0x81817F7F, 0x7F818181, 0x817F7F7F, 0x817F817F, 0x817F817F, 0x7F7F7F7F,
-0x817F817F, 0x8181817F, 0x7F7F7F81, 0x817F817F, 0x81817F7F, 0x7F7F8181, 0x817F817F, 0x7F818181,
-0x7F7F7F81, 0x81818181, 0x7F818181, 0x7F7F8181, 0x817F8181, 0x817F8181, 0x7F81817F, 0x81817F7F,
-0x81818181, 0x7F7F7F81, 0x817F817F, 0x7F81817F, 0x7F817F81, 0x7F817F7F, 0x7F7F817F, 0x817F7F81,
-0x817F817F, 0x7F81817F, 0x81818181, 0x817F8181, 0x7F817F81, 0x81817F81, 0x7F7F817F, 0x817F7F7F,
-0x817F8181, 0x8181817F, 0x7F817F81, 0x7F7F817F, 0x8181817F, 0x7F81817F, 0x7F818181, 0x81817F81,
-0x8181817F, 0x7F7F8181, 0x817F7F81, 0x7F7F8181, 0x7F7F817F, 0x7F818181, 0x7F7F817F, 0x81818181,
-0x81817F7F, 0x817F7F81, 0x817F8181, 0x7F817F81, 0x7F7F7F7F, 0x7F7F7F81, 0x81817F7F, 0x817F817F,
-0x7F817F81, 0x7F7F7F7F, 0x817F7F81, 0x817F8181, 0x7F7F7F7F, 0x81818181, 0x817F817F, 0x81817F7F,
-0x81817F7F, 0x7F817F7F, 0x7F7F7F7F, 0x7F818181, 0x817F8181, 0x7F817F7F, 0x81818181, 0x81818181,
-0x7F81817F, 0x81817F7F, 0x8181817F, 0x817F7F81, 0x817F817F, 0x81818181, 0x81817F7F, 0x817F7F81,
-0x81818181, 0x8181817F, 0x81817F81, 0x81817F7F, 0x7F7F817F, 0x7F7F7F81, 0x817F7F7F, 0x7F7F8181,
-0x7F7F8181, 0x8181817F, 0x7F817F7F, 0x817F7F81, 0x81817F81, 0x7F7F8181, 0x817F8181, 0x81817F7F,
-0x7F7F7F7F, 0x81818181, 0x817F8181, 0x817F7F81, 0x7F81817F, 0x7F818181, 0x7F7F817F, 0x817F8181,
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-0x7F7F7F81, 0x817F7F81, 0x7F817F7F, 0x7F818181, 0x8181817F, 0x7F7F8181, 0x81818181, 0x817F8181,
-0x7F817F7F, 0x7F81817F, 0x81818181, 0x817F8181, 0x7F81817F, 0x817F7F81, 0x81818181, 0x7F817F81,
-0x7F817F7F, 0x817F817F, 0x7F7F7F81, 0x7F7F7F81, 0x7F7F817F, 0x81818181, 0x817F8181, 0x7F7F7F7F,
-0x817F7F7F, 0x81818181, 0x81818181, 0x81818181, 0x7F7F8181, 0x7F7F817F, 0x81817F81, 0x817F7F81,
-0x7F81817F, 0x7F7F8181, 0x7F7F7F81, 0x7F817F7F, 0x81818181, 0x7F7F7F7F, 0x81817F7F, 0x7F7F7F7F,
-0x81817F7F, 0x7F7F817F, 0x7F7F7F81, 0x7F817F81, 0x817F817F, 0x7F817F81, 0x7F7F7F81, 0x7F817F7F,
-0x817F8181, 0x7F7F8181, 0x7F7F817F, 0x7F817F81, 0x81817F81, 0x81817F81, 0x817F817F, 0x7F818181,
-0x81818181, 0x817F817F, 0x817F7F81, 0x81818181, 0x817F7F7F, 0x7F7F8181, 0x7F817F81, 0x8181817F,
-0x7F7F7F81, 0x7F817F81, 0x7F7F8181, 0x81818181, 0x7F7F7F7F, 0x7F818181, 0x7F818181, 0x817F7F81,
-0x7F7F7F7F, 0x81818181, 0x7F817F7F, 0x8181817F, 0x81818181, 0x81817F7F, 0x81818181, 0x7F818181,
-0x81817F81, 0x7F81817F, 0x7F817F7F, 0x7F817F81, 0x7F81817F, 0x817F7F7F, 0x7F817F7F, 0x817F817F,
-0x817F7F7F, 0x81818181, 0x7F7F7F7F, 0x7F7F8181, 0x817F817F, 0x7F81817F, 0x81818181, 0x7F7F7F81,
-0x7F7F8181, 0x7F818181, 0x817F7F81, 0x7F818181, 0x817F817F, 0x7F817F81, 0x7F81817F, 0x7F817F7F,
-0x7F817F7F, 0x81817F7F, 0x81817F81, 0x817F7F7F, 0x81817F81, 0x817F7F81, 0x817F7F7F, 0x7F817F7F,
-0x817F817F, 0x7F7F8181, 0x817F8181, 0x817F817F, 0x7F7F7F81, 0x817F7F7F, 0x7F817F81, 0x7F817F7F,
-0x7F7F817F, 0x7F817F81, 0x81817F7F, 0x81817F81, 0x7F81817F, 0x81818181, 0x7F817F7F, 0x8181817F,
-0x817F8181, 0x7F7F7F81, 0x817F7F81, 0x817F817F, 0x817F8181, 0x7F818181, 0x7F81817F, 0x7F7F8181,
-0x7F81817F, 0x7F81817F, 0x81818181, 0x7F7F7F81, 0x7F818181, 0x817F7F81, 0x8181817F, 0x7F818181,
-0x7F7F817F, 0x81818181, 0x817F7F81, 0x7F817F81, 0x8181817F, 0x7F81817F, 0x817F8181, 0x7F7F8181,
-0x81818181, 0x7F7F817F, 0x7F818181, 0x817F7F7F, 0x817F7F81, 0x7F7F7F7F, 0x7F7F8181, 0x817F817F,
-0x817F7F81, 0x7F81817F, 0x817F817F, 0x8181817F, 0x7F7F7F81, 0x7F7F817F, 0x7F818181, 0x7F817F81,
-0x817F7F81, 0x7F818181, 0x81818181, 0x817F8181, 0x81817F7F, 0x7F817F81, 0x7F7F7F7F, 0x817F7F7F,
-0x7F7F817F, 0x817F8181, 0x817F7F7F, 0x7F817F81, 0x7F7F7F81, 0x7F818181, 0x7F81817F, 0x81818181,
-0x7F818181, 0x817F7F7F, 0x817F7F7F, 0x7F7F7F81, 0x817F8181, 0x81818181, 0x81817F81, 0x7F818181,
-0x81817F81, 0x817F8181, 0x7F81817F, 0x8181817F, 0x7F7F8181, 0x817F817F, 0x7F817F7F, 0x7F7F8181,
-0x817F7F81, 0x817F8181, 0x7F817F81, 0x7F818181, 0x7F7F8181, 0x81817F81, 0x817F817F, 0x7F81817F,
-0x7F818181, 0x7F7F7F81, 0x817F7F7F, 0x7F81817F, 0x817F7F7F, 0x8181817F, 0x81818181, 0x7F7F7F81,
-0x7F817F81, 0x7F818181, 0x7F7F817F, 0x7F817F81, 0x7F7F7F81, 0x81817F7F, 0x7F7F7F81, 0x7F7F7F81,
-0x7F817F81, 0x7F818181, 0x7F817F81, 0x7F7F7F7F, 0x7F81817F, 0x8181817F, 0x817F7F7F, 0x7F7F8181,
-0x81817F7F, 0x81817F7F, 0x7F818181, 0x81817F81, 0x81817F81, 0x7F7F817F, 0x817F8181, 0x817F8181,
-0x7F818181, 0x7F81817F, 0x8181817F, 0x7F7F817F, 0x81818181, 0x7F7F7F81, 0x81818181, 0x7F7F7F7F,
-0x817F817F, 0x7F7F7F7F, 0x7F7F8181, 0x817F817F, 0x7F818181, 0x817F7F81, 0x7F7F817F, 0x817F8181,
-0x7F817F81, 0x817F8181, 0x8181817F, 0x81817F7F, 0x7F817F81, 0x7F7F8181, 0x7F7F8181, 0x7F818181,
-0x817F8181, 0x7F7F7F81, 0x7F7F7F7F, 0x81818181, 0x7F7F7F81, 0x7F7F7F7F, 0x817F817F, 0x7F7F8181,
-0x817F7F7F, 0x7F817F81, 0x81817F81, 0x7F81817F, 0x81817F7F, 0x817F7F7F, 0x7F81817F, 0x7F817F81,
-0x7F7F7F7F, 0x817F7F7F, 0x7F817F81, 0x817F817F, 0x81817F81, 0x81817F7F, 0x7F817F81, 0x7F7F7F81,
-0x7F7F7F7F, 0x8181817F, 0x817F7F81, 0x7F81817F, 0x7F81817F, 0x81817F7F, 0x8181817F, 0x81817F7F,
-0x7F817F81, 0x7F818181, 0x817F817F, 0x81817F81, 0x7F7F8181, 0x817F7F81
-
-output0 =
-0x02524C20, 0xB9B1FEA2, 0xC1BAB7E5, 0xEF5714CB, 0x7DE6A64D, 0xA05F9DC9, 0x0747D1E3, 0x3B20BC86,
-0x6FCBDB0F, 0xF2FB7A23, 0x79D5E062, 0x5BF4E7C3, 0xD4A68A37, 0x07B4A6AD, 0x37E911F9, 0x7FE7B30A,
-0xBBC284A2, 0xD38D6136, 0x25FAB76B, 0xBEBBF534, 0x9A88F9DB, 0xE37FD52D, 0x691DD493, 0xED2F738C,
-0x89A96EA0, 0xD981246A, 0x17CC820E, 0x07E3B463, 0xC9FC2590, 0x7475A33C, 0xA5151BB4, 0x1F7E759E,
-0x9554F964, 0xD0FA01F4, 0xD31774D2, 0xEB73A9F6, 0x8C9FBCB1, 0xF83010FB, 0x1909E09F, 0xC46023EB,
-0x02AEDC62, 0xC6352CC7, 0x674BDC6D, 0xE17CD747, 0x4E25B0B3, 0x4BFF6B17, 0x12C9AAA3, 0xC2BC91CD,
-0x44BE23A2, 0x8A72A157, 0x6E0DAD1F, 0x6CA69A09, 0xB55B582E, 0x01818B31, 0x5CA5CAB6, 0x1917AB24,
-0x38F98BCD, 0x01917487, 0x05906FDD, 0x760AFCBA, 0x19671085, 0x64E3546E, 0xEC10F922, 0x3CF286CA,
-0x68E273EA, 0xF1001325, 0x5DCB3B49, 0xE9547370, 0x65D26AE6, 0xF621256C, 0x25D6D99C, 0x7862EBA0,
-0x43365DB0, 0x4DBF06C5, 0x92FCAA02, 0xB0FD58FA, 0x910E80A6, 0x93D24A67, 0x6E39B144, 0x3D46D6F6,
-0xEDC55081, 0x33CD70C7, 0xC74B6E8E, 0x91AA27B9, 0x55B3542D, 0xEBF8046A, 0xB9ABDB94, 0x97FC38A8,
-0xD5837B4D, 0x764B1809, 0xFBE2096A, 0xC23887AC, 0x2A45029B, 0xCBB7DF70, 0x674654E1, 0x0C6A06BD,
-0xB3E8853E, 0x03FCC4CE, 0x26806F2E, 0x2CEB35B0, 0x10538B03, 0x94B059B8, 0xA95E7FFA, 0x48AD3D0A,
-0xEB9091E1, 0x972E31EF, 0x5EBC6F8F, 0x947FF108, 0xCB3123FA, 0xFEE1D939, 0xF3DC5C49, 0xA92927AE,
-0xF49BB8D0, 0xAA59F730, 0x4A66D1CD, 0x030E1ADF, 0x238D5B19, 0x96F861F1, 0x915424E4, 0x9127880C,
-0x8E779839, 0x87375FCE, 0x61FB3D79, 0x96B1EE83, 0x47BF6667, 0x19E7D408, 0x7E91137F, 0x0E4AD8E8,
-0xDABD2E45, 0x9B60873F, 0xD0294A65, 0x2A38A862, 0x59DD046D, 0x9832BB79, 0xA5870DB6, 0xB3F1CC48,
-0x7E9A8132, 0xEEA2E4BC, 0xF23ED87B, 0x550E011F, 0x9620E0C0, 0xE7CF0834, 0xDEE69623, 0x6184D512,
-0xD3D55728, 0xFA7711D4, 0x9C77B0F9, 0x8A26462B, 0xB3F5C8D5, 0x1123246D, 0x78F36272, 0x940EE0F9,
-0x757BF240, 0x7EE2B6D0, 0xD40FD5A1, 0xAB4205CA, 0x96E6B758, 0xAC5F4294, 0xC9268C66, 0xB48DC535,
-0x3CF6ED4C, 0xF187EFED, 0x7A09B08D, 0x8709EFCE, 0x267B2468, 0x0015D770, 0xDF1B90BF, 0xA03DAD85,
-0x2633012E, 0xE5437125, 0x58B79AFF, 0xB929C532, 0x6D890DC9, 0x89A59AD2, 0x2BB99316, 0x41B5B0EB,
-0x7304B295, 0xB37F6708, 0x2F84A68E, 0x3637D79A, 0xDD36687B, 0x904BF7B6, 0x6A2CF453, 0x733DED54,
-0x5DF48BAA, 0xC3FCC99F, 0x8E3BE1DB, 0x61D9CF2D, 0xB7DC202B, 0xA959FF95, 0x860D0F14, 0x4008C478,
-0xD9325A51, 0x27A29D4C, 0x308FE6D4, 0x7A1AA889, 0x5BD38393, 0xCBCBFA5D, 0x7C7B
-
-basegraph=
-1
-
-z_c=
-320
-
-n_cb=
-21120
-
-q_m=
-4
-
-n_filler=
-688
-
-e =
-21592
-
-rv_index =
-0
-
-code_block_mode =
-1
-
-iter_max =
-20
-
-expected_iter_count =
-3
-
-op_flags =
-RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE, RTE_BBDEV_LDPC_CRC_TYPE_24B_CHECK
-
-expected_status =
-OK
diff --git a/app/test-bbdev/test_vectors/ldpc_dec_v9503.data b/app/test-bbdev/test_vectors/ldpc_dec_v9503.data
index e645602..7699ae3 100644
--- a/app/test-bbdev/test_vectors/ldpc_dec_v9503.data
+++ b/app/test-bbdev/test_vectors/ldpc_dec_v9503.data
@@ -1176,7 +1176,7 @@ output0 =
 0xEB989F98, 0x1141D335, 0x442C699F, 0x82E9758B, 0x267E6D4D, 0x71BAC54A, 0x2FBCBD52, 0xA0966795,
 0xEB08B437, 0x1A9899A0, 0x26484B82, 0x3AEE43A8, 0xC409BE45, 0xCF8C6EC9, 0x098DE63F, 0xC3BEA60B,
 0xCB7A5B6A, 0xCBF2A44B, 0x31E9FA4C, 0x34FD7E88, 0xA3C5AF89, 0xF13C8E2B, 0xC01C79FA, 0x622B9FD8,
-0x692D4C4F, 0x712BC24C, 0x16FBD6C3, 0x7B1BBC38, 0x63F1E328, 0x824C6F4B, 0xDC
+0x692D4C4F, 0x712BC24C, 0x16FBD6C3, 0x7B1BBC38, 0x63F1E328, 0x6F4B
 
 basegraph=
 2
@@ -1209,7 +1209,7 @@ expected_iter_count =
 3
 
 op_flags =
-RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE, RTE_BBDEV_LDPC_CRC_TYPE_24B_CHECK
+RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE, RTE_BBDEV_LDPC_CRC_TYPE_24B_CHECK, RTE_BBDEV_LDPC_CRC_TYPE_24B_DROP
 
 expected_status =
 OK
diff --git a/app/test-bbdev/test_vectors/turbo_dec_c1_k6144_r0_e34560_negllr.data b/app/test-bbdev/test_vectors/turbo_dec_c1_k6144_r0_e34560_negllr.data
deleted file mode 100644
index e946963..0000000
--- a/app/test-bbdev/test_vectors/turbo_dec_c1_k6144_r0_e34560_negllr.data
+++ /dev/null
@@ -1,645 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-# Copyright(c) 2017 Intel Corporation
-
-op_type =
-RTE_BBDEV_OP_TURBO_DEC
-
-input0 =
-0x7f7fb2e1, 0x467f05ef, 0x3cabba6a, 0x1f826cac, 0xbe817fe7, 0x584dab0f, 0xdcb55f81, 0xe47f915f,
-0x37b1a534, 0x4b478145, 0x9db5727f, 0x7fa6943f, 0x819550ea, 0xd18eb72a, 0xa0ba9c10, 0xcf7f817f,
-0x915a957f, 0x2c699d0a, 0x89815c0f, 0x7f569358, 0x1002587f, 0x54314130, 0x817f1b7e, 0x81a85e2a,
-0x5981bdf2, 0x0c81b00f, 0x6781be0e, 0x297fb17f, 0xfd811fb3, 0x7f077fdb, 0xd37fc2ab, 0x817f1024,
-0x81817f7f, 0x3d848ec6, 0x4486cd9c, 0x7f6d7f81, 0x1d7ffa93, 0x813648ca, 0xdc7f125e, 0xaa81a798,
-0x60838ef4, 0x815fcdbd, 0x81cb9d93, 0x817f8188, 0xc8c3d697, 0x817af2d6, 0x36888781, 0x818117ee,
-0x37a67fbf, 0x89f464b2, 0x7f1e7f81, 0x7fe5c17f, 0x8ca1effc, 0xed7f82cf, 0x4a7f5ac6, 0x7fffb8d6,
-0x427f7f73, 0x747f7f06, 0xdfcd22a9, 0x7fb99981, 0x76f77381, 0x2cd70f12, 0xd8b138e1, 0x81a4ea29,
-0x222db281, 0xc3a07fd2, 0x217f8177, 0xd1cd87c4, 0xd181679f, 0x7f7fdee2, 0x7c81a72f, 0x6e7f5a7f,
-0x77b0c96d, 0xff7f8110, 0xe8c6ad46, 0x376ade0a, 0x447f687f, 0x5916d238, 0x88816b81, 0xda7f6d88,
-0xe2b2b55f, 0x750f7fc8, 0xc624d47f, 0xc6837f79, 0x81de5272, 0xd0847f29, 0x81ad587f, 0x3e7f7f61,
-0xc803e070, 0x237ff600, 0x8c01815e, 0x814e0e81, 0x81657eef, 0xab2a62bc, 0x73d42cb4, 0xaaf03a8a,
-0x817fa57f, 0x5e7fe2c3, 0x6deda37f, 0x6e87818d, 0x767f6e4d, 0x5c76819a, 0x8182b6f0, 0xdcd3037f,
-0x81184c7f, 0x7ff1501c, 0x22c7f159, 0x45a6817f, 0x9b53c5e7, 0x57966a5e, 0x0a7f7f81, 0x4a5c155e,
-0xf37fff81, 0xad97f8f2, 0x052f397f, 0x79638181, 0x7f7f7f7f, 0x81e3fae4, 0x7659cf03, 0xbd7a5a81,
-0x46bcab7f, 0xa57f69a1, 0xba818186, 0x38a347a2, 0x91a88ec0, 0xd76087fc, 0x81818b8c, 0x7fa3424e,
-0x7f89ef7f, 0x81ac183d, 0x3aa8912a, 0xc4937da6, 0x7a4c136b, 0x81568e05, 0x8182812b, 0xebb17f1d,
-0x84b87f4c, 0xf4eab6c9, 0x81034197, 0x8183bd0a, 0xa1b92676, 0xceca2ef1, 0x9b7f7f7f, 0x5d813181,
-0x817fea35, 0x0a6c81b0, 0x9a559b4f, 0x93987691, 0xad819510, 0xa47ab324, 0xfa577f7f, 0xbba8ac3e,
-0x6694b753, 0xee63c4d7, 0x17b4ce81, 0x83c0dc81, 0x6a7f4481, 0x81d87fe0, 0x7f5cc5c0, 0xf828ea77,
-0xbb817fa3, 0x3e816619, 0x817f6aab, 0x26417f7f, 0x0c40817f, 0x9cf01834, 0x32b37f7f, 0xe74fd0a7,
-0x7f7f4167, 0x0e7f6ae0, 0x813d81b2, 0x8172027f, 0x4ea6c275, 0x814525de, 0x46817f7f, 0x7fcb2cd1,
-0x7f8198ca, 0x3d7f60aa, 0x8d7fac81, 0xe2c081ed, 0x656f8181, 0xb2ae9365, 0x6ddd8d81, 0x86e0be65,
-0x5495ec58, 0xcb981829, 0x429ee669, 0x81445fc5, 0xd3435724, 0xce51b323, 0x92b16972, 0xf0137f8e,
-0x7f199a7f, 0x81be813c, 0x8155817f, 0xd481037f, 0x167f8181, 0x5ad131d4, 0x7fbc4149, 0x81046d60,
-0x87174b9c, 0x94bc63ba, 0x68817c7f, 0x12ef7f8d, 0x7a81f4f6, 0x7f7f6db9, 0x4823417e, 0xa4989a48,
-0x7e4c787f, 0xa47f8123, 0x819afb20, 0xbf7f447f, 0x8d95af5c, 0x33a6812e, 0x07c75cd5, 0x337f8151,
-0xa2e5e15a, 0x847f7209, 0xf9f4b934, 0x72a77f2f, 0x1a9f2f7e, 0xac224bb2, 0x81467f0c, 0x3f8fd28d,
-0x4a78b07a, 0x5269a71e, 0x4fd57fb2, 0x0b5262bf, 0xea39ca0a, 0x577f3d1e, 0x509481d7, 0xb7816b48,
-0x35c31d7f, 0x818bdc1d, 0x24087fb9, 0x7fe27f07, 0x55866481, 0x7f9edd28, 0x07811ed1, 0x1b317fb2,
-0x8cb19dee, 0x396920a6, 0xd965dd85, 0x9ed5ff47, 0xc97f7f7f, 0x7f8c1d55, 0x06a69701, 0x9e348881,
-0x7f6cb281, 0x388181d1, 0xd07d61ac, 0x7fdef7f1, 0x08177f7f, 0xd87fa1c0, 0xfe9ebeb5, 0x813d3430,
-0x2181811e, 0xf4dab306, 0xa36bbb7f, 0x05e87f7f, 0x957ff3cd, 0xe4814219, 0x7fbf3f81, 0x818a7fab,
-0x43e081d9, 0x87c08729, 0x0db52785, 0x8181b0da, 0x4c94697e, 0x817fa9b2, 0x7f7f81d9, 0x8bda8193,
-0xb6811781, 0x81796220, 0xdb082ac1, 0x2c7f5d3b, 0x8c8103f3, 0x4dcbd01e, 0x7fc1a87f, 0x457f7f23,
-0x5e26bad6, 0x7f8174f3, 0x30109f08, 0xef8526cc, 0xe8690849, 0xd2b981b0, 0x7f7f7fb5, 0x8156ef7f,
-0x921a7f98, 0x7fe6681e, 0x244e497c, 0x5ef68149, 0xbfbcaa7f, 0xf5011204, 0xfe7f8163, 0x8cd08f31,
-0xc88a6b43, 0x7c8105b6, 0xf6d881aa, 0x074c2c2d, 0xd6815c7f, 0x1d15d265, 0xce816f0c, 0x14c77f2e,
-0x9a7f08c4, 0x1a8b8ed2, 0xbe9637ed, 0xb59fac5a, 0xa4d07f91, 0x7f847fab, 0xd981597f, 0x7328575d,
-0xb83af760, 0xb536b941, 0x81c1937f, 0x16b7814d, 0x3f7fb081, 0x7f41e102, 0x727f77ea, 0x9558c381,
-0x48ac819e, 0xa87f99f2, 0x819e7f05, 0x92816eb0, 0x59447f81, 0x4f6cb056, 0x818163a8, 0xe00a64e2,
-0x81bb7fa3, 0x7f816de7, 0x86ac6a50, 0x48a277b0, 0x8e37cd81, 0x7f88e646, 0x023351d8, 0x1ee7a64b,
-0x8145f239, 0x81810859, 0x557f7f7f, 0x6971d292, 0x813d7fdf, 0xe86cade7, 0xdab67f7f, 0x6d4f247f,
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-0xcac68465, 0x617fd326, 0x893981e4, 0x7f8ed9b3, 0x59467f7f, 0x0181e258, 0x7f81b281, 0xc9816629,
-0x7fbc8181, 0x08e1cadd, 0xa8328181, 0x76b6e071, 0xb36d7feb, 0x505490d7, 0x09d5dd31, 0xba81632d,
-0x7f7f6fd0, 0x9e45813c, 0x7c4c4f70, 0xd97f5090, 0x247f335c, 0x357fbb4d, 0x267fd5c8, 0x26d08181,
-0x51447fa8, 0x81358efb, 0xb9197f52, 0x40aadca1, 0x7f6781aa, 0xaf272a09, 0x8177a4b2, 0x497fb515,
-0x819b7f7f, 0x8b817f41, 0x257f7f92, 0xa8d2244e, 0x477af9ef, 0xa8817f36, 0x5ca681f5, 0x7f1a76cb,
-0x8181c5f1, 0xc4ddc7aa, 0x81a1c2bc, 0x7f466fa2, 0x625c237f, 0x3ddd1f44, 0x4f54fdde, 0xa281f2d5,
-0x95d14e95, 0xf26e7fd4, 0x9a813a90, 0x8154361c, 0x327f7f42, 0x7fa2983b, 0xd9c28197, 0xf00d1898,
-0xb95848d4, 0x387f81f0, 0x9f8e7f4a, 0x1c5cb9ec, 0x1f63b5fc, 0x187f7dcd, 0x7f1c7f05, 0xa855e2cc,
-0x5a747f98, 0x7fa1b4ee, 0xe8e51aaa, 0x7f81ec81, 0x38818175, 0x81815f07, 0x84888181, 0x81810852,
-0x316e0060, 0x819b1c6e, 0x3d814577, 0x5ecc5d81, 0x5e81814c, 0x7f76914d, 0xfc7f814b, 0xd2819d96,
-0x70a34ad0, 0x7fd544f3, 0x71e51581, 0x817d45a4, 0x7f479a68, 0x42447fae, 0x9a974f7f, 0x817fbbd2,
-0x989f367f, 0x78fa30c0, 0xbb902e75, 0x7fda7f02, 0x7f82c5b8, 0x33c325c4, 0xdf89815c, 0x81c37f33,
-0x52f37ffc, 0x7fcc4702, 0x81488124, 0x7f548196, 0x4214a4a3, 0xa034b302, 0x6a817e04, 0xc67f795e,
-0x17a98157, 0x7f7f7f5b, 0x7f7f4c56, 0x7fe0b181, 0x7f907fba, 0x42f82fd9, 0x223ea236, 0x3d2025d1,
-0x097f81b1, 0x81a35969, 0x373cb170, 0x44a57c3b, 0x26bc5a7f, 0x34657ff6, 0xc83b3d3f, 0x99be6c2c,
-0x1c811f7f, 0x5c7f81ac, 0x33fa49f6, 0xa5c38181, 0x81ed8144, 0xc88a652a, 0x7f817fe3, 0x953cfc91,
-0x466681d3, 0x366f16d6, 0x187f2ff5, 0x077ff351, 0xbe1b817f, 0x3884ec81, 0xb17f8181, 0x9a39437f,
-0x476fac61, 0x7f911514, 0x24b0038f, 0x5647567d, 0x8143c7ae, 0x81b03a31, 0xec7f085e, 0xc10d7f55,
-0x0a50b9f6, 0x7f1fd244, 0x7f81a1c7, 0xc48148ca, 0x877fc97f, 0x81115e37, 0x827ffdf3, 0x48b741c2,
-0x7f9fc5c0, 0xf87f81ce, 0x43a1029c, 0x2a78427f, 0xff9a164d, 0x7ff981f6, 0x1b7f81aa, 0x6f48ca6a,
-0x547f7f2a, 0xa9ce5cf0, 0xc07f7f7f, 0x7f6fa54d, 0x58817fbb, 0x7f96fa32, 0xfdc18381, 0x7abd7e7f,
-0xc604b981, 0x64217ffe, 0x8893bd7d, 0x7f140281, 0x7759b9e3, 0xcc648129, 0x81c981c6, 0xaf2ba351,
-0x9ecd819f, 0xac816ff2, 0xb516672e, 0x4157ab81, 0x81d21796, 0x35643433, 0xf13d5a7f, 0x9881d003,
-0x5081bbd0, 0x7d7fbdcc, 0x6ba50d3a, 0x8170677f, 0x85b29f81, 0x8aa72210, 0xfbaaa381, 0x7f0e8f34,
-0xcf367b7f, 0xe60399ab, 0x7f7f7f01, 0x817f7f11, 0x81818932, 0xe39a6e31, 0x8d3b8181, 0x107d2bc1,
-0x908164f7, 0xe41a7fc5, 0xe944503a, 0xeb4b6559, 0x22817f81, 0x816ea8ff, 0x1557e37f, 0xaa7f701c,
-0x817f828e, 0x738106c4, 0x7e0e7f05, 0xac768181, 0x17898158, 0xc081ea33, 0x827f9958, 0x3b7fd4fc,
-0x16181f7f, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x0c7f3a86, 0x7750813d, 0xd2b385bc, 0x6f7f7f72, 0x7d487fa8, 0x7f7f8d65, 0xb6578196, 0x4d93815a,
-0xf9a54748, 0x317d6469, 0xe0466f8a, 0xef869693, 0x3da5a9e2, 0x7f7f05a1, 0x14c68157, 0xc2148135,
-0xad9ed181, 0x7a7f6081, 0xf10d659b, 0x4a38dce0, 0x114d7f2a, 0x2bc7f79f, 0x0f7881f1, 0x423e5553,
-0x9c2b817f, 0xde7ffb85, 0xe18117ca, 0x67fd7f7f, 0x3fbbf57f, 0x9b34ad7a, 0x487a543f, 0xf06322f8,
-0x9ce93023, 0x3581818a, 0x6a7f4d69, 0xad3d627f, 0xbd812c92, 0x8be4cc7f, 0x23b47fc4, 0xc87f819b,
-0x104d6e7f, 0xcfcb8134, 0x0d8152cf, 0x467f7f19, 0x113f1ec5, 0x589bff9e, 0x457fa8c8, 0x2a1246d0,
-0x731e257f, 0x40e460e8, 0x13d3057f, 0x817c8de1, 0xc09dc798, 0xab81d4f1, 0xa1a49d8c, 0xbf50df7f,
-0xbc8192f7, 0x73aa4d5a, 0x1c817f43, 0x428fd6fc, 0xc282884e, 0xb9f67fd8, 0xd7777f4d, 0x1aa2d89a,
-0xa5537f81, 0x8878b631, 0x4bdfd881, 0x7f21b57f, 0xcd7f7f7c, 0x4d2aa1d0, 0x3e138144, 0x3c7fe433,
-0x146e5fe3, 0xa53b7f85, 0xa9537ffd, 0x819eda1c, 0xf93e2881, 0xc3814f7f, 0x018d69b4, 0xf87fa19f,
-0xb09f9144, 0x6ec23f94, 0xdf7f39c6, 0x48087f7f, 0xfc818184, 0x18815bc3, 0xc764598b, 0x11ed68c7,
-0x81df81bd, 0x7feceb38, 0xc90a473a, 0x81817f81, 0xef3a537f, 0x7f4d3873, 0xf45c846f, 0xfeb68afc,
-0xd326d181, 0x7fe4ae7f, 0x3e817fb5, 0x81c95de9, 0xbebdcd7f, 0x23053726, 0xdd8d8181, 0x1d545233,
-0xe37c933d, 0x81e52c1d, 0xc0ab2d81, 0x81e2667f, 0xcf2e70db, 0x9370319c, 0x21add116, 0xe6c34081,
-0x076912e7, 0xa781aca0, 0xd6f5a5d0, 0xa9af5d7f, 0x2e817c77, 0x81e1661c, 0xd5308181, 0xae7f6ec4,
-0x45815295, 0x2dbc2581, 0x50bde53d, 0xcd8cb1bc, 0x2e67977f, 0x32fc789f, 0x2b81ca3f, 0xef7f7f61,
-0x19a7d611, 0x81427f81, 0xe98181fc, 0xd4397d7f, 0xd9ab7fb7, 0x819c8c92, 0xd5478339, 0xf0555aae,
-0xfe09f481, 0x8128527f, 0x337f1081, 0x6dae3aa2, 0xccb67f81, 0xb1d8d87f, 0xc2d3dd02, 0x97af814d,
-0x812f1c5a, 0xc50c8181, 0xcd70610a, 0x7f555df4, 0x567f7f23, 0x0a0d917f, 0x4b81815c, 0x184a5b8e,
-0x5054c67f, 0x7f7f8ced, 0xf0b31f7f, 0x11698131, 0xe0ac5442, 0x57ffc57f, 0xb681cc02, 0xb78c8193,
-0xa629b48c, 0xf2a8d43b, 0x59167d37, 0x81818bf2, 0xc87c817f, 0xbf7f8e7f, 0xcdbc2243, 0x2ed78e74,
-0xfe817d61, 0xa3613c01, 0x25e281af, 0xbd6a7f36, 0xe57f4b7f, 0x81898161, 0x2a415081, 0x50b07fb6,
-0xe77f9c72, 0xd43681aa, 0xd07fb648, 0x3c7fbd5b, 0xa555c475, 0x8169dc64, 0x09106247, 0xf9b660ab,
-0x389542ac, 0x7fa22c4e, 0x81304e71, 0x29208c90, 0x317fa43a, 0x8281819d, 0x7f212065, 0xc0682681,
-0x3f2b5dc7, 0x87d86d81, 0x5c7f4192, 0x7f54332b, 0xc564a449, 0x7f817f58, 0x3c6576aa, 0x147f816d,
-0x4957d091, 0xbdaba3a7, 0xa17fa381, 0x49628138, 0x372f815b, 0x81676748, 0x8dba817f, 0xc89e8129,
-0x866fc855, 0x43ba4a81, 0x8f4b7ec2, 0xa47f054d, 0xc3b07185, 0x7f8d3ad0, 0x2c7f9f8e, 0xc17f27d3,
-0x33956381, 0x8e12a081, 0x7be52e32, 0x44b28122, 0xe4947f6d, 0x6eae4f7f, 0x34df816a, 0xd7938168,
-0xa7a9528b, 0x7f81ec45, 0x41857f6f, 0xbc28817f, 0xcbd67c06, 0xaeb678d2, 0x529a547f, 0x44813b6e,
-0xd44f247f, 0xbe1b9879, 0x877f4996, 0x5b9a8dcd, 0x2e558281, 0x1d817f84, 0xda7f8186, 0xdda9f4a6,
-0xe698ae70, 0x7fb54c8a, 0x0aae8550, 0x857ff8fb, 0x1ac42e8e, 0x3f27814b, 0xe27fdc2d, 0x2db1eb81,
-0xca817e5a, 0xec7f62e2, 0xc7dea079, 0x7f7a7f26, 0x7fdfbf81, 0x7fe89da8, 0xa9187264, 0xf98192c9,
-0x6af88181, 0x667e3981, 0xf97f3c48, 0x7fdf817f, 0x3b9bbc81, 0x55bfbc81, 0x096fa6e1, 0x1b75a67f,
-0x357f83ed, 0x7f7f6f7f, 0xf3b43812, 0x9d4c0d92, 0xa8817f4d, 0xb96c877f, 0x34818178, 0x5d7f997f,
-0xdb7f5c7f, 0x39b056a4, 0x33bcffaf, 0xb398b57f, 0x285a4bf1, 0xb181574b, 0xc1e56d31, 0x4b717fd2,
-0x56337f81, 0xed938157, 0x7f4b7f47, 0x49a3812b, 0x2e667fcd, 0xcd817240, 0x8b5470e6, 0xf693814e,
-0xd3e07f7a, 0x7f7a4781, 0xf44cd60c, 0xfd546281, 0xef995981, 0x81e70628, 0xd3b97f47, 0x07819aa8,
-0x707f447f, 0x9181c079, 0x72ae8173, 0x988d2a78, 0x7f814478, 0xb57fa076, 0xde7fb260, 0x17817f3b,
-0xf045c31b, 0x7f7feb13, 0xbee5d07f, 0x5f8192ae, 0x0c9381f7, 0x28817f7b, 0x985964d5, 0x81817d81,
-0xb381b799, 0x38b0817f, 0x3a887f0f, 0xf353fe81, 0x53817fdb, 0x5c814d56, 0x39b415ff, 0xc9c78c59,
-0xb2817fad, 0x5884bec5, 0xd629b07f, 0xb67f81cb, 0xcb81abe9, 0xab7f9b7f, 0x35815781, 0x85878181,
-0xb0b2177f, 0x86223495, 0x32cd7f69, 0x3c664743, 0x1d7981c2, 0x817f817f, 0x16cadc06, 0x03786a7f,
-0x03818107, 0x5a8dd1d1, 0x58e57f20, 0x7f818152, 0x444c50f0, 0x3d81810c, 0x66ae7f62, 0x39d01614,
-0xbd817f81, 0x789b7fa6, 0xadcd819c, 0xd37f8171, 0x291ebf81, 0xd5923ac9, 0xc37f63bf, 0x1c7981ae,
-0xda5e969d, 0x248c5899, 0x8fbdc4b3, 0x6c50d2cb, 0x2a5fab0b, 0xc42d818d, 0xa4776781, 0xaa6281fd,
-0x20534bc6, 0xb729727f, 0x6481de5c, 0xffc8a5e9, 0x707f25f2, 0xc674ba57, 0xe2ff9cb8, 0x02433e79,
-0x108e223b, 0x617f9cd7, 0xb5507f81, 0xa6f63ee6, 0x09b45856, 0x7e7fe581, 0xe4f8417f, 0xe11d98be,
-0x44817f7f, 0xc9c581df, 0xf7817fb0, 0xac6da566, 0xc681ed7f, 0x3249810f, 0xab55b281, 0x35e64c81,
-0x61e9b982, 0x8d8c4781, 0x4eafd663, 0x7fb8302e, 0x40a9bcb1, 0x17b17f9e, 0x817f92c0, 0xe35d2fb3,
-0x4ca815dd, 0x817086b9, 0x389b817f, 0x3c0d955f, 0x447f7f1a, 0x7f11307f, 0xada0815a, 0xafca7f7f,
-0xce48b124, 0x7fd94e81, 0x2edc81a4, 0xaa098a97, 0x14030263, 0x97813a7f, 0x8181d97f, 0x2581c9e6,
-0xe57f7f05, 0x16880f81, 0xa6e88184, 0x818490a2, 0xd5a87f94, 0x8b81a081, 0x38813781, 0x14a59a5a,
-0x486b8c40, 0x893449c7, 0x1f03d659, 0x81bb2831, 0xe0d8c66b, 0xa1bb7066, 0x1b7f8c71, 0x07815581,
-0x3820cb84, 0x8d3926b5, 0x81f27fd2, 0x46ff3a84, 0xfddc057f, 0x16d21ad1, 0xdbc27852, 0xf9817f34,
-0x7f81397f, 0x6c0f8101, 0xf22a100c, 0x7c998171, 0x4b68bad6, 0x7f588114, 0xc3465c81, 0x439e037f,
-0xd9817f52, 0xf1bd5594, 0xf93f9f81, 0x39447f7f, 0x46dca006, 0x93f30f7f, 0x6e215e81, 0x092ffdc3,
-0xad49e8a0, 0x7f4e7fba, 0x9b9c4fc6, 0x8131f77f, 0x0700b27f, 0xf0de61ab, 0x258181fb, 0xd8e8bb56,
-0x36932155, 0x9c7f2981, 0xb2bfe055, 0x7f0095b9, 0xaf73327f, 0x70817fbb, 0xb3a281d6, 0xfac08a53,
-0x24e4727f, 0xcbb5dbbb, 0x38be99fa, 0xbcb94e7f, 0xdf2653d0, 0x93df5efe, 0xfcdc697f, 0xe754909d,
-0xc6810060, 0x7f0ce4d1, 0xaec4a5ca, 0x4a7f81bd, 0xc17f817a, 0x7feecc3f, 0x2981285d, 0x3e0e6e81,
-0xab81814f, 0xbf27187f, 0x12409322, 0x1c9dc451, 0xc48e03e7, 0x64013b81, 0xb5847aa7, 0x350a1b84,
-0x27458181, 0xa1237f61, 0x9714287f, 0x817f8170, 0x1a7f7f09, 0xf07fecc7, 0xd686d4c9, 0x9abd7fa9,
-0x449dc0bc, 0xc1177f9d, 0x7f547f9a, 0x7fbd7fe3, 0xcab19d2b, 0xc981b27f, 0xdc8ba548, 0xe95304a6,
-0x22225820, 0xd29262ec, 0xf27f9f78, 0x1b94427f, 0x4738a436, 0x7f814fe0, 0x52817f7f, 0x1d818181,
-0xf8d92d89, 0x24817fa3, 0x66d6aadb, 0x4e55b9ca, 0x7f81de8c, 0x7f814e64, 0x24141e31, 0xa5232778,
-0x34e27f81, 0xdc87c78f, 0xc016dfb1, 0xce91829c, 0xe662c230, 0xda74e681, 0xcfb57bb8, 0xf18179ff,
-0xcc818481, 0x4736ed45, 0xcc6ee881, 0x3a815a81, 0x81b77fb2, 0x56816f2f, 0xe82bcb89, 0x3875ad5f,
-0xe05197e1, 0x1a7bc17f, 0x31a3f841, 0x7f90a77f, 0x1df3b910, 0x583f815b, 0x257f814c, 0xee7f7f8e,
-0x7dbdc37f, 0xb6810a1c, 0xce816d85, 0x459bf72d, 0xd4fe0481, 0x0d49024c, 0xbfa3a055, 0xed9baf30,
-0xf27f7f7f, 0x7dd24f9b, 0xc481817e, 0x7f899052, 0x074d5bdb, 0x2335c3fe, 0x00759f7f, 0x251bacbb,
-0x147fc935, 0x0b180994, 0x9f7fa637, 0x387ff150, 0xcbac8967, 0xf37f60cb, 0xe4c216be, 0x7829816a,
-0xd7b89981, 0xf8ae2592, 0xbeca818c, 0xf3817a81, 0xc681017f, 0x2f2f2e8f, 0xfe577f1b, 0xd503d778,
-0x2d7f7f67, 0xb281c0f0, 0xf7d7812c, 0x817f9598, 0x1af6fb36, 0x157f3781, 0x5e31a27f, 0x038181ae,
-0xf9fb81ad, 0x7a8eec81, 0xc8652e7f, 0xc67ba487, 0xbfce7f7f, 0xdf02a27f, 0xf9c1813d, 0xcaac0f90,
-0xdc448181, 0xb17f921f, 0x99be8181, 0x7fc09993, 0x11ad1bc3, 0x5c7532bf, 0x25a8ce28, 0x0ab6a823,
-0xc3c29055, 0xad55b6ea, 0xed81e0dd, 0x8caa6553, 0xff817fc8, 0x7f70d513, 0x433671dc, 0x5db37f6d,
-0x7f318170, 0x55bd4dd5, 0x00c181b7, 0x41c3bb90, 0x441a818e, 0x84e78140, 0xad8a2c81, 0x2bc38158,
-0x82654c81, 0x29d6600e, 0x227f7fc8, 0xa43d577f, 0x2b8364a3, 0x144e2a57, 0x07817f1c, 0x4a8171cd,
-0x47d5a981, 0x3c7d0781, 0xba636c7f, 0x2c7a7f7f, 0x90cf187a, 0x6b4c3671, 0x3a2c436d, 0xef81de81,
-0x4a828117, 0x814dabc0, 0xf930e17f, 0x4c3265c0, 0xe5ef7a7f, 0x819b8504, 0xd5427f81, 0xd881e992,
-0x946a45fe, 0x310162a7, 0x14819c81, 0x7f817f4a, 0x552fcf42, 0x7f707f18, 0xb9dc4881, 0xa17f81c2,
-0x9e476d98, 0x7f7f7ff0, 0x37662d4e, 0xdb7f99cc, 0xf9fe8cc1, 0x1f4c7fd1, 0x3588817f, 0x547abea9,
-0x356e7f7f, 0xab1e857f, 0xda0e7f5c, 0x9d777f7f, 0x451f1bb6, 0xa82e087f, 0xb71d347f, 0x0916d881,
-0x177e817e, 0x7f5a66a4, 0x237f2e6e, 0x816dafde, 0x2f8124c1, 0xcee67158, 0x067f667f, 0xe1258187,
-0x3a3165f7, 0x1f7fac81, 0xf636364d, 0xf2818e36, 0x0b9e207f, 0xed2d7e81, 0xaa6e2281, 0xcb50b6a3,
-0x237f72c6, 0x95819fa0, 0xd7d0c888, 0x39988141, 0xc8b07f8d, 0x5a43c942, 0xf3cd687f, 0xa2e77aec,
-0x9909bb1b, 0x7ff8e681, 0x5d39837c, 0x5625817f, 0xa9738110, 0x8b604bb2, 0xf3ffa881, 0x5f359eb5,
-0x07bf7f49, 0x7f63c67f, 0xc9db7fcb, 0xa65881c5, 0xf2818130, 0xa5817f81, 0x26b4174f, 0xc06f817f,
-0x3b8181c2, 0xbfeb4d6f, 0x9e857f91, 0x58a9a1b7, 0x67147fdc, 0xcd257081, 0xb78d4081, 0x3749ebb8,
-0x22ac7f89, 0x4af84134, 0xe3f97943, 0x2d8187c6, 0x027c8181, 0x81c1bfef, 0xc32b2267, 0x42257f81,
-0xb49b3eb3, 0xa3d47fc2, 0x27ff4d81, 0x69b4a46e, 0x81818181, 0x7fd5817f, 0x00a97d91, 0x10897f7f,
-0xd87f0d3b, 0xcbec8b7f, 0x7f814de6, 0x8286209d, 0x06e2bf7c, 0x81e28881, 0xae64afdd, 0xabc5667f,
-0xee22bee0, 0xe157d171, 0xb39a5bd6, 0xabb6d1c0, 0x53c19d81, 0x447fdb81, 0xfc086996, 0xd65f0481,
-0xc87f4d35, 0x313a12db, 0x5d81a1a0, 0x01231072, 0x327f81d6, 0x7eb1ba7b, 0xe9485dad, 0x5781767f,
-0x047f2481, 0x817f5b50, 0xda064bd7, 0x7ff07b3c, 0xfde4a68a, 0x7f83816b, 0xe67f7f34, 0x1a56f181,
-0xe2bbb681, 0xe4687f74, 0xd5a20bd8, 0x81d581a6, 0xb2395342, 0x977f0fa3, 0x81e3b5dd, 0xf1cd8147,
-0xe34f48a1, 0x258142c3, 0xe24d510b, 0x46d6816a, 0x2a608ae6, 0x5781ef81, 0xcce97f0d, 0x677f7f81,
-0xaa2381bc, 0xbde77f4d, 0xefa38185, 0x81a67f75, 0x6cceb856, 0x4976bb25, 0x3efc977f, 0x86cdf691,
-0x13497f81, 0x7fe7730a, 0xd71d8163, 0x8c7f7fbd, 0x1bec817a, 0x8154b897, 0xc71e45b6, 0xbed568c3,
-0x256c6514, 0xd481af7f, 0x19ad697f, 0x817f745f, 0xd27fa187, 0xd5e769d9, 0xd816cf7f, 0x1aa4815b,
-0x035e7ff6, 0x85de810b, 0x3ea73657, 0x216281b2, 0xe48144b7, 0x3277dfe8, 0xf8c57f20, 0x907f5091,
-0xf481b081, 0x9d8152cf, 0x0e6a81c0, 0x7fff7f06, 0xf8884d81, 0x687f81b3, 0x2657ba35, 0x527fc24c,
-0x9945694c, 0x1faa4e5b, 0x37819334, 0x57f52a7f, 0xec7f817f, 0x817fa0a8, 0xe3a8818a, 0x16beacdb,
-0x2ad2b97f, 0xb981245b, 0x359a8181, 0x7f97265e, 0x9de4387f, 0xed7f058a, 0x0e817f81, 0x4e69bdb5,
-0xc5e38552, 0x77482e81, 0x6c817542, 0x447f2990, 0x07b1f9dc, 0xc4247f82, 0x077f7f81, 0xe58bdca6,
-0x55e07f74, 0x0e7fe47f, 0x04883e81, 0x4981f87f, 0x7d7fce29, 0xe07f7d7f, 0xee817fa6, 0x7262da81,
-0xe158813b, 0xe35e41b9, 0xf17f6d65, 0xef7560ea, 0xae408493, 0x97812300, 0xf29f816e, 0x557fd5aa,
-0x328bb778, 0xa27f7f25, 0xde7fb5cb, 0x03577f0b, 0x577f18a5, 0xb9816d20, 0xe28d2a7f, 0x248c7fb9,
-0xff5fb965, 0x93b27f9c, 0x2d817581, 0x41958195, 0x3a7ff044, 0x7f7f6faa, 0xdb81b784, 0x5081603d,
-0x363ff38d, 0xc747d8b3, 0x537f812b, 0x8176a97f, 0x1d8181d3, 0x81811929, 0xe893d4c7, 0x3c7fcf7f,
-0xf6385c81, 0xaa63b42e, 0x81c3a781, 0x488142a7, 0xcbef89be, 0x3f748159, 0x50c52932, 0x298198d7,
-0x14c68e7f, 0x7fd8a798, 0x085a632f, 0x7f1d7f7f, 0xb2e34289, 0x88c3b262, 0xb044817b, 0xbf7f238a,
-0x5ae6b554, 0x9e833081, 0x607f985d, 0x0203226c, 0x333f63fb, 0xc77f8181, 0xe8297f7f, 0x9dea7f33,
-0x6f2e1f54, 0x2e41327f, 0xff0f7f81, 0x7ffa7f30, 0x343f74a6, 0x81f59f81, 0xaac67dbb, 0x6f81da1f,
-0x79ec8153, 0x78eae674, 0xec7f6e71, 0xa46a48bf, 0xe5810efa, 0x0f41b9a7, 0x3a1124a5, 0x5ff97f7f,
-0x0bd5be75, 0x7f8181f0, 0x242f409e, 0xf47ac606, 0x1e96d94f, 0x43a66a81, 0x18fc815c, 0xa51a7f7f,
-0x1185d27f, 0xa00c810f, 0x078ae481, 0x71d7866c, 0xd47ff796, 0x813cf240, 0x45814d48, 0xbc6c3618,
-0xa8b937ea, 0x838e7f7d, 0x19b3817f, 0x7f73be95, 0x00fa46b3, 0x4c43655a, 0x20f67fc2, 0x98fdda7f,
-0xe879817f, 0x4c9e7f2d, 0xcd7fefc2, 0x9681a909, 0x1e59e7b3, 0x35818136, 0x9e3a977f, 0xaf7f207e,
-0x9633227f, 0x44450e81, 0xc2c25f7f, 0x7f1a3f81, 0x08acf783, 0xd083a838, 0xd2627f59, 0x6d327f32,
-0x362c2b5e, 0xee8e507f, 0x48b431c5, 0x00816381, 0x1e6c1150, 0x7df48149, 0x36f94f81, 0xc5667844,
-0xf7cbf52c, 0x520081b8, 0xc6967f7f, 0xc88981b8, 0x328181ee, 0x697fa9f2, 0xc99a7f81, 0xb5a08181,
-0x1d74dc89, 0x643ab5cb, 0xeb81f9be, 0x987f277f, 0xad38747f, 0x61778c52, 0x59817de7, 0x05ae8144,
-0x217aa1de, 0xc0817fe9, 0xa1a6b4dc, 0xece08189, 0x4118207f, 0x9a8181a8, 0xcf0f81c9, 0xba81d081,
-0x138181b8, 0xd537957f, 0xfc7f9b8e, 0x7fc9607f, 0x16c085fe, 0x81fa7fb6, 0xf7847f66, 0xc20ee0fd,
-0xf983ec97, 0xce209f7f, 0xe2815922, 0x39b07aa8, 0xd3a82353, 0x6ee38287, 0xc60d7f29, 0xcf478f57,
-0x594d731b, 0x0e8c42fc, 0x6a702ce3, 0x7b81b301, 0x3181a450, 0x7fe94481, 0xe581b66f, 0xd87f7f2a,
-0xc1b385ee, 0x81816964, 0xbb7f5093, 0x8151817f, 0x51e3547f, 0xb3fa7549, 0xca81b044, 0x258143bf,
-0xb18181c8, 0x7f54eb08, 0xd4c9db57, 0x68a981b2, 0x4ef17f69, 0x917f977f, 0xda38865e, 0xe97f3e5f,
-0x0bbc63dc, 0xec34daaf, 0x1dc38186, 0xb381810e, 0xcbacafd2, 0xdb3ec56a, 0x22817381, 0xbc44cc4d,
-0xd681d0b0, 0xe614c8a9, 0x53577f7f, 0xdabc3012, 0x353ecdc2, 0x81728179, 0xb660cf7f, 0xef49ca49,
-0xc645dd7f, 0xd16a7f81, 0x1fb99d7f, 0x7d36d57b, 0x04ce7f46, 0x602adede, 0x1142cbb1, 0x60de427f,
-0x29814ccb, 0xe9ad7d99, 0x127b2881, 0x5c5aa08f, 0x38c0db9f, 0x7f76d981, 0x63b32381, 0xdd41ce81,
-0xce14e57f, 0x74ed7398, 0xdd81e6eb, 0xb6f2d581, 0xa581b77f, 0x468c81d7, 0x5f2d88b8, 0xf481fd21,
-0x6ec1e381, 0x71568485, 0xcbfa7f6c, 0xa02e0c9b, 0xd9a09a7f, 0x813d8176, 0xcf43c52b, 0x31a8bca1,
-0x2432dce5, 0x78277f94, 0x474e592e, 0xdefb7f81, 0xff147f51, 0xbb7f3858, 0x25f1e591, 0x36fad833,
-0x0ac87f39, 0x815d9781, 0xaebaaa81, 0x4981815f, 0xd7817781, 0xb44838b5, 0x32626981, 0x417fe2f6,
-0xdf638c92, 0x8624067f, 0x4432e69f, 0xd8688a7f, 0x06815215, 0x25bbbb7f, 0x5b5b6f63, 0x417b5b81,
-0xcc4a7b7f, 0x6ea47fd3, 0xe866b481, 0xc630c9aa, 0x083781ed, 0x69de817f, 0x0381f9f2, 0x84812ce2,
-0x027f4dd9, 0x7f5a9e81, 0x00ea319c, 0x222b9a9b, 0x34a143f0, 0x7fefd1d0, 0xb4947981, 0x11474bc1,
-0xcd44df7f, 0xa2878439, 0xd6f040b9, 0x6f86817f, 0xc67f7f81, 0x7f693443, 0x8d21b1ce, 0xdab1aed5,
-0x3f17ae71, 0x45b7ba7f, 0x05229255, 0xb181d8f5, 0x688681e3, 0xea81e181, 0xf57f817f, 0x7fdc5881,
-0x6e817f7f, 0x817f537a, 0x3987247f, 0x300a7f05, 0x3128057f, 0xe731b77f, 0x4881b50b, 0xb86dae65,
-0x00c015a0, 0x81397552, 0xb9bcab24, 0xf5818181, 0x57d18190, 0x81c3648d, 0xed813a67, 0x4c5d3a06,
-0x3581a4e3, 0x64db6467, 0x21af7d27, 0x5adf7f57, 0x66d9c99f, 0x5b183375, 0xbf4c41e5, 0x577f7ff0,
-0x4e818181, 0xf295493c, 0xd2c28170, 0x5c3a7f8e, 0x09c18181, 0x7f7f7f9c, 0xae675fa9, 0xf6d781a4,
-0x66ba10dc, 0x7f882981, 0xfe7f7f7f, 0x7f7ffea4, 0x2798d845, 0x899cb6fb, 0x4982bcd9, 0xc0815ab0,
-0x558181aa, 0x52110702, 0xd179e3c5, 0x482923bd, 0x187f8181, 0x81b3f6d9, 0xfd96a581, 0x2c5d1a81,
-0x6fde23dd, 0x9e815063, 0xfba49bcc, 0xfa775f4d, 0xb1b8b681, 0x81894f1b, 0x3c8163fa, 0x2d7f3d81,
-0xc57f6681, 0xbd7f7e81, 0x137f7f81, 0x6b3d6f81, 0xe5e2610d, 0xb4683186, 0x7f6e817f, 0x90c12abc,
-0x13a3502a, 0xdddeaa8c, 0x07a67f79, 0x1a5481ce, 0xb87fb01b, 0x0a4b1e7f, 0xd77ffcb7, 0x03535781,
-0x5a5f697f, 0x02ca7966, 0x379638bb, 0xc507c941, 0x5e7fdf8e, 0x7ce0c99b, 0xa162ccfd, 0xff8196cc,
-0xd43aa081, 0x67798185, 0xd6277f2e, 0x7f6dcb7f, 0x217fcd76, 0x2c88fb91, 0x06815b8f, 0xe37f7dae,
-0xe937257f, 0x648181ae, 0x21652c4f, 0xbf81685b, 0x36abe921, 0x3cb5de30, 0xa88e8162, 0xd87f812b,
-0xb981d14d, 0x75c181a7, 0xf7c08aa1, 0x57904e7f, 0xf6f688d8, 0x7fcf6281, 0xd33dbf7f, 0xc07f9a73,
-0x197f8135, 0xcabf8bc6, 0x3f81c37f, 0x487fac4f, 0x8ddc924b, 0x50257f7a, 0xf75e1496, 0x28d2d48f,
-0xcd91817f, 0x2a7f81b2, 0xbd7fb67f, 0x3b877fe1, 0x407fd8fd, 0xbc815f20, 0x7f50e581, 0x8bdfae4d,
-0xb1eb7f81, 0x07819f40, 0x3765274c, 0xde7fd081, 0xa0817f7f, 0x8dbe5081, 0xfa436f7f, 0x4848463b,
-0xc5c45cdb, 0x7f8b1865, 0x5bf381b6, 0x45aa497f, 0x7f813694, 0x54f15918, 0x72886c49, 0xe3fb31b0,
-0x0db1a582, 0x4aadce1b, 0x39926d8b, 0x9a30a85f, 0x1b606181, 0x1c6d165b, 0xfb057f4b, 0xcd7f81ec,
-0x12bf7ffb, 0x7f5f91d4, 0xca8158b7, 0x86134234, 0xf0f17f3c, 0x7f4e05c4, 0x34814f7f, 0xe5c1106a,
-0x2d50c67f, 0xb57fa18b, 0xb7816481, 0x7fffaadb, 0x607f817f, 0x5048ea81, 0x82495d02, 0x17819b7b,
-0xaba67981, 0xb5817f7f, 0xee57a2b6, 0x3591a602, 0x2885a153, 0x429ba160, 0x757fd0f5, 0x344e9d7f,
-0xc77a7f8d, 0x2a7f8160, 0x3198b27f, 0x81c552bd, 0x0374e058, 0x31605de1, 0x40d0817f, 0xb281a37c,
-0x156ce27f, 0x91893090, 0x06f58181, 0xc4487f6d, 0x0a7f7f9d, 0xc3a17141, 0xc03c39c5, 0xb581b2b5,
-0x526a7f7f, 0x7f7f7f4e, 0x7fec7f7f, 0x95cead7f, 0x161ba8d2, 0x8ad0d081, 0xe4f19557, 0x5bb6fca9,
-0x2d813a6d, 0xddbb7f81, 0x1cb1e281, 0xc2b43734, 0xd07f4641, 0x7f81bb39, 0xae9b1b81, 0xbe817f36,
-0x1caf7f81, 0x7f704922, 0x108f777f, 0x81662d7f, 0x479ca35b, 0x818513c2, 0xa41d8607, 0xd081b235,
-0xf6817fcb, 0x7f015960, 0xadb15f5b, 0x81be2abf, 0xf2b0e29f, 0x81819224, 0x38a7407f, 0xc9817b09,
-0xf307556c, 0x7f818181, 0x0281817f, 0x3fce810c, 0x18b47cd4, 0x81e2a53c, 0xe359840f, 0xe27f81ad,
-0xa1665081, 0x7ae062b6, 0xe0b27f35, 0xcd376e73, 0xd9a6d373, 0x817ffe7f, 0x02810946, 0x06498116,
-0x9b7fbb1b, 0x8d2b812a, 0xff14f781, 0x937de081, 0xb77ff44b, 0x4b2732c7, 0x0720bd96, 0x9e647f13,
-0xb831d474, 0x811d8183, 0xa5db837f, 0x8aa1b04a, 0xd4377cfd, 0x7f814241, 0xee8fec39, 0xcc81d881,
-0x2e29d770, 0x7ff76366, 0x7fbd363b, 0x74bbd13e, 0x2e817192, 0x9f6b81db, 0x44913bb3, 0x327f0de1,
-0x2d7f8881, 0x54f2afaa, 0x107f513c, 0x4c8191d1, 0x117fe67f, 0xffa21764, 0x2c931727, 0xd09ba693,
-0xf74e4882, 0x51ed8bc6, 0x3a23d683, 0x47437f70, 0x7fad8181, 0x9a610813, 0xa57ff47f, 0xbe1b5b9a,
-0xf4bf8c33, 0x43074944, 0xe4ef729b, 0x1e7165d6, 0x74e081c6, 0xe281810c, 0x2a4b81e4, 0x10ede221,
-0xc8375d7f, 0x81c07f81, 0x49cb7f83, 0x5f589c22, 0x276441a9, 0x7fe67f0b, 0x4d7f1d7f, 0x1872814a,
-0x05b6a577, 0x8140fa5d, 0xe47f9bc3, 0x44166064, 0x73896729, 0xb5c0867f, 0x247f445f, 0xccc92994,
-0x29611b37, 0x27531258, 0xeac27f9c, 0xd43f4e7f, 0xc27f170f, 0x6d9bfc37, 0xfc819181, 0x077f598a,
-0xe0c5d398, 0x7f23182f, 0xed171743, 0x20bff85d, 0xb0d0be7f, 0xb8938149, 0x45017f32, 0xcf2cc65d,
-0xdf7fc481, 0x7f380777, 0x81b8f0dc, 0xf6696596, 0xff007f29, 0x896e1abf, 0xfaac2d81, 0x5bc357ba,
-0x6a397f2e, 0xbfaeb45a, 0xd64e2b7f, 0xe49b4587, 0x565c6c51, 0x7f206a7f, 0xc381540b, 0xfc3d7f73,
-0xd4ec9f39, 0x887b7f27, 0xe3c1e07f, 0xb721523e, 0x0310819f, 0xc0c793ce, 0x387da141, 0x814f61ac,
-0xd1347fbe, 0x19244c1f, 0x8d3d58f9, 0x813a7fc9, 0xfae27f54, 0x7f39f481, 0xe37f818d, 0x034632d9,
-0x5b06c07f, 0x65ab8b36, 0x127f34b5, 0x18a681ad, 0x73510e20, 0x2f2ffa85, 0x6814ca9e, 0x5b7f7ead,
-0x08da93da, 0xc826da54, 0xc1686fd2, 0xb6f00fbc, 0x28bb5dbb, 0x7fe5297a, 0xb5ed8181, 0xccd9067f,
-0x177f1561, 0x71b41a19, 0xd9817f7f, 0x505b50c5, 0x309dc978, 0xb97f4f81, 0x4e81c219, 0x2d81d04a,
-0xdf3d5fa1, 0xfc6e5c30, 0xf7869481, 0xfc81e47f, 0x67b5817f, 0x7f72577f, 0x2c938136, 0xd576ad7f,
-0x63beb36f, 0x7fb3817f, 0xce56ca81, 0xd801e58d, 0x425f2522, 0x8a25817a, 0xdc7673c9, 0xd7b57fca,
-0x927fbe2a, 0x149b9881, 0x9ad781a9, 0x214b9d4d, 0x2dae1287, 0xfa772ca4, 0x3b7fdd35, 0xf59e4174,
-0xad3a28f5, 0x8144698d, 0x1ca792df, 0xdb7c7fd1, 0xe96d497f, 0x567fa7d9, 0x489b70cb, 0x3442de7f,
-0xa2554c37, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x4dc76c95, 0x29b78ec8, 0x3d927f7f, 0x307f93c2, 0x8181da7f, 0x99f741df, 0x6e1d417f, 0x1bbda834,
-0x954b5a9f, 0xc6817f07, 0x7fc01005, 0x3b5a81e4, 0x73cd7f5b, 0x7f817f3c, 0x8e7f812b, 0x59d48a03,
-0x982475ef, 0x65a1c068, 0x400cc79b, 0x81f231fe, 0x840329e0, 0x1f6054eb, 0xf8813d3a, 0x7f4a9296,
-0xbff677c5, 0x7f3c6f0c, 0x7f2890cd, 0xe0aaaad6, 0x81ae9428, 0x7f8117f1, 0x7f097f88, 0x7f27cfcc,
-0xca67205e, 0x815f7f37, 0x7f0ac07f, 0x717f95d2, 0x7f9232a7, 0x2bb803d4, 0x3c12c7e7, 0x937c81ea,
-0x7f1cdd3b, 0x0622b6c0, 0x62d71247, 0x811cb00b, 0xaef9e981, 0x0f818ff5, 0x740e6f53, 0x30616410,
-0x81fed3e0, 0x49167f3a, 0x4577315b, 0xe49130fa, 0x817c7f23, 0x7ffef7ec, 0x4fb47f17, 0xb365b1f8,
-0x81a09c38, 0x7f818134, 0x9568e717, 0x4ead1921, 0x8ebd9806, 0x7f911cf8, 0x8c7f5efc, 0xf29114a8,
-0x90bc6ae9, 0x0b5f26c1, 0x81bc9281, 0xf0fb5532, 0xc89ab77f, 0x7ec0b9d4, 0xf00bdcf7, 0x7f7f7a24,
-0x097ff51e, 0x64d62dfc, 0x7f7f819e, 0x34c05cc3, 0xa2957f19, 0x81101e05, 0x7fd68181, 0x1dff81af,
-0x7f81dc24, 0x7b3c6769, 0x7ac490dc, 0x814032c5, 0x9d81747f, 0x7fb46342, 0x72607faa, 0xd40c8161,
-0xa5ab574f, 0xf0838bba, 0x33fd7f47, 0x289f81be, 0x817f480f, 0x4bfa552d, 0x8ca1d5d5, 0x817f492b,
-0x418125e0, 0xe45d5af0, 0x811b1751, 0xe04d81f8, 0x7ff2917f, 0x65811a53, 0xe65da37f, 0xbafdd439,
-0x53818189, 0x752c7ebb, 0xc301567f, 0xb0816f27, 0x708166db, 0xc0b57f49, 0x3a818169, 0x4f16189c,
-0x13d6e83b, 0xd258a20d, 0x7fadbdb2, 0x7f93560d, 0x81fd5399, 0x6014dab2, 0x9cf45f1b, 0x107f71d5,
-0x352e8109, 0x5a5d6efa, 0xb458ef47, 0xb4a96098, 0x7ab91c37, 0x81bd762e, 0x816cb0d7, 0x3f9819d4,
-0x8113b97f, 0x7f09fa33, 0x9e7ffa99, 0xe98181ce, 0x4ffb3064, 0x7f0681ea, 0x81ef06ad, 0x385abdf5,
-0x1414457f, 0x18dabc5a, 0xc27e0d7f, 0xd87f8115, 0x703f7fcb, 0x300b7ff1, 0xb081f55d, 0x024d78f8,
-0x72949a16, 0x90603c38, 0x7fba6fd4, 0x4820e44f, 0xd57f81af, 0x9c7f7ef9, 0x61c6b27f, 0x81b6141f,
-0x7c52514a, 0x5f817f78, 0x668119a7, 0xe441aa7f, 0x53819553, 0x7f721521, 0xbd7f7f17, 0x593081de,
-0x8b252de8, 0x7f7f81c1, 0xaca9436e, 0xb5e0b104, 0x81e49d81, 0x75b48102, 0x5c278118, 0x9f6c36c9,
-0x509481fa, 0x53d1e640, 0x52108181, 0xeb7f7fff, 0xde417381, 0xa781cb33, 0x4fab55f4, 0x3e7d75f1,
-0xf17f0c1a, 0xe8e1817f, 0xcf1f7f81, 0x96d8ba40, 0x1318fc72, 0xd7ae3d1d, 0xf7e88126, 0x32bfe432,
-0x453f694b, 0x7f7fbab6, 0xeae7de30, 0x3d81d7d1, 0x438d9cc7, 0x387f4a05, 0x7f46ab81, 0x635bdf10,
-0xc281ae24, 0xc5c67fc4, 0x81acb53d, 0xba4f4d04, 0x424f72cc, 0xbf7faa1f, 0x55de1de8, 0x81429a1d,
-0xdec94147, 0xff007f42, 0x3fa74821, 0x0cb74e9c, 0xff81627e, 0x6343810f, 0xf7393529, 0x7f44ad81,
-0x7f811f39, 0x81e981a0, 0x8c8c4421, 0xc4819190, 0x81816881, 0x7f7fd234, 0x3688c16c, 0x9c34b357,
-0x6046e3f6, 0x86123bdc, 0xbd45957f, 0xe6cd777f, 0xe0951ce7, 0x9b7f63a6, 0x817f29c1, 0x7f5a81ca,
-0xde7ffcbe, 0x812c3207, 0xa099537b, 0x2a2f81d0, 0x16817f9a, 0xbb81817c, 0x7f81e538, 0x957a4200,
-0x81753bab, 0xaf63a506, 0x3081691c, 0xb0a47f2c, 0x0f157feb, 0x8e4330fe, 0x635b8189, 0x7f81ee34,
-0x7f40caae, 0xbce88e05, 0xabb52199, 0xd2ba102f, 0x7f7f8173, 0x810b32ab, 0x2e222781, 0x7f819951,
-0xfbc73dca, 0x5d81d181, 0x7fb09d81, 0x7faa3098, 0x7e81435b, 0x61e995d6, 0x7f7974f3, 0x7fef81f9,
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-0xd784acc0, 0x7f818426, 0x61ab43f8, 0xd5813c70, 0x7f817f81, 0xc9867fa8, 0x6f4b4181, 0x3881b1df,
-0x69813f27, 0x81d0780c, 0x17c84a36, 0xbf908ccc, 0x7f5e812b, 0x317f7fea, 0x7f817881, 0xf731c537,
-0x7fb221e7, 0xbae09bf7, 0xcc5d947f, 0xcfc13926, 0x6e0db67f, 0xdf17be28, 0xcaa4ea2f, 0x9870810f,
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-0x277f7fc3, 0x819c13cb, 0xe1bb65f1, 0x48151c1b, 0x8e7fd27f, 0x7f7065ac, 0xfe0bb14d, 0x588e7f0c,
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-0x7f2137f6, 0x1c57815a, 0x627f55c0, 0x69e4dbcb, 0xa68181c3, 0xb9907fea, 0x55897fa0, 0x7f54a91d,
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-0xae5b5b04, 0x86cd281f, 0x3528fe7f, 0x87217fff, 0x87860479, 0x8b7f4510, 0x7faa816c, 0xb9d62c33,
-0xdd1c6ccc, 0xb48104fd, 0xbf508f81, 0x34994944, 0x8181b843, 0x74e47f47, 0xc6baf38e, 0x624b06cc,
-0xfdadfaeb, 0x948189ac, 0x7f7f992d, 0x813edf00, 0x81c3587f, 0x5eb2819f, 0xcee54cef, 0x277f38d9,
-0x8a187fb6, 0x9736ed05, 0xed70487f, 0x4f307fa9, 0x81ba975e, 0x81dd81ed, 0xd0da7f88, 0xf24881cc,
-0x12e656d0, 0x7f9b6a1f, 0xcf7fcf7f, 0x78787ebd, 0x7f8319f2, 0x7c7fe9ed, 0x29b381ae, 0xfa4f81cb,
-0x13cc81e2, 0x9a2aa0a8, 0x817f8112, 0xfda22318, 0x7f65e85a, 0x727f6812, 0x7f814b0b, 0xcfe2bcd5,
-0x6b816ce3, 0xb2965ab7, 0x819981bf, 0x73799635, 0x82854b71, 0xbc3e8132, 0x91c714a2, 0x81817f2e,
-0x2cc55af1, 0xb87fb038, 0x7f7f1718, 0x02ba14fe, 0x5e348128, 0x817ff97f, 0x81d03daa, 0xde37813b,
-0x443781c0, 0x0e4e32e2, 0x85a7ad81, 0xba276c16, 0xb61ed9c6, 0x81ca27d3, 0x7f762e7f, 0x4181d581,
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-0x7fd127b4, 0x67e57f90, 0x4fcb6d3a, 0xc566afe7, 0xc58bdb7f, 0xe0486a7a, 0x363f8181, 0x7fdd8191,
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-0x1c387fa7, 0x7f055ed9, 0x567fbd7f, 0x4d7f7244, 0xbb8175af, 0xef7f7f5f, 0xa9a58119, 0xada9eec7,
-0x592da3bd, 0xb5a98177, 0xe17f813e, 0x94816af7, 0x69ec7fc5, 0x7f29dd4a, 0x9481c981, 0x5d3198da,
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-0x7fefd381, 0x7f907fe3, 0x7f81a862, 0x758181bc, 0x46d6507f, 0xae81a50a, 0xd1562a1d, 0x3dcb58d2,
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-0xb0fa42e3, 0x7f81563d, 0x829a817f, 0x51d48167, 0xcc817781, 0xd54f5638, 0x7fee1218, 0x81a49e22,
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-0xc7817f52, 0x85818146, 0x8781a77f, 0x8181e9f6, 0x4731f881, 0xf51a35d8, 0x236931b2, 0x6eaefadb,
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-0xab9d7800, 0x68fc444b, 0x3d7ff681, 0x93264a1d, 0x81361db5, 0x817fb6d3, 0x1681136f, 0xc5655027,
-0x792781e2, 0xeaada9c7, 0x34d1817f, 0x81687fc6, 0xa88d451a, 0xdce97f0d, 0x443935cd, 0x810a68b9,
-0x73ef4023, 0x66372979, 0x9a31076e, 0x81813dee, 0x56b11a7f, 0xc76a81da, 0xe0e48181, 0x6681b8b7,
-0xa99858ec, 0x7fb38de5, 0x7f6f817f, 0x92168381, 0x53819b02, 0xc3c27f2d, 0x5299d77f, 0x81e47f60,
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-0x7fa39bef, 0xa37ff9a1, 0x29983fc2, 0x777facc9, 0x547ff37b, 0xe6815b17, 0xec5a457f, 0xacade303,
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-0x4f817fe3, 0xc9368b0f, 0xaddb8181, 0xc210e075, 0x248f7f81, 0x697f7f11, 0x817f2f81, 0xef697ff1,
-0xd98181b9, 0x810a4f50, 0xbb9e045a, 0x8ea3771d, 0x787f6931, 0xfbb9812d, 0xb778f981, 0x7f354b27,
-0xfc813658, 0x25818137, 0x7f3402a1, 0x27eabd01, 0x81c18181, 0xfd7fa22c, 0x9784817f, 0x7fa57fb3,
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-0x7fa5a9df, 0x39818181, 0x818ea205, 0xbd819fb2, 0x7f0fa491, 0x814981d8, 0xb9c186e4, 0x817f29e5,
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-0x81f8346b, 0x6981226b, 0x81b1817f, 0x7f2081e4, 0xa2848117, 0xe4cbcc32, 0x817081d5, 0x817dbf75,
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-0x307b35ca, 0x783c7fe6, 0xa2c29081, 0x555b8101, 0xf764ee86, 0x463a8149, 0x577f837e, 0xb1948151,
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-0x209ba8a9, 0x7f311515, 0x7f519140, 0xa9549352, 0xbd817f8a, 0xafc4a005, 0x620d407f, 0x88302fd2,
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-0xad819f7f, 0x3df9422a, 0x77ca9e81, 0x684f7fca, 0x30847f81, 0x81817fda, 0xedc6a081, 0x682c00eb,
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-0x94ed5511, 0x817f944b, 0x38393d81, 0x592f7ad2, 0x75814881, 0x63275d7c, 0x4a65de10, 0xeb818ff6,
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-0x7fe15a51, 0x21894817, 0x9c810f41, 0xe9428145, 0x7f819edc, 0x7feb1761, 0x81368181, 0x2c71f15e,
-0x26813c54, 0xf09c69aa, 0xd17751da, 0x25a1c23c, 0x7f812281, 0x4317b30f, 0x66908149, 0x81869b95,
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-0xc42743ed, 0x7f8a6442, 0x79ab8152, 0xfea48ff7, 0xfbbb819c, 0xa1be81ed, 0xa481da42, 0x477f7fd0,
-0xcc1acdfb, 0x767f1533, 0x99cdda46, 0xfb9c8109, 0x7f757f7f, 0x747f88d6, 0xb5404df1, 0x8b69b739,
-0xc762670a, 0x8125bded, 0x6481a452, 0x943e5aef, 0x7fe3557f, 0x8181bfc5, 0xb14d907f, 0x7f747f9c,
-0x54b4ff28, 0xe19d7fc2, 0x7f25887f, 0x7f6cc0b5, 0x34653ba1, 0xacd70015, 0x7901cc3b, 0xb081815e,
-0x812781fd, 0x871cd81d, 0xd1818494, 0xa97fc1ed, 0x81817f86, 0x9f3cf7da, 0x9857bb81, 0x9d1661d1,
-0x167f5814, 0x037fd0e4, 0x7f337f7f, 0x7fd40904, 0x376a4a69, 0x7f77a308, 0x73b61d36, 0xb4a318cc,
-0x7f9cc3e7, 0xe0d55532, 0xab58707f, 0x9c467f07, 0x8c7f2581, 0x60155a41, 0x7f3fd21d, 0x7f7f59a3,
-0x38176d64, 0xf77fd7a6, 0x0ed2ae81, 0x7f81cdec, 0x3c0f81a2, 0x747d9be6, 0x818c5f83, 0x432e7cfb,
-0x4a44b96b, 0xc8748423, 0x6b818181, 0xe34914d7, 0x980b64bb, 0x7fbe165f, 0x7f104bbd, 0x5c7f9d02,
-0x7f307fcc, 0x8399c1a3, 0x7233316c, 0x92aae7a6, 0x81deda79, 0x812805f0, 0x7f566985, 0xdeffbea8,
-0x2bbf427f, 0x7f819e05, 0x90811687, 0x817f81a0, 0xb581c481, 0xa05cfdd4, 0xe4983e52, 0x813e81e7,
-0x2b5ba42c, 0xf75aaf0c, 0x4bbc8181, 0x817fa502, 0x1a7f2d7f, 0xe97f0700, 0x724a5029, 0xe3700308,
-0xae7fb93c, 0x7f9581ba, 0x819d7f3d, 0x2b2ef875, 0x341c52ae, 0x21b23dfc, 0x6a82a2e1, 0xaa81ecc7,
-0xcf817ff6, 0x7fa17fb5, 0x1fc21a81, 0x817f895d, 0x54973cd6, 0x81a8c919, 0x9f4c7f38, 0x89817fd1,
-0x325d7fea, 0x959581c9, 0x711638c8, 0x07bb81c4, 0x1bf0818c, 0x346b81aa, 0x5d55817f, 0x7f7f8192,
-0x3b7f81d5, 0xe783f367, 0x863038b6, 0x7f53589b, 0x7f4de47f, 0x128165ac, 0x7fa6ccfa, 0xc19f8132,
-0xc3b3483e, 0xa63d628e, 0x2d707fd1, 0xd93a1319, 0x9197277f, 0xd77f0fbf, 0x8156da7f, 0x88819a98,
-0x3eb240f2, 0x81007fbe, 0x067fe653, 0xd3aa8150, 0xa625819b, 0x767ab13b, 0x937f817b, 0xd08181e1,
-0xa47f81b9, 0x3481bd4a, 0x65507fa7, 0xb79181d1, 0xbf1d7d3e, 0xb2818178, 0x8f329d1c, 0x2081b481,
-0x7b84a853, 0x7b679ce3, 0x9ba49881, 0x695ab122, 0x23be9081, 0xd7322a4a, 0x21db3fad, 0x81fc8145,
-0x84a1bad2, 0x9f307bb8, 0x81815581, 0xb84f1450, 0x6d3acdb7, 0xfd64811d, 0x7f8132e6, 0xd7458fee,
-0x81c54610, 0x7f7f73d1, 0x81a5c3bf, 0xe15f7fa0, 0x3c7f517f, 0x047f7fd0, 0x261e438d, 0xb3c47f34,
-0x5c81a1f6, 0xa2c62f5a, 0xe67f9255, 0x4df92530, 0x58877578, 0x817fdbd6, 0x9381d867, 0xb3815eec,
-0x3d8b8ad4, 0x814aab55, 0xa5477f7b, 0xed7f98d4, 0xae7f3681, 0x3b938138, 0x58e37f90, 0x7356b00c,
-0x754181fd, 0x3181503e, 0xc58dc451, 0x818b9cbe, 0x747fcbc4, 0x0918d1f1, 0x5b5ae00e, 0x761d6116,
-0x535ba62c, 0x8c0f22b4, 0xc98fb9ad, 0xad7f6d1d, 0x4f7fec7f, 0x1b437f35, 0x9004b258, 0x787c8d15,
-0xd04b81e6, 0x703d10f0, 0x7f7f8b89, 0x1674b61c, 0x9789ac81, 0xac6c7f58, 0x0e81ac48, 0x0881812d,
-0x117f7cc2, 0xa6bd8145, 0x59817f7f, 0x89cbb4fb, 0x697f9a81, 0x813e5281, 0xf57f4898, 0xee994b1d,
-0x60228cc5, 0x4c341db8, 0x7f6e7f63, 0x107f8151, 0x14397f55, 0x81a951d6, 0xb762ed40, 0x81c39dd6,
-0x546a0438, 0x7f8e88d7, 0x81810e7f, 0x7f7f654c, 0x3b412da8, 0x8aabcfe0, 0x4b83444b, 0x65bea3ee,
-0x507fb43f, 0x16c3c7c5, 0xe322a2d9, 0xfd5a0fd9, 0xc757577f, 0x6cd0b9af, 0xc6078100, 0x3256b728,
-0xc47fdc2f, 0x81dc4bb9, 0xd8d02073, 0xc38671f2, 0xbb9104b4, 0x7fb281b6, 0xcb817f81, 0x819f44af,
-0x29f781bc, 0xdfc231b9, 0x7fae7f43, 0x575b7f79, 0xf4c4414e, 0xe807d15c, 0xd08181ae, 0x8e81cd9f,
-0x942472c9, 0x816362dc, 0x9cba9281, 0xdc6fce74, 0x2b7f7f35, 0x37810c4f, 0xe8709e85, 0x5c7f984d,
-0x8153bc24, 0xbfe581bd, 0x9a7f9c84, 0x3be9e533, 0xb6938127, 0x82ca63d5, 0x08eeb19f, 0x59ebeb0f,
-0x4d7f14f7, 0x3c558f40, 0x62d26981, 0x8181f3a8, 0xe42585ea, 0x7f08817f, 0xaf8181a0, 0x0c5d16cd,
-0xa4dfee3d, 0x3a8182fa, 0x6381883a, 0x7fe9d01c, 0x5e659f90, 0x7f7f812f, 0x4a9d8179, 0xb1e4acf3,
-0x1b8189f9, 0xd983a4d8, 0x817f81df, 0xa2cf1f55, 0x817f337f, 0x7fa3564e, 0x14ae7c44, 0x4ca3859d,
-0x81b37fa2, 0xf8a0b7b1, 0x7f79c0cc, 0x7f3010f6, 0xa5be8c16, 0x2420b129, 0x7f7898f1, 0x7e818139,
-0x7fc919eb, 0x61819a67, 0x88928b15, 0x7eade0d3, 0x4e7fc323, 0x8deb5fe6, 0x7f3f7f9c, 0x81817fbf,
-0x989026db, 0xef81c203, 0x81e4a1e1, 0x35939d41, 0xbbaae870, 0x3d217fca, 0xddd9a1ce, 0x7f7f81a3,
-0x5bf18122, 0x81c55a52, 0xc95c450c, 0x7f5a03e6, 0x65654a14, 0x75d401f6, 0xe0cb297f, 0x5f3c8132,
-0xf7a312d3, 0x81c6d3af, 0x978e8181, 0x1476539f, 0x502534be, 0xd2909112, 0x6ad663ad, 0x7f7fbbac,
-0x8b70da23, 0x4d78af31, 0x7f8159f5, 0x81bad147, 0x348151dd, 0x5e68eace, 0xc2737fa0, 0xf97fa32e,
-0x7e7f81de, 0xa68baddb, 0xbb39817f, 0x7f9bc454, 0x6d09c327, 0xc37f3c33, 0x0a865f7f, 0xba8281e1,
-0x1a3ff406, 0x652c3fd1, 0x94af367b, 0xb381d8cb, 0x4045cce5, 0x7f7fd613, 0x795f7f42, 0xb1818193,
-0x7f371d3c, 0xef816b41, 0x2ca91acc, 0x48b5aa83, 0xaae807de, 0x26813f13, 0x81817f2a, 0x6083604f,
-0xd29e81f6, 0x7fb218ca, 0x4aa50170, 0xc2d74a22, 0x4f4971a3, 0xe9dc5f10, 0x7fb8bedf, 0x1f93814a,
-0xa97f7f0e, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
-
-hard_output0=
-0xb5bc6ac8, 0xf5373664, 0x1310345c, 0xd5bae4e7, 0x1fc9e83e, 0xebfdfded, 0x84bd86ab, 0xb7aabe00,
-0x60b44fea, 0xb9067464, 0x30325378, 0xa9195955, 0xf70c6e5c, 0x90922632, 0xc90b1cdb, 0xf2f5fb69,
-0x73056b63, 0x1a33bf3f, 0x17755b5c, 0xc58bff6d, 0x2f4390b2, 0x2869d508, 0xe7c7dfe8, 0x38552963,
-0x21da5367, 0x07282b9b, 0xa4767105, 0x1e294251, 0xe350a940, 0xb8a6aa27, 0xed12d778, 0xf10d9ece,
-0xab93527f, 0xcf2da7e7, 0x68f6d0b1, 0x811f4bca, 0x577b06b2, 0x3234f13e, 0x30bab7df, 0x8dc47655,
-0xbb843bed, 0x86da3aba, 0x30950c97, 0xdd096d7a, 0xa871fd6c, 0x8bee4e6b, 0x8fea30d0, 0x6c05b4d2,
-0xf3e144d3, 0xd24ebb1f, 0x065635e5, 0x8d3f2cf9, 0x536c6c6a, 0xfbb0a5d0, 0x3d707b42, 0xc44d5982,
-0xa5f4ad8f, 0xf32c0970, 0x1bccf1a6, 0x05916020, 0xa64fb176, 0x5ede6a35, 0xaf4966da, 0x9df5e0e7,
-0x75042abc, 0x9ef10481, 0x11ddcbc8, 0xa0f5518c, 0xd5c23418, 0x2393d558, 0xfbe7dfeb, 0xed1c64c2,
-0x86a36508, 0xde2dfb1e, 0xb8d0fef9, 0x24505232, 0xc894e71c, 0xbcc752a0, 0x40b74e83, 0x90d23c8c,
-0x728e4a61, 0x108f0b08, 0x66f522ee, 0xc258d851, 0x35a31c44, 0x11311b5b, 0xfd3d5be9, 0x5ae448ff,
-0x4f64994b, 0x5b8247a9, 0x4021114d, 0x2f0b6e82, 0x5eaa9828, 0x50ac71c0, 0xfb86ee52, 0x0dc1ac9b,
-0xbbd47645, 0x8f357115, 0x978ceea0, 0xd557db99, 0x99b30388, 0xfc9a8a1c, 0x0f75be1a, 0x50143e22,
-0x8840989b, 0x738ec50e, 0xe6b2783d, 0xf67899c8, 0x27ebed69, 0x6c415a16, 0x3a6cc2dc, 0xcd4e4e5d,
-0x6cb12b2e, 0xdb88d7c0, 0x79cd1582, 0xbc422413, 0xe72ad2f4, 0x8eaac30f, 0x0bd86747, 0x6d87f69d,
-0x15d62038, 0x4b375630, 0x0d51b859, 0x16db2cb2, 0xf210603a, 0x0abeb833, 0x55c694d0, 0xe57ca43b,
-0x0ba94428, 0x1398a406, 0xe47d3889, 0x5a20203d, 0x250d7a1a, 0xd930ffec, 0x03992e79, 0xf2759376,
-0x024ec121, 0x91fc3a2c, 0xb7e11cc5, 0x4ff7d459, 0xb8700134, 0xd6e61758, 0x4eba0a32, 0xb747e3ec,
-0x7073fad7, 0xded80f99, 0x331e2f1b, 0xfa1f1bed, 0x056424a2, 0x1d1d95e0, 0x550b9ec8, 0x51ee2a38,
-0x19525153, 0xd70c4cd5, 0x0d6cd7ad, 0xe44d1cf2, 0x30dfecda, 0xdacd7fe8, 0x7321d795, 0xddf48ef4,
-0xe271e6a4, 0x9c1feecb, 0x951fcd7b, 0x8acc5a03, 0x3fb83527, 0xe306de74, 0x7b9cd6ee, 0x8e140885,
-0xd4c91e8d, 0xe8c39733, 0x0f02f87f, 0xfb06b1b9, 0x0dc9349c, 0xf76bae8e, 0x4f642a07, 0x3d48a9aa,
-0xe3ea323a, 0xa1cd5c8a, 0x40aa0e70, 0x132042d3, 0xa9732f6c, 0xd15a00c4, 0x43d3b046, 0x9a51ebd4,
-0xc46ee0ed, 0xe2a2148b, 0xf5c478f0, 0x1fb01cf3, 0xf4f321ec, 0xd973811f, 0x11ad11b9, 0x5c67adda
-
-e =
-34560
-
-k =
-6144
-
-rv_index =
-0
-
-iter_max =
-8
-
-iter_min =
-4
-
-expected_iter_count =
-8
-
-ext_scale =
-15
-
-num_maps =
-0
-
-code_block_mode =
-1
-
-op_flags =
-RTE_BBDEV_TURBO_NEG_LLR_1_BIT_IN
-
-expected_status =
-OK
diff --git a/app/test-bbdev/test_vectors/turbo_dec_c2_k3136_r0_e4920_sbd_negllr.data b/app/test-bbdev/test_vectors/turbo_dec_c2_k3136_r0_e4920_sbd_negllr.data
deleted file mode 100644
index cbf4e72..0000000
--- a/app/test-bbdev/test_vectors/turbo_dec_c2_k3136_r0_e4920_sbd_negllr.data
+++ /dev/null
@@ -1,676 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-# Copyright(c) 2017 Intel Corporation
-
-op_type =
-RTE_BBDEV_OP_TURBO_DEC
-
-input0 =
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0xD0000000, 0x33CDC8CE, 0x4FAEE4CC, 0xC7DC23C3, 0xC306D6CA, 0x2B360A24, 0xE91C423D,
-0x1F323427, 0x4B1C33B6, 0x3EC9D0E7, 0x39204DD1, 0xCCD73C37, 0xC6F6D8E1, 0x1DF828F3, 0xDEE34025,
-0xC41EC235, 0xD035E1D8, 0x3CC32843, 0x29B60C3C, 0xE92E122E, 0x454BD4C8, 0x35D02543, 0x33E4D0AC,
-0x07AF2228, 0x38C62DD1, 0x233800C5, 0x3CC02DD1, 0x35E73B19, 0xDEBED026, 0x33C5EDD9, 0x33E51527,
-0x1F21EA18, 0xCC3E3BD2, 0x013CC14C, 0x3724D23B, 0x23CDED2D, 0x21424630, 0xC5B0E64D, 0xCFC03BEF,
-0x24294241, 0x46C526BC, 0xD82F334C, 0x1E283DCB, 0x3F3F33C7, 0x4A14D2A1, 0xD92F2AF3, 0xCFA820CC,
-0xDD30C6CB, 0x2B3ACAB7, 0x4AFE29CD, 0x25BD3200, 0x2D293323, 0xD32A3B29, 0x29E64D0C, 0xBE4BFB3C,
-0xB1DD242D, 0x0427F11D, 0x3046CFDA, 0xD633C0D5, 0xC0DDBE01, 0xDA3DD9B4, 0x3BCE3638, 0x23262CC6,
-0x432BD2AE, 0x23A9E1C7, 0x1BE45609, 0x22CD35AA, 0x32D6371F, 0xCE27352A, 0xE2B73F40, 0xC2D0CE2C,
-0xE72E3A3E, 0x2FF52147, 0xEFCF2E33, 0x003103CA, 0xC6C14A33, 0x45CAC0CF, 0x011E1FD3, 0x23D3C72B,
-0x2EB644C4, 0x484BD930, 0x3AC22E1A, 0x1AB6DD42, 0xCEDDE232, 0x3ACCCC31, 0xB830CA2D, 0xC930D2D7,
-0xD0E049BB, 0xE6243524, 0x3EF53914, 0xCB083BE3, 0x411EDBE9, 0x30C3C3E8, 0x3721F5E7, 0xBBDF3FD9,
-0x2AD21F33, 0xEE402858, 0xD3AFD237, 0x3D39401D, 0x30003623, 0x4734DC46, 0x192ACD32, 0x3324CAC2,
-0xD714D4B5, 0xDC2E21D0, 0x2327CDBA, 0x15B739C3, 0x31C9EEB8, 0xFAB5372E, 0xC239B5DA, 0xE628440F,
-0x34D425C6, 0x293BE6FD, 0xBDC04BBC, 0xE0DDB7CF, 0xD627BC34, 0xA5422FCB, 0x13211ABC, 0x1708E51C,
-0xCE33DAD1, 0x51AEC731, 0x2E383824, 0xC722D0D3, 0xCB32292B, 0xCECC402B, 0x1B312EF0, 0x34CF46CA,
-0xE3BD252C, 0x0C21EC36, 0x4ADFECBE, 0xC4D2E62C, 0xADE5BAD3, 0xDDCC1D18, 0x521AC135, 0x3F302D37,
-0x22CE2DCC, 0x262A1BCF, 0x4EE7D7CA, 0xD43D3526, 0x1840E020, 0xC3201F2F, 0x3ACB453E, 0x41EAD5B6,
-0xB6C4CF17, 0x243A55D4, 0xC7501E28, 0x351DCD1C, 0xE3A8D502, 0x3235271C, 0xAC342F00, 0x34B4E3D8,
-0x36473AE4, 0xAE403CEB, 0xBC3FDA3F, 0x552CDBEC, 0xE7C42B5C, 0xE743E13D, 0x18D44650, 0xBA2EDF31,
-0xB5C3EC42, 0x432EBE2E, 0xADDE4F2A, 0x401BCAD6, 0x03D6EAEB, 0xD0DEB133, 0x153FC4D4, 0x30DA2FD3,
-0xEE282FD9, 0x242ADC39, 0xD72B42D9, 0x44C7E0D5, 0xC72CB3C7, 0x27C9472B, 0x0036DFB6, 0xD9C53112,
-0xC0360E0E, 0x4EEA0E27, 0xEDCF27C1, 0x1739D5DC, 0x22DE2CE1, 0xDCCAF633, 0x31D02417, 0xD7DCD0DA,
-0xDE1DE0DC, 0xD827DD22, 0x1CDBD7EC, 0xCE171BCB, 0xEE2347CF, 0xC22C312D, 0xDBCC2A38, 0xBE0ADED4,
-0xDC20CC2D, 0xD5380DB2, 0x2A32C701, 0x3EC7D41E, 0xCDD7D74C, 0xE83E2A44, 0xC12B26E6, 0xE70046D7,
-0xD626D1EC, 0x35DDE41D, 0x303F27BD, 0xC94D4517, 0x31D1E229, 0xAD3529BF, 0x3AC5D21C, 0xCF1DB731,
-0x2738DBEB, 0x1F382B33, 0x1ED52213, 0xFCE22CD2, 0x1330331E, 0x4A30BA0F, 0x1F38B42A, 0x2E34CB1F,
-0xE3E125D5, 0x3AC72D17, 0xBD3C342C, 0x37272810, 0x1D34E4C7, 0xE5CC2EF8, 0x1E2FF1DF, 0xB9294236,
-0x26F10017, 0xBDE3FBD1, 0xB7DB52D0, 0x2E3CB8E9, 0xB3343D3C, 0x3E3BDFDD, 0x1F46393A, 0x25FA20C1,
-0x2D194CD1, 0xE9471D26, 0x34C3242E, 0xAE012034, 0xC8F3FED7, 0xB825362B, 0x322DC136, 0x42F41511,
-0x181855C2, 0x4937D5EB, 0xE13CDC23, 0x08242A28, 0x2DCCDFC0, 0x13CEC64F, 0xB3E6F7ED, 0xD93401EE,
-0x3D02DEE0, 0xCFC52300, 0xD2F1BE38, 0x2D092924, 0x253E2AF0, 0x37DACAD0, 0xDB1ECFE7, 0x40CED84D,
-0x3706C42A, 0x4231D91A, 0xDD30471D, 0xBD272DC8, 0xCB1941D9, 0xC22FC7C5, 0x333F3C0C, 0x3F3D2518,
-0xDDCCD143, 0xB3D834D5, 0xD231BEE4, 0x2BDB3B3D, 0x2F2754E7, 0xEAF3CE64, 0x3632E4C0, 0xD83324C2,
-0x11A4D5CC, 0x00D627D3, 0xD51F2731, 0x17C92BE2, 0x1AD62E1E, 0x16DB2418, 0x16B83823, 0x2711D54B,
-0xDFB02BDF, 0x28CDA600, 0x2AE9ED3E, 0xD314CD20, 0xD04F272D, 0xD0F9CD37, 0xCC1735E5, 0xD328EC37,
-0xA7D31A26, 0x214BD9A5, 0xCFCB4226, 0x233C4AD5, 0x26EF37D8, 0xD83E3230, 0x3EC8C93C, 0x07B9282B,
-0xD1E6DAF2, 0x31C52EDD, 0x3A0038A5, 0x56C1E0DF, 0x22E437C0, 0xDBC8143B, 0xCF1DB03F, 0x1D4BE636,
-0xB8D3C23A, 0xBCC3372E, 0xAF284228, 0xDCE02F1E, 0xB9D4E3D4, 0x56D3D0D8, 0x494816C1, 0xFB1240C3,
-0x23B1BDD2, 0x1236322E, 0xC2CBCB47, 0x102FE7C8, 0xBB0AE1D9, 0x3831BC29, 0x39AECBD9, 0xC7CF1ED2,
-0x0AE43913, 0xDDD62F2C, 0x4FD522E6, 0x3CB90A55, 0x2101C8EC, 0x432604BD, 0x29E3E31E, 0xC25B3C29,
-0x20E927D4, 0xD4300C41, 0xD9AECBD5, 0x48D8E143, 0x2CEE272F, 0xD2C11FBA, 0x2F2DB8D7, 0x1CF4DFE6,
-0xCCDCCEBF, 0xE052D0EA, 0xDADDEB1E, 0xC72ACB3A, 0x332E2B1B, 0x2D26E827, 0x2A29E6A6, 0xE614D6D5,
-0x221D1CC5, 0x51102031, 0x1735C248, 0x31D4DCD5, 0x3C20DC00, 0x2D231732, 0xE54AD9CD, 0x1D24D826,
-0xE936373A, 0x20C0D3C9, 0x2B231520, 0xD6CED133, 0xDFC8C7B5, 0xDC2FE8B8, 0x3332249B, 0xC6E6E11F,
-0xB7DA17AF, 0x1FD91321, 0xEE29CD41, 0xE1262FEF, 0xB6181DC6, 0x24F618C6, 0x3BE5DA2D, 0xFC2C35C8,
-0x51C232CC, 0x36183EDF, 0x2B2CD6EF, 0x2F2DBDB9, 0x00D03413, 0xCDC9CBC4, 0xDB3309CC, 0x264EB22C,
-0xCED1EAC9, 0x38D53F27, 0x2EE7D6F3, 0xC7232C23, 0xCCD42515, 0xC9C8C8E3, 0x231E3930, 0x5BBEDFCA,
-0x34D7E5D7, 0x25CCE9A7, 0xCD4BF1E8, 0x5E2542E6, 0x38DCE43E, 0xDA34F0CA, 0x2EBFF841, 0xDA422D3E,
-0x13CA2231, 0xD5C6DA27, 0xBAC0C6B6, 0xC82C49FF, 0x31312123, 0xBF00DFBF, 0xE8F23819, 0x2C34E81E,
-0xDC4C2B0C, 0x3A5650F2, 0x2CCB0FD0, 0xC42D4C28, 0x4F19DA4B, 0xF63DE630, 0x29F51C1F, 0xD6BE14C4,
-0xD2DDCDD6, 0xE0D02825, 0x2FE0E3D1, 0x41342FE8, 0x25D547ED, 0xC5A732B5, 0x19BD503F, 0x4CD9DA3D,
-0x24D013BF, 0x4FE93FCA, 0x12DBE8B9, 0x33DF151F, 0x1E24AECD, 0x2E2E3656, 0x133500AD, 0x3641403C,
-0xBDDF2BD4, 0xE33130E0, 0x3DC02726, 0x18390C3C, 0x26C04DC9, 0xDBF22D35, 0xC3E1EC45, 0xCED12623,
-0x1CE92E39, 0xCF2FD222, 0xD8DE31E6, 0x1EE916D1, 0x35DCB621, 0x19C2EB54, 0x41B34ED4, 0xD9373BDF,
-0x203ED6D8, 0x2CD4A8C8, 0x14E0C6C6, 0xDF242131, 0xCDD921CF, 0x33AACBCC, 0x2AD1A5C6, 0x3ED42B00,
-0xBF181FD0, 0xC0CC2329, 0x1BD1EDC9, 0x3A2D47CB, 0xDD27D8CB, 0xD8E8BAE6, 0xD5DE3FF5, 0x2C30D641,
-0xDCDCDF26, 0xC2C34433, 0x2837F53D, 0x29D8E12D, 0xBF3FEBD0, 0x34CACC45, 0x30E1DA21, 0x39DDDCB3,
-0x30193518, 0xC0132E19, 0x313D3736, 0xB2D4FF34, 0xF4D92945, 0xC70D3AEA, 0x3E3034F0, 0x00DA2F07,
-0x1DD415EB, 0xCC1AC4B2, 0x232EB21C, 0xD7431E16, 0x2FCE0835, 0xCF39242C, 0x1BCA2CD4, 0xD8B6D0FA,
-0x18C3262F, 0x2CE3BDCB, 0xD839DC38, 0x26161D24, 0x1223B3DC, 0xD6D63515, 0xCFBABFC6, 0xC1BF18C7,
-0x2637C715, 0x264020EA, 0xD024D3C4, 0x4126A11D, 0x2E34442D, 0x32BB1CC9, 0x36E7DD40, 0x3113C3C5,
-0xD100C8CE, 0xD21651E8, 0xC3CFCDD9, 0x403139F1, 0xD3D02119, 0x32171AC8, 0xD2F9B62E, 0xB5B335D4,
-0xC1462835, 0x1F1C2C35, 0xD8DDBF35, 0x422D2DDA, 0x38ED19D7, 0x3326BD2F, 0x4534DFCE, 0x46403132,
-0x19CDD51E, 0xCBC3CBC0, 0xE3CF2139, 0xC646ECD8, 0x29E7C7DD, 0xE94CCAF8, 0xB8C6EA37, 0xEC2B09DA,
-0xC8C82738, 0xC6CCDDFB, 0x3FCA3B4D, 0xC6482BD1, 0x2DE1D333, 0x3530BB3A, 0xBF4838EA, 0xE4411ACB,
-0x3514D939, 0xCD372B27, 0x4BEC1C39, 0xAB21C221, 0xD8D83F37, 0xCCE0512D, 0xDA4640C2, 0x36AE1CD6,
-0xBC2F303B, 0x20C3B8CD, 0xBFE6D4E0, 0xBECCC4EB, 0xC7CC1E4E, 0xCC2BD03C, 0x3738C518, 0x23B824CC,
-0x2BECD0BC, 0x2107B945, 0x2AC21B00, 0xBE49F2EB, 0x31D2E3DC, 0xDAD23F11, 0xCDED3137, 0x3ABADA3A,
-0xD9C0C12C, 0x36CEE8CF, 0xD0D5BDD3, 0x2AC9CFCC, 0xE61FD747, 0xC7B7B12A, 0x2BD520DF, 0xD5BC1D31,
-0xE6D8423B, 0xCC21EB43, 0x1F46292D, 0x171EE038, 0xDFA5E244, 0x1BD5C4AD, 0xC622C2B5, 0x4E33CFD3,
-0x3F263F30, 0x34E4CF15, 0x0041CC36, 0x4021DB29, 0xD62E2231, 0x2C22AE21, 0x1A201F44, 0xC6D7C100,
-0x3A335125, 0x42473A2A, 0xDF32DA1F, 0xE5D8B51F, 0x3049E832, 0xE6DED531, 0x315DD01E, 0xDDD92034,
-0x2EBF0AEB, 0x4B4639DD, 0xBED6C8DA, 0xDABA3714, 0xDD133BD7, 0xC934EACF, 0x0D35C3E2, 0xB4CCC213,
-0x37EE202B, 0x0AD21AD9, 0x28D2C9CD, 0xD800DB2D, 0xD34B274A, 0xBDD33644, 0x38EFF1CC, 0xBDABD734,
-0xB11E3E32, 0x2F1C23DC, 0xE80BD7DE, 0xDBE7D6F7, 0x240248BF, 0x23CEF1F6, 0x1F56E634, 0x33CD2230,
-0xB4DB182F, 0xD338BA36, 0x33392B24, 0xBB3B3649, 0x282F30E7, 0x45CC35B1, 0x46261B30, 0x1FD9A722,
-0x3BE3E1C3, 0x25334FF0, 0xB8BB28C0, 0xD751E2CC, 0x403600E1, 0x461FC3ED, 0xCB30C202, 0xD8D2B92A,
-0x2923D71B, 0xB9DDE6CC, 0xB935CB0A, 0xEF37D723, 0xD1DA06CD, 0x303CE928, 0xF8B9BA27, 0x37370A1F,
-0xD6C1DDD9, 0x18B6463F, 0x28C71FC3, 0x38D8B53A, 0xD22DE9A1, 0x18DDB236, 0x0A28D515, 0x363B263D,
-0x1F3A122D, 0x202AE323, 0xC72337E8, 0x32ED08CC, 0x2658C347, 0xC6F4E200, 0x45D1C2C3, 0xF92D343A,
-0x3EBE1E65, 0x10EB2FD3, 0xC64FD5E5, 0xC5D3F521, 0xE9CA1A37, 0xD736CDD6, 0xDCC7C233, 0xC9C8E2D4,
-0x2B99D60A, 0x1EE3DA0D, 0x30BDD8E1, 0x16D3BE1F, 0x1C4524D4, 0xC8D5D432, 0x19AEDA3D, 0xCDD4CAD5,
-0xD835332E, 0x2412DA1B, 0xD0CBEBD7, 0xC3CEF425, 0xD1D743E3, 0x000A163B, 0x23DC3129, 0x202332D1,
-0x322F2216, 0x28F5131A, 0xD316CF0D, 0xD0344C30, 0x423325D7, 0x37204237, 0xEEDDC721, 0x2038E805,
-0xD525C522, 0xBEDDE327, 0x3AC8BCC5, 0x45402E27, 0x34DFC1D9, 0x2DB0D049, 0x322F2ACF, 0xDB3AC3C5,
-0xD8D0EB4F, 0x2A1DCCCC, 0xD0D33DC2, 0x1349DC45, 0x39CBBC32, 0x30301EBF, 0x2C00DFC0, 0x5DD0CA11,
-0xD0220C3A, 0xC527CD1A, 0x31CD372C, 0x2E0ED7DC, 0xC6F92338, 0xF537E8D0, 0x3626DBBF, 0xC9C3C6C3,
-0x30DDBE17, 0x50394C39, 0x3A11343B, 0x27E8DC2E, 0x0DDB303F, 0x1818BCF0, 0xC5DC17DB, 0x24C53A26,
-0xECB0E7E2, 0xC21B1928, 0x15D7C920, 0x4126AACE, 0xE214D8C7, 0xD40BCD42, 0xB2CBD018, 0x554436DB,
-0x3C2D25D9, 0x21CEC0DC, 0xE9251919, 0xE41ACDC3, 0xDECF67C3, 0xEDDE3225, 0xCA30EEDD, 0xCFE01E37,
-0xD231BF41, 0x34DF1EBD, 0x1DD2CC2C, 0x21142E29, 0xEA322B37, 0xCEC311DE, 0xF0F738DD, 0xEBED1A40,
-0xDCE640E8, 0xD0D1BA2B, 0xE906D6DB, 0xC71938B1, 0x13C59F39, 0x1ED6DBB6, 0x231BD3A9, 0x2C2B30DC,
-0x0ED50000, 0x2DD4EED6, 0xD9D21BEE, 0xE1442E36, 0x38CEC4AE, 0xC626CCF4, 0xC2CD3F36, 0xD71F2BD9,
-0x2F421837, 0x31B11A23, 0xD4D5282D, 0xD0E6BED7, 0x30D737CB, 0xC8142A09, 0xD8D2CFDC, 0xC22D3C44,
-0xF62DF1C9, 0x3D38DBC9, 0xBFC2E5D3, 0xDCE42128, 0x3A304038, 0xDBE6D626, 0x28250FE0, 0x27B52BCF,
-0xE0D8DC3C, 0xC8DA09DA, 0x2DF02FD4, 0xE539D7D1, 0xCDE729C2, 0x4816E313, 0x4E392AC5, 0x112CF50F,
-0x3AD94924, 0x4B22273A, 0x43D2DE9E, 0xDA22DE30, 0x3FE324DB, 0xD9CC2811, 0x29D253D4, 0xE2BC353C,
-0x0CC92147, 0xB8F0C6F5, 0x3D35DEBF, 0xED4ACBEB, 0xAC34E532, 0xEA2AC526, 0xEAC0BFC8, 0x4431D9DD,
-0xC0CE4E21, 0x0000F2DD, 0xE0D8C7BA, 0xDDDC2E36, 0xDA42C22B, 0x2B312614, 0xDC391EF4, 0xCC2E31D8,
-0x3DF4D630, 0xC72C21D9, 0xDB2BD531, 0xD916DB3C, 0xBEC11DD2, 0xD1D5CEA4, 0xBA072ED7, 0x402F2829,
-0xE3C0F627, 0xC7CC3CBD, 0xF41D3345, 0xD706DB14, 0xB2DF36AC, 0xEBC4551F, 0x32B01929, 0xC5B6DDEC,
-0xD91DE130, 0xE1213222, 0x4126D927, 0xAF52300D, 0x291B301C, 0x241A1843, 0xE43C1FDC, 0xBBCC191C,
-0x2C25E011, 0xBD3EE9DB, 0xC9BF1345, 0x2F333AD2, 0x1CD822DB, 0x23BE43EA, 0x2527EADC, 0xB52E1C1E,
-0x391CCF17, 0xD2C82C0C, 0x242E3830, 0xD328D808, 0x35CEF4CD, 0xD81BE035, 0xD0DF38DA, 0xD1D3C42E,
-0x3A2C1EEA, 0xC6D03AD2, 0x1E362E4E, 0xE6080000, 0xD018C312, 0xEFAA323B, 0xD1294BD2, 0xBAD52C3B,
-0xE0373E10, 0x260CDDE2, 0xC902E040, 0x30472BD5, 0x534BE7D2, 0x20CCB523, 0x21CCD843, 0x2259E24E,
-0xDE35FDD1, 0xD4D91D3E, 0xCFCA11D5, 0x35D724BD, 0x3C3F0CB8, 0x3EC447CB, 0xE835DDC4, 0xC3C73E31,
-0xDD432B2F, 0x2FDCBDC2, 0x2D3CCE17, 0x25B8AB31, 0x2ACCFFE5, 0x40E03C2B, 0xE7DA1841, 0x17E53020,
-0xD44E0B2F, 0x46DA22EC, 0x33422425, 0x211840C5, 0x23C1CFD5, 0xC8350BE5, 0xD833CDD0, 0xE63DC528,
-0x292ADC17, 0xD8BCD3C1, 0xCD39F02E, 0xA71EC343, 0xD6CC3A3E, 0x2E12D2CF, 0xC40B1FB1, 0x37DCDC33,
-0x20E52EEA, 0x271629E5, 0xC4BEE0C2, 0x1B3CDBD6, 0x00004934, 0x18E145C7, 0x4BE93522, 0x3029C309,
-0x31D1D50F, 0x3DB42C1A, 0x21A643B2, 0x3E26D8C2, 0xCDDE28D1, 0x44E835E1, 0xEDC4DED1, 0xC4F9C9ED,
-0xC5E1BBCC, 0x4426C1D4, 0xD9BB372B, 0x37232E0D, 0xE5D0D0AE, 0xC9D23CC5, 0xF638E2C7, 0x2DB6E6D9,
-0xC0C9B72D, 0xDF28E6D0, 0x11E2DCC8, 0xD8E2F31C, 0xEA3937DE, 0x2741B953, 0x19D5CEE6, 0x33DDC22D,
-0x2BF72326, 0x2143363C, 0x13CA1A1F, 0xB9D7DAC9, 0x22C6B72E, 0xC5DA2631, 0xCB32ECCF, 0x032D15D4,
-0xBB1EE613, 0x38C42452, 0xDBCD2726, 0x1AF44039, 0x22CF2EC6, 0xCAEDE6B4, 0x2823D423, 0xDCC61C39,
-0xC12D19BF, 0xC612C31B, 0x31F1D32D, 0x3E1C09E4, 0xD824C5E7, 0xDFFC2839, 0x2AD40000, 0xDFCCBBBC,
-0x3FC9CC12, 0xEF2626E1, 0x0FCDEA2A, 0xEBD735CF, 0x4E1A2834, 0xCDEDE1D5, 0x31CCCD29, 0x2F4618DF,
-0x48C11936, 0x29DADE41, 0xD71C1AE0, 0xDDD2285A, 0xB13DCDC8, 0xF020B8DB, 0xD0B837C2, 0xDC3B48E8,
-0x18C3C530, 0x192C2940, 0x2ADA3AE4, 0xEA34C55A, 0xDAB2BED4, 0x1A51E838, 0xC832AEBE, 0x10DE2DE2,
-0x3B2408CC, 0x22CEBD1E, 0xC919D6BE, 0x21D2D128, 0xCFE03A2A, 0xB7DEDC3B, 0x33C630ED, 0x5A0EEAD1,
-0x3CB03FCE, 0x24EC15E4, 0xD0385BBF, 0x20CB4E4B, 0x30E0C535, 0x301BCD3C, 0x3642DDD3, 0xD90FDC50,
-0xCA35BBCC, 0x393B3B2F, 0xE2BE352D, 0x362BE3BF, 0x1922B73D, 0xDE3448BD, 0xF7C0C02D, 0x00002F43,
-0x2FCAD0E4, 0xDE412A34, 0xFBF339DA, 0x2BB94330, 0x39B521D5, 0x2DE31F43, 0x382C4F23, 0x35314C2D,
-0x2DE3DBDC, 0x3A18EAB9, 0xD0DF131C, 0x45EA41E0, 0x48BBC1BF, 0x2220D7E4, 0x29C8D0C5, 0x3C0527CA,
-0xC1ED061C, 0xCB48CA3E, 0xE846E633, 0x0EB2D7CF, 0x44C42335, 0x27F0D440, 0x332FD847, 0xD72F2CE3,
-0xD7ECD6C9, 0x4026D51F, 0xD334BEE6, 0xE01B40C5, 0xD62BDA2F, 0xDEEA36AF, 0xABD039C7, 0x2E123FCE,
-0xFD3924A8, 0xD0C6D529, 0xD52AEED4, 0x211D2A35, 0x1EE9C5F1, 0xCECAF921, 0x38C92740, 0x3E4E2A1A,
-0xB8FAC7C3, 0xF11F1C36, 0xD4DA163A, 0x2701DC38, 0x0E3019D5, 0x57DB23E1, 0x43CD26D0, 0xADCC4934,
-0xE0D3D706, 0x403A0000, 0xDECED5E1, 0xDAE6CF1D, 0xD5E33C40, 0x35B3D038, 0x24D73231, 0x2EC01D40,
-0xC2D23CDC, 0x44C20BC6, 0x44C1D7A8, 0xE9D1C745, 0x36E5C2C6, 0xB81B2D42, 0x413917CC, 0xD8E031BA,
-0xCE3CC1C4, 0x3EC91AC5, 0x0DE406CE, 0x35D1DA27, 0xC8E5CAE3, 0x313EC127, 0xB61631CA, 0xD73B3444,
-0xD834C850, 0x37D31DE2, 0xCCC9153D, 0xBF41E9CA, 0xD649F9DC, 0x3A31D501, 0x50CD1DE3, 0xC8E54012,
-0x4432D4D5, 0xCBB93023, 0xE8FCD6C2, 0xCEE0CAD1, 0xE41B2E39, 0x28CC0E40, 0xDFEAEFFD, 0xB3EA2723,
-0x3534B935, 0x42D12A09, 0xED3DCA0A, 0x263C352B, 0xAD224EDF, 0x2CDF2A10, 0xF0BE4CAD, 0xBD45D8D5,
-0x263F27D4, 0xE2372FB4, 0xC35240DF, 0x1EF3DCDA, 0x3AD0D224, 0x27DAD527, 0x303A2CBE, 0xCDDCC829,
-0xE22B35C9, 0xD5DC222F, 0xEEBDCB63, 0x2042DAD8, 0x06CC3524, 0xD11BBB3E, 0xAE2229E6, 0x1FC81E1F,
-0xEF4B12DA, 0xE1D846DD, 0xBA3B1CDA, 0xE154C801, 0xD6092CD2, 0xD0F132CB, 0x3A40D027, 0x123530BB,
-0x1EC5B4DC, 0xD11825CB, 0xC603DECC, 0x28BCC5ED, 0x2C03E1CD, 0xE9AA12A5, 0xDB2DD53A, 0xCA32D01E,
-0x2F4A09C5, 0xFE411E26, 0x1354CEC8, 0x3736C5F4, 0xC62F3C3B, 0x252DDFB9, 0xD0353723, 0xD8DDC21E,
-0xE3DF21ED, 0xDAE33AC0, 0x2ADA323E, 0xDC43E1D9, 0x3A23463E, 0xD71934F8, 0xDB1037C8, 0x38B7BCCC,
-0xDA2C1CC1, 0x3EEEE349, 0x2ACB2A26, 0xD4BCBCD8, 0x4AB50000, 0x9EC941D8, 0x3824C9D0, 0x203CCD36,
-0x0DCDEDD8, 0x5B333036, 0x3125C7DD, 0xD7383F30, 0xD6C72617, 0xE1C245DD, 0xBDD3E818, 0x3210422F,
-0xD00ECF2E, 0x44411A3A, 0x02E72E22, 0xF106D24C, 0xCFC847CF, 0x0421AFCF, 0xD2C525A9, 0x3CBCE63A,
-0xE02A1E36, 0xE036E3E4, 0xDDC22B25, 0x2EC7452E, 0xE1E3EFE3, 0xD82ED6CE, 0x36C1E115, 0xD129E026,
-0x251E1C44, 0xE8E5D7CA, 0xDDE7D40F, 0xC5D8D9D8, 0xA1C52550, 0x3ACDDA25, 0x3548C4E1, 0x2913D9C8,
-0x1E28243A, 0xCA3324E2, 0xD0D7D1C0, 0xBDE9D0C4, 0x35BF4FE0, 0xCA42E33C, 0xBBFA33DA, 0xD753C9CD,
-0xDA2CE11D, 0xD9BEE407, 0xE31DD4C1, 0xCBCCD51B, 0x3BB8D6C9, 0x0000DDDD, 0x28D3CDDC, 0xD62445B5,
-0xB3211F13, 0xD7B9BF29, 0xD429D5E5, 0xB9C23CCE, 0xC219EDC1, 0x211E0B34, 0xB8F0E1C1, 0x33C0EF4C,
-0xD8D6C7D0, 0x30E8D3D8, 0xB06514D1, 0x21B9D915, 0xE2323DCD, 0xDA41311F, 0xE24AB11F, 0xE9B92BE7,
-0x33EA23C3, 0x04C430C0, 0xE849EF0D, 0xD1232C2C, 0x260FD13E, 0x002DCBDD, 0xEB3129E2, 0x20B4C7C6,
-0x25D32335, 0x2CCB39D0, 0xEA13DAC6, 0xCDEE2E14, 0xCDAA2CD0, 0xE1D339E6, 0x36DCD03B, 0xF5453114,
-0x34D428ED, 0xEAEDF458, 0xD226CC2D, 0xEDD03AD8, 0xEE1CC83D, 0x10DBB5E5, 0xF018CBDB, 0x5E33E31E,
-0xC6D9232B, 0x1A373130, 0xDFE7DDCB, 0xB21FC5C6, 0xC1CDB1B7, 0x3F2DF128, 0x482BB426, 0x323E0000,
-0xF5D43741, 0xCC1C1FB9, 0x00004E2E, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
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-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
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-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
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-0xFFFD061D, 0xC2D9251D, 0xC1D7D625, 0xBFCD3AD3, 0xB42E11D4, 0xC7230E1E, 0x24CD2C21, 0x0BD436F9,
-0xCECCD331, 0xE6BDE0D5, 0xD2C6C941, 0xE1D1D3EF, 0xEB4123CD, 0xDA1755E5, 0xCEE4C529, 0xDC43C5D1,
-0xD8FDDFEA, 0x1AC9C317, 0x22E13DCE, 0x01D7BA29, 0x1551E449, 0x43CD363E, 0xC6281B24, 0xCBD23725,
-0x3200D61C, 0x35D6CCBC, 0x262CB22C, 0xE2E43DB1, 0x26493335, 0x3AD72ACA, 0xC4244430, 0x3AD7C9C3,
-0xC91ED8D1, 0x40EAD2AC, 0x38C9CDAC, 0x413BC137, 0xCD304B1F, 0xEFCA2323, 0xAC3FE4CD, 0x3616F6E0,
-0x41C2272A, 0xDCD7B2E2, 0x27D9E018, 0xDEE2D943, 0xD5C01F22, 0xB0D93540, 0xB411C13D, 0xDE39CBE0,
-0xE2C6F126, 0x31450828, 0xD2BC2927, 0xBACA1DD1, 0x34DDCDC3, 0xD8302AD5, 0xE2D02824, 0x0B2BE03E,
-0x3BCAFD2C, 0x2E461D45, 0xBBF6F32E, 0x31E5DED2, 0x2ED4E847, 0x3BDDCD29, 0x231331D8, 0xF521CF2E,
-0xD024C718, 0x20D91011, 0xDB1E0F34, 0xD931C0BB, 0xBB310837, 0x29B7C5CB, 0x3B31DEE0, 0x0836B926,
-0x28CB1FD4, 0x31072A30, 0xEE41F300, 0x35CB501E, 0x603A2B47, 0x2C2739CE, 0xC0CFC4D9, 0xE0CED43C,
-0x22BDC9CA, 0xBAEC122D, 0x4D16F2C5, 0xB6E5C3DA, 0x19D5C9D0, 0x1D1DDFC2, 0x223A23FB, 0xCD382B09,
-0x3025C2E6, 0x3918BDD5, 0x33DFEF0E, 0x291A302B, 0x14184930, 0xD414D233, 0x473CCED7, 0xD2D318B7,
-0x3E2738D2, 0x2928D537, 0x002E14BB, 0xE2E03734, 0x1B1EDFD1, 0xCF483FD8, 0x3D043844, 0xD52E1C4C,
-0x2823EAD6, 0x1F2D241A, 0xBC4B22E6, 0x2EE7DFB8, 0x3424E2F0, 0xD41BD7CB, 0x2BBCDF1E, 0x155B5033,
-0xB527D543, 0xE3C5E9F4, 0xD9B5C92B, 0xD3CAE0DF, 0x31C4CED7, 0x0BD33B25, 0xCF3B111D, 0xE62F241F,
-0x22D93D22, 0xCF27EF43, 0xDAD2C5DD, 0xC60019BE, 0x2935D5C3, 0x2D0BCD22, 0x224714EA, 0xE7CAB817,
-0xD1282222, 0x3C25EBD0, 0x45F0A8DC, 0x3ACFB92D, 0x34B4E7E6, 0xE93523E0, 0x2C292FCA, 0x44D4C7AC,
-0xEA22C3FE, 0xEF37E524, 0x313ADCDA, 0x2212D846, 0x1BE0FF4B, 0x1CBC2E34, 0x174AF041, 0xD245223E,
-0xE1DB2BDC, 0xF2E9A515, 0xE3C33BCC, 0x43DBD5CE, 0xF11700DB, 0xDE44DD36, 0x26E1D604, 0xC2ACE419,
-0xB9D8C7D4, 0x37EFE21E, 0xE2BAC2D1, 0x3926E91A, 0xD013E8BC, 0x2C43ECD9, 0x232B30F8, 0xD6C9E0BD,
-0x26A718BC, 0xEFF6C840, 0xC13332C2, 0xC4B9BD36, 0x1B4921BD, 0xD0EBECE0, 0xBCE4D647, 0x35D4DCD5,
-0x1BBE4C27, 0xECC1B7CB, 0xD820284D, 0x0BC33DBF, 0x34D03140, 0x38EC3900, 0x29EBDBC9, 0xD43A3041,
-0x3AE0DD0C, 0x09CFCFDB, 0x44E0C7CE, 0x20DBC4E3, 0x26DC41DE, 0xBA3AD2E5, 0x2ABA34E1, 0xD70FBEB7,
-0x40E03FE2, 0xF8D62041, 0xBD47B7EA, 0xD2E03E34, 0x1FC6D2DE, 0xCF1CD155, 0x32D52630, 0x3C463D2C,
-0x253130E3, 0x1ED8BB4A, 0x411BDFDD, 0x3FD8EE35, 0x33D02BBB, 0x002ECAAE, 0xDF1FDFEB, 0x2CD8DA3C,
-0xB6352D59, 0xD5BDD3B9, 0x1946630D, 0xD9181731, 0xD419D31F, 0xCE2FB7D0, 0x32EFE3C3, 0xCDDB2FD3,
-0xD247BB3E, 0xBA41DECA, 0x23244AD2, 0xDEAAF2B2, 0xB8D525F2, 0xD327A4D0, 0x3718C0E2, 0x2D3E20D9,
-0x24CFDF12, 0x26D0BE1C, 0xC8D9282E, 0xEB54CADF, 0x44DB1AED, 0xC927BF29, 0x2E002B39, 0xBB2625E4,
-0xBB4421D2, 0x18CBAA3A, 0x213ECD37, 0x0F33163C, 0x3622E432, 0xE5C7C62B, 0xDE39E7C7, 0xF3151CCA,
-0x2ACED6D2, 0x2ADADFC4, 0xD6241ACC, 0xB92F0622, 0x1BC639E4, 0x33D92BC4, 0xAF14E0DD, 0xE6EEC2C9,
-0x16BDCAE3, 0x272E1AC3, 0x292E1EBE, 0xDCE439B1, 0x4225E1C6, 0xCD372420, 0x27D716B1, 0xD83EE339,
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-0x0E3740CE, 0xE5D82C36, 0x29D1360A, 0xCD03C8C6, 0x37CCCCD8, 0xD83AD330, 0xBFD619CD, 0xDEDDC432,
-0xD0DADAEC, 0xD3E14F26, 0xA8CD35D9, 0xA3F325BD, 0xBC1626D7, 0x3AB81BD5, 0xBBFF1832, 0xC9DB2126,
-0x16250000, 0xE003BB39, 0x35D533CE, 0x1801C610, 0xD9D44644, 0x474BD3C3, 0x1C30C51E, 0x2E3342C6,
-0xB7D6B3E9, 0x5AE44BD2, 0x46D62830, 0xDBDD4B0C, 0x38CF2F1D, 0x2D331ACB, 0x36CCDED6, 0x10D7DA10,
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-0xB636C11E, 0x25CBE2D8, 0x4711F64B, 0xBC2C2029, 0xD0E3F538, 0xB92C27DF, 0x272DE2D2, 0x0CC5BCEB,
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-0xC3CAC9B6, 0xDBC436C6, 0x19DC1FD8, 0x28CCAED1, 0x1921BDB4, 0x24BCBF33, 0x301EE244, 0x36BDBDE1,
-0x31C5B724, 0x00003ECD, 0x220B1EE7, 0xDEBAD3DC, 0x21CAB942, 0xC9193B33, 0xE3CD3A0A, 0x0DC22CC3,
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-0x5ACEC51E, 0xF2172E1C, 0x3C24DE23, 0x3320D4D5, 0x2AB53C20, 0xC328323A, 0x45EA4133, 0x24391A32,
-0xC7D8DA2B, 0xF4EAAF39, 0xDFCA36E3, 0xDEBED5C8, 0x36252C36, 0x04D7DBC7, 0x30CAC23D, 0xB60BF73D,
-0xEACA2A30, 0x34C12ABE, 0xE2D747D8, 0x19D21FE3, 0x1DFD24EC, 0xB6B5D9C4, 0xBF2C1DD2, 0xD2B442E0,
-0x37CCE1BD, 0x2AD1E1CC, 0x18DAC6BD, 0x213AD93E, 0x2031D8CB, 0xD82F2D12, 0xD112D2F2, 0x19CD43F1,
-0x36BCB9CA, 0xD7C5DDFC, 0x34011D28, 0x3BDB0000, 0xCD00E1AA, 0x5228252C, 0x3512CA34, 0x0EE53A41,
-0x242CD2C2, 0xF425DD2A, 0xF02FDDF8, 0xD82026D3, 0x4ABEE7B8, 0x2DC9DDDC, 0x3BEECD3C, 0x2ED1442A,
-0xC713E92A, 0x310CC12B, 0xE128D520, 0x48E5C1CF, 0xC91CE3ED, 0xCCCBC72F, 0x0B23E3E9, 0xC1D2C8B6,
-0x511ED534, 0x2AC7D4C3, 0xCFDCE335, 0xD4C9F643, 0xD433EBF1, 0x1BF8DA31, 0x223FC515, 0xCC2F13C2,
-0xF825FFC8, 0x35E51633, 0x36293C4A, 0xC72ACA36, 0x4544E736, 0x1BD9315C, 0xCF16DFD4, 0xD0AFEFC3,
-0xCECBBDE2, 0x05D6AA32, 0xD851F045, 0x240FD948, 0x3D35B2E6, 0x17D7C7EE, 0x0B22DACE, 0xF53AD637,
-0xB2372DDB, 0xF6DF14CB, 0xBED95B24, 0xD4D5190B, 0x0000CB29, 0x3DC1ECF5, 0x30C6B34F, 0x1D2629B6,
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-0x3AD036C0, 0x3828DB20, 0x27D63439, 0xD21026DE, 0xD60710BC, 0x13AEB9E9, 0x28C41944, 0x49D5E3D7,
-0x27163429, 0x1BBAD528, 0xB12A14BC, 0xC72FD9E2, 0x1F43213A, 0x133B3EE5, 0x3622FE21, 0xD438DCBE,
-0x41CB25E8, 0xD0D83E2C, 0x32BFC2CE, 0x362BE1DA, 0xC3CBCE24, 0x22DECDC2, 0x30CBD5CD, 0xD42DBC26,
-0xDDF6AAD0, 0xCADC0EC8, 0xDC333434, 0x333114F5, 0xCE24361A, 0xB1C5D123, 0x4B25380B, 0x2FEC3634,
-0x3EE2A610, 0xB4CEE72F, 0x29BCC721, 0xB23850CD, 0xA51AE4DD, 0xC81BBC2F, 0xD4DF0000, 0x2DE5D1E8,
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-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
-
-hard_output0 =
-0x42441F44, 0x006DFAE9, 0xDBB63AC2, 0xA3365CB3, 0xFA44372B, 0xC2603862, 0xA6C86E09, 0x416F0BF7,
-0x8E58011D, 0x47C54B99, 0x269AD14C, 0x0B286902, 0x093E4C64, 0x8D84D8E1, 0xB8AE0993, 0x49567118,
-0x8CEAABD2, 0x12D33409, 0xE3358237, 0x130176F6, 0x0986718F, 0xA18C83B5, 0x04EEF058, 0x59704040,
-0x7478FE81, 0x01D27193, 0xEA1AD7F3, 0x21E6C2B9, 0x6478A1FF, 0xED9959AD, 0xE39E57BE, 0x4D859105,
-0x056EF72D, 0xBD170BB7, 0xF01F9ADD, 0x99BF0C05, 0x44BAD09F, 0xF6ABDD61, 0xC0F8F116, 0x2972B53C,
-0x0FEC944B, 0xD1675432, 0x0025F563, 0xF42B2EA8, 0x808E5C37, 0xB6E79AD5, 0x3706284D, 0xB9C0AFA5,
-0xFF0E7E28, 0x5FA45C6F, 0x9CD5244E, 0xA013DDEA, 0x0D27D1A2, 0x2AE414AD, 0x41614379, 0xE6B68872,
-0x5585D926, 0x5098D45B, 0xF8980ABD, 0x65821418, 0xEF8968A3, 0x301DEC3A, 0x57EF2A7F, 0xC17BE446,
-0x94B65D62, 0xC9E6F350, 0x2E6130BC, 0x235F2E5E, 0xF1C13241, 0x94B291D6, 0x8C342458, 0x175B1FCA,
-0xE07310FD, 0xD24934DD, 0x3CE8D053, 0x5C8F243D, 0x945B0AB3, 0x50EB8CC1, 0x8EF499D4, 0xA67801BF,
-0x1680F061, 0x283FE705, 0xB8D7E773, 0x13AD3D2F, 0x4A6C305B, 0x1C1E5B12, 0x6F57D880, 0x8A666E5E,
-0x26511296, 0xFFC09750, 0xFF91760A, 0xAC26795C, 0x75F321FD, 0x4221B9CB, 0x2E119188, 0x0772A832,
-0x74D6036B, 0xA001B764, 0xF0D72816, 0xCBE119F5, 0xC5D6B248, 0x1BBAB091, 0x1BBE518E, 0xC647DCB1,
-0x240CE252, 0x3F8AAE65, 0xE0CDEAAB, 0xBE724062, 0x5720636C, 0xC816E67F, 0x8E5A6C7F, 0x9E2738B3,
-0x2419CBDF, 0xA6BF9B75, 0x48B21FC3, 0x8C4AED8D, 0xC1D8BCA8, 0x01353DE3, 0xA99D7D85, 0x9C6DDD20,
-0xA650398D, 0x4E7E5777, 0x623FA183, 0xF02B261F, 0xF0BBA66C, 0x35AC701F, 0xD818E590, 0x7CA713BE,
-0x01153743, 0xD1302B91, 0x55459E3C, 0x63FDA677, 0xECF93759, 0xBBE0E349, 0x73FD4FDE, 0x5C48C9E8,
-0x70F46F73, 0x0B15437C, 0x9F4159A0, 0x7C343E78, 0xB3D085E1, 0x04266351, 0x1933DAD9, 0x83AF8C77,
-0x2AC11BE1, 0x76C25CF6, 0x083E6CF7, 0x00DDBA22, 0x6AD2F284, 0xF87DBC6D, 0x7D40B45D, 0x6EBF21BD,
-0x972E8535, 0x632B51D8, 0x5BFBA23A, 0xCDF1D44D, 0x11749158, 0x06DC45D1, 0x93D63A59, 0x9D0552F7,
-0x61C8048F, 0xBFDE9FD2, 0x77827B70, 0xFFB130DC, 0xF18BBCE9, 0xD50C324F, 0x15521E17, 0x7D2470C3,
-0x5EE34C4C, 0x2AC0C8AB, 0xB2283269, 0x4107FE15, 0xE6DA1ED3, 0x66A2A3A7, 0xB204B429, 0x0E02F9D0,
-0xE5A45550, 0xEAF94102, 0x18F57A81, 0x8EEC9C68, 0xD575F397, 0xFC1BE8BF, 0x104E073F, 0xDF219F97,
-0x2EC93D4A, 0x6033EE18, 0xC1351A38, 0x420C6A87, 0x0B5DC831, 0xD90D23E2, 0x13B9E883, 0xCD65BE3C,
-0xDB17A9CC, 0xC73C2A7E, 0x3281
-
-c =
-2
-
-cab =
-1
-
-ea =
-4918
-
-eb =
-4920
-
-c_neg =
-0
-
-k_neg =
-3072
-
-k_pos =
-3136
-
-rv_index =
-0
-
-iter_max =
-8
-
-iter_min =
-4
-
-expected_iter_count =
-8
-
-ext_scale =
-15
-
-num_maps =
-0
-
-code_block_mode =
-0
-
-op_flags =
-RTE_BBDEV_TURBO_SUBBLOCK_DEINTERLEAVE, RTE_BBDEV_TURBO_NEG_LLR_1_BIT_IN
-
-expected_status =
-OK
\ No newline at end of file
diff --git a/app/test-bbdev/test_vectors/turbo_dec_c2_k3136_r0_e4920_sbd_negllr_crc24b.data b/app/test-bbdev/test_vectors/turbo_dec_c2_k3136_r0_e4920_sbd_negllr_crc24b.data
index a866878..cfff56a 100644
--- a/app/test-bbdev/test_vectors/turbo_dec_c2_k3136_r0_e4920_sbd_negllr_crc24b.data
+++ b/app/test-bbdev/test_vectors/turbo_dec_c2_k3136_r0_e4920_sbd_negllr_crc24b.data
@@ -666,12 +666,15 @@ ext_scale =
 num_maps =
 0
 
+r =
+0
+
 code_block_mode =
 0
 
 op_flags =
 RTE_BBDEV_TURBO_SUBBLOCK_DEINTERLEAVE, RTE_BBDEV_TURBO_NEG_LLR_1_BIT_IN,
-RTE_BBDEV_TURBO_DEC_TB_CRC_24B_KEEP
+RTE_BBDEV_TURBO_CRC_TYPE_24B, RTE_BBDEV_TURBO_DEC_TB_CRC_24B_KEEP
 
 expected_status =
 OK
\ No newline at end of file
diff --git a/app/test-bbdev/test_vectors/turbo_enc_c2_k5952_r0_e17868_crc24b.data b/app/test-bbdev/test_vectors/turbo_enc_c2_k5952_r0_e17868_crc24b.data
deleted file mode 100644
index 1300650..0000000
--- a/app/test-bbdev/test_vectors/turbo_enc_c2_k5952_r0_e17868_crc24b.data
+++ /dev/null
@@ -1,300 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-# Copyright(c) 2017 Intel Corporation
-
-op_type =
-RTE_BBDEV_OP_TURBO_ENC
-
-input0 =
-0x11d2bcac, 0x7715ae4d, 0xc9f4dbc6, 0x2fda3c1a, 0x09349b16, 0x2cd3c189,
-0xe5650429, 0xc73c42c1, 0xe7336bb7, 0xbb7de593, 0x83f986aa, 0xc0ade12e,
-0x6730b095, 0x78f7c059, 0xaa907199, 0x75c323d1, 0x7061f9ba, 0x97e067bf,
-0xc155cd55, 0x6a4cb08d, 0x4260e2fa, 0xff35e496, 0x37f251d3, 0x02fd9f9e,
-0x6f53345c, 0x790cda6d, 0x3b8549e4, 0x56d0c6ea, 0x70a38006, 0xfff18223,
-0x6f2035b5, 0x6cf508d3, 0x98a0a308, 0x432353fc, 0x0eb818eb, 0xdd9a128b,
-0xf92431b2, 0xad788286, 0xda07d5de, 0x44b4b3a8, 0xbe62fd67, 0x61a4eb54,
-0x90d7ac9f, 0xc4d9a930, 0xfddc3c24, 0xf5e3b1c8, 0x38143538, 0xcb1d3062,
-0xcae36df3, 0x50a73437, 0x542dcab7, 0x875973a0, 0x34690309, 0x49cb1ddb,
-0xf8a62b92, 0x82af6103, 0xc9f8c928, 0x3835b822, 0x16b044a6, 0xdae89096,
-0xa5be47d4, 0xaf61189e, 0x5cd70faf, 0x037331cf, 0xef7fa5f6, 0xb2f2b41a,
-0xa6f222c6, 0xdb60fe4c, 0x2a857a9a, 0x0b821f9d, 0x348afd17, 0x7eecbaeb,
-0x92bb9509, 0x8a3cec24, 0xd02549a2, 0x155ffa81, 0x2b7feac6, 0x3ee461e7,
-0xc981f936, 0x89b544c7, 0x9a431e36, 0x62511734, 0x769f9647, 0x211a747e,
-0x567abef4, 0xad87e2b4, 0xa3e0c3bf, 0x6d325dd5, 0xf561cc46, 0x39925735,
-0x3d8abbfd, 0xc3724c88, 0x8bdf03c9, 0x1b02a12a, 0x4f233a0c, 0x9ca9444a,
-0xc5d1f7e6, 0x4d995f37, 0xd9aefb32, 0xd0465248, 0x0f3a3b21, 0x62ea8c0c,
-0x91f8d54e, 0x5cf75514, 0x14618a01, 0x8fe9b87e, 0xf2b424f9, 0x49724ce2,
-0xa1464587, 0x5e00dc83, 0x59475455, 0x444119b1, 0x4fb9f036, 0x65fcbc1a,
-0x1c63a990, 0x767a6114, 0xb0ede06a, 0xcfb91ae3, 0x7874af5f, 0xf78772a3,
-0xa2932c81, 0x77f2759d, 0x930dc8f1, 0x95ce14a5, 0x134363ee, 0x61ee143f,
-0xf0034b35, 0xfdc75fce, 0x3be2dcf3, 0xff3a07eb, 0xdc43f0eb, 0x23ba73bb,
-0x45f7649e, 0xcacc297c, 0xa3dd98db, 0x058d46a9, 0x6bcfc154, 0x7be8e1e6,
-0x618a4754, 0x8d193c46, 0xba39e1ce, 0xc3b85cfc, 0xd80d853b, 0x38d6440d,
-0x9c1a6185, 0x90c9dfcb, 0x01c6e841, 0xeedfe6ac, 0x7b61a3ae, 0xad3924dd,
-0x514bc1a8, 0x6ed60d7e, 0x1b74b79b, 0xea295947, 0x5f9a5d33, 0xcd24311f,
-0x0bd3d10c, 0xd214ecfe, 0xcb37035d, 0x8ce95168, 0x7020cb52, 0xe432107d,
-0x042d63ac, 0x6201c8dd, 0x4bea65a2, 0x1a3cf453, 0x5b8e868d, 0x3d653bb0,
-0x24c1967e, 0x37f183a9, 0x3700e703, 0xb168a02b, 0x2592cd82, 0x5c0cdb66,
-0x70b64ebd, 0xf8dcb9a7, 0x634a8335, 0x06642398, 0xfe2f4497, 0x2e775256,
-0x30f85cbe, 0xf4d2fdaf, 0x46ca6c9d, 0x022097d6, 0xcedeb03e, 0xaf9437bc,
-0x341f8045, 0x93f6ff86, 0x2e019ec9, 0xc80116e8, 0xf984ff34, 0xe4f1be20,
-0xfe455510, 0xc561cdba, 0x2d6f560f, 0xb239fd9d, 0xd254e343, 0x8090448a,
-0xa724c4f1, 0xa00fe4f0, 0xf0379ac6, 0x0c61b383, 0x44b2228e, 0x9d223bc0,
-0xe7cfbc38, 0x62ae6a40, 0x6f8d445c, 0xc6045eaf, 0x8507df18, 0xe64c057e,
-0x4e589113, 0x3ba3bf55, 0x6a702b19, 0xea23af7d, 0xa1b98022, 0x7096c45c,
-0xace3b8c1, 0x47ed7bb4, 0x198a2b8f, 0x586b57db, 0xbf9d24d4, 0x96054c66,
-0x13f26306, 0x2a43524b, 0x1ecd419b, 0xb3a24852, 0x4ed7765f, 0x4c99fbe3,
-0x6c3b9ebb, 0x1ef7bfeb, 0x0daf1256, 0xe9c90c7f, 0xbe067ed7, 0x469102ba,
-0xedccc098, 0x96691fb1, 0x2a9b850f, 0x58aba5f2, 0x0bcad31d, 0x90b1f25b,
-0x78a55fe4, 0xdd41e626, 0xdcba3e83, 0x2209d8a9, 0x6ee2f76f, 0x55643570,
-0xd181a0ef, 0xd1b2790a, 0xc7793587, 0x3aebe10c, 0xbbde5fe0, 0x5c308948,
-0x01439ece, 0x5319fbef, 0x10b0de1b, 0x6595f4f3, 0xa3e6a7c9, 0xf97b2e10,
-0x4513cf3d, 0x8ded3394, 0x0949a772, 0x934f2269, 0x2b636628, 0x92101c68,
-0x804dfd94, 0x178315be, 0x384adf65, 0xe64d11d3, 0xc44881c0, 0x7a8e7886,
-0xb721c0c8, 0x6d0d0fc0, 0x97f0cc5a, 0x3c67c31f, 0x4906dd09, 0x6202c01a,
-0xad8d6c5b, 0x53158056, 0x13704ed5, 0xa1dfeaaa, 0xb35e4b40, 0xd9c3e6fa,
-0x0c9650ce, 0xbdfe5c22, 0x874bedb3, 0xbd07d0bd, 0x4eef4a4f, 0x2970d932,
-0xfdd003ac, 0x609fbea4, 0xad817794, 0xb4ee9f96, 0x559b3faa, 0x1edcf35f,
-0x8342e9fb, 0x69a73981, 0x5fc86a07, 0x929b45aa, 0x5c32e847, 0x43421484,
-0x9962abf5, 0x8cf07ae4, 0xba7b556d, 0x2da42ac1, 0xac0eef6f, 0xdc118ef8,
-0x6061597a, 0xc5f7a007, 0xb9b92c51, 0x87049008, 0x72c9da8a, 0x54dc48c6,
-0xb4c4b392, 0x50204c8d, 0x00b2ef59, 0xcdac687c, 0xb2158dc3, 0x4f1c65e3,
-0x8af22286, 0x4444ee49, 0x2d8921ce, 0x3c0a8d11, 0xb97325da, 0x056aec7b,
-0xa96ca31b, 0x71a5febb, 0xa3166c47, 0x5e920dcd, 0xa58b2e61, 0x4d3b392f,
-0x1b9b177b, 0x058b0dfa, 0x4bdc16ab, 0x8a4eeac3, 0xfbf2d2fc, 0x636f04a6,
-0x75a14bda, 0xa28f1947, 0xf2f248e4, 0x934e7dd6, 0xeb4401cb, 0x37f693a2,
-0xd1cb7e16, 0xbd5d9abb, 0x6f613f63, 0x9bfb5fd5, 0x6b70c5ea, 0xbdcc6c7a,
-0x41efaee1, 0xf45d3965, 0x0499b12b, 0x7820873a, 0xed53961f, 0x303c4f04,
-0x2e4bd363, 0x1bcdd589, 0xf7317de0, 0x7ba3d53a, 0x61fb36a8, 0x23e55b43,
-0x0ef838e9, 0x7b9d91a3, 0x3cd7d835, 0x5f28e517, 0xa100fad7, 0xff39800d,
-0xd7894433, 0xb61a62cd, 0xde618b70, 0x8560d770, 0xed02
-
-output0 =
-0x11d2bcac, 0x7715ae4d, 0xc9f4dbc6, 0x2fda3c1a, 0x09349b16, 0x2cd3c189,
-0xe5650429, 0xc73c42c1, 0xe7336bb7, 0xbb7de593, 0x83f986aa, 0xc0ade12e,
-0x6730b095, 0x78f7c059, 0xaa907199, 0x75c323d1, 0x7061f9ba, 0x97e067bf,
-0xc155cd55, 0x6a4cb08d, 0x4260e2fa, 0xff35e496, 0x37f251d3, 0x02fd9f9e,
-0x6f53345c, 0x790cda6d, 0x3b8549e4, 0x56d0c6ea, 0x70a38006, 0xfff18223,
-0x6f2035b5, 0x6cf508d3, 0x98a0a308, 0x432353fc, 0x0eb818eb, 0xdd9a128b,
-0xf92431b2, 0xad788286, 0xda07d5de, 0x44b4b3a8, 0xbe62fd67, 0x61a4eb54,
-0x90d7ac9f, 0xc4d9a930, 0xfddc3c24, 0xf5e3b1c8, 0x38143538, 0xcb1d3062,
-0xcae36df3, 0x50a73437, 0x542dcab7, 0x875973a0, 0x34690309, 0x49cb1ddb,
-0xf8a62b92, 0x82af6103, 0xc9f8c928, 0x3835b822, 0x16b044a6, 0xdae89096,
-0xa5be47d4, 0xaf61189e, 0x5cd70faf, 0x037331cf, 0xef7fa5f6, 0xb2f2b41a,
-0xa6f222c6, 0xdb60fe4c, 0x2a857a9a, 0x0b821f9d, 0x348afd17, 0x7eecbaeb,
-0x92bb9509, 0x8a3cec24, 0xd02549a2, 0x155ffa81, 0x2b7feac6, 0x3ee461e7,
-0xc981f936, 0x89b544c7, 0x9a431e36, 0x62511734, 0x769f9647, 0x211a747e,
-0x567abef4, 0xad87e2b4, 0xa3e0c3bf, 0x6d325dd5, 0xf561cc46, 0x39925735,
-0x3d8abbfd, 0xc3724c88, 0x8bdf03c9, 0x1b02a12a, 0x4f233a0c, 0x9ca9444a,
-0xc5d1f7e6, 0x4d995f37, 0xd9aefb32, 0xd0465248, 0x0f3a3b21, 0x62ea8c0c,
-0x91f8d54e, 0x5cf75514, 0x14618a01, 0x8fe9b87e, 0xf2b424f9, 0x49724ce2,
-0xa1464587, 0x5e00dc83, 0x59475455, 0x444119b1, 0x4fb9f036, 0x65fcbc1a,
-0x1c63a990, 0x767a6114, 0xb0ede06a, 0xcfb91ae3, 0x7874af5f, 0xf78772a3,
-0xa2932c81, 0x77f2759d, 0x930dc8f1, 0x95ce14a5, 0x134363ee, 0x61ee143f,
-0xf0034b35, 0xfdc75fce, 0x3be2dcf3, 0xff3a07eb, 0xdc43f0eb, 0x23ba73bb,
-0x45f7649e, 0xcacc297c, 0xa3dd98db, 0x058d46a9, 0x6bcfc154, 0x7be8e1e6,
-0x618a4754, 0x8d193c46, 0xba39e1ce, 0xc3b85cfc, 0xd80d853b, 0x38d6440d,
-0x9c1a6185, 0x90c9dfcb, 0x01c6e841, 0xeedfe6ac, 0x7b61a3ae, 0xad3924dd,
-0x514bc1a8, 0x6ed60d7e, 0x1b74b79b, 0xea295947, 0x5f9a5d33, 0xcd24311f,
-0x0bd3d10c, 0xd214ecfe, 0xcb37035d, 0x8ce95168, 0x7020cb52, 0xe432107d,
-0x042d63ac, 0x6201c8dd, 0x4bea65a2, 0x1a3cf453, 0x5b8e868d, 0x3d653bb0,
-0x24c1967e, 0x37f183a9, 0x3700e703, 0xb168a02b, 0x2592cd82, 0x5c0cdb66,
-0x70b64ebd, 0xf8dcb9a7, 0x634a8335, 0x06642398, 0xfe2f4497, 0x2e775256,
-0x30f85cbe, 0xf4d2fdaf, 0x46ca6c9d, 0x022097d6, 0xcedeb03e, 0xb4ca20bc,
-0x4fde636c, 0x10ea20a0, 0xe6da8721, 0xbfde5b08, 0x9c3739da, 0xb6dc015a,
-0x427db088, 0xdfdb8e6f, 0x756be6c1, 0x21f5297b, 0x06135665, 0xc1602b7d,
-0x049536c5, 0xbbb3b801, 0x0cdb0c19, 0x7b2ad622, 0xfee8218f, 0xc5c7f123,
-0x8abd3301, 0xa15b534d, 0x29dd2053, 0xd409abf9, 0x3ef19d6b, 0x70a3cbc2,
-0x7a51423a, 0x4505b2ad, 0xdc74c75e, 0x068751a9, 0xb0b56437, 0x14a10371,
-0x76af806f, 0xa8a47e19, 0x7c97a26e, 0x7998a3d6, 0xdc1ad1e2, 0xb532a301,
-0xca8a3e7d, 0xd0aef374, 0x204990c0, 0xc7011aec, 0xa69151ea, 0x53390026,
-0x7bf0d762, 0x735c2202, 0x64159e54, 0x5a3b1a56, 0x9ef1def2, 0x0ab8a961,
-0x587b0886, 0xb8cc5975, 0x2a5a0f23, 0x069d05be, 0x9cc3c207, 0x40ef1a02,
-0x4fae3f5b, 0x1f127aae, 0xd4e6d411, 0x17ac43ef, 0xe4bf891b, 0xfbb21765,
-0x2c560c7e, 0x8561988c, 0x73a01032, 0x0cfef73a, 0x694c4991, 0x885d7a3f,
-0x4218d1ff, 0xc2efaffb, 0xaf9d9715, 0xf76de6b2, 0xcce8e8ff, 0x370e3800,
-0x493675eb, 0xd8fbcbda, 0xa5b382c2, 0x86c8f1ea, 0x3d724ea4, 0xb067034c,
-0x6491d87e, 0x1a745ce4, 0xbb27180b, 0x1a2f0acc, 0xac4b7b3b, 0xe324578b,
-0xc87928df, 0x9c1de566, 0x0ce2a17d, 0xaf2e13ce, 0x146a8659, 0x8727f6ae,
-0xe2df7d03, 0x1a8e4cb4, 0xfa590976, 0x13a7c236, 0xc07489d0, 0xbe905e17,
-0xafeb3d4b, 0x201e73f2, 0x5bdca12e, 0x3e15a852, 0xbcfc3271, 0x5d398410,
-0x6bfacc15, 0x011fc61f, 0x43e43fd7, 0x0640717c, 0x96bfb3ff, 0x158eac19,
-0x3b852e91, 0x74f9ceda, 0xcac71326, 0xfc0e312a, 0x20e8137b, 0xa1162611,
-0x239ac7fe, 0xb9d00f8a, 0xea0b5241, 0x019f0d25, 0xc5153264, 0xb48a5547,
-0xe54e339f, 0x17a6cca5, 0x5065af0d, 0x5ce648b9, 0xb457b342, 0xc1cb3f0e,
-0x28d03c8b, 0x5144ed7a, 0xdb80779f, 0x53ce1b87, 0xbc071147, 0xbfe46c11,
-0x7296785e, 0x83e4a63e, 0xc58982e9, 0x9538c5b9, 0xf14abaaa, 0xd915124c,
-0x73540cd6, 0xe333696b, 0x58f9e00a, 0xd4dad10f, 0xc0de1420, 0x355e2bdc,
-0xb2faa8fd, 0xbe6a12f1, 0x45d415cc, 0x47f5aed9, 0x4754e770, 0x2bb07385,
-0x41374352, 0xf80beb47, 0xef02f35c, 0xc9c1b86e, 0x94b5785b, 0xba33123f,
-0x7e39f0c9, 0x028a9286, 0x7d52c9f1, 0x06f04da6, 0xbc6a68d1, 0xfc70bace,
-0x95b6a129, 0xfff224bb, 0x701ef3fb, 0x3309286f, 0x544ae8c1, 0xdca62c4a,
-0xf8862ee2, 0xf9e3cd29, 0x2c07cce2, 0x8d93652a, 0xf47e4611, 0x4635f586,
-0x1c03e0f4, 0x819724c7, 0x96b2a3f0, 0xeeb1ad95, 0xff08e517, 0xbd4ba6ed,
-0x49ddb12d, 0x365734b5, 0x5edf7459, 0x2ee117a9, 0x067b9462, 0x549f6d5f,
-0xe1dd8309, 0x12bb8e0a, 0x4382fe0f, 0x57fce11b, 0x1bc1c809, 0xd2741876,
-0xcffd36b9, 0x45a64a67, 0xb77955d5, 0xb5825f24, 0x86eef2a8, 0xb66cac3b,
-0xfec661f8, 0x531d5963, 0xa0a2f109, 0xe1795b68, 0x6bfd44e0, 0x0849af41,
-0xf56d7d73, 0x3eab025f, 0xd109b015, 0xec24d23b, 0x8b3f603c, 0x648f421f,
-0xc833f32a, 0x53cbda14, 0xb9b3fee4, 0xcf9ac8ab, 0x300f0548, 0xfe0bc595,
-0x4f437a1a, 0xdacfae1f, 0x284e4a6d, 0x57815e28, 0x15d32b39, 0x68f85b97,
-0x18b21602, 0x941259ef, 0x68598d90, 0x6dfd81db, 0xa8fc9a55, 0x60fef2b3,
-0xcf07961b, 0x11b96588, 0xd9928a88, 0x2bbc72fd, 0x025f81b4, 0x44794d6d,
-0x6a7420aa, 0xa73d4d89, 0x25b523ff, 0x521dbea3, 0xdacde374, 0xbf41776f,
-0x9c1e3cb6, 0xb7b3499b, 0x8e154ed3, 0x1ac8f8c8, 0x4f2cf203, 0xa293c979,
-0x2792a2e1, 0x329ca1dd, 0x01e1aa4a, 0x01a78d3e, 0x100c74ed, 0xb0db13c7,
-0x99d53541, 0xd435a3b9, 0x898bd713, 0x069287bd, 0xe3175d24, 0xb09dc7fb,
-0x7340d7d3, 0x81369cc3, 0x8f16a7a8, 0x43963d57, 0x58e0f6a3, 0x39803b6c,
-0xa419a5ac, 0xf45fd6fa, 0xec389d5b, 0x636ce34f, 0x71405df6, 0xfc504724,
-0xa3a3b192, 0x19df1379, 0xaf028f42, 0x3e1838e8, 0x6b7a64a9, 0xaa90ffee,
-0x238ee398, 0x67eae4bd, 0x0a549a15, 0x125873d3, 0x00ece005, 0x9f7b2b8f,
-0x7571f73c, 0x98940ab4, 0x192ed328, 0x8fae66da, 0x9063b323, 0x2542f666,
-0x07ac7c8e, 0xce92857a, 0x3ded4b69, 0x50204cb4, 0x2a81cd17, 0xfd6ac536,
-0xafb46424, 0xe802147b, 0x30a37858, 0x90697235, 0x1606e767, 0x26c1048e,
-0x3a20df7b, 0xe127de97, 0x481abd6c, 0xc3a61d15, 0xbb2e929c, 0xd2ec0d65,
-0xc0e53693, 0x500c2e9a, 0x316d0f4b, 0x18354452, 0xb2dd7728, 0x5a874b3e,
-0x6dcf6f9c, 0x9d7c15ce, 0x1b25566d, 0xe13d6e7a, 0x9d9d06ae, 0x4d0e7d23,
-0x33100e24, 0x7c20e0f8, 0x2cfc95bf, 0xb8e702a0, 0x5e60215b, 0xa516093e,
-0x4cf3bed7, 0x4a0d6f56, 0xaf4901cc, 0xaeb7137e, 0x07d3c34d, 0x38641bc6,
-0xf7366ca3, 0x6e01bd0d, 0x86818282, 0xf0f8712a, 0x431f57ad, 0x46b832c3,
-0xec1893b8, 0xfa43c94f, 0x8b4c382a, 0x84cc0cec, 0x3f1016f3, 0xdbc7b88d,
-0xa3c34e52, 0x50691492, 0x8b10e709, 0x5c5db670, 0xcda5888b, 0xa1ef2917,
-0x1d4689ba, 0xc6470dcc, 0x7010373d, 0x4f27b426, 0x06b0de9d, 0xba83e005,
-0x97cd5aad, 0xc1d0f41a, 0x01bae35a, 0xb30c805e, 0x8d7982eb, 0xe1a7b51d,
-0x88a9f4d2, 0x7a6742a8, 0x0d9cb569, 0x06e9bc87, 0xf8c93b93, 0x89f3e80a,
-0x96b971de, 0xcd548ef1, 0x5fbeb12a, 0x39c798e3, 0x90183352, 0x9b2476a7,
-0x9437b0ae, 0x1f8045af, 0xf6ff8634, 0x019ec993, 0x0116e82e, 0x84ff34c8,
-0xf1be20f9, 0x455510e4, 0x61cdbafe, 0x6f560fc5, 0x39fd9d2d, 0x54e343b2,
-0x90448ad2, 0x24c4f180, 0x0fe4f0a7, 0x379ac6a0, 0x61b383f0, 0xb2228e0c,
-0x223bc044, 0xcfbc389d, 0xae6a40e7, 0x8d445c62, 0x045eaf6f, 0x07df18c6,
-0x4c057e85, 0x589113e6, 0xa3bf554e, 0x702b193b, 0x23af7d6a, 0xb98022ea,
-0x96c45ca1, 0xe3b8c170, 0xed7bb4ac, 0x8a2b8f47, 0x6b57db19, 0x9d24d458,
-0x054c66bf, 0xf2630696, 0x43524b13, 0xcd419b2a, 0xa248521e, 0xd7765fb3,
-0x99fbe34e, 0x3b9ebb4c, 0xf7bfeb6c, 0xaf12561e, 0xc90c7f0d, 0x067ed7e9,
-0x9102babe, 0xccc09846, 0x691fb1ed, 0x9b850f96, 0xaba5f22a, 0xcad31d58,
-0xb1f25b0b, 0xa55fe490, 0x41e62678, 0xba3e83dd, 0x09d8a9dc, 0xe2f76f22,
-0x6435706e, 0x81a0ef55, 0xb2790ad1, 0x793587d1, 0xebe10cc7, 0xde5fe03a,
-0x308948bb, 0x439ece5c, 0x19fbef01, 0xb0de1b53, 0x95f4f310, 0xe6a7c965,
-0x7b2e10a3, 0x13cf3df9, 0xed339445, 0x49a7728d, 0x4f226909, 0x63662893,
-0x101c682b, 0x4dfd9492, 0x8315be80, 0x4adf6517, 0x4d11d338, 0x4881c0e6,
-0x8e7886c4, 0x21c0c87a, 0x0d0fc0b7, 0xf0cc5a6d, 0x67c31f97, 0x06dd093c,
-0x02c01a49, 0x8d6c5b62, 0x158056ad, 0x704ed553, 0xdfeaaa13, 0x5e4b40a1,
-0xc3e6fab3, 0x9650ced9, 0xfe5c220c, 0x4bedb3bd, 0x07d0bd87, 0xef4a4fbd,
-0x70d9324e, 0xd003ac29, 0x9fbea4fd, 0x81779460, 0xee9f96ad, 0x9b3faab4,
-0xdcf35f55, 0x42e9fb1e, 0xa7398183, 0xc86a0769, 0x9b45aa5f, 0x32e84792,
-0x4214845c, 0x62abf543, 0xf07ae499, 0x7b556d8c, 0xa42ac1ba, 0x0eef6f2d,
-0x118ef8ac, 0x61597adc, 0xf7a00760, 0xb92c51c5, 0x049008b9, 0xc9da8a87,
-0xdc48c672, 0xc4b39254, 0x204c8db4, 0xb2ef5950, 0xac687c00, 0x158dc3cd,
-0x1c65e3b2, 0xf222864f, 0x44ee498a, 0x8921ce44, 0x0a8d112d, 0x7325da3c,
-0x6aec7bb9, 0x6ca31b05, 0xa5febba9, 0x166c4771, 0x920dcda3, 0x8b2e615e,
-0x3b392fa5, 0x9b177b4d, 0x8b0dfa1b, 0xdc16ab05, 0x4eeac34b, 0xf2d2fc8a,
-0x6f04a6fb, 0xa14bda63, 0x8f194775, 0xf248e4a2, 0x4e7dd6f2, 0x4401cb93,
-0xf693a2eb, 0xcb7e1637, 0x5d9abbd1, 0x613f63bd, 0xfb5fd56f, 0x70c5ea9b,
-0xcc6c7a6b, 0xefaee1bd, 0x5d396541, 0x99b12bf4, 0x20873a04, 0x53961f78,
-0x3c4f04ed, 0x4bd36330, 0xcdd5892e, 0x317de01b, 0xa3d53af7, 0xfb36a87b,
-0xe55b4361, 0xf838e923, 0x9d91a30e, 0xd7d8357b, 0x28e5173c, 0x00fad75f,
-0x39800da1, 0x894433ff, 0x1a62cdd7, 0x618b70b6, 0x60d770de, 0xbaed0285,
-0x7bd24f54, 0x96a33975, 0x6884bd60, 0xeb75cf39, 0x19dd058a, 0xd4b8f064,
-0x045178ca, 0xd9e3c1de, 0x91b494a6, 0x3316ac81, 0xb926c7d8, 0xc190f058,
-0xce70a42c, 0x54f3b3c4, 0x79b20d90, 0x75177ad7, 0x9f010f51, 0x889a4fd5,
-0x8fbbc8f0, 0xf1340040, 0xc22acb69, 0xe1473a0a, 0x52ddd7e3, 0x4cd54494,
-0x4eb7a9ed, 0xd35e6a65, 0x3236b14c, 0x89786899, 0x3dc59704, 0x51d674be,
-0xbcf13659, 0x6ef6266e, 0xf50ef497, 0x141354bc, 0xc8a42e76, 0x59b14233,
-0x8b6cad7d, 0x061d8efe, 0xaca42513, 0x161cee21, 0xfeac5471, 0x4c499d31,
-0xac2892cb, 0x9bacf4c5, 0xfff36588, 0x898f7a06, 0xad87be87, 0xebe7cb95,
-0xa52b5fdf, 0x9f1f3945, 0xad435317, 0x1b316bcc, 0x8e6c0fd3, 0x767981d6,
-0x1f86412b, 0x32b457f5, 0x30ab14db, 0x7120e8ae, 0x3972f57e, 0x2268af9d,
-0xf45e5738, 0xc48bd523, 0x76726cae, 0x10bcdaa2, 0x49dcbe96, 0x8e28c545,
-0x25fd1cc8, 0xc272f106, 0x1a34497e, 0x5f850d98, 0x92e324e4, 0x7e59f811,
-0x0bba7ff0, 0x86b3b23f, 0x29558cee, 0xcbd55b0d, 0x15c10dc2, 0xd6617dd5,
-0x41168898, 0x920132eb, 0xd10f51c6, 0xdc6eba51, 0xa07f89cc, 0xfcea8627,
-0x44a52afa, 0x03d4230b, 0xdbb998d8, 0xf30d2a06, 0x08d35aeb, 0x9597f9bc,
-0x720d2689, 0xf64314dd, 0xcadd04c5, 0x9cab9213, 0x22205cca, 0xd6cc196e,
-0xa820e3c8, 0x7c262f92, 0xaf481f6b, 0xcecc0fe6, 0x2ec0b33a, 0x20aebc0a,
-0xb5699b4b, 0xe0a559ba, 0xb9cd5224, 0x9f7ceb48, 0x35807e3c, 0x30be0794,
-0x05463d41, 0x0e10046f, 0x776e71d6, 0xc6bac22d, 0xfee7f911, 0x3bc76715,
-0x5024f666, 0x88a07482, 0x7dc55ed7, 0x3ee1d3b6, 0xec419af3, 0x4cd0e39f,
-0x988f3802, 0x23baa080, 0xef9ce568, 0xf46ff60f, 0x2efcb093, 0x23b5b12a,
-0xd5fb68c7, 0x58d45968, 0x6dce76cd, 0xf82c5a91, 0xfe6a2bf7, 0x0303b383,
-0xf1b1196a, 0xa18d6d69, 0xb0025e33, 0x3f51e6c7, 0x0263bac1, 0x87743b29,
-0x8f62b573, 0x7a80ad05, 0x95869387, 0x33e6a0f5, 0x50950449, 0x5da456ad,
-0xb2ab1617, 0x7b345bf9, 0x7f923fd1, 0x4ca337fe, 0x95ccf61b, 0xfd8221ca,
-0x0f19808f, 0x80029266, 0x915a3c47, 0x415045d7, 0x92f91b36, 0xd23576e5,
-0x74a5652e, 0xe3d7288c, 0xba8213f7, 0x3a0ecd53, 0xa34fa01a, 0x62b4db3b,
-0x3a96a793, 0xcef7b0da, 0xb64b8d17, 0x8716c3ed, 0xbd0ab055, 0xa6896492,
-0x1250e75b, 0xb2bce1a7, 0x4100ca8f, 0x2e05625f, 0x8eb5bc83, 0x3dac8027,
-0x62b3376d, 0xd6b2cc64, 0x4c9502dc, 0x6c1cfcbe, 0x380c1dce, 0x2b238ea8,
-0x7051d59b, 0x580b122d, 0x6174b6e5, 0x4353d726, 0xba555765, 0xb645490f,
-0x58427e5f, 0x06fc96e1, 0xae8f4528, 0xab0fee5e, 0x5de960b3, 0x63e79c19,
-0x8552eeb8, 0x9344db26, 0x3326d17c, 0xa4174885, 0x6fe45472, 0x7bd20a9e,
-0xa5e4aba0, 0x77b509af, 0x22f64240, 0x40bc5144, 0x57ca1b2d, 0xc1260090,
-0x008997aa, 0xe8029716, 0x6efb01f3, 0xc73e1366, 0x9de737ff, 0x1b5fabe8,
-0x957bb682, 0x5e27f5a5, 0x7777491a, 0x9b6fc6c1, 0xb0802205, 0x16e94d46,
-0x58079aee, 0x2b24c4c4, 0xfffb2e7b, 0x7c5560e1, 0xe1ad3009, 0x6a0c0027,
-0x09aea741, 0x9af375a6, 0x7106b7bf, 0x1cdcff69, 0xa007f9c2, 0x6f7729c0,
-0xeac4297f, 0x8622ede7, 0x89346bfa, 0xc24674b5, 0xd1eabf00, 0xfa6b2d39,
-0x04b0c153, 0x6adf49dc, 0x48ea0937, 0xae771ea6, 0xd4208255, 0x4052586d,
-0x9c6aa640, 0x9adbb652, 0x017d8661, 0xb20855f0, 0x1e2ed7b6, 0x70af7f25,
-0x354df0de, 0xf2fdfde7, 0x0844478c, 0x63993fb2, 0xc49e71ae, 0x1e15ae81,
-0x932ad241, 0xba83cf8f, 0xc7e227f3, 0xd1171a85, 0x63ea34a0, 0xe74f042b,
-0xd88173d9, 0xba7d8443, 0x9d47c6c4, 0xbe282a93, 0x6142fbac, 0x69307e44,
-0xbb86a7f1, 0x9fa3418f, 0x3a3eadce, 0x9804167b, 0x2d5eb47a, 0x5aa2372d,
-0x66eb8e1c, 0xf56da1fd, 0x3753eee9, 0xac78c709, 0x787ae648, 0x42d4fa7f,
-0x5a036af5, 0xfc6dfa54, 0x269f1195, 0xef1c698d, 0x2932b2d6, 0xba10b26c,
-0xf9b58396, 0x8f04a38a, 0x31c1264d, 0xf11c5ac6, 0x693d8ef6, 0x25b1d015,
-0x01c06e8f, 0x9c250a6f, 0x4b8fffcd, 0x1eff0743, 0x5a4974ec, 0x9d2d24c1,
-0x5562b2ae, 0x2a5b2deb, 0xd4a32596, 0x8ec43665, 0xde3ae654, 0x99e979d0,
-0xb6250c7c, 0x478a2891, 0xe1d6c035, 0x1dc453e8, 0xc7490c8d, 0xd4e85297,
-0x8fa94952, 0xc863cde8, 0x724dbbc8, 0x89ba9607, 0x0144ba1b, 0x3fed833c,
-0xd16278d4, 0x0080f227, 0xfbe241c5, 0x61892e7f, 0x503dced0, 0xa54d6ea5,
-0xcb5024a3, 0x591e11d1, 0xabeb85db, 0xc8314e58, 0xfb7792cb, 0xc70e5ada,
-0xcc07e739, 0xdb3ad4d6, 0x7a2d24e8, 0x2a0e216a, 0xa04aa774, 0x1762ac59,
-0xed53f5f9, 0x261a791e, 0x7a4102ae, 0x4650dcc9, 0xffa48ffa, 0x35a8f4e1,
-0x98e0f041, 0x3e3a9a83, 0xfb43c8e9, 0x7e0e6a1e, 0x06f718e5, 0x6812c114,
-0xaf21e4a1, 0x10ce04ca, 0x6e465a05, 0x250758f2, 0xfdf02f68, 0x426ec74c,
-0x51e44567, 0x17e637cc, 0x9da657e4, 0x39ecef6e, 0xd31c4423, 0x12bc06b4,
-0x35af82e0, 0x76379d09, 0x7fb7aa1e, 0x0b73e469, 0x7b3697a4, 0x6bbbca38,
-0x018d2e07, 0x8d74a290, 0x02e00314, 0xdc9d1f4f, 0x62cbdd73, 0xd1173c86,
-0x62c1d5f2, 0xdfb16100, 0x37cc28e8, 0x43954e64, 0xeaa699d9, 0x0cd0a997,
-0xa0f26045
-
-ea =
-17868
-
-eb =
-17868
-
-cab =
-2
-
-c =
-2
-
-c_neg =
-0
-
-k_pos =
-5952
-
-k_neg =
-5888
-
-ncb_pos =
-17952
-
-ncb_neg =
-17760
-
-r =
-0
-
-rv_index =
-0
-
-code_block_mode =
-0
-
-op_flags =
-RTE_BBDEV_TURBO_CRC_24B_ATTACH
-
-expected_status =
-OK
diff --git a/app/test-bbdev/test_vectors/turbo_enc_c4_k4800_r2_e14412_crc24b.data b/app/test-bbdev/test_vectors/turbo_enc_c4_k4800_r2_e14412_crc24b.data
deleted file mode 100644
index ff95a3f..0000000
--- a/app/test-bbdev/test_vectors/turbo_enc_c4_k4800_r2_e14412_crc24b.data
+++ /dev/null
@@ -1,252 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-# Copyright(c) 2017 Intel Corporation
-
-op_type =
-RTE_BBDEV_OP_TURBO_ENC
-
-input0 =
-0xb0fe86aa, 0xffbf2968, 0x4f55a631, 0xf2152dbc, 0x195a49a5, 0xa4aa7c6c,
-0x48a7be38, 0xd32c84f2, 0xb040da60, 0xb39eb07c, 0x3443aad6, 0x19f52e13,
-0xb2914341, 0x0d5dfdb3, 0x1ba8aec0, 0x62d0c7be, 0x1d55475c, 0x10f7dd79,
-0x967e5333, 0xc0d524c1, 0xdca8da87, 0x1146ecf7, 0xfa09a85c, 0x83be800f,
-0x11b814cc, 0x362a4704, 0x4f22e7ce, 0x9985a0e2, 0x9de4be72, 0x488a45b3,
-0x6996ade2, 0xdb18c09a, 0x487d62a3, 0x94f82d13, 0xa0743f83, 0x75d2f5dd,
-0x0e470346, 0x6e2ec2e5, 0x1a67fe5f, 0xc369330d, 0x860e8766, 0x42c110f6,
-0x804a9985, 0x55db02b4, 0xb899fc5c, 0x57811d20, 0xda4f1f9d, 0x2a2efc30,
-0x953e7487, 0x4b0c3065, 0x247d5d47, 0xdde382e7, 0x1d6d2ad7, 0x4358ac24,
-0x2d0fd97f, 0x1483821e, 0xf6c74ee5, 0x23b5c2f4, 0x95d4a5fc, 0x486f370b,
-0x8dbae43d, 0x248f17d5, 0x2df76099, 0xd19ec872, 0xf592aa0e, 0x8de04c3c,
-0x3ada94fb, 0x9dd001a3, 0x2b4db6d1, 0x791cf495, 0x57dc764b, 0x21789f1f,
-0x0d38adf5, 0xd8cefdc2, 0xed98f8bf, 0x024bc4ed, 0x4f9d3062, 0x332d27c5,
-0xde70ad4e, 0xd85872d2, 0x5d0e29c0, 0xa4fd1887, 0x3fa67ba1, 0x46b9b008,
-0x055bbf61, 0xf78e59f0, 0x287d2e3b, 0x5b473fe7, 0xd7ad6e04, 0x9cdf4986,
-0x830432ae, 0xffded1ba, 0x35c00f77, 0xcf0a6648, 0x196c03aa, 0xba4e2dd3,
-0xdaf70fe4, 0x883de2cd, 0xedc3b52e, 0x14e638c1, 0xe607103a, 0xc4cfb700,
-0x4ed9843d, 0xc442a0cb, 0xc0d3bba2, 0x36789ba8, 0x9c9b7a24, 0xb943b6a4,
-0x8f2c6879, 0x0fb16a0c, 0x2677bada, 0xd14f2f7e, 0x662ec398, 0x1e37b7ae,
-0x8ad0312d, 0x21adb6a1, 0x072a11fd, 0x7ae828d1, 0xb510655f, 0x09f7b477,
-0x10a175fc, 0xb7086f51, 0x24546af3, 0xfae81b50, 0xcb328832, 0x63693615,
-0xa37c3678, 0x15fb6364, 0xb5f75a78, 0xfa9aa5f6, 0x03804a0e, 0x1d245890,
-0x06d6cdcd, 0x7485a3c7, 0x35a008ae, 0x1abeaf1c, 0xd9c55966, 0x2b694666,
-0x5341f2df, 0xcb647280, 0xfb88d81e, 0xf99a44d0, 0xb0585534, 0x0877b530,
-0x752ab39a, 0xd493d8bc, 0xfaa6a57a, 0xccb7c008, 0x9c35994b, 0x9cca47b8,
-0xff47dda2, 0xa557841a, 0x7459fb6a, 0x93ec6495, 0x0ef7e6d2, 0xa8a6e6d4,
-0x46364f91, 0xd52c5776, 0x4dfd0d25, 0xd458c769, 0x24864930, 0xf7789991,
-0xfcc231f2, 0xc8e4cfd0, 0x50975038, 0x989398d1, 0x04504b14, 0x5e529570,
-0xf8c17202, 0xaf459a8a, 0xac2fecb2, 0x0eb3a176, 0xf6bac24f, 0x6fbddade,
-0x42456542, 0x83c10198, 0xbea4efaf, 0xff2f2966, 0x5edae82b, 0x09c27f13,
-0xa094c3b4, 0xc53b810e, 0x7f1cc39d, 0x25731c8a, 0x8d34b6ee, 0x5fb78b80,
-0x2980eef8, 0x7b76a9fb, 0x37bfacb9, 0x80f7a0ea, 0xd1e3e69d, 0xcda19b8b,
-0x9af26246, 0xf55495cf, 0x6f45ad1b, 0xfe2cb329, 0xc33cb7e6, 0x67bbde4a,
-0x32310c7b, 0x80e6b00a, 0xdd4004d2, 0x0e0eb8b6, 0x6f8d951f, 0xb196cb40,
-0x6dbe29dd, 0xa138a375, 0xd4f5b058, 0x69ea638f, 0x50438a7a, 0xe5530eb3,
-0x527cb218, 0xbfa67b9d, 0x7efb86df, 0x724ed65b, 0x38006782, 0x6a9924a4,
-0x749955c2, 0x5cb82627, 0xa74ceecb, 0x89eb103d, 0x89a12973, 0x660613c4,
-0x8bdf96ae, 0xf08afcce, 0xa4023081, 0x79c6786c, 0x8026bdf0, 0x621f29a1,
-0xa8d8d3ec, 0x4ee5d537, 0xda83c99f, 0x9a69d0a8, 0xae027f9a, 0x639d9cc9,
-0xe80e2be1, 0x89d78cfb, 0x862fabb7, 0xb248c138, 0x3fe35f29, 0xf8b74cc6,
-0x27741dcf, 0xf9236485, 0x05225155, 0x4ed40ee6, 0xb30e4a95, 0x7d890ee0,
-0x0a97eb0d, 0xe7877652, 0x3de6fa67, 0xa3a5961e, 0x1bdf2af5, 0x5a7dcbbe,
-0x1641f1af, 0x4db5845b, 0x735761f2, 0x32a1431e, 0xab1e00b1, 0x495ddeb7,
-0xb480f29c, 0x47d83714, 0x8ba04129, 0x8c96062e, 0x657e7f7f, 0x30dfba23,
-0xfd4ee1bc, 0x9ffe10b1, 0xc917d2db, 0x18f0bd8d, 0x4b6c35d7, 0x54896222,
-0x7ce0f6c6, 0xb7813f4a, 0x71c52b4b, 0xac65da3a, 0x9aef9b4e, 0x85f9657e,
-0x62ba1965, 0xa1e39267, 0x40f66fb2, 0x10433b94, 0x851df333, 0xf0c6aa26,
-0xe0e19368, 0x5a706636, 0xf5de1e8c, 0x5ebc735a, 0x0967ef39, 0xf76c1fb7,
-0xe53f7f16, 0x51f2c4eb, 0x047dda3d, 0x73518b4a, 0x3ad90dd3, 0xaee51fc1,
-0x78f01060, 0x98d1502c, 0x990d5499, 0x7a19453c, 0x104c
-
-output0 =
-0xb0fe86aa, 0xffbf2968, 0x4f55a631, 0xf2152dbc, 0x195a49a5, 0xa4aa7c6c,
-0x48a7be38, 0xd32c84f2, 0xb040da60, 0xb39eb07c, 0x3443aad6, 0x19f52e13,
-0xb2914341, 0x0d5dfdb3, 0x1ba8aec0, 0x62d0c7be, 0x1d55475c, 0x10f7dd79,
-0x967e5333, 0xc0d524c1, 0xdca8da87, 0x1146ecf7, 0xfa09a85c, 0x83be800f,
-0x11b814cc, 0x362a4704, 0x4f22e7ce, 0x9985a0e2, 0x9de4be72, 0x488a45b3,
-0x6996ade2, 0xdb18c09a, 0x487d62a3, 0x94f82d13, 0xa0743f83, 0x75d2f5dd,
-0x0e470346, 0x6e2ec2e5, 0x1a67fe5f, 0xc369330d, 0x860e8766, 0x42c110f6,
-0x804a9985, 0x55db02b4, 0xb899fc5c, 0x57811d20, 0xda4f1f9d, 0x2a2efc30,
-0x953e7487, 0x4b0c3065, 0x247d5d47, 0xdde382e7, 0x1d6d2ad7, 0x4358ac24,
-0x2d0fd97f, 0x1483821e, 0xf6c74ee5, 0x23b5c2f4, 0x95d4a5fc, 0x486f370b,
-0x8dbae43d, 0x248f17d5, 0x2df76099, 0xd19ec872, 0xf592aa0e, 0x8de04c3c,
-0x3ada94fb, 0x9dd001a3, 0x2b4db6d1, 0x791cf495, 0x57dc764b, 0x21789f1f,
-0x0d38adf5, 0xd8cefdc2, 0xed98f8bf, 0x024bc4ed, 0x4f9d3062, 0x332d27c5,
-0xde70ad4e, 0xd85872d2, 0x5d0e29c0, 0xa4fd1887, 0x3fa67ba1, 0x46b9b008,
-0x055bbf61, 0xf78e59f0, 0x287d2e3b, 0x5b473fe7, 0xd7ad6e04, 0x9cdf4986,
-0x830432ae, 0xffded1ba, 0x35c00f77, 0xcf0a6648, 0x196c03aa, 0xba4e2dd3,
-0xdaf70fe4, 0x883de2cd, 0xedc3b52e, 0x14e638c1, 0xe607103a, 0xc4cfb700,
-0x4ed9843d, 0xc442a0cb, 0xc0d3bba2, 0x36789ba8, 0x9c9b7a24, 0xb943b6a4,
-0x8f2c6879, 0x0fb16a0c, 0x2677bada, 0xd14f2f7e, 0x662ec398, 0x1e37b7ae,
-0x8ad0312d, 0x21adb6a1, 0x072a11fd, 0x7ae828d1, 0xb510655f, 0x09f7b477,
-0x10a175fc, 0xb7086f51, 0x24546af3, 0xfae81b50, 0xcb328832, 0x63693615,
-0xa37c3678, 0x15fb6364, 0xb5f75a78, 0xfa9aa5f6, 0x03804a0e, 0x1d245890,
-0x06d6cdcd, 0x7485a3c7, 0x35a008ae, 0x1abeaf1c, 0xd9c55966, 0x2b694666,
-0x5341f2df, 0xcb647280, 0xfb88d81e, 0xf99a44d0, 0xb0585534, 0x0877b530,
-0x752ab39a, 0xd493d8bc, 0xfaa6a57a, 0xccb7c008, 0x9c35994b, 0x47ee26b8,
-0x94f624ac, 0xa3bd4876, 0xf7d4854e, 0x8871d433, 0x9321d942, 0x7b626be8,
-0x72c934b0, 0x3b7af8a4, 0x5102c29f, 0x710e4dbc, 0x99708292, 0x1458c4c1,
-0x61026bc5, 0xe776e388, 0x4a0222b3, 0x760e5aaf, 0x662f3583, 0x5ab1005b,
-0xe527ef70, 0x4170d611, 0x307bebc4, 0xfdd00caf, 0xbaae1044, 0xcab4d459,
-0x38281dcf, 0x90580c89, 0x49cf5986, 0xa27da769, 0xceced49b, 0x5ea37953,
-0x8a7e6c1c, 0x1e01b4e2, 0xe08026ae, 0x3754534a, 0x903b0ecf, 0x65f97a55,
-0x90798ed9, 0x9d1133bc, 0xe356a39f, 0xe47acbce, 0x01ccf326, 0x1954fd3d,
-0x240e69f8, 0x1da20bb4, 0xe1ab1684, 0x44c65d48, 0xd265e6c2, 0x51d4ef07,
-0x000970ef, 0xfeb939f4, 0x5dcc0132, 0x2bd27ae5, 0xba5dbd25, 0xa9d190e4,
-0x61556bec, 0x7fd6caba, 0x7fe312cb, 0xdd319413, 0x92a5dbbf, 0x17e61915,
-0x56067b67, 0x3dc348c0, 0x58c17fe0, 0xbe6bffcc, 0xd379026c, 0xc4174780,
-0xcce7f026, 0xb74b7eb0, 0xe4d5f625, 0x6bc16d3b, 0xff3e300e, 0x83f0d55a,
-0xf2e537df, 0x75c18f78, 0xa5458d1a, 0x47c778b0, 0x92eb8716, 0xcb5816fd,
-0xc2cc7079, 0xa7f1dc75, 0xed9e5ffa, 0xb7d6747f, 0xa2dc6907, 0x99b4d187,
-0x69f3138a, 0xbd285a1f, 0xb8ee18e0, 0x734b77a5, 0xc0700f69, 0x6c72a77a,
-0x76609ba9, 0xcfae9b73, 0x2cd329f0, 0x0d45aa12, 0x419fbcd7, 0x03e00f00,
-0x0effee99, 0x7f879eb4, 0x29a4c8df, 0x4432400a, 0x22b9cf55, 0xa1c4c645,
-0x200251b0, 0xff293906, 0xe11288e2, 0xde1e8ec7, 0x675752d1, 0x9630743e,
-0xd848c67e, 0x1eedfda9, 0x58b954fc, 0xa0dc7f1c, 0x0aea313e, 0x062b9449,
-0x0f17e57f, 0x96def6ec, 0x2ba45f14, 0xd9a5f8c5, 0x231483c8, 0x29b8783e,
-0xa6d24594, 0x1a62ffcd, 0x54c87a7f, 0x6fa9ca9a, 0xfff0f890, 0x51d6ae46,
-0xa96e82b0, 0x68cd9808, 0x56214df5, 0x2169defa, 0x72c1ecce, 0x2448e3c9,
-0x8eb2b3b3, 0x62c89c11, 0xbba20ee2, 0xea33f53a, 0x8b96a6b8, 0x9d33d551,
-0x363bd14e, 0x5fdd2b5f, 0xf8187546, 0xb692beab, 0x8df6b4c0, 0x753e2302,
-0xb90f7a37, 0x2b6bac6a, 0x13a07bc5, 0xb67f6d2b, 0x47b21569, 0xc2ab143f,
-0xf86ce30a, 0xde2dab70, 0x6f258860, 0x2878735c, 0x2aaeac20, 0xda80fb3e,
-0xe7a8ccf6, 0xbf011844, 0x40a610f8, 0x82f3fdf7, 0xadc4ec2c, 0xb8551030,
-0x76004380, 0xa384ff18, 0x080cf587, 0x6c4991d3, 0x2daea9aa, 0xa92d0c4f,
-0x4a9d117e, 0x2761f025, 0x96b40443, 0x57a82be4, 0x62374c44, 0x55dc64ae,
-0x28aa9f0c, 0x03a3b963, 0x41dbaa26, 0xb3c23735, 0x971cbd31, 0x939a9f80,
-0x76439fdc, 0xa9df79d6, 0x926ae3e2, 0x5ee75745, 0xf2396e52, 0xe18bd816,
-0x3f9834b9, 0x816a07bc, 0x8f873310, 0x45cf9b96, 0x0ce634dd, 0xe64a16d9,
-0x2733775a, 0x2b648c7e, 0xe600ee8e, 0xd99d8ae3, 0x10dadf2a, 0x904d3f87,
-0x3963e9e7, 0x47fcce89, 0xc256c898, 0x7db6cb66, 0xe1611a8b, 0xed81b10d,
-0x75eff974, 0x8a0a3d67, 0xa44311ff, 0x6f876783, 0x43dc93ce, 0x88616a33,
-0xa8706e8f, 0x33a2cbed, 0x3a6d20c3, 0x55175086, 0x39680945, 0x2d779a7b,
-0x0818a4ce, 0x55558918, 0xf7c08d35, 0x980a3038, 0x9cf068db, 0x3385d333,
-0xd81b33fb, 0x188018d5, 0x47c57bd3, 0x9ec2324f, 0x6901cd77, 0xc3bac44f,
-0x4d96aba8, 0x9094da5b, 0xa67a1353, 0x1fdfc4db, 0xa2fbeefa, 0xab4828e3,
-0x37d1db45, 0x0d33b3e9, 0x1ad72bb9, 0x7257bf9c, 0x2ec35167, 0xa4488b7f,
-0xf9dae588, 0x1038905a, 0x88ddf410, 0xaac11693, 0x24ac025d, 0x56cefbb5,
-0x6afe7f59, 0xc7f989e8, 0x15872570, 0x1bf16cdb, 0xfe9c93ce, 0x1fc9a076,
-0x85d37185, 0x1078cd31, 0xe1cd0327, 0x6d5315bc, 0x298cd836, 0xc8e21f06,
-0xe561c32d, 0x8ec404b4, 0x4d39bfbb, 0x24ede8c8, 0x451d6034, 0x3bafeea2,
-0x202f0ccf, 0x1fad37ce, 0xf04b5693, 0xeee57cd9, 0x5ef70007, 0x018e8a4f,
-0xfa61c9a9, 0x09989fcf, 0xe66b558b, 0x966efd48, 0x7525021d, 0xe7978b5e,
-0x7eb1d6dc, 0xa10c5e5b, 0xb7815e69, 0x7d486cfb, 0xcffdeb2a, 0x7375cb32,
-0x599008dc, 0xff91c796, 0x560ed4ad, 0x14e9a876, 0xfccf6a66, 0xa58be028,
-0xea9d408b, 0x3afc373b, 0xee008458, 0x19b6042e, 0x84806314, 0x431a4ba4,
-0x009ad6a1, 0xd7c62bf4, 0x1bebecba, 0x5c662f69, 0x83bfdea1, 0x45872a9a,
-0xca4700c9, 0x47dda29c, 0x57841aff, 0x59fb6aa5, 0xec649574, 0xf7e6d293,
-0xa6e6d40e, 0x364f91a8, 0x2c577646, 0xfd0d25d5, 0x58c7694d, 0x864930d4,
-0x78999124, 0xc231f2f7, 0xe4cfd0fc, 0x975038c8, 0x9398d150, 0x504b1498,
-0x52957004, 0xc172025e, 0x459a8af8, 0x2fecb2af, 0xb3a176ac, 0xbac24f0e,
-0xbddadef6, 0x4565426f, 0xc1019842, 0xa4efaf83, 0x2f2966be, 0xdae82bff,
-0xc27f135e, 0x94c3b409, 0x3b810ea0, 0x1cc39dc5, 0x731c8a7f, 0x34b6ee25,
-0xb78b808d, 0x80eef85f, 0x76a9fb29, 0xbfacb97b, 0xf7a0ea37, 0xe3e69d80,
-0xa19b8bd1, 0xf26246cd, 0x5495cf9a, 0x45ad1bf5, 0x2cb3296f, 0x3cb7e6fe,
-0xbbde4ac3, 0x310c7b67, 0xe6b00a32, 0x4004d280, 0x0eb8b6dd, 0x8d951f0e,
-0x96cb406f, 0xbe29ddb1, 0x38a3756d, 0xf5b058a1, 0xea638fd4, 0x438a7a69,
-0x530eb350, 0x7cb218e5, 0xa67b9d52, 0xfb86dfbf, 0x4ed65b7e, 0x00678272,
-0x9924a438, 0x9955c26a, 0xb8262774, 0x4ceecb5c, 0xeb103da7, 0xa1297389,
-0x0613c489, 0xdf96ae66, 0x8afcce8b, 0x023081f0, 0xc6786ca4, 0x26bdf079,
-0x1f29a180, 0xd8d3ec62, 0xe5d537a8, 0x83c99f4e, 0x69d0a8da, 0x027f9a9a,
-0x9d9cc9ae, 0x0e2be163, 0xd78cfbe8, 0x2fabb789, 0x48c13886, 0xe35f29b2,
-0xb74cc63f, 0x741dcff8, 0x23648527, 0x225155f9, 0xd40ee605, 0x0e4a954e,
-0x890ee0b3, 0x97eb0d7d, 0x8776520a, 0xe6fa67e7, 0xa5961e3d, 0xdf2af5a3,
-0x7dcbbe1b, 0x41f1af5a, 0xb5845b16, 0x5761f24d, 0xa1431e73, 0x1e00b132,
-0x5ddeb7ab, 0x80f29c49, 0xd83714b4, 0xa0412947, 0x96062e8b, 0x7e7f7f8c,
-0xdfba2365, 0x4ee1bc30, 0xfe10b1fd, 0x17d2db9f, 0xf0bd8dc9, 0x6c35d718,
-0x8962224b, 0xe0f6c654, 0x813f4a7c, 0xc52b4bb7, 0x65da3a71, 0xef9b4eac,
-0xf9657e9a, 0xba196585, 0xe3926762, 0xf66fb2a1, 0x433b9440, 0x1df33310,
-0xc6aa2685, 0xe19368f0, 0x706636e0, 0xde1e8c5a, 0xbc735af5, 0x67ef395e,
-0x6c1fb709, 0x3f7f16f7, 0xf2c4ebe5, 0x7dda3d51, 0x518b4a04, 0xd90dd373,
-0xe51fc13a, 0xf01060ae, 0xd1502c78, 0x0d549998, 0x19453c99, 0x52104c7a,
-0xc477d443, 0xce6910c0, 0x0dc163b4, 0x1dc4dab2, 0x5c4dbc0c, 0x6145ced9,
-0xf02e295b, 0x60196b15, 0x2aa68b89, 0x9ff0dd3b, 0xe4b874ce, 0x9175ec6c,
-0x9b629234, 0x644ce81d, 0x359fac36, 0x5211675f, 0xd24c092f, 0x1de9385e,
-0x1352b7e5, 0x8d650e83, 0x7057d366, 0x43371dd2, 0x61678e6e, 0xd436279b,
-0x267562b6, 0xabaf1706, 0x814bd74e, 0x3269cbda, 0x0a34b3cd, 0xa74c3d1a,
-0xd3b098c8, 0x02030412, 0xd75d7207, 0x519d1b3d, 0x1958436b, 0x69ba4221,
-0x81b6b4cf, 0xb83234e4, 0x7e652d03, 0x63bcf36e, 0xefecb5f7, 0x60550e08,
-0x394963ce, 0xfd6f2b38, 0x1342c68b, 0xbc39f1ca, 0x21bdd863, 0x59ade0af,
-0x2d0c793a, 0xa74702d4, 0xc00885f9, 0xc73c27af, 0x6566ea9e, 0xa31e0f7c,
-0x499f1706, 0xe19617ad, 0x0e19900a, 0x0a8d3669, 0xcc482af9, 0x5eb35096,
-0x269b51c1, 0x80d1145b, 0x4be232ff, 0x3d31fc83, 0x89127a6c, 0x90af3379,
-0x7726d002, 0x35f15151, 0x8393c3b5, 0x27a9ada8, 0x25940510, 0x05c49bf1,
-0xc7c1b886, 0xdb00826f, 0xf658f61f, 0xe5d77d98, 0xa637b6fb, 0x2f515fa5,
-0xb1f80c38, 0xe082d248, 0x4220acd0, 0x06360060, 0xcf42c277, 0xf5972529,
-0xf7e274fb, 0xfe41cc28, 0xde661de0, 0xa157bd26, 0x8e1f4788, 0x35c4111a,
-0x11a7360e, 0x751188e8, 0x544d9fc3, 0x33d853cd, 0x754542f7, 0x05d9979b,
-0x73e59071, 0x4909bb7e, 0x64ae94be, 0x0eb4c8e9, 0xacb903fe, 0xc716288e,
-0x1e914aa8, 0x19d127bd, 0x913a6dd4, 0x6af354d9, 0x72c29a95, 0x2fa731a5,
-0x9f206402, 0xa44abe92, 0xeb090ab4, 0x85b7584c, 0xf27cd398, 0x3b828e38,
-0x0cb8dd56, 0x37657f3c, 0x78fa0f2a, 0x3df7a0cb, 0x2621740f, 0x4d92422f,
-0x334a8fa2, 0x124f947d, 0x31be3505, 0xf6a1e561, 0x5d0c4087, 0x62971b45,
-0x312472a7, 0x933af4e3, 0x45c28196, 0x8ddd4f00, 0xa5ec20fb, 0x9acde751,
-0x23ac64e8, 0xbea00461, 0xf9d65eac, 0xe21db306, 0xcacb4f76, 0x83950ca3,
-0x66069329, 0xf7d72838, 0x5d13a747, 0x5c9ca583, 0x1d9d225e, 0xb2c705fe,
-0xd0fac625, 0x0a73b38e, 0xec8d6692, 0x0bb64587, 0xf147c00c, 0xcdd6020c,
-0x1608cede, 0xb531a423, 0x1c8b1b08, 0xdd74f03e, 0x6d3076fb, 0x2dcaaa44,
-0xe869582b, 0x0f19cde9, 0x44d15927, 0xee751f17, 0x655f24c4, 0x7508164e,
-0xab414b0d, 0x381d3525, 0x7a18cb74, 0xc91e435a, 0xb3397aa0, 0xa5567595,
-0x1da36e52, 0xb43ba598, 0x3ef0d4fd, 0x11d348c4, 0xfcb4cbfa, 0xa3dee1a7,
-0x8c6be341, 0xefafff59, 0xeaa95a58, 0x01ba74bb, 0x5b1d3193, 0x2ac942bb,
-0xbb5816ca, 0xe79720dd, 0x1683bbad, 0xea2f3992, 0xa89cdd39, 0x3a389386,
-0xc54d671f, 0xe8564365, 0x373196e0, 0xc08acfd2, 0x32f556b2, 0x15340220,
-0x817d0d1b, 0x4b9afaa3, 0xd3bbf932, 0x6c9ddf75, 0x0fca9bea, 0x2cd2d913,
-0x026e3647, 0x6e769b35, 0xdab34e6e, 0xc9b75a74, 0xfdc90304, 0xc6442959,
-0xa8f44fb4, 0x73fb26de, 0x833d2d60, 0x8cf7a461, 0xdc5c4bf9, 0x1bce371f,
-0xd1d6b743, 0xc1124cae, 0xf4d33161, 0x696956a5, 0xa5ce9c72, 0x5f84e109,
-0xa0dae0ff, 0xdfdf169e, 0xb734307c, 0x25843b5d, 0x0b710ae4, 0xafd25b2b,
-0xc013b89b, 0x5246e064, 0xeb28ab92, 0x4f92747c, 0x2f3c0c8b, 0x3268720d,
-0xef638533, 0xd0fc40ab, 0x5d29c943, 0x3fd9b311, 0x6833bf43, 0xa188ad03,
-0xacba3ad2, 0x9696f4da, 0x07b1b2fa, 0xb8f925f6, 0x082573f4, 0x506b5c0e,
-0xe290e707, 0x80933f06, 0x38dcad25, 0x276ab82f, 0x788f3a2c, 0x4b0e14bc,
-0xc1b38b43, 0x962a0efe, 0x77f19522, 0xd5bd951b, 0x90415ed2, 0x67a6a806,
-0x82d0503f, 0x814e505f, 0x6448341a, 0x2c88ba72, 0x1f783411, 0x5dcfc5d9,
-0x15cea1e2, 0x351ebdaa, 0xff083e5e, 0x173297d6, 0xbdadb9f2, 0xe82ebe50,
-0x33fff936, 0xaed0e402, 0xcd08e297, 0xeefee410, 0x023aedc0, 0x493fdd4c,
-0xd4454937, 0xa4c21893, 0xf9740292, 0x14308130, 0x2aa05568, 0xbd88a714,
-0x3f264976, 0x62203300, 0x5d9aa0bf, 0x3b9be4b0, 0xcb1c6dff, 0xe7f5ded8,
-0xb6ce0ec7, 0xdc1f094b, 0x0f93747c, 0x1768e49a, 0x1d7ebe93, 0x25d53887,
-0x144a1fe2, 0x32bc280c, 0x1d0b7884, 0x106b8928, 0x5aa38780, 0x87ca0d93,
-0x11a81f71, 0xe0957877, 0xb21fb0f7, 0x1e5a7ac0, 0x09db53a1, 0x5210dd59,
-0xa0566364
-
-ea =
-14412
-
-eb =
-14412
-
-cab =
-4
-
-c =
-4
-
-c_neg =
-0
-
-k_pos =
-4800
-
-k_neg =
-4736
-
-ncb_pos =
-14496
-
-ncb_neg =
-14304
-
-r =
-2
-
-rv_index =
-0
-
-code_block_mode =
-0
-
-op_flags =
-RTE_BBDEV_TURBO_CRC_24B_ATTACH
-
-expected_status =
-OK
\ No newline at end of file
-- 
1.8.3.1


^ permalink raw reply	[flat|nested] 115+ messages in thread

* [dpdk-dev] [PATCH v2 11/15] doc: update of testbbdev documentation
  2020-03-04 18:22   ` [dpdk-dev] [PATCH v2 00/15] bbdev new features Nicolas Chautru
                       ` (9 preceding siblings ...)
  2020-03-04 18:22     ` [dpdk-dev] [PATCH v2 10/15] test-bbdev: vectors update Nicolas Chautru
@ 2020-03-04 18:22     ` Nicolas Chautru
  2020-03-04 18:22     ` [dpdk-dev] [PATCH v2 12/15] drivers/baseband: add PMD for FPGA 5GNR FEC Nicolas Chautru
                       ` (3 subsequent siblings)
  14 siblings, 0 replies; 115+ messages in thread
From: Nicolas Chautru @ 2020-03-04 18:22 UTC (permalink / raw)
  To: thomas, akhil.goyal, dev; +Cc: ferruh.yigit, Nic Chautru

From: Nic Chautru <nicolas.chautru@intel.com>

Update related to the changes introduced by the
previous commits.

Signed-off-by: Nic Chautru <nicolas.chautru@intel.com>
---
 doc/guides/tools/testbbdev.rst | 337 +++++++++++++++++++++++++++++++++++------
 1 file changed, 291 insertions(+), 46 deletions(-)

diff --git a/doc/guides/tools/testbbdev.rst b/doc/guides/tools/testbbdev.rst
index 7e95696..016f3f9 100644
--- a/doc/guides/tools/testbbdev.rst
+++ b/doc/guides/tools/testbbdev.rst
@@ -6,9 +6,9 @@ dpdk-test-bbdev Application
 
 The ``dpdk-test-bbdev`` tool is a Data Plane Development Kit (DPDK) utility that
 allows measuring performance parameters of PMDs available in the bbdev framework.
-Available tests available for execution are: latency, throughput, validation and
-sanity tests. Execution of tests can be customized using various parameters
-passed to a python running script.
+Available tests available for execution are: latency, throughput, validation,
+bler and sanity tests. Execution of tests can be customized using various
+parameters passed to a python running script.
 
 Compiling the Application
 -------------------------
@@ -47,6 +47,8 @@ The tool application has a number of command line options:
                        [-c TEST_CASE [TEST_CASE ...]]
                        [-v TEST_VECTOR [TEST_VECTOR...]] [-n NUM_OPS]
                        [-b BURST_SIZE [BURST_SIZE ...]] [-l NUM_LCORES]
+                       [-t MAX_ITERS [MAX_ITERS ...]]
+                       [-s SNR [SNR ...]]
 
 command-line Options
 ~~~~~~~~~~~~~~~~~~~~
@@ -106,10 +108,18 @@ The following are the command-line options:
  Specifies operations enqueue/dequeue burst size. If not specified burst_size is
  set to 32. Maximum is 512.
 
+``-t MAX_ITERS [MAX_ITERS ...], --iter_max MAX_ITERS [MAX_ITERS ...]``
+ Specifies LDPC decoder operations maximum number of iterations for throughput
+ and bler tests. If not specified iter_max is set to 6.
+
+``-s SNR [SNR ...], --snr SNR [SNR ...]``
+ Specifies for LDPC decoder operations the SNR in dB used when generating LLRs
+ for bler tests. If not specified snr is set to 0 dB.
+
 Test Cases
 ~~~~~~~~~~
 
-There are 6 main test cases that can be executed using testbbdev tool:
+There are 7 main test cases that can be executed using testbbdev tool:
 
 * Sanity checks [-c unittest]
     - Performs sanity checks on BBDEV interface, validating basic functionality
@@ -149,6 +159,11 @@ There are 6 main test cases that can be executed using testbbdev tool:
     - Results are printed in million operations per second and million bits
       per second
 
+* BLER measurement [-c bler]
+    - Performs full operation of enqueue and dequeue
+    - Measures the achieved throughput on a subset or all available CPU cores
+    - Computed BLER in % based on the total number of operations.
+
 * Interrupt-mode Throughput [-c interrupt]
     - Similar to Throughput test case, but using interrupts. No polling.
 
@@ -159,7 +174,7 @@ Parameter Globbing
 Thanks to the globbing functionality in python test-bbdev.py script allows to
 run tests with different set of vector files without giving all of them explicitly.
 
-**Example usage:**
+**Example usage for 4G:**
 
 .. code-block:: console
 
@@ -221,6 +236,11 @@ It runs all tests with "default" vectors.
 * ``turbo_enc_default.data`` is a soft link to
   ``turbo_enc_c1_k6144_r0_e32256_crc24b_rm.data``
 
+* ``ldpc_dec_default.data`` is a soft link to
+  ``ldpc_dec_v6563.data``
+
+* ``ldpc_enc_default.data`` is a soft link to
+  ``ldpc_enc_c1_k8148_r0_e9372_rm.data``
 
 Running Tests
 -------------
@@ -254,6 +274,38 @@ x86_64-native-linux-icc target:
              |-- turbo_dec_c1_k6144_r0_e34560_posllr.data
              |-- turbo_enc_c1_k40_r0_e1194_rm.data
              |-- turbo_enc_c1_k6144_r0_e32256_crc24b_rm.data
+             |-- ldpc_enc_v9503.data
+             |-- ldpc_enc_v8568.data
+             |-- ldpc_enc_v7813.data
+             |-- ldpc_enc_v2342.data
+             |-- ldpc_enc_v11835.data
+             |-- ldpc_dec_v8568.data
+             |-- ldpc_dec_v8480.data
+             |-- ldpc_dec_v7813.data
+             |-- ldpc_dec_v2342_drop.data
+             |-- ldpc_dec_v11835.data
+             |-- ldpc_dec_HARQ_1_2.data
+             |-- ldpc_dec_HARQ_1_1.data
+             |-- ldpc_dec_HARQ_1_0.data
+             |-- ldpc_enc_v8568_crc24a.data
+             |-- ldpc_enc_v3964_rv1.data
+             |-- ldpc_enc_c1_k8148_r0_e9372_rm.data
+             |-- ldpc_enc_c1_k720_r0_e864_rm_crc24b.data
+             |-- ldpc_enc_c1_k720_r0_e832_rm.data
+             |-- ldpc_enc_c1_k330_r0_e360_rm.data
+             |-- ldpc_enc_c1_k1144_r0_e1380_rm_crc24b.data
+             |-- ldpc_enc_c1_k1144_r0_e1380_rm.data
+             |-- ldpc_dec_vcrc_fail.data
+             |-- ldpc_dec_v8568_low.data
+             |-- ldpc_dec_v14298.data
+             |-- ldpc_dec_HARQ_26449_1.loopback_w
+             |-- ldpc_dec_HARQ_1_3.data
+             |-- ldpc_enc_v2570_lbrm.data
+             |-- ldpc_dec_v9503.data
+             |-- ldpc_dec_v6563.data
+             |-- ldpc_dec_HARQ_3_1_harq_comp.data
+             |-- ldpc_dec_HARQ_2_1_llr_comp.data
+             |-- ldpc_dec_HARQ_26449_1.loopback_r
 
  |-- x86_64-native-linux-icc
      |-- app
@@ -280,7 +332,7 @@ baseband turbo_sw device
 
   ./test-bbdev.py -p ../../x86_64-native-linux-icc/app/testbbdev
   -e="--vdev=baseband_turbo_sw" -t 120 -c validation
-  -v ./test_vectors/turbo_* -n 64 -b 8 32
+  -v ./test_vectors/* -n 64 -b 8 32
 
 It runs **validation** test for each vector file that matches the given pattern.
 Number of operations to process on device is set to 64 and operations timeout is
@@ -342,8 +394,8 @@ Length of chain variable is calculated by parser. Can not be defined
 explicitly.
 
 Variable op_type has to be defined as a first variable in file. It specifies
-what type of operations will be executed. For decoder op_type has to be set to
-``RTE_BBDEV_OP_TURBO_DEC`` and for encoder to ``RTE_BBDEV_OP_TURBO_ENC``.
+what type of operations will be executed. For 4G decoder op_type has to be set to
+``RTE_BBDEV_OP_TURBO_DEC`` and for 4G encoder to ``RTE_BBDEV_OP_TURBO_ENC``.
 
 Full details of the meaning and valid values for the below fields are
 documented in *rte_bbdev_op.h*
@@ -469,35 +521,7 @@ uint8_t value
     num_maps =
     0
 
-Chain of flags for turbo decoder operation. Following flags can be used:
-
-- ``RTE_BBDEV_TURBO_SUBBLOCK_DEINTERLEAVE``
-
-- ``RTE_BBDEV_TURBO_CRC_TYPE_24B``
-
-- ``RTE_BBDEV_TURBO_EQUALIZER``
-
-- ``RTE_BBDEV_TURBO_SOFT_OUT_SATURATE``
-
-- ``RTE_BBDEV_TURBO_HALF_ITERATION_EVEN``
-
-- ``RTE_BBDEV_TURBO_CONTINUE_CRC_MATCH``
-
-- ``RTE_BBDEV_TURBO_SOFT_OUTPUT``
-
-- ``RTE_BBDEV_TURBO_EARLY_TERMINATION``
-
-- ``RTE_BBDEV_TURBO_DEC_INTERRUPTS``
-
-- ``RTE_BBDEV_TURBO_POS_LLR_1_BIT_IN``
-
-- ``RTE_BBDEV_TURBO_NEG_LLR_1_BIT_IN``
-
-- ``RTE_BBDEV_TURBO_POS_LLR_1_BIT_SOFT_OUT``
-
-- ``RTE_BBDEV_TURBO_NEG_LLR_1_BIT_SOFT_OUT``
-
-- ``RTE_BBDEV_TURBO_MAP_DEC``
+Chain of flags for LDPC decoder operation based on the rte_bbdev_op_td_flag_bitmasks:
 
 Example:
 
@@ -579,26 +603,247 @@ uint8_t value
     rv_index =
     0
 
-Chain of flags for turbo encoder operation. Following flags can be used:
+Chain of flags for LDPC decoder operation based on the rte_bbdev_op_te_flag_bitmasks:
+
+``RTE_BBDEV_TURBO_ENC_SCATTER_GATHER`` is used to indicate the parser to
+force the input data to be memory split and formed as a segmented mbuf.
+
+
+.. parsed-literal::
+
+    op_flags =
+    RTE_BBDEV_TURBO_RATE_MATCH
 
-- ``RTE_BBDEV_TURBO_RV_INDEX_BYPASS``
+Chain of operation statuses that are expected after operation is performed.
+Following statuses can be used:
 
-- ``RTE_BBDEV_TURBO_RATE_MATCH``
+- ``DMA``
 
-- ``RTE_BBDEV_TURBO_CRC_24B_ATTACH``
+- ``FCW``
 
-- ``RTE_BBDEV_TURBO_CRC_24A_ATTACH``
+- ``OK``
 
-- ``RTE_BBDEV_TURBO_ENC_SCATTER_GATHER``
+``OK`` means no errors are expected. Cannot be used with other values.
 
-``RTE_BBDEV_TURBO_ENC_SCATTER_GATHER`` is used to indicate the parser to
-force the input data to be memory split and formed as a segmented mbuf.
+.. parsed-literal::
+
+    expected_status =
+    OK
+
+LDPC decoder test vectors template
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+For LDPC decoder it has to be always set to ``RTE_BBDEV_OP_LDPC_DEC``
+
+.. parsed-literal::
+
+    op_type =
+    RTE_BBDEV_OP_LDPC_DEC
+
+Chain of uint32_t values. Note that it is possible to define more than one
+input/output entries which will result in chaining two or more data structures
+for *segmented Transport Blocks*
+
+.. parsed-literal::
+
+    input0 =
+    0x00000000, 0x7f817f00, 0x7f7f8100, 0x817f8100, 0x81008100, 0x7f818100, 0x81817f00, 0x7f818100,
+    0x81007f00, 0x7f818100, 0x817f8100, 0x81817f00, 0x81008100, 0x817f7f00, 0x7f7f8100, 0x81817f00
+
+.. parsed-literal::
+
+    output0 =
+    0xa7d6732e
+
+uint8_t value
+
+.. parsed-literal::
+
+    basegraph=
+    1
+
+uint16_t value
+
+.. parsed-literal::
+
+    z_c=
+    224
+
+uint16_t value
+
+.. parsed-literal::
+
+    n_cb=
+    14784
+
+uint8_t value
+
+.. parsed-literal::
+
+    q_m=
+    1
+
+uint16_t value
+
+.. parsed-literal::
+
+    n_filler=
+    40
+
+uint32_t value
+
+.. parsed-literal::
+
+    e=
+    13072
+
+uint8_t value
+
+.. parsed-literal::
+
+    rv_index=
+    2
+
+uint8_t value
+
+.. parsed-literal::
+    code_block_mode=
+    1
 
+uint8_t value
+
+.. parsed-literal::
+
+    iter_max=
+    20
+
+uint8_t value
+
+.. parsed-literal::
+
+    expected_iter_count=
+    8
+
+
+Chain of flags for LDPC decoder operation based on the rte_bbdev_op_ldpcdec_flag_bitmasks:
+
+Example:
+
+    .. parsed-literal::
+
+        op_flags =
+        RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE, RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE,
+        RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE, RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION
+
+Chain of operation statuses that are expected after operation is performed.
+Following statuses can be used:
+
+- ``SYNCRC``
+
+- ``SYN``
+
+- ``CRC``
+
+- ``OK``
+
+``OK`` means no errors are expected. Cannot be used with other values.
+
+.. parsed-literal::
+
+    expected_status =
+    CRC
+
+
+LDPC encoder test vectors template
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+For turbo encoder it has to be always set to ``RTE_BBDEV_OP_LDPC_ENC``
+
+.. parsed-literal::
+
+    op_type =
+    RTE_BBDEV_OP_LDPC_ENC
+
+Chain of uint32_t values
+
+.. parsed-literal::
+
+    input0 =
+    0x11d2bcac, 0x4d
+
+Chain of uint32_t values
+
+.. parsed-literal::
+
+    output0 =
+    0xd2399179, 0x640eb999, 0x2cbaf577, 0xaf224ae2, 0x9d139927, 0xe6909b29,
+    0xa25b7f47, 0x2aa224ce, 0x79f2
+
+
+uint8_t value
+
+.. parsed-literal::
+
+    basegraph=
+    1
+
+uint16_t value
+
+.. parsed-literal::
+
+    z_c=
+    52
+
+uint16_t value
+
+.. parsed-literal::
+
+    n_cb=
+    3432
+
+uint8_t value
+
+.. parsed-literal::
+
+    q_m=
+    6
+
+uint16_t value
+
+.. parsed-literal::
+
+    n_filler=
+    0
+
+uint32_t value
+
+.. parsed-literal::
+
+    e =
+    1380
+
+uint8_t value
+
+.. parsed-literal::
+
+    rv_index =
+    1
+
+uint8_t value
+
+.. parsed-literal::
+
+    code_block_mode =
+    1
+
+
+Chain of flags for LDPC encoder operation based on the
+rte_bbdev_op_ldpcenc_flag_bitmasks:
 
 .. parsed-literal::
 
     op_flags =
-    RTE_BBDEV_TURBO_RATE_MATCH
+    RTE_BBDEV_LDPC_RATE_MATCH
 
 Chain of operation statuses that are expected after operation is performed.
 Following statuses can be used:
-- 
1.8.3.1


^ permalink raw reply	[flat|nested] 115+ messages in thread

* [dpdk-dev] [PATCH v2 12/15] drivers/baseband: add PMD for FPGA 5GNR FEC
  2020-03-04 18:22   ` [dpdk-dev] [PATCH v2 00/15] bbdev new features Nicolas Chautru
                       ` (10 preceding siblings ...)
  2020-03-04 18:22     ` [dpdk-dev] [PATCH v2 11/15] doc: update of testbbdev documentation Nicolas Chautru
@ 2020-03-04 18:22     ` Nicolas Chautru
  2020-03-04 18:22     ` [dpdk-dev] [PATCH v2 13/15] test-bbdev: add support for FPGA driver initialization Nicolas Chautru
                       ` (2 subsequent siblings)
  14 siblings, 0 replies; 115+ messages in thread
From: Nicolas Chautru @ 2020-03-04 18:22 UTC (permalink / raw)
  To: thomas, akhil.goyal, dev; +Cc: ferruh.yigit, Nic Chautru

From: Nic Chautru <nicolas.chautru@intel.com>

Supports for FEC 5G PMD Driver on FPGA card PAC N3000

Signed-off-by: Nic Chautru <nicolas.chautru@intel.com>
---
 config/common_base                                 |    5 +
 doc/guides/bbdevs/fpga_5gnr_fec.rst                |  297 +++
 doc/guides/bbdevs/index.rst                        |    1 +
 drivers/baseband/Makefile                          |    2 +
 drivers/baseband/fpga_5gnr_fec/Makefile            |   29 +
 drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.c     | 2552 ++++++++++++++++++++
 drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h     |   74 +
 drivers/baseband/fpga_5gnr_fec/meson.build         |    6 +
 .../rte_pmd_bbdev_fpga_5gnr_fec_version.map        |   10 +
 drivers/baseband/meson.build                       |    2 +-
 mk/rte.app.mk                                      |    1 +
 11 files changed, 2978 insertions(+), 1 deletion(-)
 create mode 100644 doc/guides/bbdevs/fpga_5gnr_fec.rst
 create mode 100644 drivers/baseband/fpga_5gnr_fec/Makefile
 create mode 100644 drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.c
 create mode 100644 drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h
 create mode 100644 drivers/baseband/fpga_5gnr_fec/meson.build
 create mode 100644 drivers/baseband/fpga_5gnr_fec/rte_pmd_bbdev_fpga_5gnr_fec_version.map

diff --git a/config/common_base b/config/common_base
index 7ca2f28..7280ee2 100644
--- a/config/common_base
+++ b/config/common_base
@@ -578,6 +578,11 @@ CONFIG_RTE_LIBRTE_PMD_BBDEV_TURBO_SW=y
 CONFIG_RTE_LIBRTE_PMD_BBDEV_FPGA_LTE_FEC=y
 
 #
+# Compile PMD for Intel FPGA 5GNR FEC bbdev device
+#
+CONFIG_RTE_LIBRTE_PMD_BBDEV_FPGA_5GNR_FEC=y
+
+#
 # Compile generic crypto device library
 #
 CONFIG_RTE_LIBRTE_CRYPTODEV=y
diff --git a/doc/guides/bbdevs/fpga_5gnr_fec.rst b/doc/guides/bbdevs/fpga_5gnr_fec.rst
new file mode 100644
index 0000000..5641b1a
--- /dev/null
+++ b/doc/guides/bbdevs/fpga_5gnr_fec.rst
@@ -0,0 +1,297 @@
+..  SPDX-License-Identifier: BSD-3-Clause
+    Copyright(c) 2019 Intel Corporation
+
+Intel(R) FPGA 5GNR FEC Poll Mode Driver
+======================================
+
+The BBDEV FPGA 5GNR FEC poll mode driver (PMD) supports an FPGA implementation of a VRAN
+LDPC Encode / Decode 5GNR wireless acceleration function, using Intel's PCI-e and FPGA
+based Vista Creek device.
+
+Features
+--------
+
+FPGA 5GNR FEC PMD supports the following features:
+
+- LDPC Encode in the DL
+- LDPC Decode in the UL
+- 8 VFs per PF (physical device)
+- Maximum of 32 UL queues per VF
+- Maximum of 32 DL queues per VF
+- PCIe Gen-3 x8 Interface
+- MSI-X
+- SR-IOV
+
+FPGA 5GNR FEC PMD supports the following BBDEV capabilities:
+
+* For the LDPC encode operation:
+   - ``RTE_BBDEV_LDPC_CRC_24B_ATTACH`` :  set to attach CRC24B to CB(s)
+   - ``RTE_BBDEV_LDPC_RATE_MATCH`` :  if set then do not do Rate Match bypass
+
+* For the LDPC decode operation:
+   - ``RTE_BBDEV_LDPC_CRC_TYPE_24B_CHECK`` :  check CRC24B from CB(s)
+   - ``RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE`` :  disable early termination
+   - ``RTE_BBDEV_LDPC_CRC_TYPE_24B_DROP`` :  drops CRC24B bits appended while decoding
+   - ``RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE`` :  provides an input for HARQ combining
+   - ``RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE`` :  provides an input for HARQ combining
+   - ``RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_IN_ENABLE`` :  HARQ memory input is internal
+   - ``RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_OUT_ENABLE`` :  HARQ memory output is internal
+   - ``RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK`` :  loopback data to/from HARQ memory
+   - ``RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_FILLERS`` :  HARQ memory includes the fillers bits
+
+
+Limitations
+-----------
+
+FPGA 5GNR FEC does not support the following:
+
+- Scatter-Gather function
+
+
+Installation
+--------------
+
+Section 3 of the DPDK manual provides instuctions on installing and compiling DPDK. The
+default set of bbdev compile flags may be found in config/common_base, where for example
+the flag to build the FPGA 5GNR FEC device, ``CONFIG_RTE_LIBRTE_PMD_BBDEV_FPGA_5GNR_FEC``,
+is already set. It is assumed DPDK has been compiled using for instance:
+
+.. code-block:: console
+
+  make install T=x86_64-native-linuxapp-gcc
+
+
+DPDK requires hugepages to be configured as detailed in section 2 of the DPDK manual.
+The bbdev test application has been tested with a configuration 40 x 1GB hugepages. The
+hugepage configuration of a server may be examined using:
+
+.. code-block:: console
+
+   grep Huge* /proc/meminfo
+
+
+Initialization
+--------------
+
+When the device first powers up, its PCI Physical Functions (PF) can be listed through this command:
+
+.. code-block:: console
+
+  sudo lspci -vd8086:0d8f
+
+The physical and virtual functions are compatible with Linux UIO drivers:
+``vfio`` and ``igb_uio``. However, in order to work the FPGA 5GNR FEC device firstly needs
+to be bound to one of these linux drivers through DPDK.
+
+
+Bind PF UIO driver(s)
+~~~~~~~~~~~~~~~~~~~~~
+
+Install the DPDK igb_uio driver, bind it with the PF PCI device ID and use
+``lspci`` to confirm the PF device is under use by ``igb_uio`` DPDK UIO driver.
+
+The igb_uio driver may be bound to the PF PCI device using one of three methods:
+
+
+1. PCI functions (physical or virtual, depending on the use case) can be bound to
+the UIO driver by repeating this command for every function.
+
+.. code-block:: console
+
+  cd <dpdk-top-level-directory>
+  insmod ./build/kmod/igb_uio.ko
+  echo "8086 0d8f" > /sys/bus/pci/drivers/igb_uio/new_id
+  lspci -vd8086:0d8f
+
+
+2. Another way to bind PF with DPDK UIO driver is by using the ``dpdk-devbind.py`` tool
+
+.. code-block:: console
+
+  cd <dpdk-top-level-directory>
+  ./usertools/dpdk-devbind.py -b igb_uio 0000:06:00.0
+
+where the PCI device ID (example: 0000:06:00.0) is obtained using lspci -vd8086:0d8f
+
+
+3. A third way to bind is to use ``dpdk-setup.sh`` tool
+
+.. code-block:: console
+
+  cd <dpdk-top-level-directory>
+  ./usertools/dpdk-setup.sh
+
+  select 'Bind Ethernet/Crypto/Baseband device to IGB UIO module'
+  or
+  select 'Bind Ethernet/Crypto/Baseband device to VFIO module' depending on driver required
+  enter PCI device ID
+  select 'Display current Ethernet/Crypto/Baseband device settings' to confirm binding
+
+
+In the same way the FPGA 5GNR FEC PF can be bound with vfio, but vfio driver does not
+support SR-IOV configuration right out of the box, so it will need to be patched.
+
+
+Enable Virtual Functions
+~~~~~~~~~~~~~~~~~~~~~~~~
+
+Now, it should be visible in the printouts that PCI PF is under igb_uio control
+"``Kernel driver in use: igb_uio``"
+
+To show the number of available VFs on the device, read ``sriov_totalvfs`` file..
+
+.. code-block:: console
+
+  cat /sys/bus/pci/devices/0000\:<b>\:<d>.<f>/sriov_totalvfs
+
+  where 0000\:<b>\:<d>.<f> is the PCI device ID
+
+
+To enable VFs via igb_uio, echo the number of virtual functions intended to
+enable to ``max_vfs`` file..
+
+.. code-block:: console
+
+  echo <num-of-vfs> > /sys/bus/pci/devices/0000\:<b>\:<d>.<f>/max_vfs
+
+
+Afterwards, all VFs must be bound to appropriate UIO drivers as required, same
+way it was done with the physical function previously.
+
+Enabling SR-IOV via vfio driver is pretty much the same, except that the file
+name is different:
+
+.. code-block:: console
+
+  echo <num-of-vfs> > /sys/bus/pci/devices/0000\:<b>\:<d>.<f>/sriov_numvfs
+
+
+Configure the VFs through PF
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The PCI virtual functions must be configured before working or getting assigned
+to VMs/Containers. The configuration involves allocating the number of hardware
+queues, priorities, load balance, bandwidth and other settings necessary for the
+device to perform FEC functions.
+
+This configuration needs to be executed at least once after reboot or PCI FLR and can
+be achieved by using the function ``fpga_5gnr_fec_configure()``, which sets up the
+parameters defined in ``fpga_5gnr_fec_conf`` structure:
+
+.. code-block:: c
+
+  struct fpga_5gnr_fec_conf {
+      bool pf_mode_en;
+      uint8_t vf_ul_queues_number[FPGA_5GNR_FEC_NUM_VFS];
+      uint8_t vf_dl_queues_number[FPGA_5GNR_FEC_NUM_VFS];
+      uint8_t ul_bandwidth;
+      uint8_t dl_bandwidth;
+      uint8_t ul_load_balance;
+      uint8_t dl_load_balance;
+      uint16_t flr_time_out;
+  };
+
+- ``pf_mode_en``: identifies whether only PF is to be used, or the VFs. PF and
+  VFs are mutually exclusive and cannot run simultaneously.
+  Set to 1 for PF mode enabled.
+  If PF mode is enabled all queues available in the device are assigned
+  exclusively to PF and 0 queues given to VFs.
+
+- ``vf_*l_queues_number``: defines the hardware queue mapping for every VF.
+
+- ``*l_bandwidth``: in case of congestion on PCIe interface. The device
+  allocates different bandwidth to UL and DL. The weight is configured by this
+  setting. The unit of weight is 3 code blocks. For example, if the code block
+  cbps (code block per second) ratio between UL and DL is 12:1, then the
+  configuration value should be set to 36:3. The schedule algorithm is based
+  on code block regardless the length of each block.
+
+- ``*l_load_balance``: hardware queues are load-balanced in a round-robin
+  fashion. Queues get filled first-in first-out until they reach a pre-defined
+  watermark level, if exceeded, they won't get assigned new code blocks..
+  This watermark is defined by this setting.
+
+  If all hardware queues exceeds the watermark, no code blocks will be
+  streamed in from UL/DL code block FIFO.
+
+- ``flr_time_out``: specifies how many 16.384us to be FLR time out. The
+  time_out = flr_time_out x 16.384us. For instance, if you want to set 10ms for
+  the FLR time out then set this setting to 0x262=610.
+
+
+An example configuration code calling the function ``fpga_5gnr_fec_configure()`` is shown
+below:
+
+.. code-block:: c
+
+  struct fpga_5gnr_fec_conf conf;
+  unsigned int i;
+
+  memset(&conf, 0, sizeof(struct fpga_5gnr_fec_conf));
+  conf.pf_mode_en = 1;
+
+  for (i = 0; i < FPGA_5GNR_FEC_NUM_VFS; ++i) {
+      conf.vf_ul_queues_number[i] = 4;
+      conf.vf_dl_queues_number[i] = 4;
+  }
+  conf.ul_bandwidth = 12;
+  conf.dl_bandwidth = 5;
+  conf.dl_load_balance = 64;
+  conf.ul_load_balance = 64;
+
+  /* setup FPGA PF */
+  ret = fpga_5gnr_fec_configure(info->dev_name, &conf);
+  TEST_ASSERT_SUCCESS(ret,
+      "Failed to configure 4G FPGA PF for bbdev %s",
+      info->dev_name);
+
+
+Test Application
+----------------
+
+BBDEV provides a test application, ``test-bbdev.py`` and range of test data for testing
+the functionality of FPGA 5GNR FEC encode and decode, depending on the device's
+capabilities. The test application is located under app->test-bbdev folder and has the
+following options:
+
+.. code-block:: console
+
+  "-p", "--testapp-path": specifies path to the bbdev test app.
+  "-e", "--eal-params"	: EAL arguments which are passed to the test app.
+  "-t", "--timeout"	: Timeout in seconds (default=300).
+  "-c", "--test-cases"	: Defines test cases to run. Run all if not specified.
+  "-v", "--test-vector"	: Test vector path (default=dpdk_path+/app/test-bbdev/test_vectors/bbdev_null.data).
+  "-n", "--num-ops"	: Number of operations to process on device (default=32).
+  "-b", "--burst-size"	: Operations enqueue/dequeue burst size (default=32).
+  "-l", "--num-lcores"	: Number of lcores to run (default=16).
+  "-i", "--init-device" : Initialise PF device with default values.
+
+
+To execute the test application tool using simple decode or encode data,
+type one of the following:
+
+.. code-block:: console
+
+  ./test-bbdev.py -c validation -n 64 -b 1 -v ./ldpc_dec_default.data
+  ./test-bbdev.py -c validation -n 64 -b 1 -v ./ldpc_enc_default.data
+
+
+The test application ``test-bbdev.py``, supports the ability to configure the PF device with
+a default set of values, if the "-i" or "- -init-device" option is included. The default values
+are defined in test_bbdev_perf.c as:
+
+- VF_UL_QUEUE_VALUE 4
+- VF_DL_QUEUE_VALUE 4
+- UL_BANDWIDTH 3
+- DL_BANDWIDTH 3
+- UL_LOAD_BALANCE 128
+- DL_LOAD_BALANCE 128
+- FLR_TIMEOUT 610
+
+
+Test Vectors
+~~~~~~~~~~~~
+
+In addition to the simple LDPC decoder and LDPC encoder tests, bbdev also provides
+a range of additional tests under the test_vectors folder, which may be useful. The results
+of these tests will depend on the FPGA 5GNR FEC capabilities.
diff --git a/doc/guides/bbdevs/index.rst b/doc/guides/bbdevs/index.rst
index 005b95e..1a79343 100644
--- a/doc/guides/bbdevs/index.rst
+++ b/doc/guides/bbdevs/index.rst
@@ -11,3 +11,4 @@ Baseband Device Drivers
     null
     turbo_sw
     fpga_lte_fec
+    fpga_5gnr_fec
diff --git a/drivers/baseband/Makefile b/drivers/baseband/Makefile
index 91048be..762773c 100644
--- a/drivers/baseband/Makefile
+++ b/drivers/baseband/Makefile
@@ -12,5 +12,7 @@ DIRS-$(CONFIG_RTE_LIBRTE_PMD_BBDEV_TURBO_SW) += turbo_sw
 DEPDIRS-turbo_sw = $(core-libs)
 DIRS-$(CONFIG_RTE_LIBRTE_PMD_BBDEV_FPGA_LTE_FEC) += fpga_lte_fec
 DEPDIRS-fpga_lte_fec = $(core-libs)
+DIRS-$(CONFIG_RTE_LIBRTE_PMD_BBDEV_FPGA_LTE_FEC) += fpga_5gnr_fec
+DEPDIRS-fpga_5gnr_fec = $(core-libs)
 
 include $(RTE_SDK)/mk/rte.subdir.mk
diff --git a/drivers/baseband/fpga_5gnr_fec/Makefile b/drivers/baseband/fpga_5gnr_fec/Makefile
new file mode 100644
index 0000000..de80d67
--- /dev/null
+++ b/drivers/baseband/fpga_5gnr_fec/Makefile
@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2019 Intel Corporation
+
+include $(RTE_SDK)/mk/rte.vars.mk
+
+# library name
+LIB = librte_pmd_bbdev_fpga_5gnr_fec.a
+
+# build flags
+CFLAGS += -DALLOW_EXPERIMENTAL_API
+CFLAGS += -O3
+CFLAGS += $(WERROR_FLAGS)
+LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool -lrte_ring
+LDLIBS += -lrte_bbdev
+LDLIBS += -lrte_pci -lrte_bus_pci
+
+# versioning export map
+EXPORT_MAP := rte_pmd_bbdev_fpga_5gnr_fec_version.map
+
+# library version
+LIBABIVER := 1
+
+# library source files
+SRCS-$(CONFIG_RTE_LIBRTE_PMD_BBDEV_FPGA_5GNR_FEC) += fpga_5gnr_fec.c
+
+# export include files
+SYMLINK-$(CONFIG_RTE_LIBRTE_PMD_BBDEV_FPGA_5GNR_FEC)-include += fpga_5gnr_fec.h
+
+include $(RTE_SDK)/mk/rte.lib.mk
diff --git a/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.c b/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.c
new file mode 100644
index 0000000..5935e24
--- /dev/null
+++ b/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.c
@@ -0,0 +1,2552 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2020 Intel Corporation
+ */
+
+#include <unistd.h>
+
+#include <rte_common.h>
+#include <rte_log.h>
+#include <rte_dev.h>
+#include <rte_malloc.h>
+#include <rte_mempool.h>
+#include <rte_errno.h>
+#include <rte_pci.h>
+#include <rte_bus_pci.h>
+#include <rte_byteorder.h>
+#ifdef RTE_BBDEV_OFFLOAD_COST
+#include <rte_cycles.h>
+#endif
+
+#include <rte_bbdev.h>
+#include <rte_bbdev_pmd.h>
+
+#include "fpga_5gnr_fec.h"
+
+/* 5GNR SW PMD logging ID */
+static int fpga_5gnr_fec_logtype;
+
+/* Helper macro for logging */
+#define rte_bbdev_log(level, fmt, ...) \
+	rte_log(RTE_LOG_ ## level, fpga_5gnr_fec_logtype, fmt "\n", \
+		##__VA_ARGS__)
+
+#ifdef RTE_LIBRTE_BBDEV_DEBUG
+#define rte_bbdev_log_debug(fmt, ...) \
+		rte_bbdev_log(DEBUG, "fpga_5gnr_fec: " fmt, \
+		##__VA_ARGS__)
+#else
+#define rte_bbdev_log_debug(fmt, ...)
+#endif
+
+/* FPGA 5GNR FEC driver names */
+#define FPGA_5GNR_FEC_PF_DRIVER_NAME intel_fpga_5gnr_fec_pf
+#define FPGA_5GNR_FEC_VF_DRIVER_NAME intel_fpga_5gnr_fec_vf
+
+/* FPGA 5GNR FEC PCI vendor & device IDs */
+#define FPGA_5GNR_FEC_VENDOR_ID (0x8086)
+#define FPGA_5GNR_FEC_PF_DEVICE_ID (0x0D8F)
+#define FPGA_5GNR_FEC_VF_DEVICE_ID (0x0D90)
+
+/* Align DMA descriptors to 256 bytes - cache-aligned */
+#define FPGA_RING_DESC_ENTRY_LENGTH (8)
+/* Ring size is in 256 bits (32 bytes) units */
+#define FPGA_RING_DESC_LEN_UNIT_BYTES (32)
+/* Maximum size of queue */
+#define FPGA_RING_MAX_SIZE (1024)
+#define FPGA_FLR_TIMEOUT_UNIT (16.384)
+
+#define FPGA_NUM_UL_QUEUES (32)
+#define FPGA_NUM_DL_QUEUES (32)
+#define FPGA_TOTAL_NUM_QUEUES (FPGA_NUM_UL_QUEUES + FPGA_NUM_DL_QUEUES)
+#define FPGA_NUM_INTR_VEC (FPGA_TOTAL_NUM_QUEUES - RTE_INTR_VEC_RXTX_OFFSET)
+
+#define FPGA_INVALID_HW_QUEUE_ID (0xFFFFFFFF)
+
+#define FPGA_QUEUE_FLUSH_TIMEOUT_US (1000)
+#define FPGA_HARQ_RDY_TIMEOUT (10)
+#define FPGA_TIMEOUT_CHECK_INTERVAL (5)
+#define FPGA_DDR_OVERFLOW (0x10)
+
+#define FPGA_5GNR_FEC_DDR_WR_DATA_LEN_IN_BYTES 8
+#define FPGA_5GNR_FEC_DDR_RD_DATA_LEN_IN_BYTES 8
+
+
+/* FPGA 5GNR FEC Register mapping on BAR0 */
+enum {
+	FPGA_5GNR_FEC_VERSION_ID = 0x00000000, /* len: 4B */
+	FPGA_5GNR_FEC_CONFIGURATION = 0x00000004, /* len: 2B */
+	FPGA_5GNR_FEC_QUEUE_PF_VF_MAP_DONE = 0x00000008, /* len: 1B */
+	FPGA_5GNR_FEC_LOAD_BALANCE_FACTOR = 0x0000000a, /* len: 2B */
+	FPGA_5GNR_FEC_RING_DESC_LEN = 0x0000000c, /* len: 2B */
+	FPGA_5GNR_FEC_FLR_TIME_OUT = 0x0000000e, /* len: 2B */
+	FPGA_5GNR_FEC_VFQ_FLUSH_STATUS_LW = 0x00000018, /* len: 4B */
+	FPGA_5GNR_FEC_VFQ_FLUSH_STATUS_HI = 0x0000001c, /* len: 4B */
+	FPGA_5GNR_FEC_QUEUE_MAP = 0x00000040, /* len: 256B */
+	FPGA_5GNR_FEC_RING_CTRL_REGS = 0x00000200, /* len: 2048B */
+	FPGA_5GNR_FEC_DDR4_WR_ADDR_REGS = 0x00000A00, /* len: 4B */
+	FPGA_5GNR_FEC_DDR4_WR_DATA_REGS = 0x00000A08, /* len: 8B */
+	FPGA_5GNR_FEC_DDR4_WR_DONE_REGS = 0x00000A10, /* len: 1B */
+	FPGA_5GNR_FEC_DDR4_RD_ADDR_REGS = 0x00000A18, /* len: 4B */
+	FPGA_5GNR_FEC_DDR4_RD_DONE_REGS = 0x00000A20, /* len: 1B */
+	FPGA_5GNR_FEC_DDR4_RD_RDY_REGS = 0x00000A28, /* len: 1B */
+	FPGA_5GNR_FEC_DDR4_RD_DATA_REGS = 0x00000A30, /* len: 8B */
+	FPGA_5GNR_FEC_DDR4_ADDR_RDY_REGS = 0x00000A38, /* len: 1B */
+	FPGA_5GNR_FEC_HARQ_BUF_SIZE_RDY_REGS = 0x00000A40, /* len: 1B */
+	FPGA_5GNR_FEC_HARQ_BUF_SIZE_REGS = 0x00000A48  /* len: 4B */
+};
+
+/* FPGA 5GNR FEC Ring Control Registers */
+enum {
+	FPGA_5GNR_FEC_RING_HEAD_ADDR = 0x00000008,
+	FPGA_5GNR_FEC_RING_SIZE = 0x00000010,
+	FPGA_5GNR_FEC_RING_MISC = 0x00000014,
+	FPGA_5GNR_FEC_RING_ENABLE = 0x00000015,
+	FPGA_5GNR_FEC_RING_FLUSH_QUEUE_EN = 0x00000016,
+	FPGA_5GNR_FEC_RING_SHADOW_TAIL = 0x00000018,
+	FPGA_5GNR_FEC_RING_HEAD_POINT = 0x0000001C
+};
+
+/* FPGA 5GNR FEC DESCRIPTOR ERROR */
+enum {
+	DESC_ERR_NO_ERR = 0x0,
+	DESC_ERR_K_P_OUT_OF_RANGE = 0x1,
+	DESC_ERR_Z_C_NOT_LEGAL = 0x2,
+	DESC_ERR_DESC_OFFSET_ERR = 0x3,
+	DESC_ERR_DESC_READ_FAIL = 0x8,
+	DESC_ERR_DESC_READ_TIMEOUT = 0x9,
+	DESC_ERR_DESC_READ_TLP_POISONED = 0xA,
+	DESC_ERR_CB_READ_FAIL = 0xC,
+	DESC_ERR_CB_READ_TIMEOUT = 0xD,
+	DESC_ERR_CB_READ_TLP_POISONED = 0xE,
+	DESC_ERR_HBSTORE_ERR = 0xF
+};
+
+
+/* FPGA 5GNR FEC DMA Encoding Request Descriptor */
+struct __attribute__((__packed__)) fpga_dma_enc_desc {
+	uint32_t done:1,
+		rsrvd0:7,
+		error:4,
+		rsrvd1:4,
+		num_null:10,
+		rsrvd2:6;
+	uint32_t ncb:15,
+		rsrvd3:1,
+		k0:16;
+	uint32_t irq_en:1,
+		crc_en:1,
+		rsrvd4:1,
+		qm_idx:3,
+		bg_idx:1,
+		zc:9,
+		desc_idx:10,
+		rsrvd5:6;
+	uint16_t rm_e;
+	uint16_t k_;
+	uint32_t out_addr_lw;
+	uint32_t out_addr_hi;
+	uint32_t in_addr_lw;
+	uint32_t in_addr_hi;
+
+	union {
+		struct {
+			/* Virtual addresses used to retrieve SW context info */
+			void *op_addr;
+			/* Stores information about total number of Code Blocks
+			 * in currently processed Transport Block
+			 */
+			uint64_t cbs_in_op;
+		};
+
+		uint8_t sw_ctxt[FPGA_RING_DESC_LEN_UNIT_BYTES *
+					(FPGA_RING_DESC_ENTRY_LENGTH - 1)];
+	};
+};
+
+
+/* FPGA 5GNR DPC FEC DMA Decoding Request Descriptor */
+struct __attribute__((__packed__)) fpga_dma_dec_desc {
+	uint32_t done:1,
+		iter:5,
+		et_pass:1,
+		crcb_pass:1,
+		error:4,
+		qm_idx:3,
+		max_iter:5,
+		bg_idx:1,
+		rsrvd0:1,
+		harqin_en:1,
+		zc:9;
+	uint32_t hbstroe_offset:22,
+		num_null:10;
+	uint32_t irq_en:1,
+		ncb:15,
+		desc_idx:10,
+		drop_crc24b:1,
+		crc24b_ind:1,
+		rv:2,
+		et_dis:1,
+		rsrvd2:1;
+	uint32_t harq_input_length:16,
+		rm_e:16;/*the inbound data byte length*/
+	uint32_t out_addr_lw;
+	uint32_t out_addr_hi;
+	uint32_t in_addr_lw;
+	uint32_t in_addr_hi;
+
+	union {
+		struct {
+			/* Virtual addresses used to retrieve SW context info */
+			void *op_addr;
+			/* Stores information about total number of Code Blocks
+			 * in currently processed Transport Block
+			 */
+			uint8_t cbs_in_op;
+		};
+
+		uint32_t sw_ctxt[8 * (FPGA_RING_DESC_ENTRY_LENGTH - 1)];
+	};
+};
+
+/* FPGA 5GNR DMA Descriptor */
+union fpga_dma_desc {
+	struct fpga_dma_enc_desc enc_req;
+	struct fpga_dma_dec_desc dec_req;
+};
+
+/* FPGA 5GNR FEC Ring Control Register */
+struct __attribute__((__packed__)) fpga_ring_ctrl_reg {
+	uint64_t ring_base_addr;
+	uint64_t ring_head_addr;
+	uint16_t ring_size:11;
+	uint16_t rsrvd0;
+	union { /* Miscellaneous register */
+		uint8_t misc;
+		uint8_t max_ul_dec:5,
+			max_ul_dec_en:1,
+			rsrvd1:2;
+	};
+	uint8_t enable;
+	uint8_t flush_queue_en;
+	uint8_t rsrvd2;
+	uint16_t shadow_tail;
+	uint16_t rsrvd3;
+	uint16_t head_point;
+	uint16_t rsrvd4;
+
+};
+
+/* Private data structure for each FPGA FEC device */
+struct fpga_5gnr_fec_device {
+	/** Base address of MMIO registers (BAR0) */
+	void *mmio_base;
+	/** Base address of memory for sw rings */
+	void *sw_rings;
+	/** Physical address of sw_rings */
+	rte_iova_t sw_rings_phys;
+	/** Number of bytes available for each queue in device. */
+	uint32_t sw_ring_size;
+	/** Max number of entries available for each queue in device */
+	uint32_t sw_ring_max_depth;
+	/** Base address of response tail pointer buffer */
+	uint32_t *tail_ptrs;
+	/** Physical address of tail pointers */
+	rte_iova_t tail_ptr_phys;
+	/** Queues flush completion flag */
+	uint64_t *flush_queue_status;
+	/* Bitmap capturing which Queues are bound to the PF/VF */
+	uint64_t q_bound_bit_map;
+	/* Bitmap capturing which Queues have already been assigned */
+	uint64_t q_assigned_bit_map;
+	/** True if this is a PF FPGA FEC device */
+	bool pf_device;
+};
+
+/* Structure associated with each queue. */
+struct __rte_cache_aligned fpga_queue {
+	struct fpga_ring_ctrl_reg ring_ctrl_reg;  /* Ring Control Register */
+	union fpga_dma_desc *ring_addr;  /* Virtual address of software ring */
+	uint64_t *ring_head_addr;  /* Virtual address of completion_head */
+	uint64_t shadow_completion_head; /* Shadow completion head value */
+	uint16_t head_free_desc;  /* Ring head */
+	uint16_t tail;  /* Ring tail */
+	/* Mask used to wrap enqueued descriptors on the sw ring */
+	uint32_t sw_ring_wrap_mask;
+	uint32_t irq_enable;  /* Enable ops dequeue interrupts if set to 1 */
+	uint8_t q_idx;  /* Queue index */
+	struct fpga_5gnr_fec_device *d;
+	/* MMIO register of shadow_tail used to enqueue descriptors */
+	void *shadow_tail_addr;
+};
+
+/* Write to 16 bit MMIO register address */
+static inline void
+mmio_write_16(void *addr, uint16_t value)
+{
+	*((volatile uint16_t *)(addr)) = rte_cpu_to_le_16(value);
+}
+
+/* Write to 32 bit MMIO register address */
+static inline void
+mmio_write_32(void *addr, uint32_t value)
+{
+	*((volatile uint32_t *)(addr)) = rte_cpu_to_le_32(value);
+}
+
+/* Write to 64 bit MMIO register address */
+static inline void
+mmio_write_64(void *addr, uint64_t value)
+{
+	*((volatile uint64_t *)(addr)) = rte_cpu_to_le_64(value);
+}
+
+/* Write a 8 bit register of a FPGA 5GNR FEC device */
+static inline void
+fpga_reg_write_8(void *mmio_base, uint32_t offset, uint8_t payload)
+{
+	void *reg_addr = RTE_PTR_ADD(mmio_base, offset);
+	*((volatile uint8_t *)(reg_addr)) = payload;
+}
+
+/* Write a 16 bit register of a FPGA 5GNR FEC device */
+static inline void
+fpga_reg_write_16(void *mmio_base, uint32_t offset, uint16_t payload)
+{
+	void *reg_addr = RTE_PTR_ADD(mmio_base, offset);
+	mmio_write_16(reg_addr, payload);
+}
+
+/* Write a 32 bit register of a FPGA 5GNR FEC device */
+static inline void
+fpga_reg_write_32(void *mmio_base, uint32_t offset, uint32_t payload)
+{
+	void *reg_addr = RTE_PTR_ADD(mmio_base, offset);
+	mmio_write_32(reg_addr, payload);
+}
+
+/* Write a 64 bit register of a FPGA 5GNR FEC device */
+static inline void
+fpga_reg_write_64(void *mmio_base, uint32_t offset, uint64_t payload)
+{
+	void *reg_addr = RTE_PTR_ADD(mmio_base, offset);
+	mmio_write_64(reg_addr, payload);
+}
+
+/* Write a ring control register of a FPGA 5GNR FEC device */
+static inline void
+fpga_ring_reg_write(void *mmio_base, uint32_t offset,
+		struct fpga_ring_ctrl_reg payload)
+{
+	fpga_reg_write_64(mmio_base, offset, payload.ring_base_addr);
+	fpga_reg_write_64(mmio_base, offset + FPGA_5GNR_FEC_RING_HEAD_ADDR,
+			payload.ring_head_addr);
+	fpga_reg_write_16(mmio_base, offset + FPGA_5GNR_FEC_RING_SIZE,
+			payload.ring_size);
+	fpga_reg_write_16(mmio_base, offset + FPGA_5GNR_FEC_RING_HEAD_POINT,
+			payload.head_point);
+	fpga_reg_write_8(mmio_base, offset + FPGA_5GNR_FEC_RING_FLUSH_QUEUE_EN,
+			payload.flush_queue_en);
+	fpga_reg_write_16(mmio_base, offset + FPGA_5GNR_FEC_RING_SHADOW_TAIL,
+			payload.shadow_tail);
+	fpga_reg_write_8(mmio_base, offset + FPGA_5GNR_FEC_RING_MISC,
+			payload.misc);
+	fpga_reg_write_8(mmio_base, offset + FPGA_5GNR_FEC_RING_ENABLE,
+			payload.enable);
+}
+
+/* Read a register of FPGA 5GNR FEC device */
+static uint32_t
+fpga_reg_read_32(void *mmio_base, uint32_t offset)
+{
+	void *reg_addr = RTE_PTR_ADD(mmio_base, offset);
+	uint32_t ret = *((volatile uint32_t *)(reg_addr));
+	return rte_le_to_cpu_32(ret);
+}
+
+/* Read a register of FPGA 5GNR FEC device */
+static uint8_t
+fpga_reg_read_8(void *mmio_base, uint32_t offset)
+{
+	void *reg_addr = RTE_PTR_ADD(mmio_base, offset);
+	return *((volatile uint8_t *)(reg_addr));
+}
+
+/* Read a register of FPGA 5GNR FEC device */
+static uint64_t
+fpga_reg_read_64(void *mmio_base, uint32_t offset)
+{
+	void *reg_addr = RTE_PTR_ADD(mmio_base, offset);
+	uint64_t ret = *((volatile uint64_t *)(reg_addr));
+	return rte_le_to_cpu_64(ret);
+}
+
+#ifdef RTE_LIBRTE_BBDEV_DEBUG
+
+/* Read a register of FPGA 5GNR FEC device */
+static uint16_t
+fpga_reg_read_16(void *mmio_base, uint32_t offset)
+{
+	void *reg_addr = RTE_PTR_ADD(mmio_base, offset);
+	uint16_t ret = *((volatile uint16_t *)(reg_addr));
+	return rte_le_to_cpu_16(ret);
+}
+
+/* Read Ring Control Register of FPGA 5GNR FEC device */
+static inline void
+print_ring_reg_debug_info(void *mmio_base, uint32_t offset)
+{
+	rte_bbdev_log_debug(
+		"FPGA MMIO base address @ %p | Ring Control Register @ offset = 0x%08"
+		PRIx32, mmio_base, offset);
+	rte_bbdev_log_debug(
+		"RING_BASE_ADDR = 0x%016"PRIx64,
+		fpga_reg_read_64(mmio_base, offset));
+	rte_bbdev_log_debug(
+		"RING_HEAD_ADDR = 0x%016"PRIx64,
+		fpga_reg_read_64(mmio_base, offset +
+				FPGA_5GNR_FEC_RING_HEAD_ADDR));
+	rte_bbdev_log_debug(
+		"RING_SIZE = 0x%04"PRIx16,
+		fpga_reg_read_16(mmio_base, offset +
+				FPGA_5GNR_FEC_RING_SIZE));
+	rte_bbdev_log_debug(
+		"RING_MISC = 0x%02"PRIx8,
+		fpga_reg_read_8(mmio_base, offset +
+				FPGA_5GNR_FEC_RING_MISC));
+	rte_bbdev_log_debug(
+		"RING_ENABLE = 0x%02"PRIx8,
+		fpga_reg_read_8(mmio_base, offset +
+				FPGA_5GNR_FEC_RING_ENABLE));
+	rte_bbdev_log_debug(
+		"RING_FLUSH_QUEUE_EN = 0x%02"PRIx8,
+		fpga_reg_read_8(mmio_base, offset +
+				FPGA_5GNR_FEC_RING_FLUSH_QUEUE_EN));
+	rte_bbdev_log_debug(
+		"RING_SHADOW_TAIL = 0x%04"PRIx16,
+		fpga_reg_read_16(mmio_base, offset +
+				FPGA_5GNR_FEC_RING_SHADOW_TAIL));
+	rte_bbdev_log_debug(
+		"RING_HEAD_POINT = 0x%04"PRIx16,
+		fpga_reg_read_16(mmio_base, offset +
+				FPGA_5GNR_FEC_RING_HEAD_POINT));
+}
+
+/* Read Static Register of FPGA 5GNR FEC device */
+static inline void
+print_static_reg_debug_info(void *mmio_base)
+{
+	uint16_t config = fpga_reg_read_16(mmio_base,
+			FPGA_5GNR_FEC_CONFIGURATION);
+	uint8_t qmap_done = fpga_reg_read_8(mmio_base,
+			FPGA_5GNR_FEC_QUEUE_PF_VF_MAP_DONE);
+	uint16_t lb_factor = fpga_reg_read_16(mmio_base,
+			FPGA_5GNR_FEC_LOAD_BALANCE_FACTOR);
+	uint16_t ring_desc_len = fpga_reg_read_16(mmio_base,
+			FPGA_5GNR_FEC_RING_DESC_LEN);
+	uint16_t flr_time_out = fpga_reg_read_16(mmio_base,
+			FPGA_5GNR_FEC_FLR_TIME_OUT);
+
+	rte_bbdev_log_debug("UL.DL Weights = %u.%u",
+			((uint8_t)config), ((uint8_t)(config >> 8)));
+	rte_bbdev_log_debug("UL.DL Load Balance = %u.%u",
+			((uint8_t)lb_factor), ((uint8_t)(lb_factor >> 8)));
+	rte_bbdev_log_debug("Queue-PF/VF Mapping Table = %s",
+			(qmap_done > 0) ? "READY" : "NOT-READY");
+	rte_bbdev_log_debug("Ring Descriptor Size = %u bytes",
+			ring_desc_len*FPGA_RING_DESC_LEN_UNIT_BYTES);
+	rte_bbdev_log_debug("FLR Timeout = %f usec",
+			(float)flr_time_out*FPGA_FLR_TIMEOUT_UNIT);
+}
+
+/* Print decode DMA Descriptor of FPGA 5GNR Decoder device */
+static void
+print_dma_dec_desc_debug_info(union fpga_dma_desc *desc)
+{
+	rte_bbdev_log_debug("DMA response desc %p\n"
+		"\t-- done(%"PRIu32") | iter(%"PRIu32") | et_pass(%"PRIu32")"
+		" | crcb_pass (%"PRIu32") | error(%"PRIu32")\n"
+		"\t-- qm_idx(%"PRIu32") | max_iter(%"PRIu32") | "
+		"bg_idx (%"PRIu32") | harqin_en(%"PRIu32") | zc(%"PRIu32")\n"
+		"\t-- hbstroe_offset(%"PRIu32") | num_null (%"PRIu32") "
+		"| irq_en(%"PRIu32")\n"
+		"\t-- ncb(%"PRIu32") | desc_idx (%"PRIu32") | "
+		"drop_crc24b(%"PRIu32") | RV (%"PRIu32")\n"
+		"\t-- crc24b_ind(%"PRIu32") | et_dis (%"PRIu32")\n"
+		"\t-- harq_input_length(%"PRIu32") | rm_e(%"PRIu32")\n"
+		"\t-- cbs_in_op(%"PRIu32") | in_add (0x%08"PRIx32"%08"PRIx32")"
+		"| out_add (0x%08"PRIx32"%08"PRIx32")",
+		desc,
+		(uint32_t)desc->dec_req.done,
+		(uint32_t)desc->dec_req.iter,
+		(uint32_t)desc->dec_req.et_pass,
+		(uint32_t)desc->dec_req.crcb_pass,
+		(uint32_t)desc->dec_req.error,
+		(uint32_t)desc->dec_req.qm_idx,
+		(uint32_t)desc->dec_req.max_iter,
+		(uint32_t)desc->dec_req.bg_idx,
+		(uint32_t)desc->dec_req.harqin_en,
+		(uint32_t)desc->dec_req.zc,
+		(uint32_t)desc->dec_req.hbstroe_offset,
+		(uint32_t)desc->dec_req.num_null,
+		(uint32_t)desc->dec_req.irq_en,
+		(uint32_t)desc->dec_req.ncb,
+		(uint32_t)desc->dec_req.desc_idx,
+		(uint32_t)desc->dec_req.drop_crc24b,
+		(uint32_t)desc->dec_req.rv,
+		(uint32_t)desc->dec_req.crc24b_ind,
+		(uint32_t)desc->dec_req.et_dis,
+		(uint32_t)desc->dec_req.harq_input_length,
+		(uint32_t)desc->dec_req.rm_e,
+		(uint32_t)desc->dec_req.cbs_in_op,
+		(uint32_t)desc->dec_req.in_addr_hi,
+		(uint32_t)desc->dec_req.in_addr_lw,
+		(uint32_t)desc->dec_req.out_addr_hi,
+		(uint32_t)desc->dec_req.out_addr_lw);
+	uint32_t *word = (uint32_t *) desc;
+	rte_bbdev_log_debug("%08"PRIx32"\n%08"PRIx32"\n%08"PRIx32"\n%08"PRIx32"\n"
+			"%08"PRIx32"\n%08"PRIx32"\n%08"PRIx32"\n%08"PRIx32"\n",
+			word[0], word[1], word[2], word[3],
+			word[4], word[5], word[6], word[7]);
+}
+
+/* Print decode DMA Descriptor of FPGA 5GNR encoder device */
+static void
+print_dma_enc_desc_debug_info(union fpga_dma_desc *desc)
+{
+	rte_bbdev_log_debug("DMA response desc %p\n"
+			"%"PRIu32" %"PRIu32"\n"
+			"K' %"PRIu32" E %"PRIu32" desc %"PRIu32" Z %"PRIu32"\n"
+			"BG %"PRIu32" Qm %"PRIu32" CRC %"PRIu32" IRQ %"PRIu32"\n"
+			"k0 %"PRIu32" Ncb %"PRIu32" F %"PRIu32"\n",
+			desc,
+			(uint32_t)desc->enc_req.done,
+			(uint32_t)desc->enc_req.error,
+
+			(uint32_t)desc->enc_req.k_,
+			(uint32_t)desc->enc_req.rm_e,
+			(uint32_t)desc->enc_req.desc_idx,
+			(uint32_t)desc->enc_req.zc,
+
+			(uint32_t)desc->enc_req.bg_idx,
+			(uint32_t)desc->enc_req.qm_idx,
+			(uint32_t)desc->enc_req.crc_en,
+			(uint32_t)desc->enc_req.irq_en,
+
+			(uint32_t)desc->enc_req.k0,
+			(uint32_t)desc->enc_req.ncb,
+			(uint32_t)desc->enc_req.num_null);
+	uint32_t *word = (uint32_t *) desc;
+	rte_bbdev_log_debug("%08"PRIx32"\n%08"PRIx32"\n%08"PRIx32"\n%08"PRIx32"\n"
+			"%08"PRIx32"\n%08"PRIx32"\n%08"PRIx32"\n%08"PRIx32"\n",
+			word[0], word[1], word[2], word[3],
+			word[4], word[5], word[6], word[7]);
+}
+
+#endif
+
+static int
+fpga_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id)
+{
+	/* Number of queues bound to a PF/VF */
+	uint32_t hw_q_num = 0;
+	uint32_t ring_size, payload, address, q_id, offset;
+	rte_iova_t phys_addr;
+	struct fpga_ring_ctrl_reg ring_reg;
+	struct fpga_5gnr_fec_device *fpga_dev = dev->data->dev_private;
+
+	address = FPGA_5GNR_FEC_QUEUE_PF_VF_MAP_DONE;
+	if (!(fpga_reg_read_32(fpga_dev->mmio_base, address) & 0x1)) {
+		rte_bbdev_log(ERR,
+				"Queue-PF/VF mapping is not set! Was PF configured for device (%s) ?",
+				dev->data->name);
+		return -EPERM;
+	}
+
+	/* Clear queue registers structure */
+	memset(&ring_reg, 0, sizeof(struct fpga_ring_ctrl_reg));
+
+	/* Scan queue map.
+	 * If a queue is valid and mapped to a calling PF/VF the read value is
+	 * replaced with a queue ID and if it's not then
+	 * FPGA_INVALID_HW_QUEUE_ID is returned.
+	 */
+	for (q_id = 0; q_id < FPGA_TOTAL_NUM_QUEUES; ++q_id) {
+		uint32_t hw_q_id = fpga_reg_read_32(fpga_dev->mmio_base,
+				FPGA_5GNR_FEC_QUEUE_MAP + (q_id << 2));
+
+		rte_bbdev_log_debug("%s: queue ID: %u, registry queue ID: %u",
+				dev->device->name, q_id, hw_q_id);
+
+		if (hw_q_id != FPGA_INVALID_HW_QUEUE_ID) {
+			fpga_dev->q_bound_bit_map |= (1ULL << q_id);
+			/* Clear queue register of found queue */
+			offset = FPGA_5GNR_FEC_RING_CTRL_REGS +
+				(sizeof(struct fpga_ring_ctrl_reg) * q_id);
+			fpga_ring_reg_write(fpga_dev->mmio_base,
+					offset, ring_reg);
+			++hw_q_num;
+		}
+	}
+	if (hw_q_num == 0) {
+		rte_bbdev_log(ERR,
+			"No HW queues assigned to this device. Probably this is a VF configured for PF mode. Check device configuration!");
+		return -ENODEV;
+	}
+
+	if (num_queues > hw_q_num) {
+		rte_bbdev_log(ERR,
+			"Not enough queues for device %s! Requested: %u, available: %u",
+			dev->device->name, num_queues, hw_q_num);
+		return -EINVAL;
+	}
+
+	ring_size = FPGA_RING_MAX_SIZE * sizeof(struct fpga_dma_dec_desc);
+
+	/* Enforce 32 byte alignment */
+	RTE_BUILD_BUG_ON((RTE_CACHE_LINE_SIZE % 32) != 0);
+
+	/* Allocate memory for SW descriptor rings */
+	fpga_dev->sw_rings = rte_zmalloc_socket(dev->device->driver->name,
+			num_queues * ring_size, RTE_CACHE_LINE_SIZE,
+			socket_id);
+	if (fpga_dev->sw_rings == NULL) {
+		rte_bbdev_log(ERR,
+				"Failed to allocate memory for %s:%u sw_rings",
+				dev->device->driver->name, dev->data->dev_id);
+		return -ENOMEM;
+	}
+
+	fpga_dev->sw_rings_phys = rte_malloc_virt2iova(fpga_dev->sw_rings);
+	fpga_dev->sw_ring_size = ring_size;
+	fpga_dev->sw_ring_max_depth = FPGA_RING_MAX_SIZE;
+
+	/* Allocate memory for ring flush status */
+	fpga_dev->flush_queue_status = rte_zmalloc_socket(NULL,
+			sizeof(uint64_t), RTE_CACHE_LINE_SIZE, socket_id);
+	if (fpga_dev->flush_queue_status == NULL) {
+		rte_bbdev_log(ERR,
+				"Failed to allocate memory for %s:%u flush_queue_status",
+				dev->device->driver->name, dev->data->dev_id);
+		return -ENOMEM;
+	}
+
+	/* Set the flush status address registers */
+	phys_addr = rte_malloc_virt2iova(fpga_dev->flush_queue_status);
+
+	address = FPGA_5GNR_FEC_VFQ_FLUSH_STATUS_LW;
+	payload = (uint32_t)(phys_addr);
+	fpga_reg_write_32(fpga_dev->mmio_base, address, payload);
+
+	address = FPGA_5GNR_FEC_VFQ_FLUSH_STATUS_HI;
+	payload = (uint32_t)(phys_addr >> 32);
+	fpga_reg_write_32(fpga_dev->mmio_base, address, payload);
+
+	return 0;
+}
+
+static int
+fpga_dev_close(struct rte_bbdev *dev)
+{
+	struct fpga_5gnr_fec_device *fpga_dev = dev->data->dev_private;
+
+	rte_free(fpga_dev->sw_rings);
+	rte_free(fpga_dev->flush_queue_status);
+
+	return 0;
+}
+
+static void
+fpga_dev_info_get(struct rte_bbdev *dev,
+		struct rte_bbdev_driver_info *dev_info)
+{
+	struct fpga_5gnr_fec_device *d = dev->data->dev_private;
+	uint32_t q_id = 0;
+
+	static const struct rte_bbdev_op_cap bbdev_capabilities[] = {
+		{
+			.type   = RTE_BBDEV_OP_LDPC_ENC,
+			.cap.ldpc_enc = {
+				.capability_flags =
+						RTE_BBDEV_LDPC_RATE_MATCH |
+						RTE_BBDEV_LDPC_ENC_INTERRUPTS |
+						RTE_BBDEV_LDPC_CRC_24B_ATTACH,
+				.num_buffers_src =
+						RTE_BBDEV_LDPC_MAX_CODE_BLOCKS,
+				.num_buffers_dst =
+						RTE_BBDEV_LDPC_MAX_CODE_BLOCKS,
+			}
+		},
+		{
+		.type   = RTE_BBDEV_OP_LDPC_DEC,
+		.cap.ldpc_dec = {
+			.capability_flags =
+				RTE_BBDEV_LDPC_CRC_TYPE_24B_CHECK |
+				RTE_BBDEV_LDPC_CRC_TYPE_24B_DROP |
+				RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE |
+				RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE |
+				RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE |
+				RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_IN_ENABLE |
+				RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_OUT_ENABLE |
+				RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK |
+				RTE_BBDEV_LDPC_DEC_INTERRUPTS |
+				RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_FILLERS,
+			.llr_size = 6,
+			.llr_decimals = 2,
+			.num_buffers_src =
+					RTE_BBDEV_LDPC_MAX_CODE_BLOCKS,
+			.num_buffers_hard_out =
+					RTE_BBDEV_LDPC_MAX_CODE_BLOCKS,
+			.num_buffers_soft_out = 0,
+		}
+		},
+		RTE_BBDEV_END_OF_CAPABILITIES_LIST()
+	};
+
+	/* Check the HARQ DDR size available */
+	uint8_t timeout_counter = 0;
+	uint32_t harq_buf_ready = fpga_reg_read_32(d->mmio_base,
+			FPGA_5GNR_FEC_HARQ_BUF_SIZE_RDY_REGS);
+	while (harq_buf_ready != 1) {
+		usleep(FPGA_TIMEOUT_CHECK_INTERVAL);
+		timeout_counter++;
+		harq_buf_ready = fpga_reg_read_32(d->mmio_base,
+				FPGA_5GNR_FEC_HARQ_BUF_SIZE_RDY_REGS);
+		if (timeout_counter > FPGA_HARQ_RDY_TIMEOUT) {
+			rte_bbdev_log(ERR, "HARQ Buffer not ready %d",
+					harq_buf_ready);
+			harq_buf_ready = 1;
+		}
+	}
+	uint32_t harq_buf_size = fpga_reg_read_32(d->mmio_base,
+			FPGA_5GNR_FEC_HARQ_BUF_SIZE_REGS);
+
+	static struct rte_bbdev_queue_conf default_queue_conf;
+	default_queue_conf.socket = dev->data->socket_id;
+	default_queue_conf.queue_size = FPGA_RING_MAX_SIZE;
+
+	dev_info->driver_name = dev->device->driver->name;
+	dev_info->queue_size_lim = FPGA_RING_MAX_SIZE;
+	dev_info->hardware_accelerated = true;
+	dev_info->min_alignment = 64;
+	dev_info->harq_buffer_size = (harq_buf_size >> 10) + 1;
+	dev_info->default_queue_conf = default_queue_conf;
+	dev_info->capabilities = bbdev_capabilities;
+	dev_info->cpu_flag_reqs = NULL;
+
+	/* Calculates number of queues assigned to device */
+	dev_info->max_num_queues = 0;
+	for (q_id = 0; q_id < FPGA_TOTAL_NUM_QUEUES; ++q_id) {
+		uint32_t hw_q_id = fpga_reg_read_32(d->mmio_base,
+				FPGA_5GNR_FEC_QUEUE_MAP + (q_id << 2));
+		if (hw_q_id != FPGA_INVALID_HW_QUEUE_ID)
+			dev_info->max_num_queues++;
+	}
+}
+
+/**
+ * Find index of queue bound to current PF/VF which is unassigned. Return -1
+ * when there is no available queue
+ */
+static int
+fpga_find_free_queue_idx(struct rte_bbdev *dev,
+		const struct rte_bbdev_queue_conf *conf)
+{
+	struct fpga_5gnr_fec_device *d = dev->data->dev_private;
+	uint64_t q_idx;
+	uint8_t i = 0;
+	uint8_t range = FPGA_TOTAL_NUM_QUEUES >> 1;
+
+	if (conf->op_type == RTE_BBDEV_OP_LDPC_ENC) {
+		i = FPGA_NUM_DL_QUEUES;
+		range = FPGA_TOTAL_NUM_QUEUES;
+	}
+
+	for (; i < range; ++i) {
+		q_idx = 1ULL << i;
+		/* Check if index of queue is bound to current PF/VF */
+		if (d->q_bound_bit_map & q_idx)
+			/* Check if found queue was not already assigned */
+			if (!(d->q_assigned_bit_map & q_idx)) {
+				d->q_assigned_bit_map |= q_idx;
+				return i;
+			}
+	}
+
+	rte_bbdev_log(INFO, "Failed to find free queue on %s", dev->data->name);
+
+	return -1;
+}
+
+static int
+fpga_queue_setup(struct rte_bbdev *dev, uint16_t queue_id,
+		const struct rte_bbdev_queue_conf *conf)
+{
+	uint32_t address, ring_offset;
+	struct fpga_5gnr_fec_device *d = dev->data->dev_private;
+	struct fpga_queue *q;
+	int8_t q_idx;
+
+	/* Check if there is a free queue to assign */
+	q_idx = fpga_find_free_queue_idx(dev, conf);
+	if (q_idx == -1)
+		return -1;
+
+	/* Allocate the queue data structure. */
+	q = rte_zmalloc_socket(dev->device->driver->name, sizeof(*q),
+			RTE_CACHE_LINE_SIZE, conf->socket);
+	if (q == NULL) {
+		/* Mark queue as un-assigned */
+		d->q_assigned_bit_map &= (0xFFFFFFFF - (1ULL << q_idx));
+		rte_bbdev_log(ERR, "Failed to allocate queue memory");
+		return -ENOMEM;
+	}
+
+	q->d = d;
+	q->q_idx = q_idx;
+
+	/* Set ring_base_addr */
+	q->ring_addr = RTE_PTR_ADD(d->sw_rings, (d->sw_ring_size * queue_id));
+	q->ring_ctrl_reg.ring_base_addr = d->sw_rings_phys +
+			(d->sw_ring_size * queue_id);
+
+	/* Allocate memory for Completion Head variable*/
+	q->ring_head_addr = rte_zmalloc_socket(dev->device->driver->name,
+			sizeof(uint64_t), RTE_CACHE_LINE_SIZE, conf->socket);
+	if (q->ring_head_addr == NULL) {
+		/* Mark queue as un-assigned */
+		d->q_assigned_bit_map &= (0xFFFFFFFF - (1ULL << q_idx));
+		rte_free(q);
+		rte_bbdev_log(ERR,
+				"Failed to allocate memory for %s:%u completion_head",
+				dev->device->driver->name, dev->data->dev_id);
+		return -ENOMEM;
+	}
+	/* Set ring_head_addr */
+	q->ring_ctrl_reg.ring_head_addr =
+			rte_malloc_virt2iova(q->ring_head_addr);
+
+	/* Clear shadow_completion_head */
+	q->shadow_completion_head = 0;
+
+	/* Set ring_size */
+	if (conf->queue_size > FPGA_RING_MAX_SIZE) {
+		/* Mark queue as un-assigned */
+		d->q_assigned_bit_map &= (0xFFFFFFFF - (1ULL << q_idx));
+		rte_free(q->ring_head_addr);
+		rte_free(q);
+		rte_bbdev_log(ERR,
+				"Size of queue is too big %d (MAX: %d ) for %s:%u",
+				conf->queue_size, FPGA_RING_MAX_SIZE,
+				dev->device->driver->name, dev->data->dev_id);
+		return -EINVAL;
+	}
+	q->ring_ctrl_reg.ring_size = conf->queue_size;
+
+	/* Set Miscellaneous FPGA register*/
+	/* Max iteration number for TTI mitigation - todo */
+	q->ring_ctrl_reg.max_ul_dec = 0;
+	/* Enable max iteration number for TTI - todo */
+	q->ring_ctrl_reg.max_ul_dec_en = 0;
+
+	/* Enable the ring */
+	q->ring_ctrl_reg.enable = 1;
+
+	/* Set FPGA head_point and tail registers */
+	q->ring_ctrl_reg.head_point = q->tail = 0;
+
+	/* Set FPGA shadow_tail register */
+	q->ring_ctrl_reg.shadow_tail = q->tail;
+
+	/* Calculates the ring offset for found queue */
+	ring_offset = FPGA_5GNR_FEC_RING_CTRL_REGS +
+			(sizeof(struct fpga_ring_ctrl_reg) * q_idx);
+
+	/* Set FPGA Ring Control Registers */
+	fpga_ring_reg_write(d->mmio_base, ring_offset, q->ring_ctrl_reg);
+
+	/* Store MMIO register of shadow_tail */
+	address = ring_offset + FPGA_5GNR_FEC_RING_SHADOW_TAIL;
+	q->shadow_tail_addr = RTE_PTR_ADD(d->mmio_base, address);
+
+	q->head_free_desc = q->tail;
+
+	/* Set wrap mask */
+	q->sw_ring_wrap_mask = conf->queue_size - 1;
+
+	rte_bbdev_log_debug("Setup dev%u q%u: queue_idx=%u",
+			dev->data->dev_id, queue_id, q->q_idx);
+
+	dev->data->queues[queue_id].queue_private = q;
+
+	rte_bbdev_log_debug("BBDEV queue[%d] set up for FPGA queue[%d]",
+			queue_id, q_idx);
+
+#ifdef RTE_LIBRTE_BBDEV_DEBUG
+	/* Read FPGA Ring Control Registers after configuration*/
+	print_ring_reg_debug_info(d->mmio_base, ring_offset);
+#endif
+	return 0;
+}
+
+static int
+fpga_queue_release(struct rte_bbdev *dev, uint16_t queue_id)
+{
+	struct fpga_5gnr_fec_device *d = dev->data->dev_private;
+	struct fpga_queue *q = dev->data->queues[queue_id].queue_private;
+	struct fpga_ring_ctrl_reg ring_reg;
+	uint32_t offset;
+
+	rte_bbdev_log_debug("FPGA Queue[%d] released", queue_id);
+
+	if (q != NULL) {
+		memset(&ring_reg, 0, sizeof(struct fpga_ring_ctrl_reg));
+		offset = FPGA_5GNR_FEC_RING_CTRL_REGS +
+			(sizeof(struct fpga_ring_ctrl_reg) * q->q_idx);
+		/* Disable queue */
+		fpga_reg_write_8(d->mmio_base,
+				offset + FPGA_5GNR_FEC_RING_ENABLE, 0x00);
+		/* Clear queue registers */
+		fpga_ring_reg_write(d->mmio_base, offset, ring_reg);
+
+		/* Mark the Queue as un-assigned */
+		d->q_assigned_bit_map &= (0xFFFFFFFF - (1ULL << q->q_idx));
+		rte_free(q->ring_head_addr);
+		rte_free(q);
+		dev->data->queues[queue_id].queue_private = NULL;
+	}
+
+	return 0;
+}
+
+/* Function starts a device queue. */
+static int
+fpga_queue_start(struct rte_bbdev *dev, uint16_t queue_id)
+{
+	struct fpga_5gnr_fec_device *d = dev->data->dev_private;
+#ifdef RTE_LIBRTE_BBDEV_DEBUG
+	if (d == NULL) {
+		rte_bbdev_log(ERR, "Invalid device pointer");
+		return -1;
+	}
+#endif
+	struct fpga_queue *q = dev->data->queues[queue_id].queue_private;
+	uint32_t offset = FPGA_5GNR_FEC_RING_CTRL_REGS +
+			(sizeof(struct fpga_ring_ctrl_reg) * q->q_idx);
+	uint8_t enable = 0x01;
+	uint16_t zero = 0x0000;
+
+	/* Clear queue head and tail variables */
+	q->tail = q->head_free_desc = 0;
+
+	/* Clear FPGA head_point and tail registers */
+	fpga_reg_write_16(d->mmio_base, offset + FPGA_5GNR_FEC_RING_HEAD_POINT,
+			zero);
+	fpga_reg_write_16(d->mmio_base, offset + FPGA_5GNR_FEC_RING_SHADOW_TAIL,
+			zero);
+
+	/* Enable queue */
+	fpga_reg_write_8(d->mmio_base, offset + FPGA_5GNR_FEC_RING_ENABLE,
+			enable);
+
+	rte_bbdev_log_debug("FPGA Queue[%d] started", queue_id);
+	return 0;
+}
+
+/* Function stops a device queue. */
+static int
+fpga_queue_stop(struct rte_bbdev *dev, uint16_t queue_id)
+{
+	struct fpga_5gnr_fec_device *d = dev->data->dev_private;
+#ifdef RTE_LIBRTE_BBDEV_DEBUG
+	if (d == NULL) {
+		rte_bbdev_log(ERR, "Invalid device pointer");
+		return -1;
+	}
+#endif
+	struct fpga_queue *q = dev->data->queues[queue_id].queue_private;
+	uint32_t offset = FPGA_5GNR_FEC_RING_CTRL_REGS +
+			(sizeof(struct fpga_ring_ctrl_reg) * q->q_idx);
+	uint8_t payload = 0x01;
+	uint8_t counter = 0;
+	uint8_t timeout = FPGA_QUEUE_FLUSH_TIMEOUT_US /
+			FPGA_TIMEOUT_CHECK_INTERVAL;
+
+	/* Set flush_queue_en bit to trigger queue flushing */
+	fpga_reg_write_8(d->mmio_base,
+			offset + FPGA_5GNR_FEC_RING_FLUSH_QUEUE_EN, payload);
+
+	/** Check if queue flush is completed.
+	 * FPGA will update the completion flag after queue flushing is
+	 * completed. If completion flag is not updated within 1ms it is
+	 * considered as a failure.
+	 */
+	while (!(*((volatile uint8_t *)d->flush_queue_status + q->q_idx)
+			& payload)) {
+		if (counter > timeout) {
+			rte_bbdev_log(ERR, "FPGA Queue Flush failed for queue %d",
+					queue_id);
+			return -1;
+		}
+		usleep(FPGA_TIMEOUT_CHECK_INTERVAL);
+		counter++;
+	}
+
+	/* Disable queue */
+	payload = 0x00;
+	fpga_reg_write_8(d->mmio_base, offset + FPGA_5GNR_FEC_RING_ENABLE,
+			payload);
+
+	rte_bbdev_log_debug("FPGA Queue[%d] stopped", queue_id);
+	return 0;
+}
+
+static inline uint16_t
+get_queue_id(struct rte_bbdev_data *data, uint8_t q_idx)
+{
+	uint16_t queue_id;
+
+	for (queue_id = 0; queue_id < data->num_queues; ++queue_id) {
+		struct fpga_queue *q = data->queues[queue_id].queue_private;
+		if (q != NULL && q->q_idx == q_idx)
+			return queue_id;
+	}
+
+	return -1;
+}
+
+/* Interrupt handler triggered by FPGA dev for handling specific interrupt */
+static void
+fpga_dev_interrupt_handler(void *cb_arg)
+{
+	struct rte_bbdev *dev = cb_arg;
+	struct fpga_5gnr_fec_device *fpga_dev = dev->data->dev_private;
+	struct fpga_queue *q;
+	uint64_t ring_head;
+	uint64_t q_idx;
+	uint16_t queue_id;
+	uint8_t i;
+
+	/* Scan queue assigned to this device */
+	for (i = 0; i < FPGA_TOTAL_NUM_QUEUES; ++i) {
+		q_idx = 1ULL << i;
+		if (fpga_dev->q_bound_bit_map & q_idx) {
+			queue_id = get_queue_id(dev->data, i);
+			if (queue_id == (uint16_t) -1)
+				continue;
+
+			/* Check if completion head was changed */
+			q = dev->data->queues[queue_id].queue_private;
+			ring_head = *q->ring_head_addr;
+			if (q->shadow_completion_head != ring_head &&
+				q->irq_enable == 1) {
+				q->shadow_completion_head = ring_head;
+				rte_bbdev_pmd_callback_process(
+						dev,
+						RTE_BBDEV_EVENT_DEQUEUE,
+						&queue_id);
+			}
+		}
+	}
+}
+
+static int
+fpga_queue_intr_enable(struct rte_bbdev *dev, uint16_t queue_id)
+{
+	struct fpga_queue *q = dev->data->queues[queue_id].queue_private;
+
+	if (!rte_intr_cap_multiple(dev->intr_handle))
+		return -ENOTSUP;
+
+	q->irq_enable = 1;
+
+	return 0;
+}
+
+static int
+fpga_queue_intr_disable(struct rte_bbdev *dev, uint16_t queue_id)
+{
+	struct fpga_queue *q = dev->data->queues[queue_id].queue_private;
+	q->irq_enable = 0;
+
+	return 0;
+}
+
+static int
+fpga_intr_enable(struct rte_bbdev *dev)
+{
+	int ret;
+	uint8_t i;
+
+	if (!rte_intr_cap_multiple(dev->intr_handle)) {
+		rte_bbdev_log(ERR, "Multiple intr vector is not supported by FPGA (%s)",
+				dev->data->name);
+		return -ENOTSUP;
+	}
+
+	/* Create event file descriptors for each of 64 queue. Event fds will be
+	 * mapped to FPGA IRQs in rte_intr_enable(). This is a 1:1 mapping where
+	 * the IRQ number is a direct translation to the queue number.
+	 *
+	 * 63 (FPGA_NUM_INTR_VEC) event fds are created as rte_intr_enable()
+	 * mapped the first IRQ to already created interrupt event file
+	 * descriptor (intr_handle->fd).
+	 */
+	if (rte_intr_efd_enable(dev->intr_handle, FPGA_NUM_INTR_VEC)) {
+		rte_bbdev_log(ERR, "Failed to create fds for %u queues",
+				dev->data->num_queues);
+		return -1;
+	}
+
+	/* TODO Each event file descriptor is overwritten by interrupt event
+	 * file descriptor. That descriptor is added to epoll observed list.
+	 * It ensures that callback function assigned to that descriptor will
+	 * invoked when any FPGA queue issues interrupt.
+	 */
+	for (i = 0; i < FPGA_NUM_INTR_VEC; ++i)
+		dev->intr_handle->efds[i] = dev->intr_handle->fd;
+
+	if (!dev->intr_handle->intr_vec) {
+		dev->intr_handle->intr_vec = rte_zmalloc("intr_vec",
+				dev->data->num_queues * sizeof(int), 0);
+		if (!dev->intr_handle->intr_vec) {
+			rte_bbdev_log(ERR, "Failed to allocate %u vectors",
+					dev->data->num_queues);
+			return -ENOMEM;
+		}
+	}
+
+	ret = rte_intr_enable(dev->intr_handle);
+	if (ret < 0) {
+		rte_bbdev_log(ERR,
+				"Couldn't enable interrupts for device: %s",
+				dev->data->name);
+		return ret;
+	}
+
+	ret = rte_intr_callback_register(dev->intr_handle,
+			fpga_dev_interrupt_handler, dev);
+	if (ret < 0) {
+		rte_bbdev_log(ERR,
+				"Couldn't register interrupt callback for device: %s",
+				dev->data->name);
+		return ret;
+	}
+
+	return 0;
+}
+
+static const struct rte_bbdev_ops fpga_ops = {
+	.setup_queues = fpga_setup_queues,
+	.intr_enable = fpga_intr_enable,
+	.close = fpga_dev_close,
+	.info_get = fpga_dev_info_get,
+	.queue_setup = fpga_queue_setup,
+	.queue_stop = fpga_queue_stop,
+	.queue_start = fpga_queue_start,
+	.queue_release = fpga_queue_release,
+	.queue_intr_enable = fpga_queue_intr_enable,
+	.queue_intr_disable = fpga_queue_intr_disable
+};
+
+static inline void
+fpga_dma_enqueue(struct fpga_queue *q, uint16_t num_desc,
+		struct rte_bbdev_stats *queue_stats)
+{
+#ifdef RTE_BBDEV_OFFLOAD_COST
+	uint64_t start_time = 0;
+	queue_stats->acc_offload_cycles = 0;
+#else
+	RTE_SET_USED(queue_stats);
+#endif
+
+	/* Update tail and shadow_tail register */
+	q->tail = (q->tail + num_desc) & q->sw_ring_wrap_mask;
+
+	rte_wmb();
+
+#ifdef RTE_BBDEV_OFFLOAD_COST
+	/* Start time measurement for enqueue function offload. */
+	start_time = rte_rdtsc_precise();
+#endif
+	mmio_write_16(q->shadow_tail_addr, q->tail);
+
+#ifdef RTE_BBDEV_OFFLOAD_COST
+	rte_wmb();
+	queue_stats->acc_offload_cycles += rte_rdtsc_precise() - start_time;
+#endif
+}
+
+/* Read flag value 0/1/ from bitmap */
+static inline bool
+check_bit(uint32_t bitmap, uint32_t bitmask)
+{
+	return bitmap & bitmask;
+}
+
+/* Print an error if a descriptor error has occurred.
+ *  Return 0 on success, 1 on failure
+ */
+static inline int
+check_desc_error(uint32_t error_code) {
+	switch (error_code) {
+	case DESC_ERR_NO_ERR:
+		return 0;
+	case DESC_ERR_K_P_OUT_OF_RANGE:
+		rte_bbdev_log(ERR, "Encode block size K' is out of range");
+		break;
+	case DESC_ERR_Z_C_NOT_LEGAL:
+		rte_bbdev_log(ERR, "Zc is illegal");
+		break;
+	case DESC_ERR_DESC_OFFSET_ERR:
+		rte_bbdev_log(ERR,
+				"Queue offset does not meet the expectation in the FPGA"
+				);
+		break;
+	case DESC_ERR_DESC_READ_FAIL:
+		rte_bbdev_log(ERR, "Unsuccessful completion for descriptor read");
+		break;
+	case DESC_ERR_DESC_READ_TIMEOUT:
+		rte_bbdev_log(ERR, "Descriptor read time-out");
+		break;
+	case DESC_ERR_DESC_READ_TLP_POISONED:
+		rte_bbdev_log(ERR, "Descriptor read TLP poisoned");
+		break;
+	case DESC_ERR_CB_READ_FAIL:
+		rte_bbdev_log(ERR, "Unsuccessful completion for code block");
+		break;
+	case DESC_ERR_CB_READ_TIMEOUT:
+		rte_bbdev_log(ERR, "Code block read time-out");
+		break;
+	case DESC_ERR_CB_READ_TLP_POISONED:
+		rte_bbdev_log(ERR, "Code block read TLP poisoned");
+		break;
+	case DESC_ERR_HBSTORE_ERR:
+		rte_bbdev_log(ERR, "Hbstroe exceeds HARQ buffer size.");
+		break;
+	default:
+		rte_bbdev_log(ERR, "Descriptor error unknown error code %u",
+				error_code);
+		break;
+	}
+	return 1;
+}
+
+/* Compute value of k0.
+ * Based on 3GPP 38.212 Table 5.4.2.1-2
+ * Starting position of different redundancy versions, k0
+ */
+static inline uint16_t
+get_k0(uint16_t n_cb, uint16_t z_c, uint8_t basegraph, uint8_t rv_index)
+{
+	if (rv_index == 0)
+		return 0;
+	uint16_t n = (basegraph == 1 ? 66 : 50) * z_c;
+	if (n_cb == n) {
+		if (rv_index == 1)
+			return (basegraph == 1 ? 17 : 13) * z_c;
+		else if (rv_index == 2)
+			return (basegraph == 1 ? 33 : 25) * z_c;
+		else
+			return (basegraph == 1 ? 56 : 43) * z_c;
+	} else {
+		/* LBRM case - includes a division by N */
+		if (rv_index == 1)
+			return (((basegraph == 1 ? 17 : 13) * n_cb)
+					/ n) * z_c;
+		else if (rv_index == 2)
+			return (((basegraph == 1 ? 33 : 25) * n_cb)
+					/ n) * z_c;
+		else
+			return (((basegraph == 1 ? 56 : 43) * n_cb)
+					/ n) * z_c;
+	}
+}
+
+
+/**
+ * Set DMA descriptor for encode operation (1 Code Block)
+ *
+ * @param op
+ *   Pointer to a single encode operation.
+ * @param desc
+ *   Pointer to DMA descriptor.
+ * @param input
+ *   Pointer to pointer to input data which will be decoded.
+ * @param e
+ *   E value (length of output in bits).
+ * @param ncb
+ *   Ncb value (size of the soft buffer).
+ * @param out_length
+ *   Length of output buffer
+ * @param in_offset
+ *   Input offset in rte_mbuf structure. It is used for calculating the point
+ *   where data is starting.
+ * @param out_offset
+ *   Output offset in rte_mbuf structure. It is used for calculating the point
+ *   where hard output data will be stored.
+ * @param cbs_in_op
+ *   Number of CBs contained in one operation.
+ */
+static inline int
+fpga_dma_desc_te_fill(struct rte_bbdev_enc_op *op,
+		struct fpga_dma_enc_desc *desc, struct rte_mbuf *input,
+		struct rte_mbuf *output, uint16_t k_,  uint16_t e,
+		uint32_t in_offset, uint32_t out_offset, uint16_t desc_offset,
+		uint8_t cbs_in_op)
+{
+	/* reset */
+	desc->done = 0;
+	desc->error = 0;
+	desc->k_ = k_;
+	desc->rm_e = e;
+	desc->desc_idx = desc_offset;
+	desc->zc = op->ldpc_enc.z_c;
+	desc->bg_idx = op->ldpc_enc.basegraph - 1;
+	desc->qm_idx = op->ldpc_enc.q_m / 2;
+	desc->crc_en = check_bit(op->ldpc_enc.op_flags,
+			RTE_BBDEV_LDPC_CRC_24B_ATTACH);
+	desc->irq_en = 0;
+	desc->k0 = get_k0(op->ldpc_enc.n_cb, op->ldpc_enc.z_c,
+			op->ldpc_enc.basegraph, op->ldpc_enc.rv_index);
+	desc->ncb = op->ldpc_enc.n_cb;
+	desc->num_null = op->ldpc_enc.n_filler;
+	/* Set inbound data buffer address */
+	desc->in_addr_hi = (uint32_t)(
+			rte_pktmbuf_mtophys_offset(input, in_offset) >> 32);
+	desc->in_addr_lw = (uint32_t)(
+			rte_pktmbuf_mtophys_offset(input, in_offset));
+
+	desc->out_addr_hi = (uint32_t)(
+			rte_pktmbuf_mtophys_offset(output, out_offset) >> 32);
+	desc->out_addr_lw = (uint32_t)(
+			rte_pktmbuf_mtophys_offset(output, out_offset));
+	/* Save software context needed for dequeue */
+	desc->op_addr = op;
+	/* Set total number of CBs in an op */
+	desc->cbs_in_op = cbs_in_op;
+	return 0;
+}
+
+/**
+ * Set DMA descriptor for decode operation (1 Code Block)
+ *
+ * @param op
+ *   Pointer to a single encode operation.
+ * @param desc
+ *   Pointer to DMA descriptor.
+ * @param input
+ *   Pointer to pointer to input data which will be decoded.
+ * @param in_offset
+ *   Input offset in rte_mbuf structure. It is used for calculating the point
+ *   where data is starting.
+ * @param out_offset
+ *   Output offset in rte_mbuf structure. It is used for calculating the point
+ *   where hard output data will be stored.
+ * @param cbs_in_op
+ *   Number of CBs contained in one operation.
+ */
+static inline int
+fpga_dma_desc_ld_fill(struct rte_bbdev_dec_op *op,
+		struct fpga_dma_dec_desc *desc,
+		struct rte_mbuf *input,	struct rte_mbuf *output,
+		uint16_t harq_in_length,
+		uint32_t in_offset, uint32_t out_offset,
+		uint32_t harq_offset,
+		uint16_t desc_offset,
+		uint8_t cbs_in_op)
+{
+	/* reset */
+	desc->done = 0;
+	desc->error = 0;
+	/* Set inbound data buffer address */
+	desc->in_addr_hi = (uint32_t)(
+			rte_pktmbuf_mtophys_offset(input, in_offset) >> 32);
+	desc->in_addr_lw = (uint32_t)(
+			rte_pktmbuf_mtophys_offset(input, in_offset));
+	desc->rm_e = op->ldpc_dec.cb_params.e;
+	desc->harq_input_length = harq_in_length;
+	desc->et_dis = !check_bit(op->ldpc_dec.op_flags,
+			RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE);
+	desc->rv = op->ldpc_dec.rv_index;
+	desc->crc24b_ind = check_bit(op->ldpc_dec.op_flags,
+			RTE_BBDEV_LDPC_CRC_TYPE_24B_CHECK);
+	desc->drop_crc24b = check_bit(op->ldpc_dec.op_flags,
+			RTE_BBDEV_LDPC_CRC_TYPE_24B_DROP);
+	desc->desc_idx = desc_offset;
+	desc->ncb = op->ldpc_dec.n_cb;
+	desc->num_null = op->ldpc_dec.n_filler;
+	desc->hbstroe_offset = harq_offset >> 10;
+	desc->zc = op->ldpc_dec.z_c;
+	desc->harqin_en = check_bit(op->ldpc_dec.op_flags,
+			RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE);
+	desc->bg_idx = op->ldpc_dec.basegraph - 1;
+	desc->max_iter = op->ldpc_dec.iter_max;
+	desc->qm_idx = op->ldpc_dec.q_m / 2;
+	desc->out_addr_hi = (uint32_t)(
+			rte_pktmbuf_mtophys_offset(output, out_offset) >> 32);
+	desc->out_addr_lw = (uint32_t)(
+			rte_pktmbuf_mtophys_offset(output, out_offset));
+	/* Save software context needed for dequeue */
+	desc->op_addr = op;
+	/* Set total number of CBs in an op */
+	desc->cbs_in_op = cbs_in_op;
+
+	return 0;
+}
+
+#ifdef RTE_LIBRTE_BBDEV_DEBUG
+/* Validates LDPC encoder parameters */
+static int
+validate_enc_op(struct rte_bbdev_enc_op *op __rte_unused)
+{
+	struct rte_bbdev_op_ldpc_enc *ldpc_enc = &op->ldpc_enc;
+	struct rte_bbdev_op_enc_ldpc_cb_params *cb = NULL;
+	struct rte_bbdev_op_enc_ldpc_tb_params *tb = NULL;
+
+
+	if (ldpc_enc->input.length >
+			RTE_BBDEV_LDPC_MAX_CB_SIZE >> 3) {
+		rte_bbdev_log(ERR, "CB size (%u) is too big, max: %d",
+				ldpc_enc->input.length,
+				RTE_BBDEV_LDPC_MAX_CB_SIZE);
+		return -1;
+	}
+
+	if (op->mempool == NULL) {
+		rte_bbdev_log(ERR, "Invalid mempool pointer");
+		return -1;
+	}
+	if (ldpc_enc->input.data == NULL) {
+		rte_bbdev_log(ERR, "Invalid input pointer");
+		return -1;
+	}
+	if (ldpc_enc->output.data == NULL) {
+		rte_bbdev_log(ERR, "Invalid output pointer");
+		return -1;
+	}
+	if ((ldpc_enc->basegraph > 2) || (ldpc_enc->basegraph == 0)) {
+		rte_bbdev_log(ERR,
+				"basegraph (%u) is out of range 1 <= value <= 2",
+				ldpc_enc->basegraph);
+		return -1;
+	}
+	if (ldpc_enc->code_block_mode > 1) {
+		rte_bbdev_log(ERR,
+				"code_block_mode (%u) is out of range 0:Tb 1:CB",
+				ldpc_enc->code_block_mode);
+		return -1;
+	}
+
+	if (ldpc_enc->code_block_mode == 0) {
+		tb = &ldpc_enc->tb_params;
+		if (tb->c == 0) {
+			rte_bbdev_log(ERR,
+					"c (%u) is out of range 1 <= value <= %u",
+					tb->c, RTE_BBDEV_LDPC_MAX_CODE_BLOCKS);
+			return -1;
+		}
+		if (tb->cab > tb->c) {
+			rte_bbdev_log(ERR,
+					"cab (%u) is greater than c (%u)",
+					tb->cab, tb->c);
+			return -1;
+		}
+		if ((tb->ea < RTE_BBDEV_LDPC_MIN_CB_SIZE)
+				&& tb->r < tb->cab) {
+			rte_bbdev_log(ERR,
+					"ea (%u) is less than %u or it is not even",
+					tb->ea, RTE_BBDEV_LDPC_MIN_CB_SIZE);
+			return -1;
+		}
+		if ((tb->eb < RTE_BBDEV_LDPC_MIN_CB_SIZE)
+				&& tb->c > tb->cab) {
+			rte_bbdev_log(ERR,
+					"eb (%u) is less than %u",
+					tb->eb, RTE_BBDEV_LDPC_MIN_CB_SIZE);
+			return -1;
+		}
+		if (tb->r > (tb->c - 1)) {
+			rte_bbdev_log(ERR,
+					"r (%u) is greater than c - 1 (%u)",
+					tb->r, tb->c - 1);
+			return -1;
+		}
+	} else {
+		cb = &ldpc_enc->cb_params;
+		if (cb->e < RTE_BBDEV_LDPC_MIN_CB_SIZE) {
+			rte_bbdev_log(ERR,
+					"e (%u) is less than %u or it is not even",
+					cb->e, RTE_BBDEV_LDPC_MIN_CB_SIZE);
+			return -1;
+		}
+	}
+	return 0;
+}
+#endif
+
+static inline char *
+mbuf_append(struct rte_mbuf *m_head, struct rte_mbuf *m, uint16_t len)
+{
+	if (unlikely(len > rte_pktmbuf_tailroom(m)))
+		return NULL;
+
+	char *tail = (char *)m->buf_addr + m->data_off + m->data_len;
+	m->data_len = (uint16_t)(m->data_len + len);
+	m_head->pkt_len  = (m_head->pkt_len + len);
+	return tail;
+}
+
+#ifdef RTE_LIBRTE_BBDEV_DEBUG
+/* Validates LDPC decoder parameters */
+static int
+validate_dec_op(struct rte_bbdev_dec_op *op __rte_unused)
+{
+	struct rte_bbdev_op_ldpc_dec *ldpc_dec = &op->ldpc_dec;
+	struct rte_bbdev_op_dec_ldpc_cb_params *cb = NULL;
+	struct rte_bbdev_op_dec_ldpc_tb_params *tb = NULL;
+
+	if (op->mempool == NULL) {
+		rte_bbdev_log(ERR, "Invalid mempool pointer");
+		return -1;
+	}
+	if (ldpc_dec->rv_index > 3) {
+		rte_bbdev_log(ERR,
+				"rv_index (%u) is out of range 0 <= value <= 3",
+				ldpc_dec->rv_index);
+		return -1;
+	}
+
+	if (ldpc_dec->iter_max == 0) {
+		rte_bbdev_log(ERR,
+				"iter_max (%u) is equal to 0",
+				ldpc_dec->iter_max);
+		return -1;
+	}
+
+	if (ldpc_dec->code_block_mode > 1) {
+		rte_bbdev_log(ERR,
+				"code_block_mode (%u) is out of range 0 <= value <= 1",
+				ldpc_dec->code_block_mode);
+		return -1;
+	}
+
+	if (ldpc_dec->code_block_mode == 0) {
+		tb = &ldpc_dec->tb_params;
+		if (tb->c < 1) {
+			rte_bbdev_log(ERR,
+					"c (%u) is out of range 1 <= value <= %u",
+					tb->c, RTE_BBDEV_LDPC_MAX_CODE_BLOCKS);
+			return -1;
+		}
+		if (tb->cab > tb->c) {
+			rte_bbdev_log(ERR,
+					"cab (%u) is greater than c (%u)",
+					tb->cab, tb->c);
+			return -1;
+		}
+	} else {
+		cb = &ldpc_dec->cb_params;
+		if (cb->e < RTE_BBDEV_LDPC_MIN_CB_SIZE) {
+			rte_bbdev_log(ERR,
+					"e (%u) is out of range %u <= value <= %u",
+					cb->e, RTE_BBDEV_LDPC_MIN_CB_SIZE,
+					RTE_BBDEV_LDPC_MAX_CB_SIZE);
+			return -1;
+		}
+	}
+
+	return 0;
+}
+#endif
+
+static inline int
+fpga_harq_write_loopback(struct fpga_5gnr_fec_device *fpga_dev,
+		struct rte_mbuf *harq_input, uint16_t harq_in_length,
+		uint32_t harq_in_offset, uint32_t harq_out_offset)
+{
+	uint32_t out_offset = harq_out_offset;
+	uint32_t in_offset = harq_in_offset;
+	uint32_t left_length = harq_in_length;
+	uint32_t reg_32, increment = 0;
+	uint64_t *input = NULL;
+	uint32_t last_transaction = left_length
+			% FPGA_5GNR_FEC_DDR_WR_DATA_LEN_IN_BYTES;
+	uint64_t last_word;
+
+	if (last_transaction > 0)
+		left_length -= last_transaction;
+
+	/*
+	 * Get HARQ buffer size for each VF/PF: When 0x00, there is no
+	 * available DDR space for the corresponding VF/PF.
+	 */
+	reg_32 = fpga_reg_read_32(fpga_dev->mmio_base,
+			FPGA_5GNR_FEC_HARQ_BUF_SIZE_REGS);
+	if (reg_32 < harq_in_length) {
+		left_length = reg_32;
+		rte_bbdev_log(ERR, "HARQ in length > HARQ buffer size\n");
+	}
+
+	input = (uint64_t *)rte_pktmbuf_mtod_offset(harq_input,
+			uint8_t *, in_offset);
+
+	while (left_length > 0) {
+		if (fpga_reg_read_8(fpga_dev->mmio_base,
+				FPGA_5GNR_FEC_DDR4_ADDR_RDY_REGS) ==  1) {
+			fpga_reg_write_32(fpga_dev->mmio_base,
+					FPGA_5GNR_FEC_DDR4_WR_ADDR_REGS,
+					out_offset);
+			fpga_reg_write_64(fpga_dev->mmio_base,
+					FPGA_5GNR_FEC_DDR4_WR_DATA_REGS,
+					input[increment]);
+			left_length -= FPGA_5GNR_FEC_DDR_WR_DATA_LEN_IN_BYTES;
+			out_offset += FPGA_5GNR_FEC_DDR_WR_DATA_LEN_IN_BYTES;
+			increment++;
+			fpga_reg_write_8(fpga_dev->mmio_base,
+					FPGA_5GNR_FEC_DDR4_WR_DONE_REGS, 1);
+		}
+	}
+	while (last_transaction > 0) {
+		if (fpga_reg_read_8(fpga_dev->mmio_base,
+				FPGA_5GNR_FEC_DDR4_ADDR_RDY_REGS) ==  1) {
+			fpga_reg_write_32(fpga_dev->mmio_base,
+					FPGA_5GNR_FEC_DDR4_WR_ADDR_REGS,
+					out_offset);
+			last_word = input[increment];
+			last_word &= (uint64_t)(1 << (last_transaction * 4))
+					- 1;
+			fpga_reg_write_64(fpga_dev->mmio_base,
+					FPGA_5GNR_FEC_DDR4_WR_DATA_REGS,
+					last_word);
+			fpga_reg_write_8(fpga_dev->mmio_base,
+					FPGA_5GNR_FEC_DDR4_WR_DONE_REGS, 1);
+			last_transaction = 0;
+		}
+	}
+	return 1;
+}
+
+static inline int
+fpga_harq_read_loopback(struct fpga_5gnr_fec_device *fpga_dev,
+		struct rte_mbuf *harq_output, uint16_t harq_in_length,
+		uint32_t harq_in_offset, uint32_t harq_out_offset)
+{
+	uint32_t left_length, in_offset = harq_in_offset;
+	uint64_t reg;
+	uint32_t increment = 0;
+	uint64_t *input = NULL;
+	uint32_t last_transaction = harq_in_length
+			% FPGA_5GNR_FEC_DDR_WR_DATA_LEN_IN_BYTES;
+
+	if (last_transaction > 0)
+		harq_in_length += (8 - last_transaction);
+
+	reg = fpga_reg_read_32(fpga_dev->mmio_base,
+			FPGA_5GNR_FEC_HARQ_BUF_SIZE_REGS);
+	if (reg < harq_in_length) {
+		harq_in_length = reg;
+		rte_bbdev_log(ERR, "HARQ in length > HARQ buffer size\n");
+	}
+
+	if (!mbuf_append(harq_output, harq_output, harq_in_length)) {
+		rte_bbdev_log(ERR, "HARQ output buffer warning %d %d\n",
+				harq_output->buf_len -
+				rte_pktmbuf_headroom(harq_output),
+				harq_in_length);
+		harq_in_length = harq_output->buf_len -
+				rte_pktmbuf_headroom(harq_output);
+		if (!mbuf_append(harq_output, harq_output, harq_in_length)) {
+			rte_bbdev_log(ERR, "HARQ output buffer issue %d %d\n",
+					harq_output->buf_len, harq_in_length);
+			return -1;
+		}
+	}
+	left_length = harq_in_length;
+
+	input = (uint64_t *)rte_pktmbuf_mtod_offset(harq_output,
+			uint8_t *, harq_out_offset);
+
+	while (left_length > 0) {
+		fpga_reg_write_32(fpga_dev->mmio_base,
+			FPGA_5GNR_FEC_DDR4_RD_ADDR_REGS, in_offset);
+		fpga_reg_write_8(fpga_dev->mmio_base,
+				FPGA_5GNR_FEC_DDR4_RD_DONE_REGS, 1);
+		reg = fpga_reg_read_8(fpga_dev->mmio_base,
+			FPGA_5GNR_FEC_DDR4_RD_RDY_REGS);
+		while (reg != 1) {
+			reg = fpga_reg_read_8(fpga_dev->mmio_base,
+				FPGA_5GNR_FEC_DDR4_RD_RDY_REGS);
+			if (reg == FPGA_DDR_OVERFLOW) {
+				rte_bbdev_log(ERR,
+						"Read address is overflow!\n");
+				return -1;
+			}
+		}
+		input[increment] = fpga_reg_read_64(fpga_dev->mmio_base,
+			FPGA_5GNR_FEC_DDR4_RD_DATA_REGS);
+		left_length -= FPGA_5GNR_FEC_DDR_RD_DATA_LEN_IN_BYTES;
+		in_offset += FPGA_5GNR_FEC_DDR_WR_DATA_LEN_IN_BYTES;
+		increment++;
+		fpga_reg_write_8(fpga_dev->mmio_base,
+				FPGA_5GNR_FEC_DDR4_RD_DONE_REGS, 0);
+	}
+	return 1;
+}
+
+static inline int
+enqueue_ldpc_enc_one_op_cb(struct fpga_queue *q, struct rte_bbdev_enc_op *op,
+		uint16_t desc_offset)
+{
+	union fpga_dma_desc *desc;
+	int ret;
+	uint8_t c, crc24_bits = 0;
+	struct rte_bbdev_op_ldpc_enc *enc = &op->ldpc_enc;
+	uint16_t in_offset = enc->input.offset;
+	uint16_t out_offset = enc->output.offset;
+	struct rte_mbuf *m_in = enc->input.data;
+	struct rte_mbuf *m_out = enc->output.data;
+	struct rte_mbuf *m_out_head = enc->output.data;
+	uint32_t in_length, out_length, e;
+	uint16_t total_left = enc->input.length;
+	uint16_t ring_offset;
+	uint16_t K, k_;
+
+#ifdef RTE_LIBRTE_BBDEV_DEBUG
+	/* Validate op structure */
+	/* FIXME */
+	if (validate_enc_op(op) == -1) {
+		rte_bbdev_log(ERR, "LDPC encoder validation failed");
+		return -EINVAL;
+	}
+#endif
+
+	/* Clear op status */
+	op->status = 0;
+
+	if (m_in == NULL || m_out == NULL) {
+		rte_bbdev_log(ERR, "Invalid mbuf pointer");
+		op->status = 1 << RTE_BBDEV_DATA_ERROR;
+		return -EINVAL;
+	}
+
+	if (enc->op_flags & RTE_BBDEV_LDPC_CRC_24B_ATTACH)
+		crc24_bits = 24;
+
+	if (enc->code_block_mode == 0) {
+		/* For Transport Block mode */
+		/* FIXME */
+		c = enc->tb_params.c;
+		e = enc->tb_params.ea;
+	} else { /* For Code Block mode */
+		c = 1;
+		e = enc->cb_params.e;
+	}
+
+	/* Update total_left */
+	K = (enc->basegraph == 1 ? 22 : 10) * enc->z_c;
+	k_ = K - enc->n_filler;
+	in_length = (k_ - crc24_bits) >> 3;
+	out_length = (e + 7) >> 3;
+
+	total_left = rte_pktmbuf_data_len(m_in) - in_offset;
+
+	/* Update offsets */
+	if (total_left != in_length) {
+		op->status |= 1 << RTE_BBDEV_DATA_ERROR;
+		rte_bbdev_log(ERR,
+				"Mismatch between mbuf length and included CBs sizes %d",
+				total_left);
+	}
+
+	mbuf_append(m_out_head, m_out, out_length);
+
+	/* Offset into the ring */
+	ring_offset = ((q->tail + desc_offset) & q->sw_ring_wrap_mask);
+	/* Setup DMA Descriptor */
+	desc = q->ring_addr + ring_offset;
+
+	ret = fpga_dma_desc_te_fill(op, &desc->enc_req, m_in, m_out,
+			k_, e, in_offset, out_offset, ring_offset, c);
+	if (unlikely(ret < 0))
+		return ret;
+
+	/* Update lengths */
+	total_left -= in_length;
+	op->ldpc_enc.output.length += out_length;
+
+	if (total_left > 0) {
+		rte_bbdev_log(ERR,
+			"Mismatch between mbuf length and included CB sizes: mbuf len %u, cb len %u",
+				total_left, in_length);
+		return -1;
+	}
+
+#ifdef RTE_LIBRTE_BBDEV_DEBUG
+	print_dma_enc_desc_debug_info(desc);
+#endif
+	return 1;
+}
+
+static inline int
+enqueue_ldpc_dec_one_op_cb(struct fpga_queue *q, struct rte_bbdev_dec_op *op,
+		uint16_t desc_offset)
+{
+	union fpga_dma_desc *desc;
+	int ret;
+	uint16_t ring_offset;
+	uint8_t c;
+	uint16_t e, in_length, out_length, k0, l, seg_total_left, sys_cols;
+	uint16_t K, parity_offset, harq_in_length = 0, harq_out_length = 0;
+	uint16_t crc24_overlap = 0;
+	struct rte_bbdev_op_ldpc_dec *dec = &op->ldpc_dec;
+	struct rte_mbuf *m_in = dec->input.data;
+	struct rte_mbuf *m_out = dec->hard_output.data;
+	struct rte_mbuf *m_out_head = dec->hard_output.data;
+	uint16_t in_offset = dec->input.offset;
+	uint16_t out_offset = dec->hard_output.offset;
+	uint32_t harq_offset = 0;
+
+#ifdef RTE_LIBRTE_BBDEV_DEBUG
+		/* Validate op structure */
+		if (validate_dec_op(op) == -1) {
+			rte_bbdev_log(ERR, "LDPC decoder validation failed");
+			return -EINVAL;
+		}
+#endif
+
+	/* Clear op status */
+	op->status = 0;
+
+	/* Setup DMA Descriptor */
+	ring_offset = ((q->tail + desc_offset) & q->sw_ring_wrap_mask);
+	desc = q->ring_addr + ring_offset;
+
+	if (check_bit(dec->op_flags,
+			RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK)) {
+		struct rte_mbuf *harq_in = dec->harq_combined_input.data;
+		struct rte_mbuf *harq_out = dec->harq_combined_output.data;
+		harq_in_length = dec->harq_combined_input.length;
+		uint32_t harq_in_offset = dec->harq_combined_input.offset;
+		uint32_t harq_out_offset = dec->harq_combined_output.offset;
+
+		if (check_bit(dec->op_flags,
+				RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_OUT_ENABLE
+				)) {
+			ret = fpga_harq_write_loopback(q->d, harq_in,
+					harq_in_length, harq_in_offset,
+					harq_out_offset);
+		} else if (check_bit(dec->op_flags,
+				RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_IN_ENABLE
+				)) {
+			ret = fpga_harq_read_loopback(q->d, harq_out,
+				harq_in_length, harq_in_offset,
+				harq_out_offset);
+			dec->harq_combined_output.length = harq_in_length;
+		} else {
+			rte_bbdev_log(ERR, "OP flag Err!");
+			ret = -1;
+		}
+		/* Set descriptor for dequeue */
+		desc->dec_req.done = 1;
+		desc->dec_req.error = 0;
+		desc->dec_req.op_addr = op;
+		desc->dec_req.cbs_in_op = 1;
+		/* Mark this dummy descriptor to be dropped by HW */
+		desc->dec_req.desc_idx = (ring_offset + 1)
+				& q->sw_ring_wrap_mask;
+		return ret; /* Error or number of CB */
+	}
+
+	if (m_in == NULL || m_out == NULL) {
+		rte_bbdev_log(ERR, "Invalid mbuf pointer");
+		op->status = 1 << RTE_BBDEV_DATA_ERROR;
+		return -1;
+	}
+
+	c = 1;
+	e = dec->cb_params.e;
+
+	if (check_bit(dec->op_flags, RTE_BBDEV_LDPC_CRC_TYPE_24B_DROP))
+		crc24_overlap = 24;
+
+	sys_cols = (dec->basegraph == 1) ? 22 : 10;
+	K = sys_cols * dec->z_c;
+	parity_offset = K - 2 * dec->z_c;
+
+	out_length = ((K - crc24_overlap - dec->n_filler) >> 3);
+	in_length = e;
+	seg_total_left = dec->input.length;
+
+	if (check_bit(dec->op_flags, RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE)) {
+		harq_in_length = RTE_MIN(dec->harq_combined_input.length,
+				(uint32_t)dec->n_cb);
+	}
+
+	if (check_bit(dec->op_flags, RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE)) {
+		k0 = get_k0(dec->n_cb, dec->z_c,
+				dec->basegraph, dec->rv_index);
+		if (k0 > parity_offset)
+			l = k0 + e;
+		else
+			l = k0 + e + dec->n_filler;
+		harq_out_length = RTE_MIN(RTE_MAX(harq_in_length, l),
+				dec->n_cb - dec->n_filler);
+		dec->harq_combined_output.length = harq_out_length;
+	}
+
+	mbuf_append(m_out_head, m_out, out_length);
+	if (check_bit(dec->op_flags, RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE))
+		harq_offset = dec->harq_combined_input.offset;
+	else if (check_bit(dec->op_flags, RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE))
+		harq_offset = dec->harq_combined_output.offset;
+
+	if ((harq_offset & 0x3FF) > 0) {
+		rte_bbdev_log(ERR, "Invalid HARQ offset %d", harq_offset);
+		op->status = 1 << RTE_BBDEV_DATA_ERROR;
+		return -1;
+	}
+
+	ret = fpga_dma_desc_ld_fill(op, &desc->dec_req, m_in, m_out,
+		harq_in_length, in_offset, out_offset, harq_offset,
+		ring_offset, c);
+	if (unlikely(ret < 0))
+		return ret;
+	/* Update lengths */
+	seg_total_left -= in_length;
+	op->ldpc_dec.hard_output.length += out_length;
+	if (seg_total_left > 0) {
+		rte_bbdev_log(ERR,
+				"Mismatch between mbuf length and included CB sizes: mbuf len %u, cb len %u",
+				seg_total_left, in_length);
+		return -1;
+	}
+
+#ifdef RTE_LIBRTE_BBDEV_DEBUG
+	print_dma_dec_desc_debug_info(desc);
+#endif
+
+	return 1;
+}
+
+static uint16_t
+fpga_enqueue_ldpc_enc(struct rte_bbdev_queue_data *q_data,
+		struct rte_bbdev_enc_op **ops, uint16_t num)
+{
+	uint16_t i, total_enqueued_cbs = 0;
+	int32_t avail;
+	int enqueued_cbs;
+	struct fpga_queue *q = q_data->queue_private;
+	union fpga_dma_desc *desc;
+
+	/* Check if queue is not full */
+	if (unlikely(((q->tail + 1) & q->sw_ring_wrap_mask) ==
+			q->head_free_desc))
+		return 0;
+
+	/* Calculates available space */
+	avail = (q->head_free_desc > q->tail) ?
+		q->head_free_desc - q->tail - 1 :
+		q->ring_ctrl_reg.ring_size + q->head_free_desc - q->tail - 1;
+
+	for (i = 0; i < num; ++i) {
+
+		/* Check if there is available space for further
+		 * processing
+		 */
+		if (unlikely(avail - 1 < 0))
+			break;
+		avail -= 1;
+		enqueued_cbs = enqueue_ldpc_enc_one_op_cb(q, ops[i],
+				total_enqueued_cbs);
+
+		if (enqueued_cbs < 0)
+			break;
+
+		total_enqueued_cbs += enqueued_cbs;
+
+		rte_bbdev_log_debug("enqueuing enc ops [%d/%d] | head %d | tail %d",
+				total_enqueued_cbs, num,
+				q->head_free_desc, q->tail);
+	}
+
+	/* Set interrupt bit for last CB in enqueued ops. FPGA issues interrupt
+	 * only when all previous CBs were already processed.
+	 */
+	desc = q->ring_addr + ((q->tail + total_enqueued_cbs - 1)
+			& q->sw_ring_wrap_mask);
+	desc->enc_req.irq_en = q->irq_enable;
+
+	fpga_dma_enqueue(q, total_enqueued_cbs, &q_data->queue_stats);
+
+	/* Update stats */
+	q_data->queue_stats.enqueued_count += i;
+	q_data->queue_stats.enqueue_err_count += num - i;
+
+	return i;
+}
+
+static uint16_t
+fpga_enqueue_ldpc_dec(struct rte_bbdev_queue_data *q_data,
+		struct rte_bbdev_dec_op **ops, uint16_t num)
+{
+	uint16_t i, total_enqueued_cbs = 0;
+	int32_t avail;
+	int enqueued_cbs;
+	struct fpga_queue *q = q_data->queue_private;
+	union fpga_dma_desc *desc;
+
+	/* Check if queue is not full */
+	if (unlikely(((q->tail + 1) & q->sw_ring_wrap_mask) ==
+			q->head_free_desc))
+		return 0;
+
+	/* Calculates available space */
+	avail = (q->head_free_desc > q->tail) ?
+		q->head_free_desc - q->tail - 1 :
+		q->ring_ctrl_reg.ring_size + q->head_free_desc - q->tail - 1;
+
+	for (i = 0; i < num; ++i) {
+
+		/* Check if there is available space for further
+		 * processing
+		 */
+		if (unlikely(avail - 1 < 0))
+			break;
+		avail -= 1;
+		enqueued_cbs = enqueue_ldpc_dec_one_op_cb(q, ops[i],
+				total_enqueued_cbs);
+
+		if (enqueued_cbs < 0)
+			break;
+
+		total_enqueued_cbs += enqueued_cbs;
+
+		rte_bbdev_log_debug("enqueuing dec ops [%d/%d] | head %d | tail %d",
+				total_enqueued_cbs, num,
+				q->head_free_desc, q->tail);
+	}
+
+	/* Update stats */
+	q_data->queue_stats.enqueued_count += i;
+	q_data->queue_stats.enqueue_err_count += num - i;
+
+	/* Set interrupt bit for last CB in enqueued ops. FPGA issues interrupt
+	 * only when all previous CBs were already processed.
+	 */
+	desc = q->ring_addr + ((q->tail + total_enqueued_cbs - 1)
+			& q->sw_ring_wrap_mask);
+	desc->enc_req.irq_en = q->irq_enable;
+	fpga_dma_enqueue(q, total_enqueued_cbs, &q_data->queue_stats);
+	return i;
+}
+
+
+static inline int
+dequeue_ldpc_enc_one_op_cb(struct fpga_queue *q, struct rte_bbdev_enc_op **op,
+		uint16_t desc_offset)
+{
+	union fpga_dma_desc *desc;
+	int desc_error = 0;
+
+	/* Set current desc */
+	desc = q->ring_addr + ((q->head_free_desc + desc_offset)
+			& q->sw_ring_wrap_mask);
+
+	/*check if done */
+	if (desc->enc_req.done == 0)
+		return -1;
+
+	/* make sure the response is read atomically */
+	rte_smp_rmb();
+
+	rte_bbdev_log_debug("DMA response desc %p", desc);
+
+#ifdef RTE_LIBRTE_BBDEV_DEBUG
+	print_dma_enc_desc_debug_info(desc);
+#endif
+
+	*op = desc->enc_req.op_addr;
+	/* Check the descriptor error field, return 1 on error */
+	desc_error = check_desc_error(desc->enc_req.error);
+	(*op)->status = desc_error << RTE_BBDEV_DATA_ERROR;
+
+	return 1;
+}
+
+
+static inline int
+dequeue_ldpc_dec_one_op_cb(struct fpga_queue *q, struct rte_bbdev_dec_op **op,
+		uint16_t desc_offset)
+{
+	union fpga_dma_desc *desc;
+	int desc_error = 0;
+	/* Set descriptor */
+	desc = q->ring_addr + ((q->head_free_desc + desc_offset)
+			& q->sw_ring_wrap_mask);
+
+	/* Verify done bit is set */
+	if (desc->dec_req.done == 0)
+		return -1;
+
+	/* make sure the response is read atomically */
+	rte_smp_rmb();
+
+#ifdef RTE_LIBRTE_BBDEV_DEBUG
+	print_dma_dec_desc_debug_info(desc);
+#endif
+
+	*op = desc->dec_req.op_addr;
+
+	if (check_bit((*op)->ldpc_dec.op_flags,
+			RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK)) {
+		(*op)->status = 0;
+		return 1;
+	}
+
+	/* FPGA reports iterations based on round-up minus 1 */
+	(*op)->ldpc_dec.iter_count = desc->dec_req.iter + 1;
+	/* CRC Check criteria */
+	if (desc->dec_req.crc24b_ind && !(desc->dec_req.crcb_pass))
+		(*op)->status = 1 << RTE_BBDEV_CRC_ERROR;
+	/* et_pass = 0 when decoder fails */
+	(*op)->status |= !(desc->dec_req.et_pass) << RTE_BBDEV_SYNDROME_ERROR;
+	/* Check the descriptor error field, return 1 on error */
+	desc_error = check_desc_error(desc->dec_req.error);
+	(*op)->status |= desc_error << RTE_BBDEV_DATA_ERROR;
+	return 1;
+}
+
+static uint16_t
+fpga_dequeue_ldpc_enc(struct rte_bbdev_queue_data *q_data,
+		struct rte_bbdev_enc_op **ops, uint16_t num)
+{
+	struct fpga_queue *q = q_data->queue_private;
+	uint32_t avail = (q->tail - q->head_free_desc) & q->sw_ring_wrap_mask;
+	uint16_t i;
+	uint16_t dequeued_cbs = 0;
+	int ret;
+
+	for (i = 0; (i < num) && (dequeued_cbs < avail); ++i) {
+		ret = dequeue_ldpc_enc_one_op_cb(q, &ops[i], dequeued_cbs);
+
+		if (ret < 0)
+			break;
+
+		dequeued_cbs += ret;
+
+		rte_bbdev_log_debug("dequeuing enc ops [%d/%d] | head %d | tail %d",
+				dequeued_cbs, num, q->head_free_desc, q->tail);
+	}
+
+	/* Update head */
+	q->head_free_desc = (q->head_free_desc + dequeued_cbs) &
+			q->sw_ring_wrap_mask;
+
+	/* Update stats */
+	q_data->queue_stats.dequeued_count += i;
+
+	return i;
+}
+
+static uint16_t
+fpga_dequeue_ldpc_dec(struct rte_bbdev_queue_data *q_data,
+		struct rte_bbdev_dec_op **ops, uint16_t num)
+{
+	struct fpga_queue *q = q_data->queue_private;
+	uint32_t avail = (q->tail - q->head_free_desc) & q->sw_ring_wrap_mask;
+	uint16_t i;
+	uint16_t dequeued_cbs = 0;
+	int ret;
+
+	for (i = 0; (i < num) && (dequeued_cbs < avail); ++i) {
+		ret = dequeue_ldpc_dec_one_op_cb(q, &ops[i], dequeued_cbs);
+
+		if (ret < 0)
+			break;
+
+		dequeued_cbs += ret;
+
+		rte_bbdev_log_debug("dequeuing dec ops [%d/%d] | head %d | tail %d",
+				dequeued_cbs, num, q->head_free_desc, q->tail);
+	}
+
+	/* Update head */
+	q->head_free_desc = (q->head_free_desc + dequeued_cbs) &
+			q->sw_ring_wrap_mask;
+
+	/* Update stats */
+	q_data->queue_stats.dequeued_count += i;
+
+	return i;
+}
+
+
+/* Initialization Function */
+static void
+fpga_5gnr_fec_init(struct rte_bbdev *dev, struct rte_pci_driver *drv)
+{
+	struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
+
+	dev->dev_ops = &fpga_ops;
+	dev->enqueue_ldpc_enc_ops = fpga_enqueue_ldpc_enc;
+	dev->enqueue_ldpc_dec_ops = fpga_enqueue_ldpc_dec;
+	dev->dequeue_ldpc_enc_ops = fpga_dequeue_ldpc_enc;
+	dev->dequeue_ldpc_dec_ops = fpga_dequeue_ldpc_dec;
+
+	((struct fpga_5gnr_fec_device *) dev->data->dev_private)->pf_device =
+			!strcmp(drv->driver.name,
+					RTE_STR(FPGA_5GNR_FEC_PF_DRIVER_NAME));
+	((struct fpga_5gnr_fec_device *) dev->data->dev_private)->mmio_base =
+			pci_dev->mem_resource[0].addr;
+
+	rte_bbdev_log_debug(
+			"Init device %s [%s] @ virtaddr %p phyaddr %#"PRIx64,
+			dev->device->driver->name, dev->data->name,
+			(void *)pci_dev->mem_resource[0].addr,
+			pci_dev->mem_resource[0].phys_addr);
+}
+
+static int
+fpga_5gnr_fec_probe(struct rte_pci_driver *pci_drv,
+	struct rte_pci_device *pci_dev)
+{
+	struct rte_bbdev *bbdev = NULL;
+	char dev_name[RTE_BBDEV_NAME_MAX_LEN];
+
+	if (pci_dev == NULL) {
+		rte_bbdev_log(ERR, "NULL PCI device");
+		return -EINVAL;
+	}
+
+	rte_pci_device_name(&pci_dev->addr, dev_name, sizeof(dev_name));
+
+	/* Allocate memory to be used privately by drivers */
+	bbdev = rte_bbdev_allocate(pci_dev->device.name);
+	if (bbdev == NULL)
+		return -ENODEV;
+
+	/* allocate device private memory */
+	bbdev->data->dev_private = rte_zmalloc_socket(dev_name,
+			sizeof(struct fpga_5gnr_fec_device),
+			RTE_CACHE_LINE_SIZE,
+			pci_dev->device.numa_node);
+
+	if (bbdev->data->dev_private == NULL) {
+		rte_bbdev_log(CRIT,
+				"Allocate of %zu bytes for device \"%s\" failed",
+				sizeof(struct fpga_5gnr_fec_device), dev_name);
+				rte_bbdev_release(bbdev);
+			return -ENOMEM;
+	}
+
+	/* Fill HW specific part of device structure */
+	bbdev->device = &pci_dev->device;
+	bbdev->intr_handle = &pci_dev->intr_handle;
+	bbdev->data->socket_id = pci_dev->device.numa_node;
+
+	/* Invoke FEC FPGA device initialization function */
+	fpga_5gnr_fec_init(bbdev, pci_drv);
+
+	rte_bbdev_log_debug("bbdev id = %u [%s]",
+			bbdev->data->dev_id, dev_name);
+
+	struct fpga_5gnr_fec_device *d = bbdev->data->dev_private;
+	uint32_t version_id = fpga_reg_read_32(d->mmio_base,
+			FPGA_5GNR_FEC_VERSION_ID);
+	rte_bbdev_log(INFO, "FEC FPGA RTL v%u.%u",
+		((uint16_t)(version_id >> 16)), ((uint16_t)version_id));
+
+#ifdef RTE_LIBRTE_BBDEV_DEBUG
+	if (!strcmp(bbdev->device->driver->name,
+			RTE_STR(FPGA_5GNR_FEC_PF_DRIVER_NAME)))
+		print_static_reg_debug_info(d->mmio_base);
+#endif
+	return 0;
+}
+
+static int
+fpga_5gnr_fec_remove(struct rte_pci_device *pci_dev)
+{
+	struct rte_bbdev *bbdev;
+	int ret;
+	uint8_t dev_id;
+
+	if (pci_dev == NULL)
+		return -EINVAL;
+
+	/* Find device */
+	bbdev = rte_bbdev_get_named_dev(pci_dev->device.name);
+	if (bbdev == NULL) {
+		rte_bbdev_log(CRIT,
+				"Couldn't find HW dev \"%s\" to uninitialise it",
+				pci_dev->device.name);
+		return -ENODEV;
+	}
+	dev_id = bbdev->data->dev_id;
+
+	/* free device private memory before close */
+	rte_free(bbdev->data->dev_private);
+
+	/* Close device */
+	ret = rte_bbdev_close(dev_id);
+	if (ret < 0)
+		rte_bbdev_log(ERR,
+				"Device %i failed to close during uninit: %i",
+				dev_id, ret);
+
+	/* release bbdev from library */
+	ret = rte_bbdev_release(bbdev);
+	if (ret)
+		rte_bbdev_log(ERR, "Device %i failed to uninit: %i", dev_id,
+				ret);
+
+	rte_bbdev_log_debug("Destroyed bbdev = %u", dev_id);
+
+	return 0;
+}
+
+static inline void
+set_default_fpga_conf(struct fpga_5gnr_fec_conf *def_conf)
+{
+	/* clear default configuration before initialization */
+	memset(def_conf, 0, sizeof(struct fpga_5gnr_fec_conf));
+	/* Set pf mode to true */
+	def_conf->pf_mode_en = true;
+
+	/* Set ratio between UL and DL to 1:1 (unit of weight is 3 CBs) */
+	def_conf->ul_bandwidth = 3;
+	def_conf->dl_bandwidth = 3;
+
+	/* Set Load Balance Factor to 64 */
+	def_conf->dl_load_balance = 64;
+	def_conf->ul_load_balance = 64;
+}
+
+/* Initial configuration of FPGA 5GNR FEC device */
+int
+fpga_5gnr_fec_configure(const char *dev_name,
+		const struct fpga_5gnr_fec_conf *conf)
+{
+	uint32_t payload_32, address;
+	uint16_t payload_16;
+	uint8_t payload_8;
+	uint16_t q_id, vf_id, total_q_id, total_ul_q_id, total_dl_q_id;
+	struct rte_bbdev *bbdev = rte_bbdev_get_named_dev(dev_name);
+	struct fpga_5gnr_fec_conf def_conf;
+
+	if (bbdev == NULL) {
+		rte_bbdev_log(ERR,
+				"Invalid dev_name (%s), or device is not yet initialised",
+				dev_name);
+		return -ENODEV;
+	}
+
+	struct fpga_5gnr_fec_device *d = bbdev->data->dev_private;
+
+	if (conf == NULL) {
+		rte_bbdev_log(ERR,
+				"FPGA Configuration was not provided. Default configuration will be loaded.");
+		set_default_fpga_conf(&def_conf);
+		conf = &def_conf;
+	}
+
+	/*
+	 * Configure UL:DL ratio.
+	 * [7:0]: UL weight
+	 * [15:8]: DL weight
+	 */
+	payload_16 = (conf->dl_bandwidth << 8) | conf->ul_bandwidth;
+	address = FPGA_5GNR_FEC_CONFIGURATION;
+	fpga_reg_write_16(d->mmio_base, address, payload_16);
+
+	/* Clear all queues registers */
+	payload_32 = FPGA_INVALID_HW_QUEUE_ID;
+	for (q_id = 0; q_id < FPGA_TOTAL_NUM_QUEUES; ++q_id) {
+		address = (q_id << 2) + FPGA_5GNR_FEC_QUEUE_MAP;
+		fpga_reg_write_32(d->mmio_base, address, payload_32);
+	}
+
+	/*
+	 * If PF mode is enabled allocate all queues for PF only.
+	 *
+	 * For VF mode each VF can have different number of UL and DL queues.
+	 * Total number of queues to configure cannot exceed FPGA
+	 * capabilities - 64 queues - 32 queues for UL and 32 queues for DL.
+	 * Queues mapping is done according to configuration:
+	 *
+	 * UL queues:
+	 * |                Q_ID              | VF_ID |
+	 * |                 0                |   0   |
+	 * |                ...               |   0   |
+	 * | conf->vf_dl_queues_number[0] - 1 |   0   |
+	 * | conf->vf_dl_queues_number[0]     |   1   |
+	 * |                ...               |   1   |
+	 * | conf->vf_dl_queues_number[1] - 1 |   1   |
+	 * |                ...               |  ...  |
+	 * | conf->vf_dl_queues_number[7] - 1 |   7   |
+	 *
+	 * DL queues:
+	 * |                Q_ID              | VF_ID |
+	 * |                 32               |   0   |
+	 * |                ...               |   0   |
+	 * | conf->vf_ul_queues_number[0] - 1 |   0   |
+	 * | conf->vf_ul_queues_number[0]     |   1   |
+	 * |                ...               |   1   |
+	 * | conf->vf_ul_queues_number[1] - 1 |   1   |
+	 * |                ...               |  ...  |
+	 * | conf->vf_ul_queues_number[7] - 1 |   7   |
+	 *
+	 * Example of configuration:
+	 * conf->vf_ul_queues_number[0] = 4;  -> 4 UL queues for VF0
+	 * conf->vf_dl_queues_number[0] = 4;  -> 4 DL queues for VF0
+	 * conf->vf_ul_queues_number[1] = 2;  -> 2 UL queues for VF1
+	 * conf->vf_dl_queues_number[1] = 2;  -> 2 DL queues for VF1
+	 *
+	 * UL:
+	 * | Q_ID | VF_ID |
+	 * |   0  |   0   |
+	 * |   1  |   0   |
+	 * |   2  |   0   |
+	 * |   3  |   0   |
+	 * |   4  |   1   |
+	 * |   5  |   1   |
+	 *
+	 * DL:
+	 * | Q_ID | VF_ID |
+	 * |  32  |   0   |
+	 * |  33  |   0   |
+	 * |  34  |   0   |
+	 * |  35  |   0   |
+	 * |  36  |   1   |
+	 * |  37  |   1   |
+	 */
+	if (conf->pf_mode_en) {
+		payload_32 = 0x1;
+		for (q_id = 0; q_id < FPGA_TOTAL_NUM_QUEUES; ++q_id) {
+			address = (q_id << 2) + FPGA_5GNR_FEC_QUEUE_MAP;
+			fpga_reg_write_32(d->mmio_base, address, payload_32);
+		}
+	} else {
+		/* Calculate total number of UL and DL queues to configure */
+		total_ul_q_id = total_dl_q_id = 0;
+		for (vf_id = 0; vf_id < FPGA_5GNR_FEC_NUM_VFS; ++vf_id) {
+			total_ul_q_id += conf->vf_ul_queues_number[vf_id];
+			total_dl_q_id += conf->vf_dl_queues_number[vf_id];
+		}
+		total_q_id = total_dl_q_id + total_ul_q_id;
+		/*
+		 * Check if total number of queues to configure does not exceed
+		 * FPGA capabilities (64 queues - 32 UL and 32 DL queues)
+		 */
+		if ((total_ul_q_id > FPGA_NUM_UL_QUEUES) ||
+			(total_dl_q_id > FPGA_NUM_DL_QUEUES) ||
+			(total_q_id > FPGA_TOTAL_NUM_QUEUES)) {
+			rte_bbdev_log(ERR,
+					"FPGA Configuration failed. Too many queues to configure: UL_Q %u, DL_Q %u, FPGA_Q %u",
+					total_ul_q_id, total_dl_q_id,
+					FPGA_TOTAL_NUM_QUEUES);
+			return -EINVAL;
+		}
+		total_ul_q_id = 0;
+		for (vf_id = 0; vf_id < FPGA_5GNR_FEC_NUM_VFS; ++vf_id) {
+			for (q_id = 0; q_id < conf->vf_ul_queues_number[vf_id];
+					++q_id, ++total_ul_q_id) {
+				address = (total_ul_q_id << 2) +
+						FPGA_5GNR_FEC_QUEUE_MAP;
+				payload_32 = ((0x80 + vf_id) << 16) | 0x1;
+				fpga_reg_write_32(d->mmio_base, address,
+						payload_32);
+			}
+		}
+		total_dl_q_id = 0;
+		for (vf_id = 0; vf_id < FPGA_5GNR_FEC_NUM_VFS; ++vf_id) {
+			for (q_id = 0; q_id < conf->vf_dl_queues_number[vf_id];
+					++q_id, ++total_dl_q_id) {
+				address = ((total_dl_q_id + FPGA_NUM_UL_QUEUES)
+						<< 2) + FPGA_5GNR_FEC_QUEUE_MAP;
+				payload_32 = ((0x80 + vf_id) << 16) | 0x1;
+				fpga_reg_write_32(d->mmio_base, address,
+						payload_32);
+			}
+		}
+	}
+
+	/* Setting Load Balance Factor */
+	payload_16 = (conf->dl_load_balance << 8) | (conf->ul_load_balance);
+	address = FPGA_5GNR_FEC_LOAD_BALANCE_FACTOR;
+	fpga_reg_write_16(d->mmio_base, address, payload_16);
+
+	/* Setting length of ring descriptor entry */
+	payload_16 = FPGA_RING_DESC_ENTRY_LENGTH;
+	address = FPGA_5GNR_FEC_RING_DESC_LEN;
+	fpga_reg_write_16(d->mmio_base, address, payload_16);
+
+	/* Setting FLR timeout value */
+	payload_16 = conf->flr_time_out;
+	address = FPGA_5GNR_FEC_FLR_TIME_OUT;
+	fpga_reg_write_16(d->mmio_base, address, payload_16);
+
+	/* Queue PF/VF mapping table is ready */
+	payload_8 = 0x1;
+	address = FPGA_5GNR_FEC_QUEUE_PF_VF_MAP_DONE;
+	fpga_reg_write_8(d->mmio_base, address, payload_8);
+
+	rte_bbdev_log_debug("PF FPGA 5GNR FEC configuration complete for %s",
+			dev_name);
+
+#ifdef RTE_LIBRTE_BBDEV_DEBUG
+	print_static_reg_debug_info(d->mmio_base);
+#endif
+	return 0;
+}
+
+/* FPGA 5GNR FEC PCI PF address map */
+static struct rte_pci_id pci_id_fpga_5gnr_fec_pf_map[] = {
+	{
+		RTE_PCI_DEVICE(FPGA_5GNR_FEC_VENDOR_ID,
+				FPGA_5GNR_FEC_PF_DEVICE_ID)
+	},
+	{.device_id = 0},
+};
+
+static struct rte_pci_driver fpga_5gnr_fec_pci_pf_driver = {
+	.probe = fpga_5gnr_fec_probe,
+	.remove = fpga_5gnr_fec_remove,
+	.id_table = pci_id_fpga_5gnr_fec_pf_map,
+	.drv_flags = RTE_PCI_DRV_NEED_MAPPING
+};
+
+/* FPGA 5GNR FEC PCI VF address map */
+static struct rte_pci_id pci_id_fpga_5gnr_fec_vf_map[] = {
+	{
+		RTE_PCI_DEVICE(FPGA_5GNR_FEC_VENDOR_ID,
+				FPGA_5GNR_FEC_VF_DEVICE_ID)
+	},
+	{.device_id = 0},
+};
+
+static struct rte_pci_driver fpga_5gnr_fec_pci_vf_driver = {
+	.probe = fpga_5gnr_fec_probe,
+	.remove = fpga_5gnr_fec_remove,
+	.id_table = pci_id_fpga_5gnr_fec_vf_map,
+	.drv_flags = RTE_PCI_DRV_NEED_MAPPING
+};
+
+
+RTE_PMD_REGISTER_PCI(FPGA_5GNR_FEC_PF_DRIVER_NAME, fpga_5gnr_fec_pci_pf_driver);
+RTE_PMD_REGISTER_PCI_TABLE(FPGA_5GNR_FEC_PF_DRIVER_NAME,
+		pci_id_fpga_5gnr_fec_pf_map);
+RTE_PMD_REGISTER_PCI(FPGA_5GNR_FEC_VF_DRIVER_NAME, fpga_5gnr_fec_pci_vf_driver);
+RTE_PMD_REGISTER_PCI_TABLE(FPGA_5GNR_FEC_VF_DRIVER_NAME,
+		pci_id_fpga_5gnr_fec_vf_map);
+
+RTE_INIT(fpga_5gnr_fec_init_log)
+{
+	fpga_5gnr_fec_logtype = rte_log_register("pmd.bb.fpga_5gnr_fec");
+	if (fpga_5gnr_fec_logtype >= 0)
+#ifdef RTE_LIBRTE_BBDEV_DEBUG
+		rte_log_set_level(fpga_5gnr_fec_logtype, RTE_LOG_DEBUG);
+#else
+		rte_log_set_level(fpga_5gnr_fec_logtype, RTE_LOG_NOTICE);
+#endif
+}
diff --git a/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h b/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h
new file mode 100644
index 0000000..7eebc7d
--- /dev/null
+++ b/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h
@@ -0,0 +1,74 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2020 Intel Corporation
+ */
+
+#ifndef _FPGA_5GNR_FEC_H_
+#define _FPGA_5GNR_FEC_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+
+/**
+ * @file fpga_5gnr_fec.h
+ *
+ * Interface for Intel(R) FGPA 5GNR FEC device configuration at the host level,
+ * directly accessible by the application.
+ * Configuration related to 5GNR functionality is done through
+ * librte_bbdev library.
+ *
+ * @warning
+ * @b EXPERIMENTAL: this API may change without prior notice
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**< Number of Virtual Functions FGPA 4G FEC supports */
+#define FPGA_5GNR_FEC_NUM_VFS 8
+
+/**
+ * Structure to pass FPGA 4G FEC configuration.
+ */
+struct fpga_5gnr_fec_conf {
+	/**< 1 if PF is used for dataplane, 0 for VFs */
+	bool pf_mode_en;
+	/**< Number of UL queues per VF */
+	uint8_t vf_ul_queues_number[FPGA_5GNR_FEC_NUM_VFS];
+	/**< Number of DL queues per VF */
+	uint8_t vf_dl_queues_number[FPGA_5GNR_FEC_NUM_VFS];
+	/**< UL bandwidth. Needed for schedule algorithm */
+	uint8_t ul_bandwidth;
+	/**< DL bandwidth. Needed for schedule algorithm */
+	uint8_t dl_bandwidth;
+	/**< UL Load Balance */
+	uint8_t ul_load_balance;
+	/**< DL Load Balance */
+	uint8_t dl_load_balance;
+	/**< FLR timeout value */
+	uint16_t flr_time_out;
+};
+
+/**
+ * Configure Intel(R) FPGA 5GNR FEC device
+ *
+ * @param dev_name
+ *   The name of the device. This is the short form of PCI BDF, e.g. 00:01.0.
+ *   It can also be retrieved for a bbdev device from the dev_name field in the
+ *   rte_bbdev_info structure returned by rte_bbdev_info_get().
+ * @param conf
+ *   Configuration to apply to FPGA 4G FEC.
+ *
+ * @return
+ *   Zero on success, negative value on failure.
+ */
+__rte_experimental
+int
+fpga_5gnr_fec_configure(const char *dev_name,
+		const struct fpga_5gnr_fec_conf *conf);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _FPGA_5GNR_FEC_H_ */
diff --git a/drivers/baseband/fpga_5gnr_fec/meson.build b/drivers/baseband/fpga_5gnr_fec/meson.build
new file mode 100644
index 0000000..86121d8
--- /dev/null
+++ b/drivers/baseband/fpga_5gnr_fec/meson.build
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2020 Intel Corporation
+
+deps += ['bbdev', 'bus_vdev', 'ring', 'pci', 'bus_pci']
+allow_experimental_apis = true
+sources = files('fpga_5gnr_fec.c')
diff --git a/drivers/baseband/fpga_5gnr_fec/rte_pmd_bbdev_fpga_5gnr_fec_version.map b/drivers/baseband/fpga_5gnr_fec/rte_pmd_bbdev_fpga_5gnr_fec_version.map
new file mode 100644
index 0000000..b0fb971
--- /dev/null
+++ b/drivers/baseband/fpga_5gnr_fec/rte_pmd_bbdev_fpga_5gnr_fec_version.map
@@ -0,0 +1,10 @@
+DPDK_20.0 {
+	local: *;
+};
+
+EXPERIMENTAL {
+	global:
+
+	fpga_5gnr_fec_configure;
+
+};
diff --git a/drivers/baseband/meson.build b/drivers/baseband/meson.build
index be7677f..4d909f9 100644
--- a/drivers/baseband/meson.build
+++ b/drivers/baseband/meson.build
@@ -1,7 +1,7 @@
 # SPDX-License-Identifier: BSD-3-Clause
 # Copyright(c) 2018 Luca Boccassi <bluca@debian.org>
 
-drivers = ['null', 'turbo_sw', 'fpga_lte_fec']
+drivers = ['null', 'turbo_sw', 'fpga_lte_fec', 'fpga_5gnr_fec']
 
 config_flag_fmt = 'RTE_LIBRTE_PMD_BBDEV_@0@'
 driver_name_fmt = 'rte_pmd_bbdev_@0@'
diff --git a/mk/rte.app.mk b/mk/rte.app.mk
index d295ca0..da12b9e 100644
--- a/mk/rte.app.mk
+++ b/mk/rte.app.mk
@@ -246,6 +246,7 @@ _LDLIBS-$(CONFIG_RTE_LIBRTE_NETVSC_PMD)     += -lrte_pmd_netvsc
 ifeq ($(CONFIG_RTE_LIBRTE_BBDEV),y)
 _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_BBDEV_NULL)     += -lrte_pmd_bbdev_null
 _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_BBDEV_FPGA_LTE_FEC) += -lrte_pmd_bbdev_fpga_lte_fec
+_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_BBDEV_FPGA_5GNR_FEC) += -lrte_pmd_bbdev_fpga_5gnr_fec
 
 # TURBO SOFTWARE PMD is dependent on the FLEXRAN library
 _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_BBDEV_TURBO_SW) += -lrte_pmd_bbdev_turbo_sw
-- 
1.8.3.1


^ permalink raw reply	[flat|nested] 115+ messages in thread

* [dpdk-dev] [PATCH v2 13/15] test-bbdev: add support for FPGA driver initialization
  2020-03-04 18:22   ` [dpdk-dev] [PATCH v2 00/15] bbdev new features Nicolas Chautru
                       ` (11 preceding siblings ...)
  2020-03-04 18:22     ` [dpdk-dev] [PATCH v2 12/15] drivers/baseband: add PMD for FPGA 5GNR FEC Nicolas Chautru
@ 2020-03-04 18:22     ` Nicolas Chautru
  2020-03-04 18:22     ` [dpdk-dev] [PATCH v2 14/15] doc: add feature matrix table for bbdev devices Nicolas Chautru
  2020-03-04 18:22     ` [dpdk-dev] [PATCH v2 15/15] doc: add release note for bbdev PMD update Nicolas Chautru
  14 siblings, 0 replies; 115+ messages in thread
From: Nicolas Chautru @ 2020-03-04 18:22 UTC (permalink / raw)
  To: thomas, akhil.goyal, dev; +Cc: ferruh.yigit, Nic Chautru

From: Nic Chautru <nicolas.chautru@intel.com>

Adding capacity to initialize the device driver from
the test-bbdev environment for the new device
FPGA for 5GNR FEC.

Signed-off-by: Nic Chautru <nicolas.chautru@intel.com>
---
 app/test-bbdev/Makefile          |  3 +++
 app/test-bbdev/meson.build       |  3 +++
 app/test-bbdev/test_bbdev_perf.c | 58 ++++++++++++++++++++++++++++++++++++++++
 3 files changed, 64 insertions(+)

diff --git a/app/test-bbdev/Makefile b/app/test-bbdev/Makefile
index c53982f..e951302 100644
--- a/app/test-bbdev/Makefile
+++ b/app/test-bbdev/Makefile
@@ -24,5 +24,8 @@ LDLIBS += -lm
 ifeq ($(CONFIG_RTE_LIBRTE_PMD_BBDEV_FPGA_LTE_FEC),y)
 LDLIBS += -lrte_pmd_bbdev_fpga_lte_fec
 endif
+ifeq ($(CONFIG_RTE_LIBRTE_PMD_BBDEV_FPGA_5GNR_FEC),y)
+LDLIBS += -lrte_pmd_bbdev_fpga_5gnr_fec
+endif
 
 include $(RTE_SDK)/mk/rte.app.mk
diff --git a/app/test-bbdev/meson.build b/app/test-bbdev/meson.build
index 4f53a2e..e57e019 100644
--- a/app/test-bbdev/meson.build
+++ b/app/test-bbdev/meson.build
@@ -10,3 +10,6 @@ deps += ['bbdev', 'bus_vdev']
 if dpdk_conf.has('RTE_LIBRTE_PMD_BBDEV_FPGA_LTE_FEC')
 	deps += ['pmd_bbdev_fpga_lte_fec']
 endif
+if dpdk_conf.has('RTE_LIBRTE_PMD_BBDEV_FPGA_5GNR_FEC')
+	deps += ['pmd_bbdev_fpga_5gnr_fec']
+endif
\ No newline at end of file
diff --git a/app/test-bbdev/test_bbdev_perf.c b/app/test-bbdev/test_bbdev_perf.c
index 1017b97..50ffee0 100644
--- a/app/test-bbdev/test_bbdev_perf.c
+++ b/app/test-bbdev/test_bbdev_perf.c
@@ -39,6 +39,19 @@
 #define FLR_4G_TIMEOUT 610
 #endif
 
+#ifdef RTE_LIBRTE_PMD_BBDEV_FPGA_5GNR_FEC
+#include <fpga_5gnr_fec.h>
+#define FPGA_5GNR_PF_DRIVER_NAME ("intel_fpga_5gnr_fec_pf")
+#define FPGA_5GNR_VF_DRIVER_NAME ("intel_fpga_5gnr_fec_vf")
+#define VF_UL_5G_QUEUE_VALUE 4
+#define VF_DL_5G_QUEUE_VALUE 4
+#define UL_5G_BANDWIDTH 3
+#define DL_5G_BANDWIDTH 3
+#define UL_5G_LOAD_BALANCE 128
+#define DL_5G_LOAD_BALANCE 128
+#define FLR_5G_TIMEOUT 610
+#endif
+
 #define OPS_CACHE_SIZE 256U
 #define OPS_POOL_SIZE_MIN 511U /* 0.5K per queue */
 
@@ -587,6 +600,51 @@ typedef int (test_case_function)(struct active_device *ad,
 				info->dev_name);
 	}
 #endif
+#ifdef RTE_LIBRTE_PMD_BBDEV_FPGA_5GNR_FEC
+	if ((get_init_device() == true) &&
+		(!strcmp(info->drv.driver_name, FPGA_5GNR_PF_DRIVER_NAME))) {
+		struct fpga_5gnr_fec_conf conf;
+		unsigned int i;
+
+		printf("Configure FPGA 5GNR FEC Driver %s with default values\n",
+				info->drv.driver_name);
+
+		/* clear default configuration before initialization */
+		memset(&conf, 0, sizeof(struct fpga_5gnr_fec_conf));
+
+		/* Set PF mode :
+		 * true if PF is used for data plane
+		 * false for VFs
+		 */
+		conf.pf_mode_en = true;
+
+		for (i = 0; i < FPGA_5GNR_FEC_NUM_VFS; ++i) {
+			/* Number of UL queues per VF (fpga supports 8 VFs) */
+			conf.vf_ul_queues_number[i] = VF_UL_5G_QUEUE_VALUE;
+			/* Number of DL queues per VF (fpga supports 8 VFs) */
+			conf.vf_dl_queues_number[i] = VF_DL_5G_QUEUE_VALUE;
+		}
+
+		/* UL bandwidth. Needed for schedule algorithm */
+		conf.ul_bandwidth = UL_5G_BANDWIDTH;
+		/* DL bandwidth */
+		conf.dl_bandwidth = DL_5G_BANDWIDTH;
+
+		/* UL & DL load Balance Factor to 64 */
+		conf.ul_load_balance = UL_5G_LOAD_BALANCE;
+		conf.dl_load_balance = DL_5G_LOAD_BALANCE;
+
+		/**< FLR timeout value */
+		conf.flr_time_out = FLR_5G_TIMEOUT;
+
+		/* setup FPGA PF with configuration information */
+		ret = fpga_5gnr_fec_configure(info->dev_name, &conf);
+		TEST_ASSERT_SUCCESS(ret,
+				"Failed to configure 5G FPGA PF for bbdev %s",
+				info->dev_name);
+	}
+#endif
+
 	nb_queues = RTE_MIN(rte_lcore_count(), info->drv.max_num_queues);
 	nb_queues = RTE_MIN(nb_queues, (unsigned int) MAX_QUEUES);
 
-- 
1.8.3.1


^ permalink raw reply	[flat|nested] 115+ messages in thread

* [dpdk-dev] [PATCH v2 14/15] doc: add feature matrix table for bbdev devices
  2020-03-04 18:22   ` [dpdk-dev] [PATCH v2 00/15] bbdev new features Nicolas Chautru
                       ` (12 preceding siblings ...)
  2020-03-04 18:22     ` [dpdk-dev] [PATCH v2 13/15] test-bbdev: add support for FPGA driver initialization Nicolas Chautru
@ 2020-03-04 18:22     ` Nicolas Chautru
  2020-03-04 18:22     ` [dpdk-dev] [PATCH v2 15/15] doc: add release note for bbdev PMD update Nicolas Chautru
  14 siblings, 0 replies; 115+ messages in thread
From: Nicolas Chautru @ 2020-03-04 18:22 UTC (permalink / raw)
  To: thomas, akhil.goyal, dev; +Cc: ferruh.yigit, Nic Chautru

From: Nic Chautru <nicolas.chautru@intel.com>

Adding missing overview page in documentation with
comparison of feature set by PMD implementation.

Signed-off-by: Nic Chautru <nicolas.chautru@intel.com>
---
 .gitignore                                   |  1 +
 doc/guides/bbdevs/features/default.ini       | 16 ++++++++++++++++
 doc/guides/bbdevs/features/fpga_5gnr_fec.ini | 11 +++++++++++
 doc/guides/bbdevs/features/fpga_lte_fec.ini  | 10 ++++++++++
 doc/guides/bbdevs/features/mbc.ini           | 14 ++++++++++++++
 doc/guides/bbdevs/features/null.ini          |  7 +++++++
 doc/guides/bbdevs/features/turbo_sw.ini      | 11 +++++++++++
 doc/guides/bbdevs/index.rst                  |  1 +
 doc/guides/bbdevs/overview.rst               | 15 +++++++++++++++
 doc/guides/conf.py                           |  5 +++++
 10 files changed, 91 insertions(+)
 create mode 100644 doc/guides/bbdevs/features/default.ini
 create mode 100644 doc/guides/bbdevs/features/fpga_5gnr_fec.ini
 create mode 100644 doc/guides/bbdevs/features/fpga_lte_fec.ini
 create mode 100644 doc/guides/bbdevs/features/mbc.ini
 create mode 100644 doc/guides/bbdevs/features/null.ini
 create mode 100644 doc/guides/bbdevs/features/turbo_sw.ini
 create mode 100644 doc/guides/bbdevs/overview.rst

diff --git a/.gitignore b/.gitignore
index 2acb459..f2f8892 100644
--- a/.gitignore
+++ b/.gitignore
@@ -10,6 +10,7 @@ doc/guides/cryptodevs/overview_aead_table.txt
 doc/guides/cryptodevs/overview_asym_table.txt
 doc/guides/compressdevs/overview_feature_table.txt
 doc/guides/vdpadevs/overview_feature_table.txt
+doc/guides/bbdevs/overview_feature_table.txt
 
 # ignore generated ctags/cscope files
 cscope.out.po
diff --git a/doc/guides/bbdevs/features/default.ini b/doc/guides/bbdevs/features/default.ini
new file mode 100644
index 0000000..5fe267a
--- /dev/null
+++ b/doc/guides/bbdevs/features/default.ini
@@ -0,0 +1,16 @@
+;
+; Features of a default bbdev driver.
+;
+; This file defines the features that are valid for inclusion in
+; the other driver files and also the order that they appear in
+; the features table in the documentation.
+;
+[Features]
+Turbo Decoder (4G)     =
+Turbo Encoder (4G)     =
+LDPC Decoder (5G)      =
+LDPC Encoder (5G)      =
+LLR/HARQ Compression   =
+External DDR Access    =
+HW Accelerated         =
+BBDEV API              =
diff --git a/doc/guides/bbdevs/features/fpga_5gnr_fec.ini b/doc/guides/bbdevs/features/fpga_5gnr_fec.ini
new file mode 100644
index 0000000..7a0b8d4
--- /dev/null
+++ b/doc/guides/bbdevs/features/fpga_5gnr_fec.ini
@@ -0,0 +1,11 @@
+;
+; Supported features of the 'fpga_5ngr_fec' bbdev driver.
+;
+; Refer to default.ini for the full list of available PMD features.
+;
+[Features]
+LDPC Decoder (5G)      = Y
+LDPC Encoder (5G)      = Y
+External DDR Access    = Y
+HW Accelerated         = Y
+BBDEV API              = Y
diff --git a/doc/guides/bbdevs/features/fpga_lte_fec.ini b/doc/guides/bbdevs/features/fpga_lte_fec.ini
new file mode 100644
index 0000000..f1cfb92
--- /dev/null
+++ b/doc/guides/bbdevs/features/fpga_lte_fec.ini
@@ -0,0 +1,10 @@
+;
+; Supported features of the 'fpga_lte_fec' bbdev driver.
+;
+; Refer to default.ini for the full list of available PMD features.
+;
+[Features]
+Turbo Decoder (4G)     = Y
+Turbo Encoder (4G)     = Y
+HW Accelerated         = Y
+BBDEV API              = Y
diff --git a/doc/guides/bbdevs/features/mbc.ini b/doc/guides/bbdevs/features/mbc.ini
new file mode 100644
index 0000000..78a7b95
--- /dev/null
+++ b/doc/guides/bbdevs/features/mbc.ini
@@ -0,0 +1,14 @@
+;
+; Supported features of the 'mbc' bbdev driver.
+;
+; Refer to default.ini for the full list of available PMD features.
+;
+[Features]
+Turbo Decoder (4G)     = Y
+Turbo Encoder (4G)     = Y
+LDPC Decoder (5G)      = Y
+LDPC Encoder (5G)      = Y
+LLR/HARQ Compression   = Y
+External DDR Access    = Y
+HW Accelerated         = Y
+BBDEV API              = Y
diff --git a/doc/guides/bbdevs/features/null.ini b/doc/guides/bbdevs/features/null.ini
new file mode 100644
index 0000000..d9bbda9
--- /dev/null
+++ b/doc/guides/bbdevs/features/null.ini
@@ -0,0 +1,7 @@
+;
+; Supported features of the 'null' bbdev driver.
+;
+; Refer to default.ini for the full list of available PMD features.
+;
+[Features]
+BBDEV API              = Y
diff --git a/doc/guides/bbdevs/features/turbo_sw.ini b/doc/guides/bbdevs/features/turbo_sw.ini
new file mode 100644
index 0000000..2c7075e
--- /dev/null
+++ b/doc/guides/bbdevs/features/turbo_sw.ini
@@ -0,0 +1,11 @@
+;
+; Supported features of the 'turbo_sw' bbdev driver.
+;
+; Refer to default.ini for the full list of available PMD features.
+;
+[Features]
+Turbo Decoder (4G)     = Y
+Turbo Encoder (4G)     = Y
+LDPC Decoder (5G)      = Y
+LDPC Encoder (5G)      = Y
+BBDEV API              = Y
diff --git a/doc/guides/bbdevs/index.rst b/doc/guides/bbdevs/index.rst
index 1a79343..a8092dd 100644
--- a/doc/guides/bbdevs/index.rst
+++ b/doc/guides/bbdevs/index.rst
@@ -8,6 +8,7 @@ Baseband Device Drivers
     :maxdepth: 2
     :numbered:
 
+    overview
     null
     turbo_sw
     fpga_lte_fec
diff --git a/doc/guides/bbdevs/overview.rst b/doc/guides/bbdevs/overview.rst
new file mode 100644
index 0000000..ace4e67
--- /dev/null
+++ b/doc/guides/bbdevs/overview.rst
@@ -0,0 +1,15 @@
+..  SPDX-License-Identifier: BSD-3-Clause
+    Copyright(c) 2020 Intel Corporation.
+
+Baseband Device Supported Functionality Matrices
+==============================================
+
+Supported Feature Flags
+-----------------------
+
+.. _table_bbdev_pmd_features:
+
+.. include:: overview_feature_table.txt
+
+
+
diff --git a/doc/guides/conf.py b/doc/guides/conf.py
index c368fa5..d52b584 100644
--- a/doc/guides/conf.py
+++ b/doc/guides/conf.py
@@ -406,6 +406,11 @@ def setup(app):
                             'Features',
                             'Features availability in vDPA drivers',
                             'Feature')
+    table_file = dirname(__file__) + '/bbdevs/overview_feature_table.txt'
+    generate_overview_table(table_file, 1,
+                            'Features',
+                            'Features availability in bbdev drivers',
+                            'Feature')
 
     if LooseVersion(sphinx_version) < LooseVersion('1.3.1'):
         print('Upgrade sphinx to version >= 1.3.1 for '
-- 
1.8.3.1


^ permalink raw reply	[flat|nested] 115+ messages in thread

* [dpdk-dev] [PATCH v2 15/15] doc: add release note for bbdev PMD update
  2020-03-04 18:22   ` [dpdk-dev] [PATCH v2 00/15] bbdev new features Nicolas Chautru
                       ` (13 preceding siblings ...)
  2020-03-04 18:22     ` [dpdk-dev] [PATCH v2 14/15] doc: add feature matrix table for bbdev devices Nicolas Chautru
@ 2020-03-04 18:22     ` Nicolas Chautru
  14 siblings, 0 replies; 115+ messages in thread
From: Nicolas Chautru @ 2020-03-04 18:22 UTC (permalink / raw)
  To: thomas, akhil.goyal, dev; +Cc: ferruh.yigit, Nicolas Chautru

Add release note update related to the changes
to the bbdev PMD in 20.05.

Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
---
 doc/guides/rel_notes/release_20_05.rst | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/doc/guides/rel_notes/release_20_05.rst b/doc/guides/rel_notes/release_20_05.rst
index 2190eaf..083bb0d 100644
--- a/doc/guides/rel_notes/release_20_05.rst
+++ b/doc/guides/rel_notes/release_20_05.rst
@@ -56,6 +56,18 @@ New Features
      Also, make sure to start the actual text at the margin.
      =========================================================
 
+* **Added a FPGA_5GNR_FEC bbdev PMD.**
+
+  Added a new ``fpga_5gnr_fec`` bbdev driver for the Intel\ |reg| FPGA PAC
+  (Programmable  Acceleration Card) N3000.  See the
+  :doc:`../bbdevs/fpga_5gnr_fec` BBDEV guide for more details on this new driver.
+
+* **Updated the TURBO_SW bbdev PMD.**
+
+  Updated the ``turbo_sw`` bbdev driver with changes including:
+
+  * Support for large size code block not fitting in one mbuf segment.
+  * Exposes the accurate LLR decimal assumption.
 
 Removed Items
 -------------
-- 
1.8.3.1


^ permalink raw reply	[flat|nested] 115+ messages in thread

* Re: [dpdk-dev] [PATCH v1 00/14] bbdev new features
  2020-03-04  8:23   ` Thomas Monjalon
@ 2020-03-04 18:28     ` Chautru, Nicolas
  0 siblings, 0 replies; 115+ messages in thread
From: Chautru, Nicolas @ 2020-03-04 18:28 UTC (permalink / raw)
  To: Thomas Monjalon; +Cc: akhil.goyal, dev, Yigit, Ferruh

Monjalon, Thomas:
> > Hi Akhil, Thomas, 
> > Checking whether there is anything on your end or can we have these patches merged? 
> > I did not include the release note update in that serie but will push a trivial patchset for this later on if that's okay. 
> Why not including the release notes in the patches?
> We prefer not having separate commits for documentation and release notes.

Thanks Thomas, the release note update is added in the v2 serie now.



^ permalink raw reply	[flat|nested] 115+ messages in thread

* [dpdk-dev] [PATCH v3 00/14] bbdev new features
  2020-02-27  4:39 ` [dpdk-dev] [PATCH v1 14/14] doc: add feature matrix table for bbdev devices Nicolas Chautru
  2020-03-04 18:22   ` [dpdk-dev] [PATCH v2 00/15] bbdev new features Nicolas Chautru
@ 2020-03-04 18:54   ` Nicolas Chautru
  2020-03-04 18:54     ` [dpdk-dev] [PATCH v3 01/14] bbdev: add capability flag for filler bits inclusion in HARQ Nicolas Chautru
                       ` (14 more replies)
  2020-03-26  2:45   ` [dpdk-dev] [PATCH v4 00/10] " Nicolas Chautru
  2020-03-26  3:27   ` [dpdk-dev] [PATCH v5 00/10] bbdev new features Nicolas Chautru
  3 siblings, 15 replies; 115+ messages in thread
From: Nicolas Chautru @ 2020-03-04 18:54 UTC (permalink / raw)
  To: thomas, akhil.goyal, dev; +Cc: ferruh.yigit, Nicolas Chautru

v3: squash the release notes updates into the related commits
v2: including release note update + fix for typo in commit message reported by DPDK CI. 

This set includes extending support for the bbdev device drivers for 20.05 and notably add a new baseband PMD for FPGA 5GNR FEC implementation. 
Documentation is updated as well accordingly. 


Nic Chautru (14):
  bbdev: add capability flag for filler bits inclusion in HARQ
  bbdev: expose device HARQ buffer size at device level
  baseband/turbo_sw: fix the exposed LLR decimals assumption
  baseband/turbo_sw: support large size code block
  test-bbdev: rename FPGA LTE macros to be more explicit
  test-bbdev: support HARQ validation
  test-bbdev: support for performance tests
  test-bbdev: support for LDPC interrupt test
  test-bbdev: support for offload test for LDPC
  test-bbdev: vectors update
  doc: update of testbbdev documentation
  drivers/baseband: add PMD for FPGA 5GNR FEC
  test-bbdev: add support for FPGA driver initialization
  doc: add feature matrix table for bbdev devices

 .gitignore                                         |    1 +
 app/test-bbdev/Makefile                            |    3 +
 app/test-bbdev/ldpc_dec_default.data               |    2 +-
 app/test-bbdev/main.c                              |   29 +-
 app/test-bbdev/main.h                              |    9 +-
 app/test-bbdev/meson.build                         |    3 +
 app/test-bbdev/test_bbdev_perf.c                   | 1468 ++++++++++-
 app/test-bbdev/test_bbdev_vector.c                 |    9 +-
 app/test-bbdev/test_vectors/ldpc_dec_v2342.data    |  745 ------
 app/test-bbdev/test_vectors/ldpc_dec_v9503.data    |    4 +-
 .../turbo_dec_c1_k6144_r0_e34560_negllr.data       |  645 -----
 .../turbo_dec_c2_k3136_r0_e4920_sbd_negllr.data    |  676 ------
 ...bo_dec_c2_k3136_r0_e4920_sbd_negllr_crc24b.data |    5 +-
 .../turbo_enc_c2_k5952_r0_e17868_crc24b.data       |  300 ---
 .../turbo_enc_c4_k4800_r2_e14412_crc24b.data       |  252 --
 config/common_base                                 |    5 +
 doc/guides/bbdevs/features/default.ini             |   16 +
 doc/guides/bbdevs/features/fpga_5gnr_fec.ini       |   11 +
 doc/guides/bbdevs/features/fpga_lte_fec.ini        |   10 +
 doc/guides/bbdevs/features/mbc.ini                 |   14 +
 doc/guides/bbdevs/features/null.ini                |    7 +
 doc/guides/bbdevs/features/turbo_sw.ini            |   11 +
 doc/guides/bbdevs/fpga_5gnr_fec.rst                |  297 +++
 doc/guides/bbdevs/index.rst                        |    2 +
 doc/guides/bbdevs/overview.rst                     |   15 +
 doc/guides/conf.py                                 |    5 +
 doc/guides/rel_notes/release_20_05.rst             |   12 +
 doc/guides/tools/testbbdev.rst                     |  337 ++-
 drivers/baseband/Makefile                          |    2 +
 drivers/baseband/fpga_5gnr_fec/Makefile            |   29 +
 drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.c     | 2552 ++++++++++++++++++++
 drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h     |   74 +
 drivers/baseband/fpga_5gnr_fec/meson.build         |    6 +
 .../rte_pmd_bbdev_fpga_5gnr_fec_version.map        |   10 +
 drivers/baseband/meson.build                       |    2 +-
 drivers/baseband/turbo_sw/bbdev_turbo_software.c   |   15 +-
 lib/librte_bbdev/rte_bbdev.h                       |    4 +
 lib/librte_bbdev/rte_bbdev_op.h                    |   14 +-
 mk/rte.app.mk                                      |    1 +
 39 files changed, 4784 insertions(+), 2818 deletions(-)
 delete mode 100644 app/test-bbdev/test_vectors/ldpc_dec_v2342.data
 delete mode 100644 app/test-bbdev/test_vectors/turbo_dec_c1_k6144_r0_e34560_negllr.data
 delete mode 100644 app/test-bbdev/test_vectors/turbo_dec_c2_k3136_r0_e4920_sbd_negllr.data
 delete mode 100644 app/test-bbdev/test_vectors/turbo_enc_c2_k5952_r0_e17868_crc24b.data
 delete mode 100644 app/test-bbdev/test_vectors/turbo_enc_c4_k4800_r2_e14412_crc24b.data
 create mode 100644 doc/guides/bbdevs/features/default.ini
 create mode 100644 doc/guides/bbdevs/features/fpga_5gnr_fec.ini
 create mode 100644 doc/guides/bbdevs/features/fpga_lte_fec.ini
 create mode 100644 doc/guides/bbdevs/features/mbc.ini
 create mode 100644 doc/guides/bbdevs/features/null.ini
 create mode 100644 doc/guides/bbdevs/features/turbo_sw.ini
 create mode 100644 doc/guides/bbdevs/fpga_5gnr_fec.rst
 create mode 100644 doc/guides/bbdevs/overview.rst
 create mode 100644 drivers/baseband/fpga_5gnr_fec/Makefile
 create mode 100644 drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.c
 create mode 100644 drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h
 create mode 100644 drivers/baseband/fpga_5gnr_fec/meson.build
 create mode 100644 drivers/baseband/fpga_5gnr_fec/rte_pmd_bbdev_fpga_5gnr_fec_version.map

-- 
1.8.3.1


^ permalink raw reply	[flat|nested] 115+ messages in thread

* [dpdk-dev] [PATCH v3 01/14] bbdev: add capability flag for filler bits inclusion in HARQ
  2020-03-04 18:54   ` [dpdk-dev] [PATCH v3 00/14] bbdev new features Nicolas Chautru
@ 2020-03-04 18:54     ` Nicolas Chautru
  2020-03-13 10:42       ` Dave Burley
  2020-03-25  9:53       ` Akhil Goyal
  2020-03-04 18:54     ` [dpdk-dev] [PATCH v3 02/14] bbdev: expose device HARQ buffer size at device level Nicolas Chautru
                       ` (13 subsequent siblings)
  14 siblings, 2 replies; 115+ messages in thread
From: Nicolas Chautru @ 2020-03-04 18:54 UTC (permalink / raw)
  To: thomas, akhil.goyal, dev; +Cc: ferruh.yigit, Nic Chautru

From: Nic Chautru <nicolas.chautru@intel.com>

Adding capability flag for device variants when HARQ buffer
may or may not include the filler bits.
Minor cosmetic changes in same file.

Signed-off-by: Nic Chautru <nicolas.chautru@intel.com>
---
 lib/librte_bbdev/rte_bbdev.h    |  2 ++
 lib/librte_bbdev/rte_bbdev_op.h | 12 ++++++++++--
 2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/lib/librte_bbdev/rte_bbdev.h b/lib/librte_bbdev/rte_bbdev.h
index 591fb79..b2da190 100644
--- a/lib/librte_bbdev/rte_bbdev.h
+++ b/lib/librte_bbdev/rte_bbdev.h
@@ -607,6 +607,7 @@ struct __rte_cache_aligned rte_bbdev {
  * @param ops
  *   Pointer array where operations will be dequeued to. Must have at least
  *   @p num_ops entries
+ *   ie. A pointer to a table of void * pointers (ops) that will be filled.
  * @param num_ops
  *   The maximum number of operations to dequeue.
  *
@@ -638,6 +639,7 @@ struct __rte_cache_aligned rte_bbdev {
  * @param ops
  *   Pointer array where operations will be dequeued to. Must have at least
  *   @p num_ops entries
+ *   ie. A pointer to a table of void * pointers (ops) that will be filled.
  * @param num_ops
  *   The maximum number of operations to dequeue.
  *
diff --git a/lib/librte_bbdev/rte_bbdev_op.h b/lib/librte_bbdev/rte_bbdev_op.h
index 1e119a7..062f9ff 100644
--- a/lib/librte_bbdev/rte_bbdev_op.h
+++ b/lib/librte_bbdev/rte_bbdev_op.h
@@ -31,8 +31,11 @@
 #define RTE_BBDEV_TURBO_MAX_TB_SIZE (391656)
 /* Maximum size of Code Block (36.212, Table 5.1.3-3) */
 #define RTE_BBDEV_TURBO_MAX_CB_SIZE (6144)
-/* Maximum size of Code Block  */
+/* Maximum size of Code Block */
 #define RTE_BBDEV_LDPC_MAX_CB_SIZE (8448)
+/* Minimum size of Code Block */
+#define RTE_BBDEV_LDPC_MIN_CB_SIZE (40)
+
 /* Minimum size of Code Block (36.212, Table 5.1.3-3) */
 #define RTE_BBDEV_TURBO_MIN_CB_SIZE (40)
 /* Maximum size of circular buffer */
@@ -177,7 +180,12 @@ enum rte_bbdev_op_ldpcdec_flag_bitmasks {
 	/** Set if a device supports loop-back access to
 	 *  HARQ internal memory. Intended for troubleshooting.
 	 */
-	RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK = (1ULL << 17)
+	RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK = (1ULL << 17),
+	/** Set if a device includes LLR filler bits in the circular buffer
+	 *  for HARQ memory. If not set, it is assumed the filler are not in
+	 *  HARQ memory and handled directory by the LDPC decoder.
+	 */
+	RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_FILLERS = (1ULL << 18)
 };
 
 /** Flags for LDPC encoder operation and capability structure */
-- 
1.8.3.1


^ permalink raw reply	[flat|nested] 115+ messages in thread

* [dpdk-dev] [PATCH v3 02/14] bbdev: expose device HARQ buffer size at device level
  2020-03-04 18:54   ` [dpdk-dev] [PATCH v3 00/14] bbdev new features Nicolas Chautru
  2020-03-04 18:54     ` [dpdk-dev] [PATCH v3 01/14] bbdev: add capability flag for filler bits inclusion in HARQ Nicolas Chautru
@ 2020-03-04 18:54     ` Nicolas Chautru
  2020-03-13 10:47       ` Dave Burley
  2020-03-04 18:54     ` [dpdk-dev] [PATCH v3 03/14] baseband/turbo_sw: fix the exposed LLR decimals assumption Nicolas Chautru
                       ` (12 subsequent siblings)
  14 siblings, 1 reply; 115+ messages in thread
From: Nicolas Chautru @ 2020-03-04 18:54 UTC (permalink / raw)
  To: thomas, akhil.goyal, dev; +Cc: ferruh.yigit, Nic Chautru

From: Nic Chautru <nicolas.chautru@intel.com>

This exposes the HARQ buffer size at the device driver level
instead of using the capability of a specific operation.

This is currently not yet used by a device until
future commit.

Signed-off-by: Nic Chautru <nicolas.chautru@intel.com>
---
 drivers/baseband/turbo_sw/bbdev_turbo_software.c | 2 +-
 lib/librte_bbdev/rte_bbdev.h                     | 2 ++
 lib/librte_bbdev/rte_bbdev_op.h                  | 2 --
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/baseband/turbo_sw/bbdev_turbo_software.c b/drivers/baseband/turbo_sw/bbdev_turbo_software.c
index f2fe7a2..6d5e080 100644
--- a/drivers/baseband/turbo_sw/bbdev_turbo_software.c
+++ b/drivers/baseband/turbo_sw/bbdev_turbo_software.c
@@ -219,7 +219,6 @@ struct turbo_sw_queue {
 					RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE,
 			.llr_size = 8,
 			.llr_decimals = 2,
-			.harq_memory_size = 0,
 			.num_buffers_src =
 					RTE_BBDEV_LDPC_MAX_CODE_BLOCKS,
 			.num_buffers_hard_out =
@@ -251,6 +250,7 @@ struct turbo_sw_queue {
 	dev_info->default_queue_conf = default_queue_conf;
 	dev_info->capabilities = bbdev_capabilities;
 	dev_info->min_alignment = 64;
+	dev_info->harq_buffer_size = 0;
 
 	rte_bbdev_log_debug("got device info from %u\n", dev->data->dev_id);
 }
diff --git a/lib/librte_bbdev/rte_bbdev.h b/lib/librte_bbdev/rte_bbdev.h
index b2da190..38d9d50 100644
--- a/lib/librte_bbdev/rte_bbdev.h
+++ b/lib/librte_bbdev/rte_bbdev.h
@@ -307,6 +307,8 @@ struct rte_bbdev_driver_info {
 	bool queue_intr_supported;
 	/** Minimum alignment of buffers, in bytes */
 	uint16_t min_alignment;
+	/** HARQ memory available in kB */
+	uint32_t harq_buffer_size;
 	/** Default queue configuration used if none is supplied  */
 	struct rte_bbdev_queue_conf default_queue_conf;
 	/** Device operation capabilities */
diff --git a/lib/librte_bbdev/rte_bbdev_op.h b/lib/librte_bbdev/rte_bbdev_op.h
index 062f9ff..8122089 100644
--- a/lib/librte_bbdev/rte_bbdev_op.h
+++ b/lib/librte_bbdev/rte_bbdev_op.h
@@ -712,8 +712,6 @@ struct rte_bbdev_op_cap_ldpc_dec {
 	int8_t llr_size;
 	/** LLR numbers of decimals bit for arithmetic representation */
 	int8_t llr_decimals;
-	/** Amount of memory for HARQ in external DDR in MB */
-	uint16_t harq_memory_size;
 	/** Num input code block buffers */
 	uint16_t num_buffers_src;
 	/** Num hard output code block buffers */
-- 
1.8.3.1


^ permalink raw reply	[flat|nested] 115+ messages in thread

* [dpdk-dev] [PATCH v3 03/14] baseband/turbo_sw: fix the exposed LLR decimals assumption
  2020-03-04 18:54   ` [dpdk-dev] [PATCH v3 00/14] bbdev new features Nicolas Chautru
  2020-03-04 18:54     ` [dpdk-dev] [PATCH v3 01/14] bbdev: add capability flag for filler bits inclusion in HARQ Nicolas Chautru
  2020-03-04 18:54     ` [dpdk-dev] [PATCH v3 02/14] bbdev: expose device HARQ buffer size at device level Nicolas Chautru
@ 2020-03-04 18:54     ` Nicolas Chautru
  2020-03-04 18:54     ` [dpdk-dev] [PATCH v3 04/14] baseband/turbo_sw: support large size code block Nicolas Chautru
                       ` (11 subsequent siblings)
  14 siblings, 0 replies; 115+ messages in thread
From: Nicolas Chautru @ 2020-03-04 18:54 UTC (permalink / raw)
  To: thomas, akhil.goyal, dev; +Cc: ferruh.yigit, Nic Chautru

From: Nic Chautru <nicolas.chautru@intel.com>

The actual LLR representation was incorrectly assumed to be 2
instead of 4. This would impact wireless performance but is not
critical to be back ported on LTS branches.

Fixes: c769c711757a ("baseband/turbo_sw: extend for 5G")

Signed-off-by: Nic Chautru <nicolas.chautru@intel.com>
---
 drivers/baseband/turbo_sw/bbdev_turbo_software.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/baseband/turbo_sw/bbdev_turbo_software.c b/drivers/baseband/turbo_sw/bbdev_turbo_software.c
index 6d5e080..5ca8ca1 100644
--- a/drivers/baseband/turbo_sw/bbdev_turbo_software.c
+++ b/drivers/baseband/turbo_sw/bbdev_turbo_software.c
@@ -218,7 +218,7 @@ struct turbo_sw_queue {
 					RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE |
 					RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE,
 			.llr_size = 8,
-			.llr_decimals = 2,
+			.llr_decimals = 4,
 			.num_buffers_src =
 					RTE_BBDEV_LDPC_MAX_CODE_BLOCKS,
 			.num_buffers_hard_out =
-- 
1.8.3.1


^ permalink raw reply	[flat|nested] 115+ messages in thread

* [dpdk-dev] [PATCH v3 04/14] baseband/turbo_sw: support large size code block
  2020-03-04 18:54   ` [dpdk-dev] [PATCH v3 00/14] bbdev new features Nicolas Chautru
                       ` (2 preceding siblings ...)
  2020-03-04 18:54     ` [dpdk-dev] [PATCH v3 03/14] baseband/turbo_sw: fix the exposed LLR decimals assumption Nicolas Chautru
@ 2020-03-04 18:54     ` Nicolas Chautru
  2020-03-13 16:10       ` Dave Burley
  2020-03-25 10:18       ` Akhil Goyal
  2020-03-04 18:54     ` [dpdk-dev] [PATCH v3 05/14] test-bbdev: rename FPGA LTE macros to be more explicit Nicolas Chautru
                       ` (10 subsequent siblings)
  14 siblings, 2 replies; 115+ messages in thread
From: Nicolas Chautru @ 2020-03-04 18:54 UTC (permalink / raw)
  To: thomas, akhil.goyal, dev; +Cc: ferruh.yigit, Nic Chautru

From: Nic Chautru <nicolas.chautru@intel.com>

This is to support cases when the input data for
decoding a code block is larger than 64kB and would
not fit as a contiguous block of data into one
mbuf. In that case the length from the opearation
supersedes the mbug default structure.

Signed-off-by: Nic Chautru <nicolas.chautru@intel.com>
---
 app/test-bbdev/test_bbdev_perf.c                 | 40 +++++++++++++++++++-----
 doc/guides/rel_notes/release_20_05.rst           |  6 ++++
 drivers/baseband/turbo_sw/bbdev_turbo_software.c | 11 ++++---
 3 files changed, 45 insertions(+), 12 deletions(-)

diff --git a/app/test-bbdev/test_bbdev_perf.c b/app/test-bbdev/test_bbdev_perf.c
index d8db58e..d46966d 100644
--- a/app/test-bbdev/test_bbdev_perf.c
+++ b/app/test-bbdev/test_bbdev_perf.c
@@ -764,6 +764,7 @@ typedef int (test_case_function)(struct active_device *ad,
 {
 	int ret;
 	unsigned int i, j;
+	bool large_input = false;
 
 	for (i = 0; i < n; ++i) {
 		char *data;
@@ -774,24 +775,47 @@ typedef int (test_case_function)(struct active_device *ad,
 				op_type, n * ref_entries->nb_segments,
 				mbuf_pool->size);
 
-		TEST_ASSERT_SUCCESS(((seg->length + RTE_PKTMBUF_HEADROOM) >
-				(uint32_t)UINT16_MAX),
-				"Given data is bigger than allowed mbuf segment size");
-
+		if (seg->length > 64000) {
+			/*
+			 * Special case when DPDK mbuf cannot handle
+			 * the required input size
+			 */
+			printf("Warning: Larger input size than DPDK mbuf %d\n",
+					seg->length);
+			large_input = true;
+		} else {
+			TEST_ASSERT_SUCCESS(
+					((seg->length + RTE_PKTMBUF_HEADROOM)
+					> (uint32_t)UINT16_MAX),
+					"Given data is bigger than allowed mbuf segment size"
+					);
+		}
 		bufs[i].data = m_head;
 		bufs[i].offset = 0;
 		bufs[i].length = 0;
 
 		if ((op_type == DATA_INPUT) || (op_type == DATA_HARQ_INPUT)) {
-			data = rte_pktmbuf_append(m_head, seg->length);
-			TEST_ASSERT_NOT_NULL(data,
+			if ((op_type == DATA_INPUT) && large_input) {
+				/* Allocate a fake overused mbuf */
+				data = rte_malloc(NULL, 128 * 1024, 0);
+				memcpy(data, seg->addr, seg->length);
+				m_head->buf_addr = data;
+				m_head->buf_iova = rte_mem_virt2phy(data);
+				m_head->data_off = 0;
+				m_head->data_len = seg->length;
+			} else {
+				data = rte_pktmbuf_append(m_head, seg->length);
+				TEST_ASSERT_NOT_NULL(data,
 					"Couldn't append %u bytes to mbuf from %d data type mbuf pool",
 					seg->length, op_type);
 
-			TEST_ASSERT(data == RTE_PTR_ALIGN(data, min_alignment),
+				TEST_ASSERT(data == RTE_PTR_ALIGN(
+						data, min_alignment),
 					"Data addr in mbuf (%p) is not aligned to device min alignment (%u)",
 					data, min_alignment);
-			rte_memcpy(data, seg->addr, seg->length);
+				rte_memcpy(data, seg->addr, seg->length);
+			}
+
 			bufs[i].length += seg->length;
 
 			for (j = 1; j < ref_entries->nb_segments; ++j) {
diff --git a/doc/guides/rel_notes/release_20_05.rst b/doc/guides/rel_notes/release_20_05.rst
index 2190eaf..d6c3dfb 100644
--- a/doc/guides/rel_notes/release_20_05.rst
+++ b/doc/guides/rel_notes/release_20_05.rst
@@ -56,6 +56,12 @@ New Features
      Also, make sure to start the actual text at the margin.
      =========================================================
 
+* **Updated the TURBO_SW bbdev PMD.**
+
+  Updated the ``turbo_sw`` bbdev driver with changes including:
+
+  * Support for large size code block not fitting in one mbuf segment.
+  * Exposes the accurate LLR decimal assumption.
 
 Removed Items
 -------------
diff --git a/drivers/baseband/turbo_sw/bbdev_turbo_software.c b/drivers/baseband/turbo_sw/bbdev_turbo_software.c
index 5ca8ca1..ea3fecb 100644
--- a/drivers/baseband/turbo_sw/bbdev_turbo_software.c
+++ b/drivers/baseband/turbo_sw/bbdev_turbo_software.c
@@ -1335,7 +1335,7 @@ struct turbo_sw_queue {
 
 static inline void
 process_ldpc_dec_cb(struct turbo_sw_queue *q, struct rte_bbdev_dec_op *op,
-		uint8_t c, uint16_t out_length, uint16_t e,
+		uint8_t c, uint16_t out_length, uint32_t e,
 		struct rte_mbuf *m_in,
 		struct rte_mbuf *m_out_head, struct rte_mbuf *m_out,
 		struct rte_mbuf *m_harq_in,
@@ -1617,8 +1617,8 @@ struct turbo_sw_queue {
 		struct rte_bbdev_stats *queue_stats)
 {
 	uint8_t c, r = 0;
-	uint16_t e, out_length;
-	uint16_t crc24_overlap = 0;
+	uint32_t e;
+	uint16_t out_length, crc24_overlap = 0;
 	struct rte_bbdev_op_ldpc_dec *dec = &op->ldpc_dec;
 	struct rte_mbuf *m_in = dec->input.data;
 	struct rte_mbuf *m_harq_in = dec->harq_combined_input.data;
@@ -1661,7 +1661,10 @@ struct turbo_sw_queue {
 			e = (r < dec->tb_params.cab) ?
 				dec->tb_params.ea : dec->tb_params.eb;
 
-		seg_total_left = rte_pktmbuf_data_len(m_in) - in_offset;
+		if (e < 64000) /* Special case handling when overusing mbuf */
+			seg_total_left = rte_pktmbuf_data_len(m_in) - in_offset;
+		else
+			seg_total_left = e;
 
 		process_ldpc_dec_cb(q, op, c, out_length, e,
 				m_in, m_out_head, m_out,
-- 
1.8.3.1


^ permalink raw reply	[flat|nested] 115+ messages in thread

* [dpdk-dev] [PATCH v3 05/14] test-bbdev: rename FPGA LTE macros to be more explicit
  2020-03-04 18:54   ` [dpdk-dev] [PATCH v3 00/14] bbdev new features Nicolas Chautru
                       ` (3 preceding siblings ...)
  2020-03-04 18:54     ` [dpdk-dev] [PATCH v3 04/14] baseband/turbo_sw: support large size code block Nicolas Chautru
@ 2020-03-04 18:54     ` Nicolas Chautru
  2020-03-13 10:55       ` Dave Burley
  2020-03-04 18:54     ` [dpdk-dev] [PATCH v3 06/14] test-bbdev: support HARQ validation Nicolas Chautru
                       ` (9 subsequent siblings)
  14 siblings, 1 reply; 115+ messages in thread
From: Nicolas Chautru @ 2020-03-04 18:54 UTC (permalink / raw)
  To: thomas, akhil.goyal, dev; +Cc: ferruh.yigit, Nic Chautru

From: Nic Chautru <nicolas.chautru@intel.com>

Self-contained and cosmetic renaming of macro
so that to be more explicit for future extension.

Signed-off-by: Nic Chautru <nicolas.chautru@intel.com>
---
 app/test-bbdev/test_bbdev_perf.c | 51 +++++++++++++++-------------------------
 1 file changed, 19 insertions(+), 32 deletions(-)

diff --git a/app/test-bbdev/test_bbdev_perf.c b/app/test-bbdev/test_bbdev_perf.c
index d46966d..aa8bb71 100644
--- a/app/test-bbdev/test_bbdev_perf.c
+++ b/app/test-bbdev/test_bbdev_perf.c
@@ -18,10 +18,6 @@
 #include <rte_hexdump.h>
 #include <rte_interrupts.h>
 
-#ifdef RTE_LIBRTE_PMD_BBDEV_FPGA_LTE_FEC
-#include <fpga_lte_fec.h>
-#endif
-
 #include "main.h"
 #include "test_bbdev_vector.h"
 
@@ -31,15 +27,16 @@
 #define TEST_REPETITIONS 1000
 
 #ifdef RTE_LIBRTE_PMD_BBDEV_FPGA_LTE_FEC
-#define FPGA_PF_DRIVER_NAME ("intel_fpga_lte_fec_pf")
-#define FPGA_VF_DRIVER_NAME ("intel_fpga_lte_fec_vf")
-#define VF_UL_QUEUE_VALUE 4
-#define VF_DL_QUEUE_VALUE 4
-#define UL_BANDWIDTH 3
-#define DL_BANDWIDTH 3
-#define UL_LOAD_BALANCE 128
-#define DL_LOAD_BALANCE 128
-#define FLR_TIMEOUT 610
+#include <fpga_lte_fec.h>
+#define FPGA_LTE_PF_DRIVER_NAME ("intel_fpga_lte_fec_pf")
+#define FPGA_LTE_VF_DRIVER_NAME ("intel_fpga_lte_fec_vf")
+#define VF_UL_4G_QUEUE_VALUE 4
+#define VF_DL_4G_QUEUE_VALUE 4
+#define UL_4G_BANDWIDTH 3
+#define DL_4G_BANDWIDTH 3
+#define UL_4G_LOAD_BALANCE 128
+#define DL_4G_LOAD_BALANCE 128
+#define FLR_4G_TIMEOUT 610
 #endif
 
 #define OPS_CACHE_SIZE 256U
@@ -521,11 +518,11 @@ typedef int (test_case_function)(struct active_device *ad,
  */
 #ifdef RTE_LIBRTE_PMD_BBDEV_FPGA_LTE_FEC
 	if ((get_init_device() == true) &&
-		(!strcmp(info->drv.driver_name, FPGA_PF_DRIVER_NAME))) {
+		(!strcmp(info->drv.driver_name, FPGA_LTE_PF_DRIVER_NAME))) {
 		struct fpga_lte_fec_conf conf;
 		unsigned int i;
 
-		printf("Configure FPGA FEC Driver %s with default values\n",
+		printf("Configure FPGA LTE FEC Driver %s with default values\n",
 				info->drv.driver_name);
 
 		/* clear default configuration before initialization */
@@ -539,22 +536,22 @@ typedef int (test_case_function)(struct active_device *ad,
 
 		for (i = 0; i < FPGA_LTE_FEC_NUM_VFS; ++i) {
 			/* Number of UL queues per VF (fpga supports 8 VFs) */
-			conf.vf_ul_queues_number[i] = VF_UL_QUEUE_VALUE;
+			conf.vf_ul_queues_number[i] = VF_UL_4G_QUEUE_VALUE;
 			/* Number of DL queues per VF (fpga supports 8 VFs) */
-			conf.vf_dl_queues_number[i] = VF_DL_QUEUE_VALUE;
+			conf.vf_dl_queues_number[i] = VF_DL_4G_QUEUE_VALUE;
 		}
 
 		/* UL bandwidth. Needed for schedule algorithm */
-		conf.ul_bandwidth = UL_BANDWIDTH;
+		conf.ul_bandwidth = UL_4G_BANDWIDTH;
 		/* DL bandwidth */
-		conf.dl_bandwidth = DL_BANDWIDTH;
+		conf.dl_bandwidth = DL_4G_BANDWIDTH;
 
 		/* UL & DL load Balance Factor to 64 */
-		conf.ul_load_balance = UL_LOAD_BALANCE;
-		conf.dl_load_balance = DL_LOAD_BALANCE;
+		conf.ul_load_balance = UL_4G_LOAD_BALANCE;
+		conf.dl_load_balance = DL_4G_LOAD_BALANCE;
 
 		/**< FLR timeout value */
-		conf.flr_time_out = FLR_TIMEOUT;
+		conf.flr_time_out = FLR_4G_TIMEOUT;
 
 		/* setup FPGA PF with configuration information */
 		ret = fpga_lte_fec_configure(info->dev_name, &conf);
@@ -2862,11 +2859,6 @@ typedef int (test_case_function)(struct active_device *ad,
 
 		start_time = rte_rdtsc_precise();
 
-		/*
-		 * printf("Latency Debug %d\n",
-		 * ops_enq[0]->ldpc_enc.cb_params.z_c); REMOVEME
-		 */
-
 		enq = rte_bbdev_enqueue_ldpc_enc_ops(dev_id, queue_id,
 				&ops_enq[enq], burst_sz);
 		TEST_ASSERT(enq == burst_sz,
@@ -2892,11 +2884,6 @@ typedef int (test_case_function)(struct active_device *ad,
 			TEST_ASSERT_SUCCESS(ret, "Validation failed!");
 		}
 
-		/*
-		 * printf("Ready to free - deq %d num_to_process %d\n", FIXME
-		 *		deq, num_to_process);
-		 * printf("cache %d\n", ops_enq[0]->mempool->cache_size);
-		 */
 		rte_bbdev_enc_op_free_bulk(ops_enq, deq);
 		dequeued += deq;
 	}
-- 
1.8.3.1


^ permalink raw reply	[flat|nested] 115+ messages in thread

* [dpdk-dev] [PATCH v3 06/14] test-bbdev: support HARQ validation
  2020-03-04 18:54   ` [dpdk-dev] [PATCH v3 00/14] bbdev new features Nicolas Chautru
                       ` (4 preceding siblings ...)
  2020-03-04 18:54     ` [dpdk-dev] [PATCH v3 05/14] test-bbdev: rename FPGA LTE macros to be more explicit Nicolas Chautru
@ 2020-03-04