From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id F0061A058E; Thu, 26 Mar 2020 03:47:00 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id CC0BF1C06D; Thu, 26 Mar 2020 03:46:29 +0100 (CET) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by dpdk.org (Postfix) with ESMTP id 238EC1C02A for ; Thu, 26 Mar 2020 03:46:22 +0100 (CET) IronPort-SDR: 0LhYhFj6G+Nhkmxy7XRN2gsJQAhclII3bl9rqwnrfXpf4gq4Ymj+Af4XGhbDyUqqpkqRCnHxsk 0qxI6ZOzqkHw== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Mar 2020 19:46:21 -0700 IronPort-SDR: UWPskop/vReQ4puEfsL4uOR4Us4qs4TlhbDHgQGy1vDMLtKgebjlfqg93c+MLmOVhWfwyCxIz1 cFXjzcg23dew== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.72,306,1580803200"; d="scan'208";a="247400827" Received: from skx-5gnr-sc12-4.sc.intel.com ([172.25.69.210]) by orsmga003.jf.intel.com with ESMTP; 25 Mar 2020 19:46:21 -0700 From: Nicolas Chautru To: thomas@monjalon.net, akhil.goyal@nxp.com, dev@dpdk.org Cc: ferruh.yigit@intel.com, Nic Chautru Date: Wed, 25 Mar 2020 19:45:54 -0700 Message-Id: <1585190759-71604-6-git-send-email-nicolas.chautru@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1585190759-71604-1-git-send-email-nicolas.chautru@intel.com> References: <1582778348-113547-15-git-send-email-nicolas.chautru@intel.com> <1585190759-71604-1-git-send-email-nicolas.chautru@intel.com> Subject: [dpdk-dev] [PATCH v4 05/10] test-bbdev: rename FPGA LTE macros to be more explicit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Nic Chautru Self-contained and cosmetic renaming of macro so that to be more explicit for future extension. Signed-off-by: Nic Chautru --- app/test-bbdev/test_bbdev_perf.c | 51 +++++++++++++++------------------------- 1 file changed, 19 insertions(+), 32 deletions(-) diff --git a/app/test-bbdev/test_bbdev_perf.c b/app/test-bbdev/test_bbdev_perf.c index e998d0b..b17fc95 100644 --- a/app/test-bbdev/test_bbdev_perf.c +++ b/app/test-bbdev/test_bbdev_perf.c @@ -18,10 +18,6 @@ #include #include -#ifdef RTE_LIBRTE_PMD_BBDEV_FPGA_LTE_FEC -#include -#endif - #include "main.h" #include "test_bbdev_vector.h" @@ -31,15 +27,16 @@ #define TEST_REPETITIONS 1000 #ifdef RTE_LIBRTE_PMD_BBDEV_FPGA_LTE_FEC -#define FPGA_PF_DRIVER_NAME ("intel_fpga_lte_fec_pf") -#define FPGA_VF_DRIVER_NAME ("intel_fpga_lte_fec_vf") -#define VF_UL_QUEUE_VALUE 4 -#define VF_DL_QUEUE_VALUE 4 -#define UL_BANDWIDTH 3 -#define DL_BANDWIDTH 3 -#define UL_LOAD_BALANCE 128 -#define DL_LOAD_BALANCE 128 -#define FLR_TIMEOUT 610 +#include +#define FPGA_LTE_PF_DRIVER_NAME ("intel_fpga_lte_fec_pf") +#define FPGA_LTE_VF_DRIVER_NAME ("intel_fpga_lte_fec_vf") +#define VF_UL_4G_QUEUE_VALUE 4 +#define VF_DL_4G_QUEUE_VALUE 4 +#define UL_4G_BANDWIDTH 3 +#define DL_4G_BANDWIDTH 3 +#define UL_4G_LOAD_BALANCE 128 +#define DL_4G_LOAD_BALANCE 128 +#define FLR_4G_TIMEOUT 610 #endif #define OPS_CACHE_SIZE 256U @@ -521,11 +518,11 @@ typedef int (test_case_function)(struct active_device *ad, */ #ifdef RTE_LIBRTE_PMD_BBDEV_FPGA_LTE_FEC if ((get_init_device() == true) && - (!strcmp(info->drv.driver_name, FPGA_PF_DRIVER_NAME))) { + (!strcmp(info->drv.driver_name, FPGA_LTE_PF_DRIVER_NAME))) { struct fpga_lte_fec_conf conf; unsigned int i; - printf("Configure FPGA FEC Driver %s with default values\n", + printf("Configure FPGA LTE FEC Driver %s with default values\n", info->drv.driver_name); /* clear default configuration before initialization */ @@ -539,22 +536,22 @@ typedef int (test_case_function)(struct active_device *ad, for (i = 0; i < FPGA_LTE_FEC_NUM_VFS; ++i) { /* Number of UL queues per VF (fpga supports 8 VFs) */ - conf.vf_ul_queues_number[i] = VF_UL_QUEUE_VALUE; + conf.vf_ul_queues_number[i] = VF_UL_4G_QUEUE_VALUE; /* Number of DL queues per VF (fpga supports 8 VFs) */ - conf.vf_dl_queues_number[i] = VF_DL_QUEUE_VALUE; + conf.vf_dl_queues_number[i] = VF_DL_4G_QUEUE_VALUE; } /* UL bandwidth. Needed for schedule algorithm */ - conf.ul_bandwidth = UL_BANDWIDTH; + conf.ul_bandwidth = UL_4G_BANDWIDTH; /* DL bandwidth */ - conf.dl_bandwidth = DL_BANDWIDTH; + conf.dl_bandwidth = DL_4G_BANDWIDTH; /* UL & DL load Balance Factor to 64 */ - conf.ul_load_balance = UL_LOAD_BALANCE; - conf.dl_load_balance = DL_LOAD_BALANCE; + conf.ul_load_balance = UL_4G_LOAD_BALANCE; + conf.dl_load_balance = DL_4G_LOAD_BALANCE; /**< FLR timeout value */ - conf.flr_time_out = FLR_TIMEOUT; + conf.flr_time_out = FLR_4G_TIMEOUT; /* setup FPGA PF with configuration information */ ret = fpga_lte_fec_configure(info->dev_name, &conf); @@ -2856,11 +2853,6 @@ typedef int (test_case_function)(struct active_device *ad, start_time = rte_rdtsc_precise(); - /* - * printf("Latency Debug %d\n", - * ops_enq[0]->ldpc_enc.cb_params.z_c); REMOVEME - */ - enq = rte_bbdev_enqueue_ldpc_enc_ops(dev_id, queue_id, &ops_enq[enq], burst_sz); TEST_ASSERT(enq == burst_sz, @@ -2886,11 +2878,6 @@ typedef int (test_case_function)(struct active_device *ad, TEST_ASSERT_SUCCESS(ret, "Validation failed!"); } - /* - * printf("Ready to free - deq %d num_to_process %d\n", FIXME - * deq, num_to_process); - * printf("cache %d\n", ops_enq[0]->mempool->cache_size); - */ rte_bbdev_enc_op_free_bulk(ops_enq, deq); dequeued += deq; } -- 1.8.3.1