From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id B7C73A058E; Thu, 26 Mar 2020 04:28:18 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id F22041C0C2; Thu, 26 Mar 2020 04:28:13 +0100 (CET) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id CE73C1C065 for ; Thu, 26 Mar 2020 04:28:10 +0100 (CET) IronPort-SDR: TNedQuU+kDqeWQMKoJ0+Gre7McMsnUQRvBiD7xaH28VO4O0CEHme/lwf7h5FxOsVGkDr7MsQoB u7NT3oHTk1cw== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Mar 2020 20:28:09 -0700 IronPort-SDR: 7opQKs0HxSHcS8n87eyqEs0NTXkSI3ingerM71W7cUWl29dO80rVUkvM0d2dQNRqgbn+2MFMwH gfIQ2r1brl4A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.72,306,1580803200"; d="scan'208";a="265733787" Received: from skx-5gnr-sc12-4.sc.intel.com ([172.25.69.210]) by orsmga002.jf.intel.com with ESMTP; 25 Mar 2020 20:28:09 -0700 From: Nicolas Chautru To: thomas@monjalon.net, akhil.goyal@nxp.com, dev@dpdk.org Cc: ferruh.yigit@intel.com, Nic Chautru Date: Wed, 25 Mar 2020 20:27:39 -0700 Message-Id: <1585193268-74468-2-git-send-email-nicolas.chautru@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1585193268-74468-1-git-send-email-nicolas.chautru@intel.com> References: <1582778348-113547-15-git-send-email-nicolas.chautru@intel.com> <1585193268-74468-1-git-send-email-nicolas.chautru@intel.com> Subject: [dpdk-dev] [PATCH v5 01/10] bbdev: add capability flag for filler bits inclusion in HARQ X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Nic Chautru Adding capability flag for device variants when HARQ buffer may or may not include the filler bits. Minor cosmetic changes in same file. Signed-off-by: Nic Chautru --- lib/librte_bbdev/rte_bbdev.h | 2 ++ lib/librte_bbdev/rte_bbdev_op.h | 12 ++++++++++-- 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/lib/librte_bbdev/rte_bbdev.h b/lib/librte_bbdev/rte_bbdev.h index 591fb79..b2da190 100644 --- a/lib/librte_bbdev/rte_bbdev.h +++ b/lib/librte_bbdev/rte_bbdev.h @@ -607,6 +607,7 @@ struct __rte_cache_aligned rte_bbdev { * @param ops * Pointer array where operations will be dequeued to. Must have at least * @p num_ops entries + * ie. A pointer to a table of void * pointers (ops) that will be filled. * @param num_ops * The maximum number of operations to dequeue. * @@ -638,6 +639,7 @@ struct __rte_cache_aligned rte_bbdev { * @param ops * Pointer array where operations will be dequeued to. Must have at least * @p num_ops entries + * ie. A pointer to a table of void * pointers (ops) that will be filled. * @param num_ops * The maximum number of operations to dequeue. * diff --git a/lib/librte_bbdev/rte_bbdev_op.h b/lib/librte_bbdev/rte_bbdev_op.h index 1e119a7..c8a354e 100644 --- a/lib/librte_bbdev/rte_bbdev_op.h +++ b/lib/librte_bbdev/rte_bbdev_op.h @@ -31,8 +31,11 @@ #define RTE_BBDEV_TURBO_MAX_TB_SIZE (391656) /* Maximum size of Code Block (36.212, Table 5.1.3-3) */ #define RTE_BBDEV_TURBO_MAX_CB_SIZE (6144) -/* Maximum size of Code Block */ +/* Maximum size of Code Block */ #define RTE_BBDEV_LDPC_MAX_CB_SIZE (8448) +/* Minimum size of Code Block */ +#define RTE_BBDEV_LDPC_MIN_CB_SIZE (40) + /* Minimum size of Code Block (36.212, Table 5.1.3-3) */ #define RTE_BBDEV_TURBO_MIN_CB_SIZE (40) /* Maximum size of circular buffer */ @@ -177,7 +180,12 @@ enum rte_bbdev_op_ldpcdec_flag_bitmasks { /** Set if a device supports loop-back access to * HARQ internal memory. Intended for troubleshooting. */ - RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK = (1ULL << 17) + RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK = (1ULL << 17), + /** Set if a device includes LLR filler bits in the circular buffer + * for HARQ memory. If not set, it is assumed the filler bits are not + * in HARQ memory and handled directly by the LDPC decoder. + */ + RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_FILLERS = (1ULL << 18) }; /** Flags for LDPC encoder operation and capability structure */ -- 1.8.3.1