From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 35FC4A0562; Mon, 30 Mar 2020 02:05:19 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 3DB5C1C0C0; Mon, 30 Mar 2020 02:04:10 +0200 (CEST) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by dpdk.org (Postfix) with ESMTP id 0EE234C93 for ; Mon, 30 Mar 2020 02:03:53 +0200 (CEST) IronPort-SDR: 6s4ukwrpoGe0QluOkkpIQ8ulHk2fPENrs9ahUbY6zhJFvWHcPVAl8/DH+mg9d6Vd7kISLaV4Pn 6TUpGz4GVmgQ== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Mar 2020 17:03:52 -0700 IronPort-SDR: PvBNaK8fNeQdv6147XdmmKDR74xUX+2uotkAC39ccpoX7FCuxFg/tkU+Brd2YwG9mfgLm/bw3A xMpdslyHQb+g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.72,322,1580803200"; d="scan'208";a="248455362" Received: from skx-5gnr-sc12-4.sc.intel.com ([172.25.69.210]) by orsmga003.jf.intel.com with ESMTP; 29 Mar 2020 17:03:51 -0700 From: Nicolas Chautru To: dev@dpdk.org, akhil.goyal@nxp.com Cc: bruce.richardson@intel.com, Nicolas Chautru Date: Sun, 29 Mar 2020 17:02:58 -0700 Message-Id: <1585526580-113508-12-git-send-email-nicolas.chautru@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1585526580-113508-1-git-send-email-nicolas.chautru@intel.com> References: <1585526580-113508-1-git-send-email-nicolas.chautru@intel.com> Subject: [dpdk-dev] [PATCH v2 11/13] baseband/fpga_5gnr_fec: add harq loopback capability X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Adding optional capability to support loopback preloading and check of the extern HARQ memory. This function is required to run the HARQ bit exact test successfully. Signed-off-by: Nicolas Chautru --- drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c | 171 +++++++++++++++++++++ 1 file changed, 171 insertions(+) diff --git a/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c b/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c index 2559da5..b8cad1a 100644 --- a/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c +++ b/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c @@ -417,6 +417,7 @@ RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE | RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_IN_ENABLE | RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_OUT_ENABLE | + RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK | RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_FILLERS, .llr_size = 6, .llr_decimals = 2, @@ -1148,6 +1149,140 @@ #endif static inline int +fpga_harq_write_loopback(struct fpga_5gnr_fec_device *fpga_dev, + struct rte_mbuf *harq_input, uint16_t harq_in_length, + uint32_t harq_in_offset, uint32_t harq_out_offset) +{ + uint32_t out_offset = harq_out_offset; + uint32_t in_offset = harq_in_offset; + uint32_t left_length = harq_in_length; + uint32_t reg_32, increment = 0; + uint64_t *input = NULL; + uint32_t last_transaction = left_length + % FPGA_5GNR_FEC_DDR_WR_DATA_LEN_IN_BYTES; + uint64_t last_word; + + if (last_transaction > 0) + left_length -= last_transaction; + + /* + * Get HARQ buffer size for each VF/PF: When 0x00, there is no + * available DDR space for the corresponding VF/PF. + */ + reg_32 = fpga_reg_read_32(fpga_dev->mmio_base, + FPGA_5GNR_FEC_HARQ_BUF_SIZE_REGS); + if (reg_32 < harq_in_length) { + left_length = reg_32; + rte_bbdev_log(ERR, "HARQ in length > HARQ buffer size\n"); + } + + input = (uint64_t *)rte_pktmbuf_mtod_offset(harq_input, + uint8_t *, in_offset); + + while (left_length > 0) { + if (fpga_reg_read_8(fpga_dev->mmio_base, + FPGA_5GNR_FEC_DDR4_ADDR_RDY_REGS) == 1) { + fpga_reg_write_32(fpga_dev->mmio_base, + FPGA_5GNR_FEC_DDR4_WR_ADDR_REGS, + out_offset); + fpga_reg_write_64(fpga_dev->mmio_base, + FPGA_5GNR_FEC_DDR4_WR_DATA_REGS, + input[increment]); + left_length -= FPGA_5GNR_FEC_DDR_WR_DATA_LEN_IN_BYTES; + out_offset += FPGA_5GNR_FEC_DDR_WR_DATA_LEN_IN_BYTES; + increment++; + fpga_reg_write_8(fpga_dev->mmio_base, + FPGA_5GNR_FEC_DDR4_WR_DONE_REGS, 1); + } + } + while (last_transaction > 0) { + if (fpga_reg_read_8(fpga_dev->mmio_base, + FPGA_5GNR_FEC_DDR4_ADDR_RDY_REGS) == 1) { + fpga_reg_write_32(fpga_dev->mmio_base, + FPGA_5GNR_FEC_DDR4_WR_ADDR_REGS, + out_offset); + last_word = input[increment]; + last_word &= (uint64_t)(1 << (last_transaction * 4)) + - 1; + fpga_reg_write_64(fpga_dev->mmio_base, + FPGA_5GNR_FEC_DDR4_WR_DATA_REGS, + last_word); + fpga_reg_write_8(fpga_dev->mmio_base, + FPGA_5GNR_FEC_DDR4_WR_DONE_REGS, 1); + last_transaction = 0; + } + } + return 1; +} + +static inline int +fpga_harq_read_loopback(struct fpga_5gnr_fec_device *fpga_dev, + struct rte_mbuf *harq_output, uint16_t harq_in_length, + uint32_t harq_in_offset, uint32_t harq_out_offset) +{ + uint32_t left_length, in_offset = harq_in_offset; + uint64_t reg; + uint32_t increment = 0; + uint64_t *input = NULL; + uint32_t last_transaction = harq_in_length + % FPGA_5GNR_FEC_DDR_WR_DATA_LEN_IN_BYTES; + + if (last_transaction > 0) + harq_in_length += (8 - last_transaction); + + reg = fpga_reg_read_32(fpga_dev->mmio_base, + FPGA_5GNR_FEC_HARQ_BUF_SIZE_REGS); + if (reg < harq_in_length) { + harq_in_length = reg; + rte_bbdev_log(ERR, "HARQ in length > HARQ buffer size\n"); + } + + if (!mbuf_append(harq_output, harq_output, harq_in_length)) { + rte_bbdev_log(ERR, "HARQ output buffer warning %d %d\n", + harq_output->buf_len - + rte_pktmbuf_headroom(harq_output), + harq_in_length); + harq_in_length = harq_output->buf_len - + rte_pktmbuf_headroom(harq_output); + if (!mbuf_append(harq_output, harq_output, harq_in_length)) { + rte_bbdev_log(ERR, "HARQ output buffer issue %d %d\n", + harq_output->buf_len, harq_in_length); + return -1; + } + } + left_length = harq_in_length; + + input = (uint64_t *)rte_pktmbuf_mtod_offset(harq_output, + uint8_t *, harq_out_offset); + + while (left_length > 0) { + fpga_reg_write_32(fpga_dev->mmio_base, + FPGA_5GNR_FEC_DDR4_RD_ADDR_REGS, in_offset); + fpga_reg_write_8(fpga_dev->mmio_base, + FPGA_5GNR_FEC_DDR4_RD_DONE_REGS, 1); + reg = fpga_reg_read_8(fpga_dev->mmio_base, + FPGA_5GNR_FEC_DDR4_RD_RDY_REGS); + while (reg != 1) { + reg = fpga_reg_read_8(fpga_dev->mmio_base, + FPGA_5GNR_FEC_DDR4_RD_RDY_REGS); + if (reg == FPGA_DDR_OVERFLOW) { + rte_bbdev_log(ERR, + "Read address is overflow!\n"); + return -1; + } + } + input[increment] = fpga_reg_read_64(fpga_dev->mmio_base, + FPGA_5GNR_FEC_DDR4_RD_DATA_REGS); + left_length -= FPGA_5GNR_FEC_DDR_RD_DATA_LEN_IN_BYTES; + in_offset += FPGA_5GNR_FEC_DDR_WR_DATA_LEN_IN_BYTES; + increment++; + fpga_reg_write_8(fpga_dev->mmio_base, + FPGA_5GNR_FEC_DDR4_RD_DONE_REGS, 0); + } + return 1; +} + +static inline int enqueue_ldpc_enc_one_op_cb(struct fpga_queue *q, struct rte_bbdev_enc_op *op, uint16_t desc_offset) { @@ -1275,6 +1410,42 @@ ring_offset = ((q->tail + desc_offset) & q->sw_ring_wrap_mask); desc = q->ring_addr + ring_offset; + if (check_bit(dec->op_flags, + RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK)) { + struct rte_mbuf *harq_in = dec->harq_combined_input.data; + struct rte_mbuf *harq_out = dec->harq_combined_output.data; + harq_in_length = dec->harq_combined_input.length; + uint32_t harq_in_offset = dec->harq_combined_input.offset; + uint32_t harq_out_offset = dec->harq_combined_output.offset; + + if (check_bit(dec->op_flags, + RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_OUT_ENABLE + )) { + ret = fpga_harq_write_loopback(q->d, harq_in, + harq_in_length, harq_in_offset, + harq_out_offset); + } else if (check_bit(dec->op_flags, + RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_IN_ENABLE + )) { + ret = fpga_harq_read_loopback(q->d, harq_out, + harq_in_length, harq_in_offset, + harq_out_offset); + dec->harq_combined_output.length = harq_in_length; + } else { + rte_bbdev_log(ERR, "OP flag Err!"); + ret = -1; + } + /* Set descriptor for dequeue */ + desc->dec_req.done = 1; + desc->dec_req.error = 0; + desc->dec_req.op_addr = op; + desc->dec_req.cbs_in_op = 1; + /* Mark this dummy descriptor to be dropped by HW */ + desc->dec_req.desc_idx = (ring_offset + 1) + & q->sw_ring_wrap_mask; + return ret; /* Error or number of CB */ + } + if (m_in == NULL || m_out == NULL) { rte_bbdev_log(ERR, "Invalid mbuf pointer"); op->status = 1 << RTE_BBDEV_DATA_ERROR; -- 1.8.3.1