From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 22EB5A0562; Mon, 30 Mar 2020 02:04:23 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 23FE51BFD7; Mon, 30 Mar 2020 02:03:59 +0200 (CEST) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by dpdk.org (Postfix) with ESMTP id 41124FFA for ; Mon, 30 Mar 2020 02:03:52 +0200 (CEST) IronPort-SDR: 7uasXgEsHULJybSn5NbDzgLNU7OVFhblVjf4kfIXJYcCyAeeF+t41PeClQHZdIwQ6QMY8uwH0r Ig8GE5nih4fg== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Mar 2020 17:03:51 -0700 IronPort-SDR: dya0qpf4ZHYil3QO8HuL5X3w7B3gpHL1tQ4TYuRayDeXyc9gBLP1IdSncA1f4pqbkpniQJA+9n xnh/4kfGn07A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.72,322,1580803200"; d="scan'208";a="248455343" Received: from skx-5gnr-sc12-4.sc.intel.com ([172.25.69.210]) by orsmga003.jf.intel.com with ESMTP; 29 Mar 2020 17:03:50 -0700 From: Nicolas Chautru To: dev@dpdk.org, akhil.goyal@nxp.com Cc: bruce.richardson@intel.com, Nicolas Chautru Date: Sun, 29 Mar 2020 17:02:52 -0700 Message-Id: <1585526580-113508-6-git-send-email-nicolas.chautru@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1585526580-113508-1-git-send-email-nicolas.chautru@intel.com> References: <1585526580-113508-1-git-send-email-nicolas.chautru@intel.com> Subject: [dpdk-dev] [PATCH v2 05/13] baseband/fpga_5gnr_fec: add device info_get function X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add in the "info_get" function to the driver, to allow us to query the device. No capability are available yet. Linking bbdev-test to support the PMD with null capability. Signed-off-by: Nicolas Chautru --- app/test-bbdev/Makefile | 3 ++ app/test-bbdev/meson.build | 3 ++ drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c | 62 ++++++++++++++++++++++ 3 files changed, 68 insertions(+) diff --git a/app/test-bbdev/Makefile b/app/test-bbdev/Makefile index c53982f..e951302 100644 --- a/app/test-bbdev/Makefile +++ b/app/test-bbdev/Makefile @@ -24,5 +24,8 @@ LDLIBS += -lm ifeq ($(CONFIG_RTE_LIBRTE_PMD_BBDEV_FPGA_LTE_FEC),y) LDLIBS += -lrte_pmd_bbdev_fpga_lte_fec endif +ifeq ($(CONFIG_RTE_LIBRTE_PMD_BBDEV_FPGA_5GNR_FEC),y) +LDLIBS += -lrte_pmd_bbdev_fpga_5gnr_fec +endif include $(RTE_SDK)/mk/rte.app.mk diff --git a/app/test-bbdev/meson.build b/app/test-bbdev/meson.build index 4f53a2e..e57e019 100644 --- a/app/test-bbdev/meson.build +++ b/app/test-bbdev/meson.build @@ -10,3 +10,6 @@ deps += ['bbdev', 'bus_vdev'] if dpdk_conf.has('RTE_LIBRTE_PMD_BBDEV_FPGA_LTE_FEC') deps += ['pmd_bbdev_fpga_lte_fec'] endif +if dpdk_conf.has('RTE_LIBRTE_PMD_BBDEV_FPGA_5GNR_FEC') + deps += ['pmd_bbdev_fpga_5gnr_fec'] +endif \ No newline at end of file diff --git a/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c b/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c index ee9577d..595107e 100644 --- a/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c +++ b/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c @@ -22,14 +22,76 @@ /* 5GNR SW PMD logging ID */ static int fpga_5gnr_fec_logtype; +/* Read a register of FPGA 5GNR FEC device */ +static uint32_t +fpga_reg_read_32(void *mmio_base, uint32_t offset) +{ + void *reg_addr = RTE_PTR_ADD(mmio_base, offset); + uint32_t ret = *((volatile uint32_t *)(reg_addr)); + return rte_le_to_cpu_32(ret); +} + static int fpga_dev_close(struct rte_bbdev *dev __rte_unused) { return 0; } +static void +fpga_dev_info_get(struct rte_bbdev *dev, + struct rte_bbdev_driver_info *dev_info) +{ + struct fpga_5gnr_fec_device *d = dev->data->dev_private; + uint32_t q_id = 0; + + static const struct rte_bbdev_op_cap bbdev_capabilities[] = { + RTE_BBDEV_END_OF_CAPABILITIES_LIST() + }; + + /* Check the HARQ DDR size available */ + uint8_t timeout_counter = 0; + uint32_t harq_buf_ready = fpga_reg_read_32(d->mmio_base, + FPGA_5GNR_FEC_HARQ_BUF_SIZE_RDY_REGS); + while (harq_buf_ready != 1) { + usleep(FPGA_TIMEOUT_CHECK_INTERVAL); + timeout_counter++; + harq_buf_ready = fpga_reg_read_32(d->mmio_base, + FPGA_5GNR_FEC_HARQ_BUF_SIZE_RDY_REGS); + if (timeout_counter > FPGA_HARQ_RDY_TIMEOUT) { + rte_bbdev_log(ERR, "HARQ Buffer not ready %d", + harq_buf_ready); + harq_buf_ready = 1; + } + } + uint32_t harq_buf_size = fpga_reg_read_32(d->mmio_base, + FPGA_5GNR_FEC_HARQ_BUF_SIZE_REGS); + + static struct rte_bbdev_queue_conf default_queue_conf; + default_queue_conf.socket = dev->data->socket_id; + default_queue_conf.queue_size = FPGA_RING_MAX_SIZE; + + dev_info->driver_name = dev->device->driver->name; + dev_info->queue_size_lim = FPGA_RING_MAX_SIZE; + dev_info->hardware_accelerated = true; + dev_info->min_alignment = 64; + dev_info->harq_buffer_size = (harq_buf_size >> 10) + 1; + dev_info->default_queue_conf = default_queue_conf; + dev_info->capabilities = bbdev_capabilities; + dev_info->cpu_flag_reqs = NULL; + + /* Calculates number of queues assigned to device */ + dev_info->max_num_queues = 0; + for (q_id = 0; q_id < FPGA_TOTAL_NUM_QUEUES; ++q_id) { + uint32_t hw_q_id = fpga_reg_read_32(d->mmio_base, + FPGA_5GNR_FEC_QUEUE_MAP + (q_id << 2)); + if (hw_q_id != FPGA_INVALID_HW_QUEUE_ID) + dev_info->max_num_queues++; + } +} + static const struct rte_bbdev_ops fpga_ops = { .close = fpga_dev_close, + .info_get = fpga_dev_info_get, }; /* Initialization Function */ -- 1.8.3.1