From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id D6E27A0577; Mon, 13 Apr 2020 21:42:05 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 05D361BF0B; Mon, 13 Apr 2020 21:41:55 +0200 (CEST) Received: from mail-pl1-f182.google.com (mail-pl1-f182.google.com [209.85.214.182]) by dpdk.org (Postfix) with ESMTP id 4B8661BE9D for ; Mon, 13 Apr 2020 21:41:50 +0200 (CEST) Received: by mail-pl1-f182.google.com with SMTP id h11so3765394plk.7 for ; Mon, 13 Apr 2020 12:41:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=FJ+LyMvjWz7RoxnqBsb9qJ4Y6P98NghSsRzce2uAEmM=; b=SRUhpVSMx4CY6HIshxjJGFEwWXvG1hdPRqEJBN6q6asuww+ifgEoIWcKMuk7jVD9qk giOM83LQjMVoZn2tCBi9mkzTuBRH9iprUBbO6HIizEu/p5miWDTy1uyTMwPuxfJKF99j PQq5HMz9ub9mV96KEuogGqDIHRsXRTk22zKzk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FJ+LyMvjWz7RoxnqBsb9qJ4Y6P98NghSsRzce2uAEmM=; b=Ys2wTj7O1/aUK6eWc6nrvyLL2j//EuFr0zhotGp8t9yG3cLtb5SXReaqv+Lx5bVCk4 j+eTM0XazASBDoBbjUcEDQet4bKg1cPJrVkxyoLUiMq93KNyBQeBST5BTLW1Cpxmac/x fiwISoG+w/py3HC20h5JDfY619R2ZWupFLK8hwuQ60Pi/6HEeBmdZBQWDCJf1FQ2mwzR DU71V526DMCZmEPysg2KI6iL1i+rv+QZbJSO4KAjoPVwAEMwIup4nnezzke7SOg7j3D1 JUjjdcRLHsz73ploaGPi/HHsWx9OJeHw7ngscYFHVHHFVQkYhBUwu6dehezs6rQhtegw cAUg== X-Gm-Message-State: AGi0PuZ0oR8Yg0I6cWmuKeahkED1w2OAFolm/0gmLiBPGbehJPLkfdFS qnlkBP3ySNCBiKgnx/7FJ9Z1oKDcA233/yR0fTrtNfKSku1mdb9gHxIPovnaXo4z3sXCAblEVAr dh0pa3QvwOwvij324IgL95av1d2m/4Q7c2m80izzHLui0qAxptNe659r74eaOUoYwmvzF X-Google-Smtp-Source: APiQypJLkVgwqczXCo6RUbSqn+FWEAYYMnis4b5CqR6jDR8RwcJ7bVR4MxFU43L5yTFCELdMOhW9BA== X-Received: by 2002:a17:90a:aa95:: with SMTP id l21mr23753305pjq.4.1586806905487; Mon, 13 Apr 2020 12:41:45 -0700 (PDT) Received: from S60.dhcp.broadcom.net ([192.19.234.250]) by smtp.gmail.com with ESMTPSA id 9sm1381663pfn.204.2020.04.13.12.41.41 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 13 Apr 2020 12:41:44 -0700 (PDT) From: Venkat Duvvuru To: dev@dpdk.org Cc: Ajit Kumar Khaparde , Randy Schacher Date: Tue, 14 Apr 2020 01:09:38 +0530 Message-Id: <1586806811-21736-2-git-send-email-venkatkumar.duvvuru@broadcom.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1586806811-21736-1-git-send-email-venkatkumar.duvvuru@broadcom.com> References: <1584459511-5353-1-git-send-email-venkatkumar.duvvuru@broadcom.com> <1586806811-21736-1-git-send-email-venkatkumar.duvvuru@broadcom.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [dpdk-dev] [PATCH v2 01/34] net/bnxt: add updated dpdk hsi structure X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Ajit Kumar Khaparde - Add most recent bnxt dpdk header. - HWRM version updated to 1.10.1.30 Signed-off-by: Ajit Kumar Khaparde Signed-off-by: Randy Schacher Reviewed-by: Lance Richardson --- drivers/net/bnxt/hsi_struct_def_dpdk.h | 3786 +++++++++++++++++++++++++++++--- 1 file changed, 3436 insertions(+), 350 deletions(-) diff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h index c2bae0f..cde96e7 100644 --- a/drivers/net/bnxt/hsi_struct_def_dpdk.h +++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright (c) 2014-2019 Broadcom Inc. + * Copyright (c) 2014-2020 Broadcom Inc. * All rights reserved. * * DO NOT MODIFY!!! This file is automatically generated. @@ -386,6 +386,8 @@ struct cmd_nums { #define HWRM_PORT_PHY_MDIO_READ UINT32_C(0xb6) #define HWRM_PORT_PHY_MDIO_BUS_ACQUIRE UINT32_C(0xb7) #define HWRM_PORT_PHY_MDIO_BUS_RELEASE UINT32_C(0xb8) + #define HWRM_PORT_QSTATS_EXT_PFC_WD UINT32_C(0xb9) + #define HWRM_PORT_ECN_QSTATS UINT32_C(0xba) #define HWRM_FW_RESET UINT32_C(0xc0) #define HWRM_FW_QSTATUS UINT32_C(0xc1) #define HWRM_FW_HEALTH_CHECK UINT32_C(0xc2) @@ -404,6 +406,8 @@ struct cmd_nums { #define HWRM_FW_GET_STRUCTURED_DATA UINT32_C(0xcb) /* Experimental */ #define HWRM_FW_IPC_MAILBOX UINT32_C(0xcc) + #define HWRM_FW_ECN_CFG UINT32_C(0xcd) + #define HWRM_FW_ECN_QCFG UINT32_C(0xce) #define HWRM_EXEC_FWD_RESP UINT32_C(0xd0) #define HWRM_REJECT_FWD_RESP UINT32_C(0xd1) #define HWRM_FWD_RESP UINT32_C(0xd2) @@ -419,6 +423,7 @@ struct cmd_nums { #define HWRM_TEMP_MONITOR_QUERY UINT32_C(0xe0) #define HWRM_REG_POWER_QUERY UINT32_C(0xe1) #define HWRM_CORE_FREQUENCY_QUERY UINT32_C(0xe2) + #define HWRM_REG_POWER_HISTOGRAM UINT32_C(0xe3) #define HWRM_WOL_FILTER_ALLOC UINT32_C(0xf0) #define HWRM_WOL_FILTER_FREE UINT32_C(0xf1) #define HWRM_WOL_FILTER_QCFG UINT32_C(0xf2) @@ -510,7 +515,7 @@ struct cmd_nums { #define HWRM_CFA_EEM_OP UINT32_C(0x123) /* Experimental */ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS UINT32_C(0x124) - /* Experimental */ + /* Experimental - DEPRECATED */ #define HWRM_CFA_TFLIB UINT32_C(0x125) /* Engine CKV - Get the current allocation status of keys provisioned in the key vault. */ #define HWRM_ENGINE_CKV_STATUS UINT32_C(0x12e) @@ -629,6 +634,56 @@ struct cmd_nums { * to the host test. */ #define HWRM_MFG_HDMA_TEST UINT32_C(0x209) + /* Tells the fw to program the fru memory */ + #define HWRM_MFG_FRU_EEPROM_WRITE UINT32_C(0x20a) + /* Tells the fw to read the fru memory */ + #define HWRM_MFG_FRU_EEPROM_READ UINT32_C(0x20b) + /* Experimental */ + #define HWRM_TF UINT32_C(0x2bc) + /* Experimental */ + #define HWRM_TF_VERSION_GET UINT32_C(0x2bd) + /* Experimental */ + #define HWRM_TF_SESSION_OPEN UINT32_C(0x2c6) + /* Experimental */ + #define HWRM_TF_SESSION_ATTACH UINT32_C(0x2c7) + /* Experimental */ + #define HWRM_TF_SESSION_CLOSE UINT32_C(0x2c8) + /* Experimental */ + #define HWRM_TF_SESSION_QCFG UINT32_C(0x2c9) + /* Experimental */ + #define HWRM_TF_SESSION_RESC_QCAPS UINT32_C(0x2ca) + /* Experimental */ + #define HWRM_TF_SESSION_RESC_ALLOC UINT32_C(0x2cb) + /* Experimental */ + #define HWRM_TF_SESSION_RESC_FREE UINT32_C(0x2cc) + /* Experimental */ + #define HWRM_TF_SESSION_RESC_FLUSH UINT32_C(0x2cd) + /* Experimental */ + #define HWRM_TF_TBL_TYPE_GET UINT32_C(0x2d0) + /* Experimental */ + #define HWRM_TF_TBL_TYPE_SET UINT32_C(0x2d1) + /* Experimental */ + #define HWRM_TF_CTXT_MEM_RGTR UINT32_C(0x2da) + /* Experimental */ + #define HWRM_TF_CTXT_MEM_UNRGTR UINT32_C(0x2db) + /* Experimental */ + #define HWRM_TF_EXT_EM_QCAPS UINT32_C(0x2dc) + /* Experimental */ + #define HWRM_TF_EXT_EM_OP UINT32_C(0x2dd) + /* Experimental */ + #define HWRM_TF_EXT_EM_CFG UINT32_C(0x2de) + /* Experimental */ + #define HWRM_TF_EXT_EM_QCFG UINT32_C(0x2df) + /* Experimental */ + #define HWRM_TF_TCAM_SET UINT32_C(0x2ee) + /* Experimental */ + #define HWRM_TF_TCAM_GET UINT32_C(0x2ef) + /* Experimental */ + #define HWRM_TF_TCAM_MOVE UINT32_C(0x2f0) + /* Experimental */ + #define HWRM_TF_TCAM_FREE UINT32_C(0x2f1) + /* Experimental */ + #define HWRM_SV UINT32_C(0x400) /* Experimental */ #define HWRM_DBG_READ_DIRECT UINT32_C(0xff10) /* Experimental */ @@ -658,6 +713,8 @@ struct cmd_nums { #define HWRM_DBG_CRASHDUMP_HEADER UINT32_C(0xff1d) /* Experimental */ #define HWRM_DBG_CRASHDUMP_ERASE UINT32_C(0xff1e) + /* Send driver debug information to firmware */ + #define HWRM_DBG_DRV_TRACE UINT32_C(0xff1f) /* Experimental */ #define HWRM_NVM_FACTORY_DEFAULTS UINT32_C(0xffee) #define HWRM_NVM_VALIDATE_OPTION UINT32_C(0xffef) @@ -857,8 +914,8 @@ struct hwrm_err_output { #define HWRM_VERSION_MINOR 10 #define HWRM_VERSION_UPDATE 1 /* non-zero means beta version */ -#define HWRM_VERSION_RSVD 6 -#define HWRM_VERSION_STR "1.10.1.6" +#define HWRM_VERSION_RSVD 30 +#define HWRM_VERSION_STR "1.10.1.30" /**************** * hwrm_ver_get * @@ -1143,6 +1200,7 @@ struct hwrm_ver_get_output { #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED \ UINT32_C(0x1000) /* + * Deprecated and replaced with cfa_truflow_supported. * If set to 1, the firmware is able to support TFLIB features. * If set to 0, then the firmware doesn’t support TFLIB features. * By default, this flag should be 0 for older version of core firmware. @@ -1150,6 +1208,14 @@ struct hwrm_ver_get_output { #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TFLIB_SUPPORTED \ UINT32_C(0x2000) /* + * If set to 1, the firmware is able to support TruFlow features. + * If set to 0, then the firmware doesn’t support TruFlow features. + * By default, this flag should be 0 for older version of + * core firmware. + */ + #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED \ + UINT32_C(0x4000) + /* * This field represents the major version of RoCE firmware. * A change in major version represents a major release. */ @@ -4508,10 +4574,16 @@ struct hwrm_async_event_cmpl { */ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE \ UINT32_C(0x3c) - /* TFLIB unique default VNIC Configuration Change */ + /* + * Deprecated. + * TFLIB unique default VNIC Configuration Change + */ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_DEFAULT_VNIC_CHANGE \ UINT32_C(0x3d) - /* TFLIB unique link status changed */ + /* + * Deprecated. + * TFLIB unique link status changed + */ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_LINK_STATUS_CHANGE \ UINT32_C(0x3e) /* @@ -4521,6 +4593,19 @@ struct hwrm_async_event_cmpl { #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_QUIESCE_DONE \ UINT32_C(0x3f) /* + * An event signifying a HWRM command is in progress and its + * response will be deferred. This event is used on crypto controllers + * only. + */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEFERRED_RESPONSE \ + UINT32_C(0x40) + /* + * An event signifying that a PFC WatchDog configuration + * has changed on any port / cos. + */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE \ + UINT32_C(0x41) + /* * A trace log message. This contains firmware trace logs string * embedded in the asynchronous message. This is an experimental * event, not meant for production use at this time. @@ -6393,6 +6478,36 @@ struct hwrm_async_event_cmpl_quiesce_done { UINT32_C(0x2) #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_LAST \ HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_ERROR + /* opaque is 8 b */ + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_OPAQUE_MASK \ + UINT32_C(0xff00) + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_OPAQUE_SFT \ + 8 + /* + * Additional information about internal hardware state related to + * idle/quiesce state. QUIESCE may succeed per quiesce_status + * regardless of idle_state_flags. If QUIESCE fails, the host may + * inspect idle_state_flags to determine whether a retry is warranted. + */ + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_MASK \ + UINT32_C(0xff0000) + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_SFT \ + 16 + /* + * Failure to quiesce is caused by host not updating the NQ consumer + * index. + */ + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_INCOMPLETE_NQ \ + UINT32_C(0x10000) + /* Flag 1 indicating partial non-idle state. */ + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_IDLE_STATUS_1 \ + UINT32_C(0x20000) + /* Flag 2 indicating partial non-idle state. */ + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_IDLE_STATUS_2 \ + UINT32_C(0x40000) + /* Flag 3 indicating partial non-idle state. */ + #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_IDLE_STATUS_3 \ + UINT32_C(0x80000) uint8_t opaque_v; /* * This value is written by the NIC such that it will be different @@ -6414,6 +6529,152 @@ struct hwrm_async_event_cmpl_quiesce_done { UINT32_C(0x1) } __attribute__((packed)); +/* hwrm_async_event_cmpl_deferred_response (size:128b/16B) */ +struct hwrm_async_event_cmpl_deferred_response { + uint16_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* + * An event signifying a HWRM command is in progress and its + * response will be deferred + */ + #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE \ + UINT32_C(0x40) + #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE + /* Event specific data */ + uint32_t event_data2; + /* + * The PF's mailbox is clear to issue another command. + * A command with this seq_id is still in progress + * and will return a regualr HWRM completion when done. + * 'event_data1' field, if non-zero, contains the estimated + * execution time for the command. + */ + #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_MASK \ + UINT32_C(0xffff) + #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_SFT \ + 0 + uint8_t opaque_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_V \ + UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* Estimated remaining time of command execution in ms (if not zero) */ + uint32_t event_data1; +} __attribute__((packed)); + +/* hwrm_async_event_cmpl_pfc_watchdog_cfg_change (size:128b/16B) */ +struct hwrm_async_event_cmpl_pfc_watchdog_cfg_change { + uint16_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_SFT \ + 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* PFC watchdog configuration change for given port/cos */ + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE \ + UINT32_C(0x41) + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE + /* Event specific data */ + uint32_t event_data2; + uint8_t opaque_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_V \ + UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_OPAQUE_SFT 1 + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* + * 1 in bit position X indicates PFC watchdog should + * be on for COSX + */ + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_MASK \ + UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_SFT \ + 0 + /* 1 means PFC WD for COS0 is on, 0 - off. */ + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS0 \ + UINT32_C(0x1) + /* 1 means PFC WD for COS1 is on, 0 - off. */ + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS1 \ + UINT32_C(0x2) + /* 1 means PFC WD for COS2 is on, 0 - off. */ + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS2 \ + UINT32_C(0x4) + /* 1 means PFC WD for COS3 is on, 0 - off. */ + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS3 \ + UINT32_C(0x8) + /* 1 means PFC WD for COS4 is on, 0 - off. */ + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS4 \ + UINT32_C(0x10) + /* 1 means PFC WD for COS5 is on, 0 - off. */ + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS5 \ + UINT32_C(0x20) + /* 1 means PFC WD for COS6 is on, 0 - off. */ + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS6 \ + UINT32_C(0x40) + /* 1 means PFC WD for COS7 is on, 0 - off. */ + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS7 \ + UINT32_C(0x80) + /* PORT ID */ + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK \ + UINT32_C(0xffff00) + #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT \ + 8 +} __attribute__((packed)); + /* hwrm_async_event_cmpl_fw_trace_msg (size:128b/16B) */ struct hwrm_async_event_cmpl_fw_trace_msg { uint16_t type; @@ -7220,7 +7481,7 @@ struct hwrm_func_qcaps_input { uint8_t unused_0[6]; } __attribute__((packed)); -/* hwrm_func_qcaps_output (size:640b/80B) */ +/* hwrm_func_qcaps_output (size:704b/88B) */ struct hwrm_func_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; @@ -7441,6 +7702,33 @@ struct hwrm_func_qcaps_output { */ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_NOTIFY_VF_DEF_VNIC_CHNG_SUPPORTED \ UINT32_C(0x4000000) + /* If set to 1, then the vlan acceleration for TX is disabled. */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VLAN_ACCELERATION_TX_DISABLED \ + UINT32_C(0x8000000) + /* + * When this bit is '1', it indicates that core firmware supports + * DBG_COREDUMP_XXX commands. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_COREDUMP_CMD_SUPPORTED \ + UINT32_C(0x10000000) + /* + * When this bit is '1', it indicates that core firmware supports + * DBG_CRASHDUMP_XXX commands. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_CRASHDUMP_CMD_SUPPORTED \ + UINT32_C(0x20000000) + /* + * If the query is for a VF, then this flag should be ignored. + * If the query is for a PF and this flag is set to 1, then + * the PF has the capability to support retrieval of + * rx_port_stats_ext_pfc_wd statistics (supported by the PFC + * WatchDog feature) via the hwrm_port_qstats_ext_pfc_wd command. + * If this flag is set to 1, only that (supported) command should + * be used for retrieval of PFC related statistics (rather than + * hwrm_port_qstats_ext command, which could previously be used). + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PFC_WD_STATS_SUPPORTED \ + UINT32_C(0x40000000) /* * This value is current MAC address configured for this * function. A value of 00-00-00-00-00-00 indicates no @@ -7551,7 +7839,22 @@ struct hwrm_func_qcaps_output { * (max_tx_rings) to the function. */ uint16_t max_sp_tx_rings; - uint8_t unused_0; + uint8_t unused_0[2]; + uint32_t flags_ext; + /* + * If 1, the device can be configured to set the ECN bits in the + * IP header of received packets if the receive queue length + * exceeds a given threshold. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_ECN_MARK_SUPPORTED \ + UINT32_C(0x1) + /* + * If 1, the device can report the number of received packets + * that it marked as having experienced congestion. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_ECN_STATS_SUPPORTED \ + UINT32_C(0x2) + uint8_t unused_1[3]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -7606,7 +7909,7 @@ struct hwrm_func_qcfg_input { uint8_t unused_0[6]; } __attribute__((packed)); -/* hwrm_func_qcfg_output (size:704b/88B) */ +/* hwrm_func_qcfg_output (size:768b/96B) */ struct hwrm_func_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; @@ -8016,7 +8319,17 @@ struct hwrm_func_qcfg_output { * this value to find out the doorbell page offset from the BAR. */ uint16_t legacy_l2_db_size_kb; - uint8_t unused_2[1]; + uint16_t svif_info; + /* + * This field specifies the source virtual interface of the function being + * queried. Drivers can use this to program svif field in the L2 context + * table + */ + #define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK UINT32_C(0x7fff) + #define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_SFT 0 + /* This field specifies whether svif is valid or not */ + #define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID UINT32_C(0x8000) + uint8_t unused_2[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -9862,8 +10175,12 @@ struct hwrm_func_backing_store_qcaps_output { uint32_t rsvd; /* Reserved for future. */ uint16_t rsvd1; - /* Reserved for future. */ - uint8_t rsvd2; + /* + * Count of TQM fastpath rings to be used for allocating backing store. + * Backing store configuration must be specified for each TQM ring from + * this count in `backing_store_cfg`. + */ + uint8_t tqm_fp_rings_count; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -12178,116 +12495,163 @@ struct hwrm_error_recovery_qcfg_output { * this much time after writing reset_reg_val in reset_reg. */ uint8_t delay_after_reset[16]; - uint8_t unused_1[7]; /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal - * processor, the order of writes has to be such that this field - * is written last. - */ - uint8_t valid; -} __attribute__((packed)); - -/*********************** - * hwrm_func_vlan_qcfg * - ***********************/ - - -/* hwrm_func_vlan_qcfg_input (size:192b/24B) */ -struct hwrm_func_vlan_qcfg_input { - /* The HWRM command request type. */ - uint16_t req_type; - /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. - */ - uint16_t cmpl_ring; - /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. - */ - uint16_t seq_id; - /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM + * Error recovery counter. + * Lower 2 bits indicates address space location and upper 30 bits + * indicates actual address. + * A value of 0xFFFF-FFFF indicates this register does not exist. */ - uint16_t target_id; + uint32_t err_recovery_cnt_reg; + /* Lower 2 bits indicates address space location. */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_MASK \ + UINT32_C(0x3) + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_SFT \ + 0 /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. + * If value is 0, this register is located in PCIe config space. + * Drivers have to map appropriate window to access this + * register. */ - uint64_t resp_addr; + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_PCIE_CFG \ + UINT32_C(0x0) /* - * Function ID of the function that is being - * configured. - * If set to 0xFF... (All Fs), then the configuration is - * for the requesting function. + * If value is 1, this register is located in GRC address space. + * Drivers have to map appropriate window to access this + * register. */ - uint16_t fid; - uint8_t unused_0[6]; -} __attribute__((packed)); - -/* hwrm_func_vlan_qcfg_output (size:320b/40B) */ -struct hwrm_func_vlan_qcfg_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - uint64_t unused_0; - /* S-TAG VLAN identifier configured for the function. */ - uint16_t stag_vid; - /* S-TAG PCP value configured for the function. */ - uint8_t stag_pcp; - uint8_t unused_1; + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_GRC \ + UINT32_C(0x1) /* - * S-TAG TPID value configured for the function. This field is specified in - * network byte order. + * If value is 2, this register is located in first BAR address + * space. Drivers have to map appropriate window to access this + * register. */ - uint16_t stag_tpid; - /* C-TAG VLAN identifier configured for the function. */ - uint16_t ctag_vid; - /* C-TAG PCP value configured for the function. */ - uint8_t ctag_pcp; - uint8_t unused_2; + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR0 \ + UINT32_C(0x2) /* - * C-TAG TPID value configured for the function. This field is specified in - * network byte order. + * If value is 3, this register is located in second BAR address + * space. Drivers have to map appropriate window to access this + * register. */ - uint16_t ctag_tpid; - /* Future use. */ - uint32_t rsvd2; - /* Future use. */ - uint32_t rsvd3; - uint8_t unused_3[3]; + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 \ + UINT32_C(0x3) + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_LAST \ + HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 + /* Upper 30bits of the register address. */ + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_MASK \ + UINT32_C(0xfffffffc) + #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SFT \ + 2 + uint8_t unused_1[3]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. */ uint8_t valid; } __attribute__((packed)); -/********************** - * hwrm_func_vlan_cfg * - **********************/ +/*********************** + * hwrm_func_vlan_qcfg * + ***********************/ -/* hwrm_func_vlan_cfg_input (size:384b/48B) */ -struct hwrm_func_vlan_cfg_input { +/* hwrm_func_vlan_qcfg_input (size:192b/24B) */ +struct hwrm_func_vlan_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Function ID of the function that is being + * configured. + * If set to 0xFF... (All Fs), then the configuration is + * for the requesting function. + */ + uint16_t fid; + uint8_t unused_0[6]; +} __attribute__((packed)); + +/* hwrm_func_vlan_qcfg_output (size:320b/40B) */ +struct hwrm_func_vlan_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint64_t unused_0; + /* S-TAG VLAN identifier configured for the function. */ + uint16_t stag_vid; + /* S-TAG PCP value configured for the function. */ + uint8_t stag_pcp; + uint8_t unused_1; + /* + * S-TAG TPID value configured for the function. This field is specified in + * network byte order. + */ + uint16_t stag_tpid; + /* C-TAG VLAN identifier configured for the function. */ + uint16_t ctag_vid; + /* C-TAG PCP value configured for the function. */ + uint8_t ctag_pcp; + uint8_t unused_2; + /* + * C-TAG TPID value configured for the function. This field is specified in + * network byte order. + */ + uint16_t ctag_tpid; + /* Future use. */ + uint32_t rsvd2; + /* Future use. */ + uint32_t rsvd3; + uint8_t unused_3[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __attribute__((packed)); + +/********************** + * hwrm_func_vlan_cfg * + **********************/ + + +/* hwrm_func_vlan_cfg_input (size:384b/48B) */ +struct hwrm_func_vlan_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -14039,6 +14403,9 @@ struct hwrm_port_phy_qcfg_output { /* Module is not inserted. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTINSERTED \ UINT32_C(0x4) + /* Module is powered down becuase of over current fault. */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_CURRENTFAULT \ + UINT32_C(0x5) /* Module status is not applicable. */ #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTAPPLICABLE \ UINT32_C(0xff) @@ -15010,7 +15377,7 @@ struct hwrm_port_mac_qcfg_input { uint8_t unused_0[6]; } __attribute__((packed)); -/* hwrm_port_mac_qcfg_output (size:192b/24B) */ +/* hwrm_port_mac_qcfg_output (size:256b/32B) */ struct hwrm_port_mac_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; @@ -15250,6 +15617,20 @@ struct hwrm_port_mac_qcfg_output { UINT32_C(0xe0) #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_DEFAULT_COS_SFT \ 5 + uint8_t unused_1; + uint16_t port_svif_info; + /* + * This field specifies the source virtual interface of the port being + * queried. Drivers can use this to program port svif field in the + * L2 context table + */ + #define HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_MASK \ + UINT32_C(0x7fff) + #define HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_SFT 0 + /* This field specifies whether port_svif is valid or not */ + #define HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_VALID \ + UINT32_C(0x8000) + uint8_t unused_2[5]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -15322,17 +15703,17 @@ struct hwrm_port_mac_ptp_qcfg_output { #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS \ UINT32_C(0x1) /* - * When this bit is set to '1', the PTP information is accessible - * via HWRM commands. - */ - #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS \ - UINT32_C(0x2) - /* * When this bit is set to '1', the device supports one-step * Tx timestamping. */ #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS \ UINT32_C(0x4) + /* + * When this bit is set to '1', the PTP information is accessible + * via HWRM commands. + */ + #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS \ + UINT32_C(0x8) uint8_t unused_0[3]; /* Offset of the PTP register for the lower 32 bits of timestamp for RX. */ uint32_t rx_ts_reg_off_lower; @@ -15375,7 +15756,7 @@ struct hwrm_port_mac_ptp_qcfg_output { uint8_t valid; } __attribute__((packed)); -/* Port Tx Statistics Formats */ +/* Port Tx Statistics Format */ /* tx_port_stats (size:3264b/408B) */ struct tx_port_stats { /* Total Number of 64 Bytes frames transmitted */ @@ -15516,7 +15897,7 @@ struct tx_port_stats { uint64_t tx_stat_error; } __attribute__((packed)); -/* Port Rx Statistics Formats */ +/* Port Rx Statistics Format */ /* rx_port_stats (size:4224b/528B) */ struct rx_port_stats { /* Total Number of 64 Bytes frames received */ @@ -15806,7 +16187,7 @@ struct hwrm_port_qstats_output { uint8_t valid; } __attribute__((packed)); -/* Port Tx Statistics extended Formats */ +/* Port Tx Statistics extended Format */ /* tx_port_stats_ext (size:2048b/256B) */ struct tx_port_stats_ext { /* Total number of tx bytes count on cos queue 0 */ @@ -15875,7 +16256,7 @@ struct tx_port_stats_ext { uint64_t pfc_pri7_tx_transitions; } __attribute__((packed)); -/* Port Rx Statistics extended Formats */ +/* Port Rx Statistics extended Format */ /* rx_port_stats_ext (size:3648b/456B) */ struct rx_port_stats_ext { /* Number of times link state changed to down */ @@ -15997,6 +16378,424 @@ struct rx_port_stats_ext { uint64_t rx_discard_packets_cos7; } __attribute__((packed)); +/* + * Port Rx Statistics extended PFC WatchDog Format. + * StormDetect and StormRevert event determination is based + * on an integration period and a percentage threshold. + * StormDetect event - when percentage of XOFF frames receieved + * within an integration period exceeds the configured threshold. + * StormRevert event - when percentage of XON frames received + * within an integration period exceeds the configured threshold. + * Actual number of XOFF/XON frames for the events to be triggered + * depends on both configured integration period and sampling rate. + * The statistics in this structure represent counts of specified + * events from the moment the feature (PFC WatchDog) is enabled via + * hwrm_queue_pfc_enable_cfg call. + */ +/* rx_port_stats_ext_pfc_wd (size:5120b/640B) */ +struct rx_port_stats_ext_pfc_wd { + /* + * Total number of PFC WatchDog StormDetect events detected + * for Pri 0 + */ + uint64_t rx_pfc_watchdog_storms_detected_pri0; + /* + * Total number of PFC WatchDog StormDetect events detected + * for Pri 1 + */ + uint64_t rx_pfc_watchdog_storms_detected_pri1; + /* + * Total number of PFC WatchDog StormDetect events detected + * for Pri 2 + */ + uint64_t rx_pfc_watchdog_storms_detected_pri2; + /* + * Total number of PFC WatchDog StormDetect events detected + * for Pri 3 + */ + uint64_t rx_pfc_watchdog_storms_detected_pri3; + /* + * Total number of PFC WatchDog StormDetect events detected + * for Pri 4 + */ + uint64_t rx_pfc_watchdog_storms_detected_pri4; + /* + * Total number of PFC WatchDog StormDetect events detected + * for Pri 5 + */ + uint64_t rx_pfc_watchdog_storms_detected_pri5; + /* + * Total number of PFC WatchDog StormDetect events detected + * for Pri 6 + */ + uint64_t rx_pfc_watchdog_storms_detected_pri6; + /* + * Total number of PFC WatchDog StormDetect events detected + * for Pri 7 + */ + uint64_t rx_pfc_watchdog_storms_detected_pri7; + /* + * Total number of PFC WatchDog StormRevert events detected + * for Pri 0 + */ + uint64_t rx_pfc_watchdog_storms_reverted_pri0; + /* + * Total number of PFC WatchDog StormRevert events detected + * for Pri 1 + */ + uint64_t rx_pfc_watchdog_storms_reverted_pri1; + /* + * Total number of PFC WatchDog StormRevert events detected + * for Pri 2 + */ + uint64_t rx_pfc_watchdog_storms_reverted_pri2; + /* + * Total number of PFC WatchDog StormRevert events detected + * for Pri 3 + */ + uint64_t rx_pfc_watchdog_storms_reverted_pri3; + /* + * Total number of PFC WatchDog StormRevert events detected + * for Pri 4 + */ + uint64_t rx_pfc_watchdog_storms_reverted_pri4; + /* + * Total number of PFC WatchDog StormRevert events detected + * for Pri 5 + */ + uint64_t rx_pfc_watchdog_storms_reverted_pri5; + /* + * Total number of PFC WatchDog StormRevert events detected + * for Pri 6 + */ + uint64_t rx_pfc_watchdog_storms_reverted_pri6; + /* + * Total number of PFC WatchDog StormRevert events detected + * for Pri 7 + */ + uint64_t rx_pfc_watchdog_storms_reverted_pri7; + /* + * Total number of packets received during PFC watchdog storm + * for pri 0 + */ + uint64_t rx_pfc_watchdog_storms_rx_packets_pri0; + /* + * Total number of packets received during PFC watchdog storm + * for pri 1 + */ + uint64_t rx_pfc_watchdog_storms_rx_packets_pri1; + /* + * Total number of packets received during PFC watchdog storm + * for pri 2 + */ + uint64_t rx_pfc_watchdog_storms_rx_packets_pri2; + /* + * Total number of packets received during PFC watchdog storm + * for pri 3 + */ + uint64_t rx_pfc_watchdog_storms_rx_packets_pri3; + /* + * Total number of packets received during PFC watchdog storm + * for pri 4 + */ + uint64_t rx_pfc_watchdog_storms_rx_packets_pri4; + /* + * Total number of packets received during PFC watchdog storm + * for pri 5 + */ + uint64_t rx_pfc_watchdog_storms_rx_packets_pri5; + /* + * Total number of packets received during PFC watchdog storm + * for pri 6 + */ + uint64_t rx_pfc_watchdog_storms_rx_packets_pri6; + /* + * Total number of packets received during PFC watchdog storm + * for pri 7 + */ + uint64_t rx_pfc_watchdog_storms_rx_packets_pri7; + /* + * Total number of bytes received during PFC watchdog storm + * for pri 0 + */ + uint64_t rx_pfc_watchdog_storms_rx_bytes_pri0; + /* + * Total number of bytes received during PFC watchdog storm + * for pri 1 + */ + uint64_t rx_pfc_watchdog_storms_rx_bytes_pri1; + /* + * Total number of bytes received during PFC watchdog storm + * for pri 2 + */ + uint64_t rx_pfc_watchdog_storms_rx_bytes_pri2; + /* + * Total number of bytes received during PFC watchdog storm + * for pri 3 + */ + uint64_t rx_pfc_watchdog_storms_rx_bytes_pri3; + /* + * Total number of bytes received during PFC watchdog storm + * for pri 4 + */ + uint64_t rx_pfc_watchdog_storms_rx_bytes_pri4; + /* + * Total number of bytes received during PFC watchdog storm + * for pri 5 + */ + uint64_t rx_pfc_watchdog_storms_rx_bytes_pri5; + /* + * Total number of bytes received during PFC watchdog storm + * for pri 6 + */ + uint64_t rx_pfc_watchdog_storms_rx_bytes_pri6; + /* + * Total number of bytes received during PFC watchdog storm + * for pri 7 + */ + uint64_t rx_pfc_watchdog_storms_rx_bytes_pri7; + /* + * Total number of packets dropped on rx during PFC watchdog storm + * for pri 0 + */ + uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri0; + /* + * Total number of packets dropped on rx during PFC watchdog storm + * for pri 1 + */ + uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri1; + /* + * Total number of packets dropped on rx during PFC watchdog storm + * for pri 2 + */ + uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri2; + /* + * Total number of packets dropped on rx during PFC watchdog storm + * for pri 3 + */ + uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri3; + /* + * Total number of packets dropped on rx during PFC watchdog storm + * for pri 4 + */ + uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri4; + /* + * Total number of packets dropped on rx during PFC watchdog storm + * for pri 5 + */ + uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri5; + /* + * Total number of packets dropped on rx during PFC watchdog storm + * for pri 6 + */ + uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri6; + /* + * Total number of packets dropped on rx during PFC watchdog storm + * for pri 7 + */ + uint64_t rx_pfc_watchdog_storms_rx_packets_dropped_pri7; + /* + * Total number of bytes dropped on rx during PFC watchdog storm + * for pri 0 + */ + uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri0; + /* + * Total number of bytes dropped on rx during PFC watchdog storm + * for pri 1 + */ + uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri1; + /* + * Total number of bytes dropped on rx during PFC watchdog storm + * for pri 2 + */ + uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri2; + /* + * Total number of bytes dropped on rx during PFC watchdog storm + * for pri 3 + */ + uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri3; + /* + * Total number of bytes dropped on rx during PFC watchdog storm + * for pri 4 + */ + uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri4; + /* + * Total number of bytes dropped on rx during PFC watchdog storm + * for pri 5 + */ + uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri5; + /* + * Total number of bytes dropped on rx during PFC watchdog storm + * for pri 6 + */ + uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri6; + /* + * Total number of bytes dropped on rx during PFC watchdog storm + * for pri 7 + */ + uint64_t rx_pfc_watchdog_storms_rx_bytes_dropped_pri7; + /* + * Number of packets received during last PFC watchdog storm + * for pri 0 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri0; + /* + * Number of packets received during last PFC watchdog storm + * for pri 1 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri1; + /* + * Number of packets received during last PFC watchdog storm + * for pri 2 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri2; + /* + * Number of packets received during last PFC watchdog storm + * for pri 3 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri3; + /* + * Number of packets received during last PFC watchdog storm + * for pri 4 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri4; + /* + * Number of packets received during last PFC watchdog storm + * for pri 5 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri5; + /* + * Number of packets received during last PFC watchdog storm + * for pri 6 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri6; + /* + * Number of packets received during last PFC watchdog storm + * for pri 7 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_packets_pri7; + /* + * Number of bytes received during last PFC watchdog storm + * for pri 0 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri0; + /* + * Number of bytes received during last PFC watchdog storm + * for pri 1 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri1; + /* + * Number of bytes received during last PFC watchdog storm + * for pri 2 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri2; + /* + * Number of bytes received during last PFC watchdog storm + * for pri 3 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri3; + /* + * Number of bytes received during last PFC watchdog storm + * for pri 4 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri4; + /* + * Number of bytes received during last PFC watchdog storm + * for pri 5 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri5; + /* + * Number of bytes received during last PFC watchdog storm + * for pri 6 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri6; + /* + * Number of bytes received during last PFC watchdog storm + * for pri 7 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_bytes_pri7; + /* + * Number of packets dropped on rx during last PFC watchdog storm + * for pri 0 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri0; + /* + * Number of packets dropped on rx during last PFC watchdog storm + * for pri 1 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri1; + /* + * Number of packets dropped on rx during last PFC watchdog storm + * for pri 2 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri2; + /* + * Number of packets dropped on rx during last PFC watchdog storm + * for pri 3 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri3; + /* + * Number of packets dropped on rx during last PFC watchdog storm + * for pri 4 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri4; + /* + * Number of packets dropped on rx during last PFC watchdog storm + * for pri 5 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri5; + /* + * Number of packets dropped on rx during last PFC watchdog storm + * for pri 6 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri6; + /* + * Number of packets dropped on rx during last PFC watchdog storm + * for pri 7 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_packets_dropped_pri7; + /* + * Total number of bytes dropped on rx during PFC watchdog storm + * for pri 0 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri0; + /* + * Number of bytes dropped on rx during last PFC watchdog storm + * for pri 1 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri1; + /* + * Number of bytes dropped on rx during last PFC watchdog storm + * for pri 2 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri2; + /* + * Number of bytes dropped on rx during last PFC watchdog storm + * for pri 3 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri3; + /* + * Number of bytes dropped on rx during last PFC watchdog storm + * for pri 4 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri4; + /* + * Number of bytes dropped on rx during last PFC watchdog storm + * for pri 5 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri5; + /* + * Number of bytes dropped on rx during last PFC watchdog storm + * for pri 6 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri6; + /* + * Number of bytes dropped on rx during last PFC watchdog storm + * for pri 7 + */ + uint64_t rx_pfc_watchdog_last_storm_rx_bytes_dropped_pri7; +} __attribute__((packed)); + /************************ * hwrm_port_qstats_ext * ************************/ @@ -16090,6 +16889,83 @@ struct hwrm_port_qstats_ext_output { uint8_t valid; } __attribute__((packed)); +/******************************* + * hwrm_port_qstats_ext_pfc_wd * + *******************************/ + + +/* hwrm_port_qstats_ext_pfc_wd_input (size:256b/32B) */ +struct hwrm_port_qstats_ext_pfc_wd_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Port ID of port that is being queried. */ + uint16_t port_id; + /* + * The size of rx_port_stats_ext_pfc_wd + * block in bytes + */ + uint16_t pfc_wd_stat_size; + uint8_t unused_0[4]; + /* + * This is the host address where + * rx_port_stats_ext_pfc_wd will be stored + */ + uint64_t pfc_wd_stat_host_addr; +} __attribute__((packed)); + +/* hwrm_port_qstats_ext_pfc_wd_output (size:128b/16B) */ +struct hwrm_port_qstats_ext_pfc_wd_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * The size of rx_port_stats_ext_pfc_wd + * statistics block in bytes. + */ + uint16_t pfc_wd_stat_size; + uint8_t flags; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; + uint8_t unused_0[4]; +} __attribute__((packed)); + /************************* * hwrm_port_lpbk_qstats * *************************/ @@ -16168,6 +17044,91 @@ struct hwrm_port_lpbk_qstats_output { uint8_t valid; } __attribute__((packed)); +/************************ + * hwrm_port_ecn_qstats * + ************************/ + + +/* hwrm_port_ecn_qstats_input (size:192b/24B) */ +struct hwrm_port_ecn_qstats_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Port ID of port that is being queried. Unused if NIC is in + * multi-host mode. + */ + uint16_t port_id; + uint8_t unused_0[6]; +} __attribute__((packed)); + +/* hwrm_port_ecn_qstats_output (size:384b/48B) */ +struct hwrm_port_ecn_qstats_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Number of packets marked in CoS queue 0. */ + uint32_t mark_cnt_cos0; + /* Number of packets marked in CoS queue 1. */ + uint32_t mark_cnt_cos1; + /* Number of packets marked in CoS queue 2. */ + uint32_t mark_cnt_cos2; + /* Number of packets marked in CoS queue 3. */ + uint32_t mark_cnt_cos3; + /* Number of packets marked in CoS queue 4. */ + uint32_t mark_cnt_cos4; + /* Number of packets marked in CoS queue 5. */ + uint32_t mark_cnt_cos5; + /* Number of packets marked in CoS queue 6. */ + uint32_t mark_cnt_cos6; + /* Number of packets marked in CoS queue 7. */ + uint32_t mark_cnt_cos7; + /* + * Bitmask that indicates which CoS queues have ECN marking enabled. + * Bit i corresponds to CoS queue i. + */ + uint8_t mark_en; + uint8_t unused_0[6]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __attribute__((packed)); + /*********************** * hwrm_port_clr_stats * ***********************/ @@ -18322,7 +19283,7 @@ struct hwrm_port_phy_mdio_bus_acquire_input { * Timeout in milli seconds, MDIO BUS will be released automatically * after this time, if another mdio acquire command is not received * within the timeout window from the same client. - * A 0xFFFF will hold the bus until this bus is released. + * A 0xFFFF will hold the bus untill this bus is released. */ uint16_t mdio_bus_timeout; uint8_t unused_0[2]; @@ -19158,6 +20119,30 @@ struct hwrm_queue_pfcenable_qcfg_output { /* If set to 1, then PFC is enabled on PRI 7. */ #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI7_PFC_ENABLED \ UINT32_C(0x80) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI0. */ + #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI0_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x100) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI1. */ + #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI1_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x200) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI2. */ + #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI2_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x400) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI3. */ + #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI3_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x800) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI4. */ + #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI4_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x1000) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI5. */ + #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI5_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x2000) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI6. */ + #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI6_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x4000) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI7. */ + #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI7_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x8000) uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output @@ -19229,6 +20214,30 @@ struct hwrm_queue_pfcenable_cfg_input { /* If set to 1, then PFC is requested to be enabled on PRI 7. */ #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI7_PFC_ENABLED \ UINT32_C(0x80) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI0. */ + #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI0_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x100) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI1. */ + #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI1_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x200) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI2. */ + #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI2_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x400) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI3. */ + #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI3_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x800) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI4. */ + #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI4_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x1000) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI5. */ + #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI5_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x2000) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI6. */ + #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI6_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x4000) + /* If set to 1, then PFC WatchDog is requested to be enabled on PRI7. */ + #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI7_PFC_WATCHDOG_ENABLED \ + UINT32_C(0x8000) /* * Port ID of port for which the table is being configured. * The HWRM needs to check whether this function is allowed @@ -31831,15 +32840,2172 @@ struct hwrm_cfa_eem_qcfg_input { */ uint64_t resp_addr; uint32_t flags; - /* When set to 1, indicates the configuration is the TX flow. */ - #define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x1) - /* When set to 1, indicates the configuration is the RX flow. */ - #define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x2) - uint32_t unused_0; + /* When set to 1, indicates the configuration is the TX flow. */ + #define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x1) + /* When set to 1, indicates the configuration is the RX flow. */ + #define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x2) + uint32_t unused_0; +} __attribute__((packed)); + +/* hwrm_cfa_eem_qcfg_output (size:256b/32B) */ +struct hwrm_cfa_eem_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint32_t flags; + /* When set to 1, indicates the configuration is the TX flow. */ + #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_TX \ + UINT32_C(0x1) + /* When set to 1, indicates the configuration is the RX flow. */ + #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_RX \ + UINT32_C(0x2) + /* When set to 1, all offloaded flows will be sent to EEM. */ + #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PREFERRED_OFFLOAD \ + UINT32_C(0x4) + /* The number of entries the FW has configured for EEM. */ + uint32_t num_entries; + /* Configured EEM with the given context if for KEY0 table. */ + uint16_t key0_ctx_id; + /* Configured EEM with the given context if for KEY1 table. */ + uint16_t key1_ctx_id; + /* Configured EEM with the given context if for RECORD table. */ + uint16_t record_ctx_id; + /* Configured EEM with the given context if for EFC table. */ + uint16_t efc_ctx_id; + /* Configured EEM with the given context if for EFC table. */ + uint16_t fid_ctx_id; + uint8_t unused_2[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __attribute__((packed)); + +/******************* + * hwrm_cfa_eem_op * + *******************/ + + +/* hwrm_cfa_eem_op_input (size:192b/24B) */ +struct hwrm_cfa_eem_op_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t flags; + /* + * When set to 1, indicates the host memory which is passed will be + * used for the TX flow offload function specified in fid. + * Note if this bit is set then the path_rx bit can't be set. + */ + #define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_TX UINT32_C(0x1) + /* + * When set to 1, indicates the host memory which is passed will be + * used for the RX flow offload function specified in fid. + * Note if this bit is set then the path_tx bit can't be set. + */ + #define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_RX UINT32_C(0x2) + uint16_t unused_0; + /* The number of EEM key table entries to be configured. */ + uint16_t op; + /* This value is reserved and should not be used. */ + #define HWRM_CFA_EEM_OP_INPUT_OP_RESERVED UINT32_C(0x0) + /* + * To properly stop EEM and ensure there are no DMA's, the caller + * must disable EEM for the given PF, using this call. This will + * safely disable EEM and ensure that all DMA'ed to the + * keys/records/efc have been completed. + */ + #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_DISABLE UINT32_C(0x1) + /* + * Once the EEM host memory has been configured, EEM options have + * been configured. Then the caller should enable EEM for the given + * PF. Note once this call has been made, then the EEM mechanism + * will be active and DMA's will occur as packets are processed. + */ + #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_ENABLE UINT32_C(0x2) + /* + * Clear EEM settings for the given PF so that the register values + * are reset back to there initial state. + */ + #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP UINT32_C(0x3) + #define HWRM_CFA_EEM_OP_INPUT_OP_LAST \ + HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP +} __attribute__((packed)); + +/* hwrm_cfa_eem_op_output (size:128b/16B) */ +struct hwrm_cfa_eem_op_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __attribute__((packed)); + +/******************************** + * hwrm_cfa_adv_flow_mgnt_qcaps * + ********************************/ + + +/* hwrm_cfa_adv_flow_mgnt_qcaps_input (size:256b/32B) */ +struct hwrm_cfa_adv_flow_mgnt_qcaps_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t unused_0[4]; +} __attribute__((packed)); + +/* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */ +struct hwrm_cfa_adv_flow_mgnt_qcaps_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint32_t flags; + /* + * Value of 1 to indicate firmware support 16-bit flow handle. + * Value of 0 to indicate firmware not support 16-bit flow handle. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_16BIT_SUPPORTED \ + UINT32_C(0x1) + /* + * Value of 1 to indicate firmware support 64-bit flow handle. + * Value of 0 to indicate firmware not support 64-bit flow handle. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_64BIT_SUPPORTED \ + UINT32_C(0x2) + /* + * Value of 1 to indicate firmware support flow batch delete operation through + * HWRM_CFA_FLOW_FLUSH command. + * Value of 0 to indicate that the firmware does not support flow batch delete + * operation. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_BATCH_DELETE_SUPPORTED \ + UINT32_C(0x4) + /* + * Value of 1 to indicate that the firmware support flow reset all operation through + * HWRM_CFA_FLOW_FLUSH command. + * Value of 0 indicates firmware does not support flow reset all operation. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_RESET_ALL_SUPPORTED \ + UINT32_C(0x8) + /* + * Value of 1 to indicate that firmware supports use of FID as dest_id in + * HWRM_CFA_NTUPLE_ALLOC/CFG commands. + * Value of 0 indicates firmware does not support use of FID as dest_id. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED \ + UINT32_C(0x10) + /* + * Value of 1 to indicate that firmware supports TX EEM flows. + * Value of 0 indicates firmware does not support TX EEM flows. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_TX_EEM_FLOW_SUPPORTED \ + UINT32_C(0x20) + /* + * Value of 1 to indicate that firmware supports RX EEM flows. + * Value of 0 indicates firmware does not support RX EEM flows. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RX_EEM_FLOW_SUPPORTED \ + UINT32_C(0x40) + /* + * Value of 1 to indicate that firmware supports the dynamic allocation of an + * on-chip flow counter which can be used for EEM flows. + * Value of 0 indicates firmware does not support the dynamic allocation of an + * on-chip flow counter. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED \ + UINT32_C(0x80) + /* + * Value of 1 to indicate that firmware supports setting of + * rfs_ring_tbl_idx in HWRM_CFA_NTUPLE_ALLOC command. + * Value of 0 indicates firmware does not support rfs_ring_tbl_idx. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_SUPPORTED \ + UINT32_C(0x100) + /* + * Value of 1 to indicate that firmware supports untagged matching + * criteria on HWRM_CFA_L2_FILTER_ALLOC command. Value of 0 + * indicates firmware does not support untagged matching. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_UNTAGGED_VLAN_SUPPORTED \ + UINT32_C(0x200) + /* + * Value of 1 to indicate that firmware supports XDP filter. Value + * of 0 indicates firmware does not support XDP filter. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_XDP_SUPPORTED \ + UINT32_C(0x400) + /* + * Value of 1 to indicate that the firmware support L2 header source + * fields matching criteria on HWRM_CFA_L2_FILTER_ALLOC command. + * Value of 0 indicates firmware does not support L2 header source + * fields matching. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED \ + UINT32_C(0x800) + /* + * If set to 1, firmware is capable of supporting ARP ethertype as + * matching criteria for HWRM_CFA_NTUPLE_FILTER_ALLOC command on the + * RX direction. By default, this flag should be 0 for older version + * of firmware. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ARP_SUPPORTED \ + UINT32_C(0x1000) + /* + * Value of 1 to indicate that firmware supports setting of + * rfs_ring_tbl_idx in dst_id field of the HWRM_CFA_NTUPLE_ALLOC + * command. Value of 0 indicates firmware does not support + * rfs_ring_tbl_idx in dst_id field. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED \ + UINT32_C(0x2000) + /* + * If set to 1, firmware is capable of supporting IPv4/IPv6 as + * ethertype in HWRM_CFA_NTUPLE_FILTER_ALLOC command on the RX + * direction. By default, this flag should be 0 for older version + * of firmware. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ETHERTYPE_IP_SUPPORTED \ + UINT32_C(0x4000) + uint8_t unused_0[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __attribute__((packed)); + +/****************** + * hwrm_cfa_tflib * + ******************/ + + +/* hwrm_cfa_tflib_input (size:1024b/128B) */ +struct hwrm_cfa_tflib_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* TFLIB message type. */ + uint16_t tf_type; + /* TFLIB message subtype. */ + uint16_t tf_subtype; + /* unused. */ + uint8_t unused0[4]; + /* TFLIB request data. */ + uint32_t tf_req[26]; +} __attribute__((packed)); + +/* hwrm_cfa_tflib_output (size:5632b/704B) */ +struct hwrm_cfa_tflib_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* TFLIB message type. */ + uint16_t tf_type; + /* TFLIB message subtype. */ + uint16_t tf_subtype; + /* TFLIB response code */ + uint32_t tf_resp_code; + /* TFLIB response data. */ + uint32_t tf_resp[170]; + /* unused. */ + uint8_t unused1[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __attribute__((packed)); + +/*********** + * hwrm_tf * + ***********/ + + +/* hwrm_tf_input (size:1024b/128B) */ +struct hwrm_tf_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* TF message type. */ + uint16_t type; + /* TF message subtype. */ + uint16_t subtype; + /* unused. */ + uint8_t unused0[4]; + /* TF request data. */ + uint32_t req[26]; +} __attribute__((packed)); + +/* hwrm_tf_output (size:5632b/704B) */ +struct hwrm_tf_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* TF message type. */ + uint16_t type; + /* TF message subtype. */ + uint16_t subtype; + /* TF response code */ + uint32_t resp_code; + /* TF response data. */ + uint32_t resp[170]; + /* unused. */ + uint8_t unused1[7]; + /* + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been + * completely written. When writing a command completion or + * response to an internal processor, the order of writes has + * to be such that this field is written last. + */ + uint8_t valid; +} __attribute__((packed)); + +/*********************** + * hwrm_tf_version_get * + ***********************/ + + +/* hwrm_tf_version_get_input (size:128b/16B) */ +struct hwrm_tf_version_get_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; +} __attribute__((packed)); + +/* hwrm_tf_version_get_output (size:128b/16B) */ +struct hwrm_tf_version_get_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Version Major number. */ + uint8_t major; + /* Version Minor number. */ + uint8_t minor; + /* Version Update number. */ + uint8_t update; + /* unused. */ + uint8_t unused0[4]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __attribute__((packed)); + +/************************ + * hwrm_tf_session_open * + ************************/ + + +/* hwrm_tf_session_open_input (size:640b/80B) */ +struct hwrm_tf_session_open_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Name of the session. */ + uint8_t session_name[64]; +} __attribute__((packed)); + +/* hwrm_tf_session_open_output (size:128b/16B) */ +struct hwrm_tf_session_open_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * Unique session identifier for the session created by the + * firmware. It includes PCIe bus info to distinguish the PF + * and session info to identify the associated TruFlow + * session. + */ + uint32_t fw_session_id; + /* unused. */ + uint8_t unused0[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __attribute__((packed)); + +/************************** + * hwrm_tf_session_attach * + **************************/ + + +/* hwrm_tf_session_attach_input (size:704b/88B) */ +struct hwrm_tf_session_attach_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Unique session identifier for the session that the attach + * request want to attach to. This value originates from the + * shared session memory that the attach request opened by + * way of the 'attach name' that was passed in to the core + * attach API. + * The fw_session_id of the attach session includes PCIe bus + * info to distinguish the PF and session info to identify + * the associated TruFlow session. + */ + uint32_t attach_fw_session_id; + /* unused. */ + uint32_t unused0; + /* Name of the session it self. */ + uint8_t session_name[64]; +} __attribute__((packed)); + +/* hwrm_tf_session_attach_output (size:128b/16B) */ +struct hwrm_tf_session_attach_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * Unique session identifier for the session created by the + * firmware. It includes PCIe bus info to distinguish the PF + * and session info to identify the associated TruFlow + * session. This fw_session_id is unique to the attach + * request. + */ + uint32_t fw_session_id; + /* unused. */ + uint8_t unused0[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __attribute__((packed)); + +/************************* + * hwrm_tf_session_close * + *************************/ + + +/* hwrm_tf_session_close_input (size:192b/24B) */ +struct hwrm_tf_session_close_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* unused. */ + uint8_t unused0[4]; +} __attribute__((packed)); + +/* hwrm_tf_session_close_output (size:128b/16B) */ +struct hwrm_tf_session_close_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* unused. */ + uint8_t unused0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; +} __attribute__((packed)); + +/************************ + * hwrm_tf_session_qcfg * + ************************/ + + +/* hwrm_tf_session_qcfg_input (size:192b/24B) */ +struct hwrm_tf_session_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* unused. */ + uint8_t unused0[4]; +} __attribute__((packed)); + +/* hwrm_tf_session_qcfg_output (size:128b/16B) */ +struct hwrm_tf_session_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* RX action control settings flags. */ + uint8_t rx_act_flags; + /* + * A value of 1 in this field indicates that Global Flow ID + * reporting into cfa_code and cfa_metadata is enabled. + */ + #define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_ABCR_GFID_EN \ + UINT32_C(0x1) + /* + * A value of 1 in this field indicates that both inner and outer + * are stripped and inner tag is passed. + * Enabled. + */ + #define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_ABCR_VTAG_DLT_BOTH \ + UINT32_C(0x2) + /* + * A value of 1 in this field indicates that the re-use of + * existing tunnel L2 header SMAC is enabled for + * Non-tunnel L2, L2-L3 and IP-IP tunnel. + */ + #define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_TECT_SMAC_OVR_RUTNSL2 \ + UINT32_C(0x4) + /* TX Action control settings flags. */ + uint8_t tx_act_flags; + /* Disabled. */ + #define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_ABCR_VEB_EN \ + UINT32_C(0x1) + /* + * When set to 1 any GRE tunnels will include the + * optional Key field. + */ + #define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_GRE_SET_K \ + UINT32_C(0x2) + /* + * When set to 1, for GRE tunnels, the IPV6 Traffic Class (TC) + * field of the outer header is inherited from the inner header + * (if present) or the fixed value as taken from the encap + * record. + */ + #define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_IPV6_TC_IH \ + UINT32_C(0x4) + /* + * When set to 1, for GRE tunnels, the IPV4 Type Of Service (TOS) + * field of the outer header is inherited from the inner header + * (if present) or the fixed value as taken from the encap record. + */ + #define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_IPV4_TOS_IH \ + UINT32_C(0x8) + /* unused. */ + uint8_t unused0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; +} __attribute__((packed)); + +/****************************** + * hwrm_tf_session_resc_qcaps * + ******************************/ + + +/* hwrm_tf_session_resc_qcaps_input (size:256b/32B) */ +struct hwrm_tf_session_resc_qcaps_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ + uint16_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_TX + /* + * Defines the size, in bytes, of the provided qcaps_addr + * buffer. The size should be set to the Resource Manager + * provided max qcaps value that is device specific. This is + * the max size possible. + */ + uint16_t size; + /* + * This is the DMA address for the qcaps output data + * array. Array is of tf_rm_cap type and is device specific. + */ + uint64_t qcaps_addr; +} __attribute__((packed)); + +/* hwrm_tf_session_resc_qcaps_output (size:192b/24B) */ +struct hwrm_tf_session_resc_qcaps_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Control flags. */ + uint32_t flags; + /* Session reservation strategy. */ + #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RES_STRATEGY_MASK \ + UINT32_C(0x3) + #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RES_STRATEGY_SFT \ + 0 + /* Static partitioning. */ + #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RES_STRATEGY_STATIC \ + UINT32_C(0x0) + /* Strategy 1. */ + #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RES_STRATEGY_1 \ + UINT32_C(0x1) + /* Strategy 2. */ + #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RES_STRATEGY_2 \ + UINT32_C(0x2) + /* Strategy 3. */ + #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RES_STRATEGY_3 \ + UINT32_C(0x3) + #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RES_STRATEGY_LAST \ + HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RES_STRATEGY_3 + /* + * Size of the returned tf_rm_cap data array. The value + * cannot exceed the size defined by the input msg. The data + * array is returned using the qcaps_addr specified DMA + * address also provided by the input msg. + */ + uint16_t size; + /* unused. */ + uint16_t unused0; + /* unused. */ + uint8_t unused1[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __attribute__((packed)); + +/****************************** + * hwrm_tf_session_resc_alloc * + ******************************/ + + +/* hwrm_tf_session_resc_alloc_input (size:256b/32B) */ +struct hwrm_tf_session_resc_alloc_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ + uint16_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_TX + /* + * Defines the size, in bytes, of the provided num_addr + * buffer. + */ + uint16_t size; + /* + * This is the DMA address for the num input data array + * buffer. Array is of tf_rm_num type. Size of the buffer is + * provided by the 'size' field in this message. + */ + uint64_t num_addr; +} __attribute__((packed)); + +/* hwrm_tf_session_resc_alloc_output (size:128b/16B) */ +struct hwrm_tf_session_resc_alloc_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* unused. */ + uint8_t unused0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __attribute__((packed)); + +/***************************** + * hwrm_tf_session_resc_free * + *****************************/ + + +/* hwrm_tf_session_resc_free_input (size:256b/32B) */ +struct hwrm_tf_session_resc_free_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ + uint16_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_TX + /* + * Defines the size, in bytes, of the provided free_addr + * buffer. + */ + uint16_t size; + /* + * This is the DMA address for the free input data array + * buffer. Array of tf_rm_res type. Size of the buffer is + * provided by the 'size field of this message. + */ + uint64_t free_addr; +} __attribute__((packed)); + +/* hwrm_tf_session_resc_free_output (size:128b/16B) */ +struct hwrm_tf_session_resc_free_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* unused. */ + uint8_t unused0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __attribute__((packed)); + +/****************************** + * hwrm_tf_session_resc_flush * + ******************************/ + + +/* hwrm_tf_session_resc_flush_input (size:256b/32B) */ +struct hwrm_tf_session_resc_flush_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ + uint16_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_TX + /* + * Defines the size, in bytes, of the provided flush_addr + * buffer. + */ + uint16_t size; + /* + * This is the DMA address for the flush input data array + * buffer. Array of tf_rm_res type. Size of the buffer is + * provided by the 'size' field in this message. + */ + uint64_t flush_addr; +} __attribute__((packed)); + +/* hwrm_tf_session_resc_flush_output (size:128b/16B) */ +struct hwrm_tf_session_resc_flush_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* unused. */ + uint8_t unused0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __attribute__((packed)); + +/* TruFlow RM capability of a resource. */ +/* tf_rm_cap (size:64b/8B) */ +struct tf_rm_cap { + /* + * Type of the resource, defined globally in the + * hwrm_tf_resc_type enum. + */ + uint32_t type; + /* Minimum value. */ + uint16_t min; + /* Maximum value. */ + uint16_t max; +} __attribute__((packed)); + +/* TruFlow RM number of a resource. */ +/* tf_rm_num (size:64b/8B) */ +struct tf_rm_num { + /* + * Type of the resource, defined globally in the + * hwrm_tf_resc_type enum. + */ + uint32_t type; + /* Number of resources. */ + uint32_t num; +} __attribute__((packed)); + +/* TruFlow RM reservation information. */ +/* tf_rm_res (size:64b/8B) */ +struct tf_rm_res { + /* + * Type of the resource, defined globally in the + * hwrm_tf_resc_type enum. + */ + uint32_t type; + /* Start offset. */ + uint16_t start; + /* Number of resources. */ + uint16_t stride; +} __attribute__((packed)); + +/************************ + * hwrm_tf_tbl_type_get * + ************************/ + + +/* hwrm_tf_tbl_type_get_input (size:256b/32B) */ +struct hwrm_tf_tbl_type_get_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ + uint16_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX + /* unused. */ + uint8_t unused0[2]; + /* + * Type of the resource, defined globally in the + * hwrm_tf_resc_type enum. + */ + uint32_t type; + /* Index of the type to retrieve. */ + uint32_t index; +} __attribute__((packed)); + +/* hwrm_tf_tbl_type_get_output (size:1216b/152B) */ +struct hwrm_tf_tbl_type_get_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Response code. */ + uint32_t resp_code; + /* Response size. */ + uint16_t size; + /* unused */ + uint16_t unused0; + /* Response data. */ + uint8_t data[128]; + /* unused */ + uint8_t unused1[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; +} __attribute__((packed)); + +/************************ + * hwrm_tf_tbl_type_set * + ************************/ + + +/* hwrm_tf_tbl_type_set_input (size:1024b/128B) */ +struct hwrm_tf_tbl_type_set_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ + uint16_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX + /* unused. */ + uint8_t unused0[2]; + /* + * Type of the resource, defined globally in the + * hwrm_tf_resc_type enum. + */ + uint32_t type; + /* Index of the type to retrieve. */ + uint32_t index; + /* Size of the data to set. */ + uint16_t size; + /* unused */ + uint8_t unused1[6]; + /* Data to be set. */ + uint8_t data[88]; +} __attribute__((packed)); + +/* hwrm_tf_tbl_type_set_output (size:128b/16B) */ +struct hwrm_tf_tbl_type_set_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* unused. */ + uint8_t unused0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; +} __attribute__((packed)); + +/************************* + * hwrm_tf_ctxt_mem_rgtr * + *************************/ + + +/* hwrm_tf_ctxt_mem_rgtr_input (size:256b/32B) */ +struct hwrm_tf_ctxt_mem_rgtr_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Control flags. */ + uint16_t flags; + /* Counter PBL indirect levels. */ + uint8_t page_level; + /* PBL pointer is physical start address. */ + #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0) + /* PBL pointer points to PTE table. */ + #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1) + /* + * PBL pointer points to PDE table with each entry pointing + * to PTE tables. + */ + #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2) + #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LAST \ + HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 + /* Page size. */ + uint8_t page_size; + /* 4KB page size. */ + #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_4K UINT32_C(0x0) + /* 8KB page size. */ + #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_8K UINT32_C(0x1) + /* 64KB page size. */ + #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_64K UINT32_C(0x4) + /* 256KB page size. */ + #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_256K UINT32_C(0x6) + /* 1MB page size. */ + #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1M UINT32_C(0x8) + /* 2MB page size. */ + #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_2M UINT32_C(0x9) + /* 4MB page size. */ + #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_4M UINT32_C(0xa) + /* 1GB page size. */ + #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1G UINT32_C(0x12) + #define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_LAST \ + HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1G + /* unused. */ + uint32_t unused0; + /* Pointer to the PBL, or PDL depending on number of levels */ + uint64_t page_dir; +} __attribute__((packed)); + +/* hwrm_tf_ctxt_mem_rgtr_output (size:128b/16B) */ +struct hwrm_tf_ctxt_mem_rgtr_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * Id/Handle to the recently register context memory. This + * handle is passed to the TF session. + */ + uint16_t ctx_id; + /* unused. */ + uint8_t unused0[5]; + /* + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been + * completely written. When writing a command completion or + * response to an internal processor, the order of writes has + * to be such that this field is written last. + */ + uint8_t valid; +} __attribute__((packed)); + +/*************************** + * hwrm_tf_ctxt_mem_unrgtr * + ***************************/ + + +/* hwrm_tf_ctxt_mem_unrgtr_input (size:192b/24B) */ +struct hwrm_tf_ctxt_mem_unrgtr_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Id/Handle to the recently register context memory. This + * handle is passed to the TF session. + */ + uint16_t ctx_id; + /* unused. */ + uint8_t unused0[6]; +} __attribute__((packed)); + +/* hwrm_tf_ctxt_mem_unrgtr_output (size:128b/16B) */ +struct hwrm_tf_ctxt_mem_unrgtr_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* unused. */ + uint8_t unused0[7]; + /* + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been + * completely written. When writing a command completion or + * response to an internal processor, the order of writes has + * to be such that this field is written last. + */ + uint8_t valid; +} __attribute__((packed)); + +/************************ + * hwrm_tf_ext_em_qcaps * + ************************/ + + +/* hwrm_tf_ext_em_qcaps_input (size:192b/24B) */ +struct hwrm_tf_ext_em_qcaps_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Control flags. */ + uint32_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR \ + UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_RX \ + UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_TX \ + UINT32_C(0x1) + #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_TX + /* When set to 1, all offloaded flows will be sent to EXT EM. */ + #define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_PREFERRED_OFFLOAD \ + UINT32_C(0x2) + /* unused. */ + uint32_t unused0; +} __attribute__((packed)); + +/* hwrm_tf_ext_em_qcaps_output (size:320b/40B) */ +struct hwrm_tf_ext_em_qcaps_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint32_t flags; + /* + * When set to 1, indicates the the FW supports the Centralized + * Memory Model. The concept designates one entity for the + * memory allocation while all others ‘subscribe’ to it. + */ + #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED \ + UINT32_C(0x1) + /* + * When set to 1, indicates the the FW supports the Detached + * Centralized Memory Model. The memory is allocated and managed + * as a separate entity. All PFs and VFs will be granted direct + * or semi-direct access to the allocated memory while none of + * which can interfere with the management of the memory. + */ + #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED \ + UINT32_C(0x2) + /* unused. */ + uint32_t unused0; + /* Support flags. */ + uint32_t supported; + /* + * If set to 1, then EXT EM KEY0 table is supported using + * crc32 hash. + * If set to 0, EXT EM KEY0 table is not supported. + */ + #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_KEY0_TABLE \ + UINT32_C(0x1) + /* + * If set to 1, then EXT EM KEY1 table is supported using + * lookup3 hash. + * If set to 0, EXT EM KEY1 table is not supported. + */ + #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_KEY1_TABLE \ + UINT32_C(0x2) + /* + * If set to 1, then EXT EM External Record table is supported. + * If set to 0, EXT EM External Record table is not + * supported. (This table includes action record, EFC + * pointers, encap pointers) + */ + #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_RECORD_TABLE \ + UINT32_C(0x4) + /* + * If set to 1, then EXT EM External Flow Counters table is + * supported. + * If set to 0, EXT EM External Flow Counters table is not + * supported. + */ + #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE \ + UINT32_C(0x8) + /* + * If set to 1, then FID table used for implicit flow flush + * is supported. + * If set to 0, then FID table used for implicit flow flush + * is not supported. + */ + #define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_FID_TABLE \ + UINT32_C(0x10) + /* + * The maximum number of entries supported by EXT EM. When + * configuring the host memory the number of numbers of + * entries that can supported are - + * 32k, 64k 128k, 256k, 512k, 1M, 2M, 4M, 8M, 32M, 64M, + * 128M entries. + * Any value that are not these values, the FW will round + * down to the closest support number of entries. + */ + uint32_t max_entries_supported; + /* + * The entry size in bytes of each entry in the EXT EM + * KEY0/KEY1 tables. + */ + uint16_t key_entry_size; + /* + * The entry size in bytes of each entry in the EXT EM RECORD + * tables. + */ + uint16_t record_entry_size; + /* The entry size in bytes of each entry in the EXT EM EFC tables. */ + uint16_t efc_entry_size; + /* The FID size in bytes of each entry in the EXT EM FID tables. */ + uint16_t fid_entry_size; + /* unused. */ + uint8_t unused1[7]; + /* + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been + * completely written. When writing a command completion or + * response to an internal processor, the order of writes has + * to be such that this field is written last. + */ + uint8_t valid; +} __attribute__((packed)); + +/********************* + * hwrm_tf_ext_em_op * + *********************/ + + +/* hwrm_tf_ext_em_op_input (size:192b/24B) */ +struct hwrm_tf_ext_em_op_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Control flags. */ + uint16_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_TX + /* unused. */ + uint16_t unused0; + /* The number of EXT EM key table entries to be configured. */ + uint16_t op; + /* This value is reserved and should not be used. */ + #define HWRM_TF_EXT_EM_OP_INPUT_OP_RESERVED UINT32_C(0x0) + /* + * To properly stop EXT EM and ensure there are no DMA's, + * the caller must disable EXT EM for the given PF, using + * this call. This will safely disable EXT EM and ensure + * that all DMA'ed to the keys/records/efc have been + * completed. + */ + #define HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_DISABLE UINT32_C(0x1) + /* + * Once the EXT EM host memory has been configured, EXT EM + * options have been configured. Then the caller should + * enable EXT EM for the given PF. Note once this call has + * been made, then the EXT EM mechanism will be active and + * DMA's will occur as packets are processed. + */ + #define HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_ENABLE UINT32_C(0x2) + /* + * Clear EXT EM settings for the given PF so that the + * register values are reset back to their initial state. + */ + #define HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_CLEANUP UINT32_C(0x3) + #define HWRM_TF_EXT_EM_OP_INPUT_OP_LAST \ + HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_CLEANUP + /* unused. */ + uint16_t unused1; +} __attribute__((packed)); + +/* hwrm_tf_ext_em_op_output (size:128b/16B) */ +struct hwrm_tf_ext_em_op_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* unused. */ + uint8_t unused0[7]; + /* + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been + * completely written. When writing a command completion or + * response to an internal processor, the order of writes has + * to be such that this field is written last. + */ + uint8_t valid; +} __attribute__((packed)); + +/********************** + * hwrm_tf_ext_em_cfg * + **********************/ + + +/* hwrm_tf_ext_em_cfg_input (size:384b/48B) */ +struct hwrm_tf_ext_em_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Control flags. */ + uint32_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR \ + UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_RX \ + UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_TX \ + UINT32_C(0x1) + #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_TX + /* When set to 1, all offloaded flows will be sent to EXT EM. */ + #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_PREFERRED_OFFLOAD \ + UINT32_C(0x2) + /* When set to 1, secondary, 0 means primary. */ + #define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_SECONDARY_PF \ + UINT32_C(0x4) + /* + * Group_id which used by Firmware to identify memory pools belonging + * to certain group. + */ + uint16_t group_id; + /* + * Dynamically reconfigure EEM pending cache every 1/10th of second. + * If set to 0 it will disable the EEM HW flush of the pending cache. + */ + uint8_t flush_interval; + /* unused. */ + uint8_t unused0; + /* + * Configured EXT EM with the given number of entries. All + * the EXT EM tables KEY0, KEY1, RECORD, EFC all have the + * same number of entries and all tables will be configured + * using this value. Current minimum value is 32k. Current + * maximum value is 128M. + */ + uint32_t num_entries; + /* unused. */ + uint32_t unused1; + /* Configured EXT EM with the given context if for KEY0 table. */ + uint16_t key0_ctx_id; + /* Configured EXT EM with the given context if for KEY1 table. */ + uint16_t key1_ctx_id; + /* Configured EXT EM with the given context if for RECORD table. */ + uint16_t record_ctx_id; + /* Configured EXT EM with the given context if for EFC table. */ + uint16_t efc_ctx_id; + /* Configured EXT EM with the given context if for EFC table. */ + uint16_t fid_ctx_id; + /* unused. */ + uint16_t unused2; + /* unused. */ + uint32_t unused3; +} __attribute__((packed)); + +/* hwrm_tf_ext_em_cfg_output (size:128b/16B) */ +struct hwrm_tf_ext_em_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* unused. */ + uint8_t unused0[7]; + /* + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been + * completely written. When writing a command completion or + * response to an internal processor, the order of writes has + * to be such that this field is written last. + */ + uint8_t valid; +} __attribute__((packed)); + +/*********************** + * hwrm_tf_ext_em_qcfg * + ***********************/ + + +/* hwrm_tf_ext_em_qcfg_input (size:192b/24B) */ +struct hwrm_tf_ext_em_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Control flags. */ + uint32_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX + /* unused. */ + uint32_t unused0; +} __attribute__((packed)); + +/* hwrm_tf_ext_em_qcfg_output (size:256b/32B) */ +struct hwrm_tf_ext_em_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Control flags. */ + uint32_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR \ + UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_RX \ + UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_TX \ + UINT32_C(0x1) + #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_LAST \ + HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_TX + /* When set to 1, all offloaded flows will be sent to EXT EM. */ + #define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_PREFERRED_OFFLOAD \ + UINT32_C(0x2) + /* The number of entries the FW has configured for EXT EM. */ + uint32_t num_entries; + /* Configured EXT EM with the given context if for KEY0 table. */ + uint16_t key0_ctx_id; + /* Configured EXT EM with the given context if for KEY1 table. */ + uint16_t key1_ctx_id; + /* Configured EXT EM with the given context if for RECORD table. */ + uint16_t record_ctx_id; + /* Configured EXT EM with the given context if for EFC table. */ + uint16_t efc_ctx_id; + /* Configured EXT EM with the given context if for EFC table. */ + uint16_t fid_ctx_id; + /* unused. */ + uint8_t unused0[5]; + /* + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been + * completely written. When writing a command completion or + * response to an internal processor, the order of writes has + * to be such that this field is written last. + */ + uint8_t valid; +} __attribute__((packed)); + +/******************** + * hwrm_tf_tcam_set * + ********************/ + + +/* hwrm_tf_tcam_set_input (size:1024b/128B) */ +struct hwrm_tf_tcam_set_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ + uint32_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_TX + /* + * Indicate device data is being sent via DMA, the device + * data is packing does not change. + */ + #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DMA UINT32_C(0x2) + /* + * TCAM type of the resource, defined globally in the + * hwrm_tf_resc_type enum. + */ + uint32_t type; + /* Index of TCAM entry. */ + uint16_t idx; + /* Number of bytes in the TCAM key. */ + uint8_t key_size; + /* Number of bytes in the TCAM result. */ + uint8_t result_size; + /* + * Offset from which the mask bytes start in the device data + * array, key offset is always 0. + */ + uint8_t mask_offset; + /* Offset from which the result bytes start in the device data array. */ + uint8_t result_offset; + /* unused. */ + uint8_t unused0[6]; + /* + * TCAM key located at offset 0, mask located at mask_offsec + * and result at result_offsec for the device. + */ + uint8_t dev_data[88]; } __attribute__((packed)); -/* hwrm_cfa_eem_qcfg_output (size:256b/32B) */ -struct hwrm_cfa_eem_qcfg_output { +/* hwrm_tf_tcam_set_output (size:128b/16B) */ +struct hwrm_tf_tcam_set_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -31848,46 +35014,26 @@ struct hwrm_cfa_eem_qcfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint32_t flags; - /* When set to 1, indicates the configuration is the TX flow. */ - #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_TX \ - UINT32_C(0x1) - /* When set to 1, indicates the configuration is the RX flow. */ - #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_RX \ - UINT32_C(0x2) - /* When set to 1, all offloaded flows will be sent to EEM. */ - #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PREFERRED_OFFLOAD \ - UINT32_C(0x4) - /* The number of entries the FW has configured for EEM. */ - uint32_t num_entries; - /* Configured EEM with the given context if for KEY0 table. */ - uint16_t key0_ctx_id; - /* Configured EEM with the given context if for KEY1 table. */ - uint16_t key1_ctx_id; - /* Configured EEM with the given context if for RECORD table. */ - uint16_t record_ctx_id; - /* Configured EEM with the given context if for EFC table. */ - uint16_t efc_ctx_id; - /* Configured EEM with the given context if for EFC table. */ - uint16_t fid_ctx_id; - uint8_t unused_2[5]; + /* unused. */ + uint8_t unused0[7]; /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been + * completely written. When writing a command completion or + * response to an internal processor, the order of writes has + * to be such that this field is written last. */ uint8_t valid; } __attribute__((packed)); -/******************* - * hwrm_cfa_eem_op * - *******************/ +/******************** + * hwrm_tf_tcam_get * + ********************/ -/* hwrm_cfa_eem_op_input (size:192b/24B) */ -struct hwrm_cfa_eem_op_input { +/* hwrm_tf_tcam_get_input (size:256b/32B) */ +struct hwrm_tf_tcam_get_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -31916,49 +35062,31 @@ struct hwrm_cfa_eem_op_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ uint32_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX /* - * When set to 1, indicates the host memory which is passed will be - * used for the TX flow offload function specified in fid. - * Note if this bit is set then the path_rx bit can't be set. - */ - #define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_TX UINT32_C(0x1) - /* - * When set to 1, indicates the host memory which is passed will be - * used for the RX flow offload function specified in fid. - * Note if this bit is set then the path_tx bit can't be set. - */ - #define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_RX UINT32_C(0x2) - uint16_t unused_0; - /* The number of EEM key table entries to be configured. */ - uint16_t op; - /* This value is reserved and should not be used. */ - #define HWRM_CFA_EEM_OP_INPUT_OP_RESERVED UINT32_C(0x0) - /* - * To properly stop EEM and ensure there are no DMA's, the caller - * must disable EEM for the given PF, using this call. This will - * safely disable EEM and ensure that all DMA'ed to the - * keys/records/efc have been completed. - */ - #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_DISABLE UINT32_C(0x1) - /* - * Once the EEM host memory has been configured, EEM options have - * been configured. Then the caller should enable EEM for the given - * PF. Note once this call has been made, then the EEM mechanism - * will be active and DMA's will occur as packets are processed. + * TCAM type of the resource, defined globally in the + * hwrm_tf_resc_type enum. */ - #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_ENABLE UINT32_C(0x2) - /* - * Clear EEM settings for the given PF so that the register values - * are reset back to there initial state. - */ - #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP UINT32_C(0x3) - #define HWRM_CFA_EEM_OP_INPUT_OP_LAST \ - HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP + uint32_t type; + /* Index of a TCAM entry. */ + uint16_t idx; + /* unused. */ + uint16_t unused0; } __attribute__((packed)); -/* hwrm_cfa_eem_op_output (size:128b/16B) */ -struct hwrm_cfa_eem_op_output { +/* hwrm_tf_tcam_get_output (size:2368b/296B) */ +struct hwrm_tf_tcam_get_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -31967,24 +35095,41 @@ struct hwrm_cfa_eem_op_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_0[7]; + /* Number of bytes in the TCAM key. */ + uint8_t key_size; + /* Number of bytes in the TCAM entry. */ + uint8_t result_size; + /* Offset from which the mask bytes start in the device data array. */ + uint8_t mask_offset; + /* Offset from which the result bytes start in the device data array. */ + uint8_t result_offset; + /* unused. */ + uint8_t unused0[4]; /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * TCAM key located at offset 0, mask located at mask_offsec + * and result at result_offsec for the device. + */ + uint8_t dev_data[272]; + /* unused. */ + uint8_t unused1[7]; + /* + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been + * completely written. When writing a command completion or + * response to an internal processor, the order of writes has + * to be such that this field is written last. */ uint8_t valid; } __attribute__((packed)); -/******************************** - * hwrm_cfa_adv_flow_mgnt_qcaps * - ********************************/ +/********************* + * hwrm_tf_tcam_move * + *********************/ -/* hwrm_cfa_adv_flow_mgnt_qcaps_input (size:256b/32B) */ -struct hwrm_cfa_adv_flow_mgnt_qcaps_input { +/* hwrm_tf_tcam_move_input (size:1024b/128B) */ +struct hwrm_tf_tcam_move_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -32013,11 +35158,33 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - uint32_t unused_0[4]; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ + uint32_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX + /* + * TCAM type of the resource, defined globally in the + * hwrm_tf_resc_type enum. + */ + uint32_t type; + /* Number of TCAM index pairs to be swapped for the device. */ + uint16_t count; + /* unused. */ + uint16_t unused0; + /* TCAM index pairs to be swapped for the device. */ + uint16_t idx_pairs[48]; } __attribute__((packed)); -/* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */ -struct hwrm_cfa_adv_flow_mgnt_qcaps_output { +/* hwrm_tf_tcam_move_output (size:128b/16B) */ +struct hwrm_tf_tcam_move_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -32026,131 +35193,26 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint32_t flags; - /* - * Value of 1 to indicate firmware support 16-bit flow handle. - * Value of 0 to indicate firmware not support 16-bit flow handle. - */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_16BIT_SUPPORTED \ - UINT32_C(0x1) - /* - * Value of 1 to indicate firmware support 64-bit flow handle. - * Value of 0 to indicate firmware not support 64-bit flow handle. - */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_64BIT_SUPPORTED \ - UINT32_C(0x2) - /* - * Value of 1 to indicate firmware support flow batch delete operation through - * HWRM_CFA_FLOW_FLUSH command. - * Value of 0 to indicate that the firmware does not support flow batch delete - * operation. - */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_BATCH_DELETE_SUPPORTED \ - UINT32_C(0x4) - /* - * Value of 1 to indicate that the firmware support flow reset all operation through - * HWRM_CFA_FLOW_FLUSH command. - * Value of 0 indicates firmware does not support flow reset all operation. - */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_RESET_ALL_SUPPORTED \ - UINT32_C(0x8) - /* - * Value of 1 to indicate that firmware supports use of FID as dest_id in - * HWRM_CFA_NTUPLE_ALLOC/CFG commands. - * Value of 0 indicates firmware does not support use of FID as dest_id. - */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED \ - UINT32_C(0x10) - /* - * Value of 1 to indicate that firmware supports TX EEM flows. - * Value of 0 indicates firmware does not support TX EEM flows. - */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_TX_EEM_FLOW_SUPPORTED \ - UINT32_C(0x20) - /* - * Value of 1 to indicate that firmware supports RX EEM flows. - * Value of 0 indicates firmware does not support RX EEM flows. - */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RX_EEM_FLOW_SUPPORTED \ - UINT32_C(0x40) - /* - * Value of 1 to indicate that firmware supports the dynamic allocation of an - * on-chip flow counter which can be used for EEM flows. - * Value of 0 indicates firmware does not support the dynamic allocation of an - * on-chip flow counter. - */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED \ - UINT32_C(0x80) - /* - * Value of 1 to indicate that firmware supports setting of - * rfs_ring_tbl_idx in HWRM_CFA_NTUPLE_ALLOC command. - * Value of 0 indicates firmware does not support rfs_ring_tbl_idx. - */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_SUPPORTED \ - UINT32_C(0x100) - /* - * Value of 1 to indicate that firmware supports untagged matching - * criteria on HWRM_CFA_L2_FILTER_ALLOC command. Value of 0 - * indicates firmware does not support untagged matching. - */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_UNTAGGED_VLAN_SUPPORTED \ - UINT32_C(0x200) - /* - * Value of 1 to indicate that firmware supports XDP filter. Value - * of 0 indicates firmware does not support XDP filter. - */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_XDP_SUPPORTED \ - UINT32_C(0x400) - /* - * Value of 1 to indicate that the firmware support L2 header source - * fields matching criteria on HWRM_CFA_L2_FILTER_ALLOC command. - * Value of 0 indicates firmware does not support L2 header source - * fields matching. - */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED \ - UINT32_C(0x800) - /* - * If set to 1, firmware is capable of supporting ARP ethertype as - * matching criteria for HWRM_CFA_NTUPLE_FILTER_ALLOC command on the - * RX direction. By default, this flag should be 0 for older version - * of firmware. - */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ARP_SUPPORTED \ - UINT32_C(0x1000) - /* - * Value of 1 to indicate that firmware supports setting of - * rfs_ring_tbl_idx in dst_id field of the HWRM_CFA_NTUPLE_ALLOC - * command. Value of 0 indicates firmware does not support - * rfs_ring_tbl_idx in dst_id field. - */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED \ - UINT32_C(0x2000) - /* - * If set to 1, firmware is capable of supporting IPv4/IPv6 as - * ethertype in HWRM_CFA_NTUPLE_FILTER_ALLOC command on the RX - * direction. By default, this flag should be 0 for older version - * of firmware. - */ - #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ETHERTYPE_IP_SUPPORTED \ - UINT32_C(0x4000) - uint8_t unused_0[3]; + /* unused. */ + uint8_t unused0[7]; /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been + * completely written. When writing a command completion or + * response to an internal processor, the order of writes has + * to be such that this field is written last. */ uint8_t valid; } __attribute__((packed)); -/****************** - * hwrm_cfa_tflib * - ******************/ +/********************* + * hwrm_tf_tcam_free * + *********************/ -/* hwrm_cfa_tflib_input (size:1024b/128B) */ -struct hwrm_cfa_tflib_input { +/* hwrm_tf_tcam_free_input (size:1024b/128B) */ +struct hwrm_tf_tcam_free_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -32179,18 +35241,33 @@ struct hwrm_cfa_tflib_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* TFLIB message type. */ - uint16_t tf_type; - /* TFLIB message subtype. */ - uint16_t tf_subtype; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ + uint32_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates that tx flow. */ + #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX + /* + * TCAM type of the resource, defined globally in the + * hwrm_tf_resc_type enum. + */ + uint32_t type; + /* Number of TCAM index to be deleted for the device. */ + uint16_t count; /* unused. */ - uint8_t unused0[4]; - /* TFLIB request data. */ - uint32_t tf_req[26]; + uint16_t unused0; + /* TCAM index list to be deleted for the device. */ + uint16_t idx_list[48]; } __attribute__((packed)); -/* hwrm_cfa_tflib_output (size:5632b/704B) */ -struct hwrm_cfa_tflib_output { +/* hwrm_tf_tcam_free_output (size:128b/16B) */ +struct hwrm_tf_tcam_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -32199,22 +35276,15 @@ struct hwrm_cfa_tflib_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* TFLIB message type. */ - uint16_t tf_type; - /* TFLIB message subtype. */ - uint16_t tf_subtype; - /* TFLIB response code */ - uint32_t tf_resp_code; - /* TFLIB response data. */ - uint32_t tf_resp[170]; /* unused. */ - uint8_t unused1[7]; + uint8_t unused0[7]; /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been + * completely written. When writing a command completion or + * response to an internal processor, the order of writes has + * to be such that this field is written last. */ uint8_t valid; } __attribute__((packed)); @@ -33155,9 +36225,9 @@ struct pcie_ctx_hw_stats { uint64_t pcie_tl_signal_integrity; /* Number of times LTSSM entered Recovery state */ uint64_t pcie_link_integrity; - /* Number of TLP bytes that have been transmitted */ + /* Report number of TLP bits that have been transmitted in Mbps */ uint64_t pcie_tx_traffic_rate; - /* Number of TLP bytes that have been received */ + /* Report number of TLP bits that have been received in Mbps */ uint64_t pcie_rx_traffic_rate; /* Number of DLLP bytes that have been transmitted */ uint64_t pcie_tx_dllp_statistics; @@ -33981,7 +37051,23 @@ struct hwrm_nvm_modify_input { uint64_t host_src_addr; /* 16-bit directory entry index. */ uint16_t dir_idx; - uint8_t unused_0[2]; + uint16_t flags; + /* + * This flag indicates the sender wants to modify a continuous NVRAM + * area using a batch of this HWRM requests. The offset of a request + * must be continuous to the end of previous request's. Firmware does + * not update the directory entry until receiving the last request, + * which is indicated by the batch_last flag. + * This flag is set usually when a sender does not have a block of + * memory that is big enough to hold the entire NVRAM data for send + * at one time. + */ + #define HWRM_NVM_MODIFY_INPUT_FLAGS_BATCH_MODE UINT32_C(0x1) + /* + * This flag can be used only when the batch_mode flag is set. + * It indicates this request is the last of batch requests. + */ + #define HWRM_NVM_MODIFY_INPUT_FLAGS_BATCH_LAST UINT32_C(0x2) /* 32-bit NVRAM byte-offset to modify content from. */ uint32_t offset; /* -- 2.7.4