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From: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
To: dev@dpdk.org
Cc: Mike Baucom <michael.baucom@broadcom.com>,
 Kishore Padmanabha <kishore.padmanabha@broadcom.com>,
 Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
Date: Tue, 14 Apr 2020 13:43:17 +0530
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 <1586852011-37536-1-git-send-email-venkatkumar.duvvuru@broadcom.com>
Subject: [dpdk-dev] [PATCH v3 20/34] net/bnxt: add support to process key
	tables
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From: Mike Baucom <michael.baucom@broadcom.com>

This patch creates the classifier table entries for a flow.

Signed-off-by: Mike Baucom <michael.baucom@broadcom.com>
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
Reviewed-by: Lance Richardson <lance.richardson@broadcom.com>
Reviewed-by: Ajit Kumar Khaparde <ajit.khaparde@broadcom.com>
---
 drivers/net/bnxt/tf_ulp/ulp_mapper.c            | 773 +++++++++++++++++++++-
 drivers/net/bnxt/tf_ulp/ulp_mapper.h            |   2 +
 drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c          |  80 ++-
 drivers/net/bnxt/tf_ulp/ulp_mark_mgr.h          |  18 +
 drivers/net/bnxt/tf_ulp/ulp_template_db.c       | 829 ++++++++++++++++++++++++
 drivers/net/bnxt/tf_ulp/ulp_template_db.h       | 142 +++-
 drivers/net/bnxt/tf_ulp/ulp_template_field_db.h | 133 ++++
 drivers/net/bnxt/tf_ulp/ulp_template_struct.h   |  93 ++-
 8 files changed, 2062 insertions(+), 8 deletions(-)
 create mode 100644 drivers/net/bnxt/tf_ulp/ulp_template_field_db.h

diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
index 9cfc382..a041394 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
@@ -19,6 +19,9 @@
 int32_t
 ulp_mapper_action_tbls_process(struct bnxt_ulp_mapper_parms *parms);
 
+int32_t
+ulp_mapper_class_tbls_process(struct bnxt_ulp_mapper_parms *parms);
+
 /*
  * Get the size of the action property for a given index.
  *
@@ -37,10 +40,65 @@ ulp_mapper_act_prop_size_get(uint32_t idx)
 /*
  * Get the list of result fields that implement the flow action
  *
+ * ctxt [in] The ulp context
+ *
+ * tbl [in] A single table instance to get the key fields from
+ *
+ * num_flds [out] The number of key fields in the returned array
+ *
+ * returns array of Key fields, or NULL on error
+ */
+static struct bnxt_ulp_mapper_class_key_field_info *
+ulp_mapper_key_fields_get(struct bnxt_ulp_mapper_class_tbl_info *tbl,
+			  uint32_t *num_flds)
+{
+	uint32_t idx;
+
+	if (!tbl || !num_flds)
+		return NULL;
+
+	idx		= tbl->key_start_idx;
+	*num_flds	= tbl->key_num_fields;
+
+	/* NOTE: Need template to provide range checking define */
+	return &ulp_class_key_field_list[idx];
+}
+
+/*
+ * Get the list of data fields that implement the flow.
+ *
+ * ctxt [in] The ulp context
+ *
+ * tbl [in] A single table instance to get the data fields from
+ *
+ * num_flds [out] The number of data fields in the returned array.
+ *
+ * Returns array of data fields, or NULL on error.
+ */
+static struct bnxt_ulp_mapper_result_field_info *
+ulp_mapper_result_fields_get(struct bnxt_ulp_mapper_class_tbl_info *tbl,
+			     uint32_t *num_flds)
+{
+	uint32_t idx;
+
+	if (!tbl || !num_flds)
+		return NULL;
+
+	idx		= tbl->result_start_idx;
+	*num_flds	= tbl->result_num_fields;
+
+	/* NOTE: Need template to provide range checking define */
+	return &ulp_class_result_field_list[idx];
+}
+
+/*
+ * Get the list of result fields that implement the flow action.
+ *
  * tbl [in] A single table instance to get the results fields
  * from num_flds [out] The number of data fields in the returned
- * array
- * returns array of data fields, or NULL on error
+ * array.
+ *
+ * Returns array of data fields, or NULL on error.
  */
 static struct bnxt_ulp_mapper_result_field_info *
 ulp_mapper_act_result_fields_get(struct bnxt_ulp_mapper_act_tbl_info *tbl,
@@ -60,6 +118,106 @@ ulp_mapper_act_result_fields_get(struct bnxt_ulp_mapper_act_tbl_info *tbl,
 	return &ulp_act_result_field_list[idx];
 }
 
+/*
+ * Get the list of ident fields that implement the flow
+ *
+ * tbl [in] A single table instance to get the ident fields from
+ *
+ * num_flds [out] The number of ident fields in the returned array
+ *
+ * returns array of ident fields, or NULL on error
+ */
+static struct bnxt_ulp_mapper_ident_info *
+ulp_mapper_ident_fields_get(struct bnxt_ulp_mapper_class_tbl_info *tbl,
+			    uint32_t *num_flds)
+{
+	uint32_t idx;
+
+	if (!tbl || !num_flds)
+		return NULL;
+
+	idx = tbl->ident_start_idx;
+	*num_flds = tbl->ident_nums;
+
+	/* NOTE: Need template to provide range checking define */
+	return &ulp_ident_list[idx];
+}
+
+static int32_t
+ulp_mapper_ident_process(struct bnxt_ulp_mapper_parms *parms,
+			 struct bnxt_ulp_mapper_class_tbl_info *tbl,
+			 struct bnxt_ulp_mapper_ident_info *ident)
+{
+	struct ulp_flow_db_res_params	fid_parms;
+	uint64_t id = 0;
+	int32_t idx;
+	struct tf_alloc_identifier_parms iparms = { 0 };
+	struct tf_free_identifier_parms free_parms = { 0 };
+	struct tf *tfp;
+	int rc;
+
+	tfp = bnxt_ulp_cntxt_tfp_get(parms->ulp_ctx);
+	if (!tfp) {
+		BNXT_TF_DBG(ERR, "Failed to get tf pointer\n");
+		return -EINVAL;
+	}
+
+	idx = ident->regfile_wr_idx;
+
+	iparms.ident_type = ident->ident_type;
+	iparms.dir = tbl->direction;
+
+	rc = tf_alloc_identifier(tfp, &iparms);
+	if (rc) {
+		BNXT_TF_DBG(ERR, "Alloc ident %s:%d failed.\n",
+			    (iparms.dir == TF_DIR_RX) ? "RX" : "TX",
+			    iparms.ident_type);
+		return rc;
+	}
+
+	id = (uint64_t)tfp_cpu_to_be_64(iparms.id);
+	if (!ulp_regfile_write(parms->regfile, idx, id)) {
+		BNXT_TF_DBG(ERR, "Regfile[%d] write failed.\n", idx);
+		rc = -EINVAL;
+		/* Need to free the identifier, so goto error */
+		goto error;
+	}
+
+	/* Link the resource to the flow in the flow db */
+	memset(&fid_parms, 0, sizeof(fid_parms));
+	fid_parms.direction		= tbl->direction;
+	fid_parms.resource_func	= ident->resource_func;
+	fid_parms.resource_type	= ident->ident_type;
+	fid_parms.resource_hndl	= iparms.id;
+	fid_parms.critical_resource	= 0;
+
+	rc = ulp_flow_db_resource_add(parms->ulp_ctx,
+				      parms->tbl_idx,
+				      parms->fid,
+				      &fid_parms);
+	if (rc) {
+		BNXT_TF_DBG(ERR, "Failed to link resource to flow rc = %d\n",
+			    rc);
+		/* Need to free the identifier, so goto error */
+		goto error;
+	}
+
+	return 0;
+
+error:
+	/* Need to free the identifier */
+	free_parms.dir		= tbl->direction;
+	free_parms.ident_type	= ident->ident_type;
+	free_parms.id		= iparms.id;
+
+	(void)tf_free_identifier(tfp, &free_parms);
+
+	BNXT_TF_DBG(ERR, "Ident process failed for %s:%s\n",
+		    ident->name,
+		    (tbl->direction == TF_DIR_RX) ? "RX" : "TX");
+	return rc;
+}
+
 static int32_t
 ulp_mapper_result_field_process(struct bnxt_ulp_mapper_parms *parms,
 				struct bnxt_ulp_mapper_result_field_info *fld,
@@ -163,6 +321,89 @@ ulp_mapper_result_field_process(struct bnxt_ulp_mapper_parms *parms,
 
 /* Function to alloc action record and set the table. */
 static int32_t
+ulp_mapper_keymask_field_process(struct bnxt_ulp_mapper_parms *parms,
+				 struct bnxt_ulp_mapper_class_key_field_info *f,
+				 struct ulp_blob *blob,
+				 uint8_t is_key)
+{
+	uint64_t regval;
+	uint16_t idx, bitlen;
+	uint32_t opcode;
+	uint8_t *operand;
+	struct ulp_regfile *regfile = parms->regfile;
+	uint8_t *val = NULL;
+	struct bnxt_ulp_mapper_class_key_field_info *fld = f;
+
+	if (is_key) {
+		operand = fld->spec_operand;
+		opcode	= fld->spec_opcode;
+	} else {
+		operand = fld->mask_operand;
+		opcode	= fld->mask_opcode;
+	}
+
+	bitlen = fld->field_bit_size;
+
+	switch (opcode) {
+	case BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT:
+		val = operand;
+		if (!ulp_blob_push(blob, val, bitlen)) {
+			BNXT_TF_DBG(ERR, "push to key blob failed\n");
+			return -EINVAL;
+		}
+		break;
+	case BNXT_ULP_SPEC_OPC_ADD_PAD:
+		if (!ulp_blob_pad_push(blob, bitlen)) {
+			BNXT_TF_DBG(ERR, "Pad too large for blob\n");
+			return -EINVAL;
+		}
+
+		break;
+	case BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD:
+		if (!ulp_operand_read(operand, (uint8_t *)&idx,
+				      sizeof(uint16_t))) {
+			BNXT_TF_DBG(ERR, "key operand read failed.\n");
+			return -EINVAL;
+		}
+		idx = tfp_be_to_cpu_16(idx);
+		if (is_key)
+			val = parms->hdr_field[idx].spec;
+		else
+			val = parms->hdr_field[idx].mask;
+
+		if (!ulp_blob_push(blob, val, bitlen)) {
+			BNXT_TF_DBG(ERR, "push to key blob failed\n");
+			return -EINVAL;
+		}
+		break;
+	case BNXT_ULP_SPEC_OPC_SET_TO_REGFILE:
+		if (!ulp_operand_read(operand, (uint8_t *)&idx,
+				      sizeof(uint16_t))) {
+			BNXT_TF_DBG(ERR, "key operand read failed.\n");
+			return -EINVAL;
+		}
+		idx = tfp_be_to_cpu_16(idx);
+
+		if (!ulp_regfile_read(regfile, idx, &regval)) {
+			BNXT_TF_DBG(ERR, "regfile[%d] read failed.\n",
+				    idx);
+			return -EINVAL;
+		}
+
+		val = ulp_blob_push_64(blob, &regval, bitlen);
+		if (!val) {
+			BNXT_TF_DBG(ERR, "push to key blob failed\n");
+			return -EINVAL;
+		}
+	default:
+		break;
+	}
+
+	return 0;
+}
+
+/* Function to alloc action record and set the table. */
+static int32_t
 ulp_mapper_action_alloc_and_set(struct bnxt_ulp_mapper_parms *parms,
 				struct ulp_blob *blob)
 {
@@ -338,6 +579,489 @@ ulp_mapper_action_info_process(struct bnxt_ulp_mapper_parms *parms,
 	return rc;
 }
 
+static int32_t
+ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms,
+			    struct bnxt_ulp_mapper_class_tbl_info *tbl)
+{
+	struct bnxt_ulp_mapper_class_key_field_info	*kflds;
+	struct ulp_blob key, mask, data;
+	uint32_t i, num_kflds;
+	struct tf *tfp;
+	int32_t rc, trc;
+	struct tf_alloc_tcam_entry_parms aparms		= { 0 };
+	struct tf_set_tcam_entry_parms sparms		= { 0 };
+	struct ulp_flow_db_res_params	fid_parms	= { 0 };
+	struct tf_free_tcam_entry_parms free_parms	= { 0 };
+	uint32_t hit = 0;
+	uint16_t tmplen = 0;
+
+	tfp = bnxt_ulp_cntxt_tfp_get(parms->ulp_ctx);
+	if (!tfp) {
+		BNXT_TF_DBG(ERR, "Failed to get truflow pointer\n");
+		return -EINVAL;
+	}
+
+	kflds = ulp_mapper_key_fields_get(tbl, &num_kflds);
+	if (!kflds || !num_kflds) {
+		BNXT_TF_DBG(ERR, "Failed to get key fields\n");
+		return -EINVAL;
+	}
+
+	if (!ulp_blob_init(&key, tbl->key_bit_size, parms->order) ||
+	    !ulp_blob_init(&mask, tbl->key_bit_size, parms->order) ||
+	    !ulp_blob_init(&data, tbl->result_bit_size, parms->order)) {
+		BNXT_TF_DBG(ERR, "blob inits failed.\n");
+		return -EINVAL;
+	}
+
+	/* create the key/mask */
+	/*
+	 * NOTE: The WC table will require some kind of flag to handle the
+	 * mode bits within the key/mask
+	 */
+	for (i = 0; i < num_kflds; i++) {
+		/* Setup the key */
+		rc = ulp_mapper_keymask_field_process(parms, &kflds[i],
+						      &key, 1);
+		if (rc) {
+			BNXT_TF_DBG(ERR, "Key field set failed.\n");
+			return rc;
+		}
+
+		/* Setup the mask */
+		rc = ulp_mapper_keymask_field_process(parms, &kflds[i],
+						      &mask, 0);
+		if (rc) {
+			BNXT_TF_DBG(ERR, "Mask field set failed.\n");
+			return rc;
+		}
+	}
+
+	aparms.dir		= tbl->direction;
+	aparms.tcam_tbl_type	= tbl->table_type;
+	aparms.search_enable	= tbl->srch_b4_alloc;
+	aparms.key_sz_in_bits	= tbl->key_bit_size;
+	aparms.key		= ulp_blob_data_get(&key, &tmplen);
+	if (tbl->key_bit_size != tmplen) {
+		BNXT_TF_DBG(ERR, "Key len (%d) != Expected (%d)\n",
+			    tmplen, tbl->key_bit_size);
+		return -EINVAL;
+	}
+
+	aparms.mask		= ulp_blob_data_get(&mask, &tmplen);
+	if (tbl->key_bit_size != tmplen) {
+		BNXT_TF_DBG(ERR, "Mask len (%d) != Expected (%d)\n",
+			    tmplen, tbl->key_bit_size);
+		return -EINVAL;
+	}
+
+	aparms.priority		= tbl->priority;
+
+	/*
+	 * All failures after this succeeds require the entry to be freed.
+	 * cannot return directly on failure, but needs to goto error
+	 */
+	rc = tf_alloc_tcam_entry(tfp, &aparms);
+	if (rc) {
+		BNXT_TF_DBG(ERR, "tcam alloc failed rc=%d.\n", rc);
+		return rc;
+	}
+
+	hit = aparms.hit;
+
+	/* Build the result */
+	if (!tbl->srch_b4_alloc || !hit) {
+		struct bnxt_ulp_mapper_result_field_info *dflds;
+		struct bnxt_ulp_mapper_ident_info *idents;
+		uint32_t num_dflds, num_idents;
+
+		/* Alloc identifiers */
+		idents = ulp_mapper_ident_fields_get(tbl, &num_idents);
+
+		for (i = 0; i < num_idents; i++) {
+			rc = ulp_mapper_ident_process(parms, tbl, &idents[i]);
+
+			/* Already logged the error, just return */
+			if (rc)
+				goto error;
+		}
+
+		/* Create the result data blob */
+		dflds = ulp_mapper_result_fields_get(tbl, &num_dflds);
+		if (!dflds || !num_dflds) {
+			BNXT_TF_DBG(ERR, "Failed to get data fields.\n");
+			rc = -EINVAL;
+			goto error;
+		}
+
+		for (i = 0; i < num_dflds; i++) {
+			rc = ulp_mapper_result_field_process(parms,
+							     &dflds[i],
+							     &data);
+			if (rc) {
+				BNXT_TF_DBG(ERR, "Failed to set data fields\n");
+				goto error;
+			}
+		}
+
+		sparms.dir		= aparms.dir;
+		sparms.tcam_tbl_type	= aparms.tcam_tbl_type;
+		sparms.idx		= aparms.idx;
+		/* Already verified the key/mask lengths */
+		sparms.key		= ulp_blob_data_get(&key, &tmplen);
+		sparms.mask		= ulp_blob_data_get(&mask, &tmplen);
+		sparms.key_sz_in_bits	= tbl->key_bit_size;
+		sparms.result		= ulp_blob_data_get(&data, &tmplen);
+
+		if (tbl->result_bit_size != tmplen) {
+			BNXT_TF_DBG(ERR, "Result len (%d) != Expected (%d)\n",
+				    tmplen, tbl->result_bit_size);
+			rc = -EINVAL;
+			goto error;
+		}
+		sparms.result_sz_in_bits = tbl->result_bit_size;
+
+		rc = tf_set_tcam_entry(tfp, &sparms);
+		if (rc) {
+			BNXT_TF_DBG(ERR, "tcam[%d][%s][%d] write failed.\n",
+				    sparms.tcam_tbl_type,
+				    (sparms.dir == TF_DIR_RX) ? "RX" : "TX",
+				    sparms.idx);
+			goto error;
+		}
+	} else {
+		BNXT_TF_DBG(ERR, "Not supporting search before alloc now\n");
+		rc = -EINVAL;
+		goto error;
+	}
+
+	/* Link the resource to the flow in the flow db */
+	fid_parms.direction = tbl->direction;
+	fid_parms.resource_func	= tbl->resource_func;
+	fid_parms.resource_type	= tbl->table_type;
+	fid_parms.critical_resource = tbl->critical_resource;
+	fid_parms.resource_hndl	= aparms.idx;
+
+	rc = ulp_flow_db_resource_add(parms->ulp_ctx,
+				      parms->tbl_idx,
+				      parms->fid,
+				      &fid_parms);
+	if (rc) {
+		BNXT_TF_DBG(ERR, "Failed to link resource to flow rc = %d\n",
+			    rc);
+		/* Need to free the identifier, so goto error */
+		goto error;
+	}
+
+	return 0;
+error:
+	free_parms.dir			= tbl->direction;
+	free_parms.tcam_tbl_type	= tbl->table_type;
+	free_parms.idx			= aparms.idx;
+	trc = tf_free_tcam_entry(tfp, &free_parms);
+	if (trc)
+		BNXT_TF_DBG(ERR, "Failed to free tcam[%d][%d][%d] on failure\n",
+			    tbl->table_type, tbl->direction, aparms.idx);
+
+	return rc;
+}
+
+static int32_t
+ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms,
+			  struct bnxt_ulp_mapper_class_tbl_info *tbl)
+{
+	struct bnxt_ulp_mapper_class_key_field_info	*kflds;
+	struct bnxt_ulp_mapper_result_field_info *dflds;
+	struct ulp_blob key, data;
+	uint32_t i, num_kflds, num_dflds;
+	uint16_t tmplen;
+	struct tf *tfp = bnxt_ulp_cntxt_tfp_get(parms->ulp_ctx);
+	struct ulp_rte_act_prop	 *a_prop = parms->act_prop;
+	struct ulp_flow_db_res_params	fid_parms = { 0 };
+	struct tf_insert_em_entry_parms iparms = { 0 };
+	struct tf_delete_em_entry_parms free_parms = { 0 };
+	int32_t	trc;
+	int32_t rc = 0;
+
+	kflds = ulp_mapper_key_fields_get(tbl, &num_kflds);
+	if (!kflds || !num_kflds) {
+		BNXT_TF_DBG(ERR, "Failed to get key fields\n");
+		return -EINVAL;
+	}
+
+	/* Initialize the key/result blobs */
+	if (!ulp_blob_init(&key, tbl->blob_key_bit_size, parms->order) ||
+	    !ulp_blob_init(&data, tbl->result_bit_size, parms->order)) {
+		BNXT_TF_DBG(ERR, "blob inits failed.\n");
+		return -EINVAL;
+	}
+
+	/* create the key */
+	for (i = 0; i < num_kflds; i++) {
+		/* Setup the key */
+		rc = ulp_mapper_keymask_field_process(parms, &kflds[i],
+						      &key, 1);
+		if (rc) {
+			BNXT_TF_DBG(ERR, "Key field set failed.\n");
+			return rc;
+		}
+	}
+
+	/*
+	 * TBD: Normally should process identifiers in case of using recycle or
+	 * loopback.  Not supporting recycle for now.
+	 */
+
+	/* Create the result data blob */
+	dflds = ulp_mapper_result_fields_get(tbl, &num_dflds);
+	if (!dflds || !num_dflds) {
+		BNXT_TF_DBG(ERR, "Failed to get data fields.\n");
+		return -EINVAL;
+	}
+
+	for (i = 0; i < num_dflds; i++) {
+		struct bnxt_ulp_mapper_result_field_info *fld;
+
+		fld = &dflds[i];
+
+		rc = ulp_mapper_result_field_process(parms,
+						     fld,
+						     &data);
+		if (rc) {
+			BNXT_TF_DBG(ERR, "Failed to set data fields.\n");
+			return rc;
+		}
+	}
+
+	rc = bnxt_ulp_cntxt_tbl_scope_id_get(parms->ulp_ctx,
+					     &iparms.tbl_scope_id);
+	if (rc) {
+		BNXT_TF_DBG(ERR, "Failed to get table scope rc=%d\n", rc);
+		return rc;
+	}
+
+	/*
+	 * NOTE: the actual blob size will differ from the size in the tbl
+	 * entry due to the padding.
+	 */
+	iparms.dup_check		= 0;
+	iparms.dir			= tbl->direction;
+	iparms.mem			= tbl->mem;
+	iparms.key			= ulp_blob_data_get(&key, &tmplen);
+	iparms.key_sz_in_bits		= tbl->key_bit_size;
+	iparms.em_record		= ulp_blob_data_get(&data, &tmplen);
+	iparms.em_record_sz_in_bits	= tbl->result_bit_size;
+
+	rc = tf_insert_em_entry(tfp, &iparms);
+	if (rc) {
+		BNXT_TF_DBG(ERR, "Failed to insert em entry rc=%d.\n", rc);
+		return rc;
+	}
+
+	if (tbl->mark_enable &&
+	    ULP_BITMAP_ISSET(parms->act_bitmap->bits,
+			     BNXT_ULP_ACTION_BIT_MARK)) {
+		uint32_t val, mark, gfid, flag;
+		/* TBD: Need to determine if GFID is enabled globally */
+		if (sizeof(val) != BNXT_ULP_ACT_PROP_SZ_MARK) {
+			BNXT_TF_DBG(ERR, "Mark size (%d) != expected (%ld)\n",
+				    BNXT_ULP_ACT_PROP_SZ_MARK, sizeof(val));
+			rc = -EINVAL;
+			goto error;
+		}
+
+		memcpy(&val,
+		       &a_prop->act_details[BNXT_ULP_ACT_PROP_IDX_MARK],
+		       sizeof(val));
+
+		mark = tfp_be_to_cpu_32(val);
+
+		TF_GET_GFID_FROM_FLOW_ID(iparms.flow_id, gfid);
+		TF_GET_FLAG_FROM_FLOW_ID(iparms.flow_id, flag);
+
+		rc = ulp_mark_db_mark_add(parms->ulp_ctx,
+					  (flag == TF_GFID_TABLE_EXTERNAL),
+					  gfid,
+					  mark);
+		if (rc) {
+			BNXT_TF_DBG(ERR, "Failed to add mark to flow\n");
+			goto error;
+		}
+
+		/*
+		 * Link the mark resource to the flow in the flow db
+		 * The mark is never the critical resource, so it is 0.
+		 */
+		memset(&fid_parms, 0, sizeof(fid_parms));
+		fid_parms.direction	= tbl->direction;
+		fid_parms.resource_func	= BNXT_ULP_RESOURCE_FUNC_HW_FID;
+		fid_parms.resource_type	= tbl->table_type;
+		fid_parms.resource_hndl	= iparms.flow_id;
+		fid_parms.critical_resource = 0;
+
+		rc = ulp_flow_db_resource_add(parms->ulp_ctx,
+					      parms->tbl_idx,
+					      parms->fid,
+					      &fid_parms);
+		if (rc) {
+			BNXT_TF_DBG(ERR, "Fail to link res to flow rc = %d\n",
+				    rc);
+			/* Need to free the identifier, so goto error */
+			goto error;
+		}
+	}
+
+	/* Link the EM resource to the flow in the flow db */
+	memset(&fid_parms, 0, sizeof(fid_parms));
+	fid_parms.direction		= tbl->direction;
+	fid_parms.resource_func		= tbl->resource_func;
+	fid_parms.resource_type		= tbl->table_type;
+	fid_parms.critical_resource	= tbl->critical_resource;
+	fid_parms.resource_hndl		= iparms.flow_handle;
+
+	rc = ulp_flow_db_resource_add(parms->ulp_ctx,
+				      parms->tbl_idx,
+				      parms->fid,
+				      &fid_parms);
+	if (rc) {
+		BNXT_TF_DBG(ERR, "Fail to link res to flow rc = %d\n",
+			    rc);
+		/* Need to free the identifier, so goto error */
+		goto error;
+	}
+
+	return 0;
+error:
+	free_parms.dir		= iparms.dir;
+	free_parms.mem		= iparms.mem;
+	free_parms.tbl_scope_id	= iparms.tbl_scope_id;
+	free_parms.flow_handle	= iparms.flow_handle;
+
+	trc = tf_delete_em_entry(tfp, &free_parms);
+	if (trc)
+		BNXT_TF_DBG(ERR, "Failed to delete EM entry on failed add\n");
+
+	return rc;
+}
+
+static int32_t
+ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,
+			     struct bnxt_ulp_mapper_class_tbl_info *tbl)
+{
+	struct bnxt_ulp_mapper_result_field_info *flds;
+	struct ulp_flow_db_res_params	fid_parms;
+	struct ulp_blob	data;
+	uint64_t idx;
+	uint16_t tmplen;
+	uint32_t i, num_flds;
+	int32_t rc = 0, trc = 0;
+	struct tf_alloc_tbl_entry_parms	aparms = { 0 };
+	struct tf_set_tbl_entry_parms	sparms = { 0 };
+	struct tf_free_tbl_entry_parms	free_parms = { 0 };
+
+	struct tf *tfp = bnxt_ulp_cntxt_tfp_get(parms->ulp_ctx);
+
+	if (!ulp_blob_init(&data, tbl->result_bit_size, parms->order)) {
+		BNXT_TF_DBG(ERR, "Failed initial index table blob\n");
+		return -EINVAL;
+	}
+
+	flds = ulp_mapper_result_fields_get(tbl, &num_flds);
+	if (!flds || !num_flds) {
+		BNXT_TF_DBG(ERR, "Template undefined for action\n");
+		return -EINVAL;
+	}
+
+	for (i = 0; i < num_flds; i++) {
+		rc = ulp_mapper_result_field_process(parms,
+						     &flds[i],
+						     &data);
+		if (rc) {
+			BNXT_TF_DBG(ERR, "data field failed\n");
+			return rc;
+		}
+	}
+
+	aparms.dir		= tbl->direction;
+	aparms.type		= tbl->table_type;
+	aparms.search_enable	= tbl->srch_b4_alloc;
+	aparms.result		= ulp_blob_data_get(&data, &tmplen);
+	aparms.result_sz_in_bytes = ULP_SZ_BITS2BYTES(tbl->result_bit_size);
+
+	/* All failures after the alloc succeeds require a free */
+	rc = tf_alloc_tbl_entry(tfp, &aparms);
+	if (rc) {
+		BNXT_TF_DBG(ERR, "Alloc table[%d][%s] failed rc=%d\n",
+			    tbl->table_type,
+			    (tbl->direction == TF_DIR_RX) ? "RX" : "TX",
+			    rc);
+		return rc;
+	}
+
+	/* Always storing values in Regfile in BE */
+	idx = tfp_cpu_to_be_64(aparms.idx);
+	rc = ulp_regfile_write(parms->regfile, tbl->regfile_wr_idx, idx);
+	if (!rc) {
+		BNXT_TF_DBG(ERR, "Write regfile[%d] failed\n",
+			    tbl->regfile_wr_idx);
+		goto error;
+	}
+
+	if (!tbl->srch_b4_alloc) {
+		sparms.dir		= tbl->direction;
+		sparms.type		= tbl->table_type;
+		sparms.data		= ulp_blob_data_get(&data, &tmplen);
+		sparms.data_sz_in_bytes =
+			ULP_SZ_BITS2BYTES(tbl->result_bit_size);
+		sparms.idx		= aparms.idx;
+
+		rc = tf_set_tbl_entry(tfp, &sparms);
+		if (rc) {
+			BNXT_TF_DBG(ERR, "Set table[%d][%s][%d] failed rc=%d\n",
+				    tbl->table_type,
+				    (tbl->direction == TF_DIR_RX) ? "RX" : "TX",
+				    sparms.idx,
+				    rc);
+
+			goto error;
+		}
+	}
+
+	/* Link the resource to the flow in the flow db */
+	memset(&fid_parms, 0, sizeof(fid_parms));
+	fid_parms.direction	= tbl->direction;
+	fid_parms.resource_func	= tbl->resource_func;
+	fid_parms.resource_type	= tbl->table_type;
+	fid_parms.resource_hndl	= aparms.idx;
+	fid_parms.critical_resource	= 0;
+
+	rc = ulp_flow_db_resource_add(parms->ulp_ctx,
+				      parms->tbl_idx,
+				      parms->fid,
+				      &fid_parms);
+	if (rc) {
+		BNXT_TF_DBG(ERR, "Failed to link resource to flow rc = %d\n",
+			    rc);
+		goto error;
+	}
+
+	return rc;
+error:
+	/*
+	 * Free the allocated resource since we failed to either
+	 * write to the entry or link the flow
+	 */
+	free_parms.dir	= tbl->direction;
+	free_parms.type	= tbl->table_type;
+	free_parms.idx	= aparms.idx;
+
+	trc = tf_free_tbl_entry(tfp, &free_parms);
+	if (trc)
+		BNXT_TF_DBG(ERR, "Failed to free tbl entry on failure\n");
+
+	return rc;
+}
+
 /*
  * Function to process the action template. Iterate through the list
  * action info templates and process it.
@@ -362,3 +1086,48 @@ ulp_mapper_action_tbls_process(struct bnxt_ulp_mapper_parms *parms)
 
 	return rc;
 }
+
+/* Create the classifier table entries for a flow. */
+int32_t
+ulp_mapper_class_tbls_process(struct bnxt_ulp_mapper_parms *parms)
+{
+	uint32_t	i;
+	int32_t		rc = 0;
+
+	if (!parms)
+		return -EINVAL;
+
+	if (!parms->ctbls || !parms->num_ctbls) {
+		BNXT_TF_DBG(ERR, "No class tables for template[%d][%d].\n",
+			    parms->dev_id, parms->class_tid);
+		return -EINVAL;
+	}
+
+	for (i = 0; i < parms->num_ctbls; i++) {
+		struct bnxt_ulp_mapper_class_tbl_info *tbl = &parms->ctbls[i];
+
+		switch (tbl->resource_func) {
+		case BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE:
+			rc = ulp_mapper_tcam_tbl_process(parms, tbl);
+			break;
+		case BNXT_ULP_RESOURCE_FUNC_EM_TABLE:
+			rc = ulp_mapper_em_tbl_process(parms, tbl);
+			break;
+		case BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE:
+			rc = ulp_mapper_index_tbl_process(parms, tbl);
+			break;
+		default:
+			BNXT_TF_DBG(ERR, "Unexpected class resource %d\n",
+				    tbl->resource_func);
+			return -EINVAL;
+		}
+
+		if (rc) {
+			BNXT_TF_DBG(ERR, "Resource type %d failed\n",
+				    tbl->resource_func);
+			return rc;
+		}
+	}
+
+	return rc;
+}
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.h b/drivers/net/bnxt/tf_ulp/ulp_mapper.h
index adbcec2..2221e12 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.h
@@ -15,6 +15,8 @@
 #include "bnxt_ulp.h"
 #include "ulp_utils.h"
 
+#define ULP_SZ_BITS2BYTES(x) (((x) + 7) / 8)
+
 /* Internal Structure for passing the arguments around */
 struct bnxt_ulp_mapper_parms {
 	uint32_t				dev_id;
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c b/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c
index 9e4307e..837064e 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c
@@ -6,14 +6,71 @@
 #include <rte_common.h>
 #include <rte_malloc.h>
 #include <rte_log.h>
+#include "bnxt.h"
 #include "bnxt_ulp.h"
 #include "tf_ext_flow_handle.h"
 #include "ulp_mark_mgr.h"
 #include "bnxt_tf_common.h"
-#include "../bnxt.h"
 #include "ulp_template_db.h"
 #include "ulp_template_struct.h"
 
+static inline uint32_t
+ulp_mark_db_idx_get(bool is_gfid, uint32_t fid, struct bnxt_ulp_mark_tbl *mtbl)
+{
+	uint32_t idx = 0, hashtype = 0;
+
+	if (is_gfid) {
+		TF_GET_HASH_TYPE_FROM_GFID(fid, hashtype);
+		TF_GET_HASH_INDEX_FROM_GFID(fid, idx);
+
+		/* Need to truncate anything beyond supported flows */
+		idx &= mtbl->gfid_mask;
+
+		if (hashtype)
+			idx |= mtbl->gfid_type_bit;
+	} else {
+		idx = fid;
+	}
+
+	return idx;
+}
+
+static int32_t
+ulp_mark_db_mark_set(struct bnxt_ulp_context *ctxt,
+		     bool is_gfid,
+		     uint32_t fid,
+		     uint32_t mark)
+{
+	struct		bnxt_ulp_mark_tbl *mtbl;
+	uint32_t	idx = 0;
+
+	if (!ctxt) {
+		BNXT_TF_DBG(ERR, "Invalid ulp context\n");
+		return -EINVAL;
+	}
+
+	mtbl = bnxt_ulp_cntxt_ptr2_mark_db_get(ctxt);
+	if (!mtbl) {
+		BNXT_TF_DBG(ERR, "Unable to get Mark DB\n");
+		return -EINVAL;
+	}
+
+	idx = ulp_mark_db_idx_get(is_gfid, fid, mtbl);
+
+	if (is_gfid) {
+		BNXT_TF_DBG(ERR, "Set GFID[0x%0x] = 0x%0x\n", idx, mark);
+
+		mtbl->gfid_tbl[idx].mark_id = mark;
+		mtbl->gfid_tbl[idx].valid = true;
+	} else {
+		/* For the LFID, the FID is used as the index */
+		mtbl->lfid_tbl[fid].mark_id = mark;
+		mtbl->lfid_tbl[fid].valid = true;
+	}
+
+	return 0;
+}
+
 /*
  * Allocate and Initialize all Mark Manager resources for this ulp context.
  *
@@ -117,3 +174,24 @@ ulp_mark_db_deinit(struct bnxt_ulp_context *ctxt)
 
 	return 0;
 }
+
+/*
+ * Adds a Mark to the Mark Manager
+ *
+ * ctxt [in] The ulp context for the mark manager
+ *
+ * is_gfid [in] The type of fid (GFID or LFID)
+ *
+ * fid [in] The flow id that is returned by HW in BD
+ *
+ * mark [in] The mark to be associated with the FID
+ *
+ */
+int32_t
+ulp_mark_db_mark_add(struct bnxt_ulp_context *ctxt,
+		     bool is_gfid,
+		     uint32_t gfid,
+		     uint32_t mark)
+{
+	return ulp_mark_db_mark_set(ctxt, is_gfid, gfid, mark);
+}
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.h b/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.h
index 5948683..18abea4 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_mark_mgr.h
@@ -54,4 +54,22 @@ ulp_mark_db_init(struct bnxt_ulp_context *ctxt);
 int32_t
 ulp_mark_db_deinit(struct bnxt_ulp_context *ctxt);
 
+/*
+ * Adds a Mark to the Mark Manager
+ *
+ * ctxt [in] The ulp context for the mark manager
+ *
+ * is_gfid [in] The type of fid (GFID or LFID)
+ *
+ * fid [in] The flow id that is returned by HW in BD
+ *
+ * mark [in] The mark to be associated with the FID
+ *
+ */
+int32_t
+ulp_mark_db_mark_add(struct bnxt_ulp_context *ctxt,
+		     bool is_gfid,
+		     uint32_t gfid,
+		     uint32_t mark);
+
 #endif /* _ULP_MARK_MGR_H_ */
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db.c b/drivers/net/bnxt/tf_ulp/ulp_template_db.c
index fc77800..aefece8 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db.c
@@ -9,6 +9,7 @@
  */
 
 #include "ulp_template_db.h"
+#include "ulp_template_field_db.h"
 #include "ulp_template_struct.h"
 
 uint32_t ulp_act_prop_map_table[] = {
@@ -109,6 +110,834 @@ struct bnxt_ulp_device_params ulp_device_params[] = {
 	}
 };
 
+struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
+	{
+	.field_bit_size = 12,
+	.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+	.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 12,
+	.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+	.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 48,
+	.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+	.spec_operand = {(BNXT_ULP_HF0_O_ETH_DMAC >> 8) & 0xff,
+		BNXT_ULP_HF0_O_ETH_DMAC & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 8,
+	.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_HDR_FIELD,
+	.mask_operand = {(BNXT_ULP_HF0_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF0_SVIF_INDEX & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+	.spec_operand = {(BNXT_ULP_HF0_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF0_SVIF_INDEX & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 4,
+	.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+	.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 12,
+	.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+	.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 12,
+	.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+	.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 48,
+	.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+	.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+	.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+	.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 4,
+	.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+	.spec_operand = {BNXT_ULP_SYM_TUN_HDR_TYPE_NONE,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+	.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+	.spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+	.spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 4,
+	.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+	.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+	.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+	.spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+	.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+	.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+	.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 4,
+	.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+	.spec_operand = {BNXT_ULP_SYM_L3_HDR_TYPE_IPV4,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+	.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+	.spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+	.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+	.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+	.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+	.spec_operand = {BNXT_ULP_SYM_L2_HDR_TYPE_DIX,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+	.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+	.spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 3,
+	.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+	.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 4,
+	.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+	.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+	.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+	.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+	.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 4,
+	.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+	.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+	.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+	.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+	.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+	.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+	.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 4,
+	.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+	.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+	.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+	.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+	.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+	.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+	.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+	.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+	.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+	.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 9,
+	.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+	.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 7,
+	.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+	.spec_operand = {0x40, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+	.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+	.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 4,
+	.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+	.spec_operand = {BNXT_ULP_SYM_PKT_TYPE_L2,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+	.spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 251,
+	.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.spec_opcode = BNXT_ULP_SPEC_OPC_ADD_PAD,
+	.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 3,
+	.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+	.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 16,
+	.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+	.spec_operand = {(BNXT_ULP_HF0_O_UDP_DST_PORT >> 8) & 0xff,
+		BNXT_ULP_HF0_O_UDP_DST_PORT & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 16,
+	.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+	.spec_operand = {(BNXT_ULP_HF0_O_UDP_SRC_PORT >> 8) & 0xff,
+		BNXT_ULP_HF0_O_UDP_SRC_PORT & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 8,
+	.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+	.spec_operand = {BNXT_ULP_SYM_IP_PROTO_UDP,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 32,
+	.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+	.spec_operand = {(BNXT_ULP_HF0_O_IPV4_DST_ADDR >> 8) & 0xff,
+		BNXT_ULP_HF0_O_IPV4_DST_ADDR & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 32,
+	.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+	.spec_operand = {(BNXT_ULP_HF0_O_IPV4_SRC_ADDR >> 8) & 0xff,
+		BNXT_ULP_HF0_O_IPV4_SRC_ADDR & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 48,
+	.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD,
+	.spec_operand = {(BNXT_ULP_HF0_O_ETH_SMAC >> 8) & 0xff,
+		BNXT_ULP_HF0_O_ETH_SMAC & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 24,
+	.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+	.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 10,
+	.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_REGFILE,
+	.spec_operand = {(BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
+		BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 8,
+	.mask_opcode = BNXT_ULP_MASK_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.spec_opcode = BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT,
+	.spec_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	}
+};
+
+struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
+	{
+	.field_bit_size = 10,
+	.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+	.result_operand = {(BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
+		BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 7,
+	.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+	.result_operand = {0x40, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+	.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 4,
+	.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+	.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 8,
+	.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+	.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 3,
+	.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+	.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 6,
+	.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+	.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 3,
+	.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+	.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+	.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 16,
+	.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+	.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+	.result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 2,
+	.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+	.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 2,
+	.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+	.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 4,
+	.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+	.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 8,
+	.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+	.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+	.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 10,
+	.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+	.result_operand = {(0x00fd >> 8) & 0xff,
+		0x00fd & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 5,
+	.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+	.result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 8,
+	.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+	.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+	.result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+	.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 33,
+	.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_REGFILE,
+	.result_operand = {(BNXT_ULP_REGFILE_INDEX_ACTION_PTR_MAIN >> 8) & 0xff,
+		BNXT_ULP_REGFILE_INDEX_ACTION_PTR_MAIN & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+	.result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+	.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 5,
+	.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+	.result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 9,
+	.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+	.result_operand = {(0x00c5 >> 8) & 0xff,
+		0x00c5 & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 11,
+	.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+	.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 2,
+	.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+	.result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+	.result_operand = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_RESULT_OPC_SET_TO_CONSTANT,
+	.result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	}
+};
+
+struct bnxt_ulp_mapper_ident_info ulp_ident_list[] = {
+	{
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+	.ident_type = TF_IDENT_TYPE_L2_CTXT,
+	.regfile_wr_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0,
+	.ident_bit_size = 10,
+	.ident_bit_pos = 54
+	},
+	{
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+	.ident_type = TF_IDENT_TYPE_EM_PROF,
+	.regfile_wr_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0,
+	.ident_bit_size = 8,
+	.ident_bit_pos = 2
+	}
+};
+
 struct bnxt_ulp_mapper_result_field_info ulp_act_result_field_list[] = {
 	{
 	.field_bit_size = 14,
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db.h b/drivers/net/bnxt/tf_ulp/ulp_template_db.h
index e52cc3f..733836a 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db.h
@@ -13,6 +13,37 @@
 
 #define BNXT_ULP_MAX_NUM_DEVICES 4
 
+enum bnxt_ulp_action_bit {
+	BNXT_ULP_ACTION_BIT_MARK             = 0x0000000000000001,
+	BNXT_ULP_ACTION_BIT_DROP             = 0x0000000000000002,
+	BNXT_ULP_ACTION_BIT_COUNT            = 0x0000000000000004,
+	BNXT_ULP_ACTION_BIT_RSS              = 0x0000000000000008,
+	BNXT_ULP_ACTION_BIT_METER            = 0x0000000000000010,
+	BNXT_ULP_ACTION_BIT_VNIC             = 0x0000000000000020,
+	BNXT_ULP_ACTION_BIT_VPORT            = 0x0000000000000040,
+	BNXT_ULP_ACTION_BIT_VXLAN_DECAP      = 0x0000000000000080,
+	BNXT_ULP_ACTION_BIT_NVGRE_DECAP      = 0x0000000000000100,
+	BNXT_ULP_ACTION_BIT_OF_POP_MPLS      = 0x0000000000000200,
+	BNXT_ULP_ACTION_BIT_OF_PUSH_MPLS     = 0x0000000000000400,
+	BNXT_ULP_ACTION_BIT_MAC_SWAP         = 0x0000000000000800,
+	BNXT_ULP_ACTION_BIT_SET_MAC_SRC      = 0x0000000000001000,
+	BNXT_ULP_ACTION_BIT_SET_MAC_DST      = 0x0000000000002000,
+	BNXT_ULP_ACTION_BIT_OF_POP_VLAN      = 0x0000000000004000,
+	BNXT_ULP_ACTION_BIT_OF_PUSH_VLAN     = 0x0000000000008000,
+	BNXT_ULP_ACTION_BIT_OF_SET_VLAN_PCP  = 0x0000000000010000,
+	BNXT_ULP_ACTION_BIT_OF_SET_VLAN_VID  = 0x0000000000020000,
+	BNXT_ULP_ACTION_BIT_SET_IPV4_SRC     = 0x0000000000040000,
+	BNXT_ULP_ACTION_BIT_SET_IPV4_DST     = 0x0000000000080000,
+	BNXT_ULP_ACTION_BIT_SET_IPV6_SRC     = 0x0000000000100000,
+	BNXT_ULP_ACTION_BIT_SET_IPV6_DST     = 0x0000000000200000,
+	BNXT_ULP_ACTION_BIT_DEC_TTL          = 0x0000000000400000,
+	BNXT_ULP_ACTION_BIT_SET_TP_SRC       = 0x0000000000800000,
+	BNXT_ULP_ACTION_BIT_SET_TP_DST       = 0x0000000001000000,
+	BNXT_ULP_ACTION_BIT_VXLAN_ENCAP      = 0x0000000002000000,
+	BNXT_ULP_ACTION_BIT_NVGRE_ENCAP      = 0x0000000004000000,
+	BNXT_ULP_ACTION_BIT_LAST             = 0x0000000008000000
+};
+
 enum bnxt_ulp_byte_order {
 	BNXT_ULP_BYTE_ORDER_BE,
 	BNXT_ULP_BYTE_ORDER_LE,
@@ -35,8 +66,48 @@ enum bnxt_ulp_fmf_mask {
 	BNXT_ULP_FMF_MASK_LAST
 };
 
+enum bnxt_ulp_mark_enable {
+	BNXT_ULP_MARK_ENABLE_NO = 0,
+	BNXT_ULP_MARK_ENABLE_YES = 1,
+	BNXT_ULP_MARK_ENABLE_LAST = 2
+};
+
+enum bnxt_ulp_mask_opc {
+	BNXT_ULP_MASK_OPC_SET_TO_CONSTANT = 0,
+	BNXT_ULP_MASK_OPC_SET_TO_HDR_FIELD = 1,
+	BNXT_ULP_MASK_OPC_SET_TO_REGFILE = 2,
+	BNXT_ULP_MASK_OPC_ADD_PAD = 3,
+	BNXT_ULP_MASK_OPC_LAST = 4
+};
+
+enum bnxt_ulp_priority {
+	BNXT_ULP_PRIORITY_LEVEL_0 = 0,
+	BNXT_ULP_PRIORITY_LEVEL_1 = 1,
+	BNXT_ULP_PRIORITY_LEVEL_2 = 2,
+	BNXT_ULP_PRIORITY_LEVEL_3 = 3,
+	BNXT_ULP_PRIORITY_LEVEL_4 = 4,
+	BNXT_ULP_PRIORITY_LEVEL_5 = 5,
+	BNXT_ULP_PRIORITY_LEVEL_6 = 6,
+	BNXT_ULP_PRIORITY_LEVEL_7 = 7,
+	BNXT_ULP_PRIORITY_NOT_USED = 8,
+	BNXT_ULP_PRIORITY_LAST = 9
+};
+
 enum bnxt_ulp_regfile_index {
-	BNXT_ULP_REGFILE_INDEX_LAST
+	BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 = 0,
+	BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_1 = 1,
+	BNXT_ULP_REGFILE_INDEX_PROF_FUNC_ID_0 = 2,
+	BNXT_ULP_REGFILE_INDEX_PROF_FUNC_ID_1 = 3,
+	BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 = 4,
+	BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_1 = 5,
+	BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_0 = 6,
+	BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_1 = 7,
+	BNXT_ULP_REGFILE_INDEX_ACTION_PTR_MAIN = 8,
+	BNXT_ULP_REGFILE_INDEX_ACTION_PTR_0 = 9,
+	BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 = 10,
+	BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_1 = 11,
+	BNXT_ULP_REGFILE_INDEX_NOT_USED = 12,
+	BNXT_ULP_REGFILE_INDEX_LAST = 13
 };
 
 enum bnxt_ulp_resource_func {
@@ -56,9 +127,78 @@ enum bnxt_ulp_result_opc {
 	BNXT_ULP_RESULT_OPC_LAST = 4
 };
 
+enum bnxt_ulp_spec_opc {
+	BNXT_ULP_SPEC_OPC_SET_TO_CONSTANT = 0,
+	BNXT_ULP_SPEC_OPC_SET_TO_HDR_FIELD = 1,
+	BNXT_ULP_SPEC_OPC_SET_TO_REGFILE = 2,
+	BNXT_ULP_SPEC_OPC_ADD_PAD = 3,
+	BNXT_ULP_SPEC_OPC_LAST = 4
+};
+
 enum bnxt_ulp_sym {
+	BNXT_ULP_SYM_BIG_ENDIAN = 0,
 	BNXT_ULP_SYM_DECAP_FUNC_NONE = 0,
+	BNXT_ULP_SYM_DECAP_FUNC_THRU_L2 = 11,
+	BNXT_ULP_SYM_DECAP_FUNC_THRU_L3 = 12,
+	BNXT_ULP_SYM_DECAP_FUNC_THRU_L4 = 13,
+	BNXT_ULP_SYM_DECAP_FUNC_THRU_TL2 = 3,
+	BNXT_ULP_SYM_DECAP_FUNC_THRU_TL3 = 8,
+	BNXT_ULP_SYM_DECAP_FUNC_THRU_TL4 = 9,
+	BNXT_ULP_SYM_DECAP_FUNC_THRU_TUN = 10,
+	BNXT_ULP_SYM_ECV_L3_TYPE_IPV4 = 4,
+	BNXT_ULP_SYM_ECV_L3_TYPE_IPV6 = 5,
+	BNXT_ULP_SYM_ECV_L3_TYPE_MPLS_8847 = 6,
+	BNXT_ULP_SYM_ECV_L3_TYPE_MPLS_8848 = 7,
+	BNXT_ULP_SYM_ECV_L3_TYPE_NONE = 0,
+	BNXT_ULP_SYM_ECV_L4_TYPE_NONE = 0,
+	BNXT_ULP_SYM_ECV_L4_TYPE_UDP = 4,
+	BNXT_ULP_SYM_ECV_L4_TYPE_UDP_CSUM = 5,
+	BNXT_ULP_SYM_ECV_L4_TYPE_UDP_ENTROPY = 6,
+	BNXT_ULP_SYM_ECV_L4_TYPE_UDP_ENTROPY_CSUM = 7,
+	BNXT_ULP_SYM_ECV_TUN_TYPE_GENERIC = 1,
+	BNXT_ULP_SYM_ECV_TUN_TYPE_GRE = 5,
+	BNXT_ULP_SYM_ECV_TUN_TYPE_NGE = 3,
+	BNXT_ULP_SYM_ECV_TUN_TYPE_NONE = 0,
+	BNXT_ULP_SYM_ECV_TUN_TYPE_NVGRE = 4,
+	BNXT_ULP_SYM_ECV_TUN_TYPE_VXLAN = 2,
+	BNXT_ULP_SYM_IP_PROTO_UDP = 17,
+	BNXT_ULP_SYM_L2_HDR_TYPE_DIX = 0,
+	BNXT_ULP_SYM_L2_HDR_TYPE_LLC = 2,
+	BNXT_ULP_SYM_L2_HDR_TYPE_LLC_SNAP = 1,
+	BNXT_ULP_SYM_L3_HDR_TYPE_ARP = 2,
+	BNXT_ULP_SYM_L3_HDR_TYPE_EAPOL = 4,
+	BNXT_ULP_SYM_L3_HDR_TYPE_FCOE = 6,
+	BNXT_ULP_SYM_L3_HDR_TYPE_IPV4 = 0,
+	BNXT_ULP_SYM_L3_HDR_TYPE_IPV6 = 1,
+	BNXT_ULP_SYM_L3_HDR_TYPE_PTP = 3,
+	BNXT_ULP_SYM_L3_HDR_TYPE_ROCE = 5,
+	BNXT_ULP_SYM_L3_HDR_TYPE_UPAR1 = 7,
+	BNXT_ULP_SYM_L3_HDR_TYPE_UPAR2 = 8,
+	BNXT_ULP_SYM_L4_HDR_TYPE_BTH_V1 = 5,
+	BNXT_ULP_SYM_L4_HDR_TYPE_ICMP = 2,
+	BNXT_ULP_SYM_L4_HDR_TYPE_TCP = 0,
+	BNXT_ULP_SYM_L4_HDR_TYPE_UDP = 1,
+	BNXT_ULP_SYM_L4_HDR_TYPE_UPAR1 = 3,
+	BNXT_ULP_SYM_L4_HDR_TYPE_UPAR2 = 4,
 	BNXT_ULP_SYM_LITTLE_ENDIAN = 1,
+	BNXT_ULP_SYM_NO = 0,
+	BNXT_ULP_SYM_PKT_TYPE_L2 = 0,
+	BNXT_ULP_SYM_TL2_HDR_TYPE_DIX = 0,
+	BNXT_ULP_SYM_TL3_HDR_TYPE_IPV4 = 0,
+	BNXT_ULP_SYM_TL3_HDR_TYPE_IPV6 = 1,
+	BNXT_ULP_SYM_TL4_HDR_TYPE_TCP = 0,
+	BNXT_ULP_SYM_TL4_HDR_TYPE_UDP = 1,
+	BNXT_ULP_SYM_TUN_HDR_TYPE_GENEVE = 1,
+	BNXT_ULP_SYM_TUN_HDR_TYPE_GRE = 3,
+	BNXT_ULP_SYM_TUN_HDR_TYPE_IPV4 = 4,
+	BNXT_ULP_SYM_TUN_HDR_TYPE_IPV6 = 5,
+	BNXT_ULP_SYM_TUN_HDR_TYPE_MPLS = 7,
+	BNXT_ULP_SYM_TUN_HDR_TYPE_NONE = 15,
+	BNXT_ULP_SYM_TUN_HDR_TYPE_NVGRE = 2,
+	BNXT_ULP_SYM_TUN_HDR_TYPE_PPPOE = 6,
+	BNXT_ULP_SYM_TUN_HDR_TYPE_UPAR1 = 8,
+	BNXT_ULP_SYM_TUN_HDR_TYPE_UPAR2 = 9,
+	BNXT_ULP_SYM_TUN_HDR_TYPE_VXLAN = 0,
 	BNXT_ULP_SYM_YES = 1
 };
 
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_field_db.h b/drivers/net/bnxt/tf_ulp/ulp_template_field_db.h
new file mode 100644
index 0000000..1f58ace
--- /dev/null
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_field_db.h
@@ -0,0 +1,133 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2014-2020 Broadcom
+ * All rights reserved_
+ */
+
+/* date: Mon Mar  9 02:37:53 2020
+ * version: 0_0
+ */
+
+#ifndef _ULP_HDR_FIELD_ENUMS_H_
+#define _ULP_HDR_FIELD_ENUMS_H_
+
+/* class_template_id = 0: ingress flow */
+enum bnxt_ulp_hf0 {
+	BNXT_ULP_HF0_MPLS_TAG_NUM = 0,
+	BNXT_ULP_HF0_O_VTAG_NUM = 1,
+	BNXT_ULP_HF0_I_VTAG_NUM = 2,
+	BNXT_ULP_HF0_SVIF_INDEX = 3,
+	BNXT_ULP_HF0_O_ETH_DMAC = 4,
+	BNXT_ULP_HF0_O_ETH_SMAC = 5,
+	BNXT_ULP_HF0_O_ETH_TYPE = 6,
+	BNXT_ULP_HF0_OO_VLAN_CFI_PRI = 7,
+	BNXT_ULP_HF0_OO_VLAN_VID = 8,
+	BNXT_ULP_HF0_OO_VLAN_TYPE = 9,
+	BNXT_ULP_HF0_OI_VLAN_CFI_PRI = 10,
+	BNXT_ULP_HF0_OI_VLAN_VID = 11,
+	BNXT_ULP_HF0_OI_VLAN_TYPE = 12,
+	BNXT_ULP_HF0_O_IPV4_VER = 13,
+	BNXT_ULP_HF0_O_IPV4_TOS = 14,
+	BNXT_ULP_HF0_O_IPV4_LEN = 15,
+	BNXT_ULP_HF0_O_IPV4_FRAG_ID = 16,
+	BNXT_ULP_HF0_O_IPV4_FRAG_OFF = 17,
+	BNXT_ULP_HF0_O_IPV4_TTL = 18,
+	BNXT_ULP_HF0_O_IPV4_NEXT_PID = 19,
+	BNXT_ULP_HF0_O_IPV4_CSUM = 20,
+	BNXT_ULP_HF0_O_IPV4_SRC_ADDR = 21,
+	BNXT_ULP_HF0_O_IPV4_DST_ADDR = 22,
+	BNXT_ULP_HF0_O_UDP_SRC_PORT = 23,
+	BNXT_ULP_HF0_O_UDP_DST_PORT = 24,
+	BNXT_ULP_HF0_O_UDP_LENGTH = 25,
+	BNXT_ULP_HF0_O_UDP_CSUM = 26,
+	BNXT_ULP_HF0_T_VXLAN_FLAGS = 27,
+	BNXT_ULP_HF0_T_VXLAN_RSVD0 = 28,
+	BNXT_ULP_HF0_T_VXLAN_VNI = 29,
+	BNXT_ULP_HF0_T_VXLAN_RSVD1 = 30,
+	BNXT_ULP_HF0_I_ETH_DMAC = 31,
+	BNXT_ULP_HF0_I_ETH_SMAC = 32,
+	BNXT_ULP_HF0_I_ETH_TYPE = 33,
+	BNXT_ULP_HF0_IO_VLAN_CFI_PRI = 34,
+	BNXT_ULP_HF0_IO_VLAN_VID = 35,
+	BNXT_ULP_HF0_IO_VLAN_TYPE = 36,
+	BNXT_ULP_HF0_II_VLAN_CFI_PRI = 37,
+	BNXT_ULP_HF0_II_VLAN_VID = 38,
+	BNXT_ULP_HF0_II_VLAN_TYPE = 39,
+	BNXT_ULP_HF0_I_IPV4_VER = 40,
+	BNXT_ULP_HF0_I_IPV4_TOS = 41,
+	BNXT_ULP_HF0_I_IPV4_LEN = 42,
+	BNXT_ULP_HF0_I_IPV4_FRAG_ID = 43,
+	BNXT_ULP_HF0_I_IPV4_FRAG_OFF = 44,
+	BNXT_ULP_HF0_I_IPV4_TTL = 45,
+	BNXT_ULP_HF0_I_IPV4_NEXT_PID = 46,
+	BNXT_ULP_HF0_I_IPV4_CSUM = 47,
+	BNXT_ULP_HF0_I_IPV4_SRC_ADDR = 48,
+	BNXT_ULP_HF0_I_IPV4_DST_ADDR = 49,
+	BNXT_ULP_HF0_I_UDP_SRC_PORT = 50,
+	BNXT_ULP_HF0_I_UDP_DST_PORT = 51,
+	BNXT_ULP_HF0_I_UDP_LENGTH = 52,
+	BNXT_ULP_HF0_I_UDP_CSUM = 53
+};
+
+/* class_template_id = 1: egress flow */
+enum bnxt_ulp_hf1 {
+	BNXT_ULP_HF1_MPLS_TAG_NUM = 0,
+	BNXT_ULP_HF1_O_VTAG_NUM = 1,
+	BNXT_ULP_HF1_I_VTAG_NUM = 2,
+	BNXT_ULP_HF1_SVIF_INDEX = 3,
+	BNXT_ULP_HF1_O_ETH_DMAC = 4,
+	BNXT_ULP_HF1_O_ETH_SMAC = 5,
+	BNXT_ULP_HF1_O_ETH_TYPE = 6,
+	BNXT_ULP_HF1_OO_VLAN_CFI_PRI = 7,
+	BNXT_ULP_HF1_OO_VLAN_VID = 8,
+	BNXT_ULP_HF1_OO_VLAN_TYPE = 9,
+	BNXT_ULP_HF1_OI_VLAN_CFI_PRI = 10,
+	BNXT_ULP_HF1_OI_VLAN_VID = 11,
+	BNXT_ULP_HF1_OI_VLAN_TYPE = 12,
+	BNXT_ULP_HF1_O_IPV4_VER = 13,
+	BNXT_ULP_HF1_O_IPV4_TOS = 14,
+	BNXT_ULP_HF1_O_IPV4_LEN = 15,
+	BNXT_ULP_HF1_O_IPV4_FRAG_ID = 16,
+	BNXT_ULP_HF1_O_IPV4_FRAG_OFF = 17,
+	BNXT_ULP_HF1_O_IPV4_TTL = 18,
+	BNXT_ULP_HF1_O_IPV4_NEXT_PID = 19,
+	BNXT_ULP_HF1_O_IPV4_CSUM = 20,
+	BNXT_ULP_HF1_O_IPV4_SRC_ADDR = 21,
+	BNXT_ULP_HF1_O_IPV4_DST_ADDR = 22,
+	BNXT_ULP_HF1_O_UDP_SRC_PORT = 23,
+	BNXT_ULP_HF1_O_UDP_DST_PORT = 24,
+	BNXT_ULP_HF1_O_UDP_LENGTH = 25,
+	BNXT_ULP_HF1_O_UDP_CSUM = 26
+};
+
+/* class_template_id = 2: ingress flow */
+enum bnxt_ulp_hf2 {
+	BNXT_ULP_HF2_MPLS_TAG_NUM = 0,
+	BNXT_ULP_HF2_O_VTAG_NUM = 1,
+	BNXT_ULP_HF2_I_VTAG_NUM = 2,
+	BNXT_ULP_HF2_SVIF_INDEX = 3,
+	BNXT_ULP_HF2_O_ETH_DMAC = 4,
+	BNXT_ULP_HF2_O_ETH_SMAC = 5,
+	BNXT_ULP_HF2_O_ETH_TYPE = 6,
+	BNXT_ULP_HF2_OO_VLAN_CFI_PRI = 7,
+	BNXT_ULP_HF2_OO_VLAN_VID = 8,
+	BNXT_ULP_HF2_OO_VLAN_TYPE = 9,
+	BNXT_ULP_HF2_OI_VLAN_CFI_PRI = 10,
+	BNXT_ULP_HF2_OI_VLAN_VID = 11,
+	BNXT_ULP_HF2_OI_VLAN_TYPE = 12,
+	BNXT_ULP_HF2_O_IPV4_VER = 13,
+	BNXT_ULP_HF2_O_IPV4_TOS = 14,
+	BNXT_ULP_HF2_O_IPV4_LEN = 15,
+	BNXT_ULP_HF2_O_IPV4_FRAG_ID = 16,
+	BNXT_ULP_HF2_O_IPV4_FRAG_OFF = 17,
+	BNXT_ULP_HF2_O_IPV4_TTL = 18,
+	BNXT_ULP_HF2_O_IPV4_NEXT_PID = 19,
+	BNXT_ULP_HF2_O_IPV4_CSUM = 20,
+	BNXT_ULP_HF2_O_IPV4_SRC_ADDR = 21,
+	BNXT_ULP_HF2_O_IPV4_DST_ADDR = 22,
+	BNXT_ULP_HF2_O_UDP_SRC_PORT = 23,
+	BNXT_ULP_HF2_O_UDP_DST_PORT = 24,
+	BNXT_ULP_HF2_O_UDP_LENGTH = 25,
+	BNXT_ULP_HF2_O_UDP_CSUM = 26
+};
+
+#endif /* _ULP_HDR_FIELD_ENUMS_H_ */
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
index 2b0a3d7..e28d049 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
@@ -17,9 +17,21 @@
 #include "rte_flow.h"
 #include "tf_core.h"
 
+/* Structure to store the protocol fields */
+#define RTE_PARSER_FLOW_HDR_FIELD_SIZE		16
+struct ulp_rte_hdr_field {
+	uint8_t		spec[RTE_PARSER_FLOW_HDR_FIELD_SIZE];
+	uint8_t		mask[RTE_PARSER_FLOW_HDR_FIELD_SIZE];
+	uint32_t	size;
+};
+
+struct ulp_rte_act_bitmap {
+	uint64_t	bits;
+};
+
 /*
- * structure to hold the action property details
- * It is a array of 128 bytes
+ * Structure to hold the action property details.
+ * It is a array of 128 bytes.
  */
 struct ulp_rte_act_prop {
 	uint8_t	act_details[BNXT_ULP_ACT_PROP_IDX_LAST];
@@ -39,6 +51,35 @@ struct bnxt_ulp_device_params {
 	uint32_t			num_resources_per_flow;
 };
 
+struct bnxt_ulp_mapper_class_tbl_info {
+	enum bnxt_ulp_resource_func	resource_func;
+	uint32_t	table_type;
+	uint8_t		direction;
+	uint8_t		mem;
+	uint32_t	priority;
+	uint8_t		srch_b4_alloc;
+	uint32_t	critical_resource;
+
+	/* Information for accessing the ulp_key_field_list */
+	uint32_t	key_start_idx;
+	uint16_t	key_bit_size;
+	uint16_t	key_num_fields;
+	/* Size of the blob that holds the key */
+	uint16_t	blob_key_bit_size;
+
+	/* Information for accessing the ulp_class_result_field_list */
+	uint32_t	result_start_idx;
+	uint16_t	result_bit_size;
+	uint16_t	result_num_fields;
+
+	/* Information for accessing the ulp_ident_list */
+	uint32_t	ident_start_idx;
+	uint16_t	ident_nums;
+
+	uint8_t		mark_enable;
+	enum bnxt_ulp_regfile_index	regfile_wr_idx;
+};
+
 struct bnxt_ulp_mapper_act_tbl_info {
 	enum bnxt_ulp_resource_func	resource_func;
 	enum tf_tbl_type table_type;
@@ -52,6 +93,15 @@ struct bnxt_ulp_mapper_act_tbl_info {
 	enum bnxt_ulp_regfile_index	regfile_wr_idx;
 };
 
+struct bnxt_ulp_mapper_class_key_field_info {
+	uint8_t			name[64];
+	enum bnxt_ulp_mask_opc	mask_opcode;
+	enum bnxt_ulp_spec_opc	spec_opcode;
+	uint16_t		field_bit_size;
+	uint8_t			mask_operand[16];
+	uint8_t			spec_operand[16];
+};
+
 struct bnxt_ulp_mapper_result_field_info {
 	uint8_t				name[64];
 	enum bnxt_ulp_result_opc	result_opcode;
@@ -59,14 +109,36 @@ struct bnxt_ulp_mapper_result_field_info {
 	uint8_t				result_operand[16];
 };
 
+struct bnxt_ulp_mapper_ident_info {
+	uint8_t		name[64];
+	uint32_t	resource_func;
+
+	uint16_t	ident_type;
+	uint16_t	ident_bit_size;
+	uint16_t	ident_bit_pos;
+	enum bnxt_ulp_regfile_index	regfile_wr_idx;
+};
+
+/*
+ * Flow Mapper Static Data Externs:
+ * Access to the below static data should be done through access functions and
+ * directly throughout the code.
+ */
+
 /*
- * The ulp_device_params is indexed by the dev_id
- * This table maintains the device specific parameters
+ * The ulp_device_params is indexed by the dev_id.
+ * This table maintains the device specific parameters.
  */
 extern struct bnxt_ulp_device_params ulp_device_params[];
 
 /*
  * The ulp_data_field_list provides the instructions for creating an action
+ * records such as tcam/em results.
+ */
+extern struct bnxt_ulp_mapper_result_field_info	ulp_class_result_field_list[];
+
+/*
+ * The ulp_data_field_list provides the instructions for creating an action
  * record.  It uses the same structure as the result list, but is only used for
  * actions.
  */
@@ -75,6 +147,19 @@ struct bnxt_ulp_mapper_result_field_info ulp_act_result_field_list[];
 
 /*
  * The ulp_act_prop_map_table provides the mapping to index and size of action
+ * tcam and em tables.
+ */
+extern
+struct bnxt_ulp_mapper_class_key_field_info	ulp_class_key_field_list[];
+
+/*
+ * The ulp_ident_list provides the instructions for creating identifiers such
+ * as profile ids.
+ */
+extern struct bnxt_ulp_mapper_ident_info	ulp_ident_list[];
+
+/*
+ * The ulp_act_prop_map_table provides the mapping to index and size of action
  * properties.
  */
 extern uint32_t ulp_act_prop_map_table[];
-- 
2.7.4