From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0F80AA0598; Sun, 19 Apr 2020 00:47:43 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 2E9BE1D50F; Sun, 19 Apr 2020 00:47:03 +0200 (CEST) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by dpdk.org (Postfix) with ESMTP id C4EB11D444 for ; Sun, 19 Apr 2020 00:46:55 +0200 (CEST) IronPort-SDR: QzCCl4GZQtHEn60HUlZp/Q/0Q6KnHWsABEgHjuU55VaqzDpADZcMFswGBTCy4weKypfloJYUXh ajLF+fERFwmQ== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Apr 2020 15:46:51 -0700 IronPort-SDR: Uf1k5svWABRoEob+vW1JQNS3j4+222X7VrY/4OUArk0J2y7rJBizR0iKcxSbtqVv+NWI5bkk5y AzPp1g9uwnig== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.72,400,1580803200"; d="scan'208";a="455111245" Received: from skx-5gnr-sc12-4.sc.intel.com ([172.25.69.210]) by fmsmga005.fm.intel.com with ESMTP; 18 Apr 2020 15:46:51 -0700 From: Nicolas Chautru To: dev@dpdk.org, akhil.goyal@nxp.com Cc: bruce.richardson@intel.com, Nicolas Chautru Date: Sat, 18 Apr 2020 15:46:43 -0700 Message-Id: <1587250008-69892-7-git-send-email-nicolas.chautru@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1587250008-69892-1-git-send-email-nicolas.chautru@intel.com> References: <1587250008-69892-1-git-send-email-nicolas.chautru@intel.com> Subject: [dpdk-dev] [PATCH v5 06/11] baseband/fpga_5gnr_fec: add HW error capture X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Adding HW specific parsing of error report for negative scenarios. Not hit through unit test. Signed-off-by: Nicolas Chautru --- drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c | 62 ++++++++++++++++++++-- 1 file changed, 59 insertions(+), 3 deletions(-) diff --git a/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c b/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c index 2d0fb4f..ed07cab 100644 --- a/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c +++ b/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c @@ -519,6 +519,54 @@ return bitmap & bitmask; } +/* Print an error if a descriptor error has occurred. + * Return 0 on success, 1 on failure + */ +static inline int +check_desc_error(uint32_t error_code) { + switch (error_code) { + case DESC_ERR_NO_ERR: + return 0; + case DESC_ERR_K_P_OUT_OF_RANGE: + rte_bbdev_log(ERR, "Encode block size K' is out of range"); + break; + case DESC_ERR_Z_C_NOT_LEGAL: + rte_bbdev_log(ERR, "Zc is illegal"); + break; + case DESC_ERR_DESC_OFFSET_ERR: + rte_bbdev_log(ERR, + "Queue offset does not meet the expectation in the FPGA" + ); + break; + case DESC_ERR_DESC_READ_FAIL: + rte_bbdev_log(ERR, "Unsuccessful completion for descriptor read"); + break; + case DESC_ERR_DESC_READ_TIMEOUT: + rte_bbdev_log(ERR, "Descriptor read time-out"); + break; + case DESC_ERR_DESC_READ_TLP_POISONED: + rte_bbdev_log(ERR, "Descriptor read TLP poisoned"); + break; + case DESC_ERR_CB_READ_FAIL: + rte_bbdev_log(ERR, "Unsuccessful completion for code block"); + break; + case DESC_ERR_CB_READ_TIMEOUT: + rte_bbdev_log(ERR, "Code block read time-out"); + break; + case DESC_ERR_CB_READ_TLP_POISONED: + rte_bbdev_log(ERR, "Code block read TLP poisoned"); + break; + case DESC_ERR_HBSTORE_ERR: + rte_bbdev_log(ERR, "Hbstroe exceeds HARQ buffer size."); + break; + default: + rte_bbdev_log(ERR, "Descriptor error unknown error code %u", + error_code); + break; + } + return 1; +} + /* Compute value of k0. * Based on 3GPP 38.212 Table 5.4.2.1-2 * Starting position of different redundancy versions, k0 @@ -982,11 +1030,11 @@ static inline int dequeue_ldpc_enc_one_op_cb(struct fpga_queue *q, - struct rte_bbdev_enc_op **op __rte_unused, + struct rte_bbdev_enc_op **op, uint16_t desc_offset) { union fpga_dma_desc *desc; - + int desc_error; /* Set current desc */ desc = q->ring_addr + ((q->head_free_desc + desc_offset) & q->sw_ring_wrap_mask); @@ -1000,6 +1048,11 @@ rte_bbdev_log_debug("DMA response desc %p", desc); + *op = desc->enc_req.op_addr; + /* Check the descriptor error field, return 1 on error */ + desc_error = check_desc_error(desc->enc_req.error); + (*op)->status = desc_error << RTE_BBDEV_DATA_ERROR; + return 1; } @@ -1009,7 +1062,7 @@ uint16_t desc_offset) { union fpga_dma_desc *desc; - + int desc_error; /* Set descriptor */ desc = q->ring_addr + ((q->head_free_desc + desc_offset) & q->sw_ring_wrap_mask); @@ -1036,6 +1089,9 @@ (*op)->status = 1 << RTE_BBDEV_CRC_ERROR; /* et_pass = 0 when decoder fails */ (*op)->status |= !(desc->dec_req.et_pass) << RTE_BBDEV_SYNDROME_ERROR; + /* Check the descriptor error field, return 1 on error */ + desc_error = check_desc_error(desc->dec_req.error); + (*op)->status |= desc_error << RTE_BBDEV_DATA_ERROR; return 1; } -- 1.8.3.1