From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 05D08A053B; Fri, 17 Jul 2020 16:28:52 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id A4D8C1BF8D; Fri, 17 Jul 2020 16:28:36 +0200 (CEST) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by dpdk.org (Postfix) with ESMTP id 2C8E91BF5F for ; Fri, 17 Jul 2020 16:28:34 +0200 (CEST) Received: from Internal Mail-Server by MTLPINE1 (envelope-from viacheslavo@mellanox.com) with SMTP; 17 Jul 2020 17:28:30 +0300 Received: from pegasus12.mtr.labs.mlnx (pegasus12.mtr.labs.mlnx [10.210.17.40]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 06HESU4g000791; Fri, 17 Jul 2020 17:28:30 +0300 Received: from pegasus12.mtr.labs.mlnx (localhost [127.0.0.1]) by pegasus12.mtr.labs.mlnx (8.14.7/8.14.7) with ESMTP id 06HESUoT000413; Fri, 17 Jul 2020 14:28:30 GMT Received: (from viacheslavo@localhost) by pegasus12.mtr.labs.mlnx (8.14.7/8.14.7/Submit) id 06HESUwn000412; Fri, 17 Jul 2020 14:28:30 GMT X-Authentication-Warning: pegasus12.mtr.labs.mlnx: viacheslavo set sender to viacheslavo@mellanox.com using -f From: Viacheslav Ovsiienko To: dev@dpdk.org Cc: matan@mellanox.com, rasland@mellanox.com, thomas@monjalon.net Date: Fri, 17 Jul 2020 14:28:23 +0000 Message-Id: <1594996104-372-2-git-send-email-viacheslavo@mellanox.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1594996104-372-1-git-send-email-viacheslavo@mellanox.com> References: <1591771085-24959-1-git-send-email-viacheslavo@mellanox.com> <1594996104-372-1-git-send-email-viacheslavo@mellanox.com> Subject: [dpdk-dev] [PATCH 2/3] net/mlx5: fix compilation issue with atomic128 exchange X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" For naw the rte_atomic128_cmp_exchange() is available on x86-64 and ARM64 architectures. The patch fixes the compilation condition for the code using this atomic transaction. Fixes: 244788055199 ("net/mlx5: introduce clock queue service routine") Signed-off-by: Viacheslav Ovsiienko --- drivers/net/mlx5/mlx5_txpp.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/net/mlx5/mlx5_txpp.c b/drivers/net/mlx5/mlx5_txpp.c index 42776b8..cdb0079 100644 --- a/drivers/net/mlx5/mlx5_txpp.c +++ b/drivers/net/mlx5/mlx5_txpp.c @@ -644,7 +644,15 @@ * update by hardware with soecified rate. We have to * read timestump and WQE completion index atomically. */ -#if defined(RTE_ARCH_PPC_64) || defined(RTE_ARCH_32) +#if defined(RTE_ARCH_X86_64) || defined(RTE_ARCH_ARM64) + rte_int128_t src; + + memset(&src, 0, sizeof(src)); + *ts = src; + /* if (*from == *ts) *from = *src else *ts = *from; */ + rte_atomic128_cmp_exchange(from, ts, &src, 0, + __ATOMIC_RELAXED, __ATOMIC_RELAXED); +#else rte_atomic64_t *cqe = (rte_atomic64_t *)from; /* Power architecture does not support 16B compare-and-swap. */ @@ -665,14 +673,6 @@ ps[1] = op; return; } -#else - rte_int128_t src; - - memset(&src, 0, sizeof(src)); - *ts = src; - /* if (*from == *ts) *from = *src else *ts = *from; */ - rte_atomic128_cmp_exchange(from, ts, &src, 0, - __ATOMIC_RELAXED, __ATOMIC_RELAXED); #endif } -- 1.8.3.1