From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id AA5C1A04BC; Thu, 8 Oct 2020 10:33:57 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 9220A1BA6F; Thu, 8 Oct 2020 10:33:56 +0200 (CEST) Received: from out4-smtp.messagingengine.com (out4-smtp.messagingengine.com [66.111.4.28]) by dpdk.org (Postfix) with ESMTP id A86471B9F0 for ; Thu, 8 Oct 2020 10:33:53 +0200 (CEST) Received: from compute2.internal (compute2.nyi.internal [10.202.2.42]) by mailout.nyi.internal (Postfix) with ESMTP id 338795C01E9; Thu, 8 Oct 2020 04:33:50 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute2.internal (MEProxy); Thu, 08 Oct 2020 04:33:50 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=monjalon.net; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s=fm2; bh= D1g0Lz+qEoEevZEExjgYKwhaWm2tSCBFNWB4Us1DXnI=; b=wf+iqtr3Pxo5kDZW uFcm/rSh4KO86QEUgMfG6g/iQ0cqDs/fNfAnrGG+MxI282je//eROfNVivV7tA9w NMckTnq8T+qxZOwQBuIvlguwL52eWrrmHM06FPvVA/wxuH2e57RZJDVlDMNU7tAX SUL1k00WPxunhU6O1gf+vJ4slSB1XW9Xa1WUskwdq9cuSDDsvKU41h8W0o+J5Pwv dVF6kiIh0aygQOX2GlswL5c5gEXLlvITNmMfzcMHj2+QAGcr/JGRuQ6Z7kPYWNtH KpgjU/mNG7PnIDKUbnPhV+P5F7CqAFg7zqiMJP6RojxKZRSJhGFx42eTIMy1m+Zl 10I5Aw== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-proxy:x-me-proxy:x-me-sender:x-me-sender :x-sasl-enc; s=fm1; bh=D1g0Lz+qEoEevZEExjgYKwhaWm2tSCBFNWB4Us1DX nI=; b=nZu/eHFx6PAtIipixHf9TuZ/vyecOHOqqNy0MZeFc/ia2Kdxqg6bG/JMZ HISkZ34Wg5T8UommlyjCBlvkypZqblsHoaL18HHRkSHNCmP3SF65DfiHSP4oHWn1 HEyBFP6L4iZukEhL9WxSJWiD581Yu+dxEkdmiq/KSnVkrPoFuwoeToDXVH4lW52Q wvjfRNocNWdiWPMW9McCi2IkfobYUWV8p/t00uAW9NLPahTEQ6NxaDVdy7D5a3Hm oPYb/FSx8s7pyTS+Khhbj1iQX/gZif+lWUTPllMmSszDZM88KXfHR9OcKQIIclCB zoAyxtyS662bl5qyETCbsVyMem5Ag== X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedujedrgeekgddtiecutefuodetggdotefrodftvf curfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfghnecu uegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenuc fjughrpefhvffufffkjghfggfgtgesthfuredttddtvdenucfhrhhomhepvfhhohhmrghs ucfoohhnjhgrlhhonhcuoehthhhomhgrshesmhhonhhjrghlohhnrdhnvghtqeenucggtf frrghtthgvrhhnpedugefgvdefudfftdefgeelgffhueekgfffhfeujedtteeutdejueei iedvffegheenucfkphepjeejrddufeegrddvtdefrddukeegnecuvehluhhsthgvrhfuih iivgeptdenucfrrghrrghmpehmrghilhhfrhhomhepthhhohhmrghssehmohhnjhgrlhho nhdrnhgvth X-ME-Proxy: Received: from xps.localnet (184.203.134.77.rev.sfr.net [77.134.203.184]) by mail.messagingengine.com (Postfix) with ESMTPA id 25331328005A; Thu, 8 Oct 2020 04:33:48 -0400 (EDT) From: Thomas Monjalon To: Liang Ma Cc: dev@dpdk.org, david.hunt@intel.com, stephen@networkplumber.org, konstantin.ananyev@intel.com, Anatoly Burakov , Liang Ma , honnappa.nagarahalli@arm.com, ruifeng.wang@arm.com, David Christensen , jerinj@marvell.com Date: Thu, 08 Oct 2020 10:33:47 +0200 Message-ID: <16022545.g3EcnA0i2J@thomas> In-Reply-To: <1601647919-25312-2-git-send-email-liang.j.ma@intel.com> References: <1599214740-3927-1-git-send-email-liang.j.ma@intel.com> <1601647919-25312-1-git-send-email-liang.j.ma@intel.com> <1601647919-25312-2-git-send-email-liang.j.ma@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Subject: Re: [dpdk-dev] [PATCH v4 02/10] eal: add power management intrinsics X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > Add two new power management intrinsics, and provide an implementation > in eal/x86 based on UMONITOR/UMWAIT instructions. The instructions > are implemented as raw byte opcodes because there is not yet widespread > compiler support for these instructions. > > The power management instructions provide an architecture-specific > function to either wait until a specified TSC timestamp is reached, or > optionally wait until either a TSC timestamp is reached or a memory > location is written to. The monitor function also provides an optional > comparison, to avoid sleeping when the expected write has already > happened, and no more writes are expected. > > For more details, Please reference Intel SDM Volume 2. I really would like to see feedbacks from other arch maintainers. Unfortunately they were not Cc'ed. Also please mark the new functions as experimental.