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* [dpdk-dev] [PATCH 00/14] bnxt patches
@ 2020-10-17  6:27 Venkat Duvvuru
  2020-10-17  6:27 ` [dpdk-dev] [PATCH 01/14] net/bnxt: device cleanup of FW Venkat Duvvuru
                   ` (14 more replies)
  0 siblings, 15 replies; 32+ messages in thread
From: Venkat Duvvuru @ 2020-10-17  6:27 UTC (permalink / raw)
  To: dev; +Cc: Venkat Duvvuru

This patchset has support for vxlan decap full offload,
SR device support in tf_core and a few bug fixes.

Farah Smith (3):
  net/bnxt: map table scope API
  net/bnxt: table scope to PF Mapping for SR and Wh+
  net/bnxt: update SR ULP resource counts

Jay Ding (2):
  net/bnxt: add stingray support
  net/bnxt: changes to support 2 table scopes

Kishore Padmanabha (2):
  net/bnxt: add support for parent flow accumulation counters
  net/bnxt: add mapper support for wildcard TCAM entry

Peter Spreadborough (2):
  net/bnxt: device cleanup of FW
  net/bnxt: add build option for EM slot allocation

Somnath Kotur (2):
  net/bnxt: fix infinite loop in flow query count API
  net/bnxt: use cfa pair alloc for configuring reps

Venkat Duvvuru (3):
  net/bnxt: refactor flow id allocation
  net/bnxt: add support for VXLAN decap templates
  net/bnxt: add VXLAN decap offload support

 drivers/net/bnxt/bnxt.h                            |    6 +-
 drivers/net/bnxt/bnxt_ethdev.c                     |    2 +
 drivers/net/bnxt/bnxt_hwrm.c                       |   60 +-
 drivers/net/bnxt/bnxt_hwrm.h                       |    2 -
 drivers/net/bnxt/bnxt_reps.c                       |   18 +-
 drivers/net/bnxt/hcapi/hcapi_cfa.h                 |   39 +-
 drivers/net/bnxt/meson.build                       |    1 +
 drivers/net/bnxt/tf_core/cfa_resource_types.h      |   95 +-
 drivers/net/bnxt/tf_core/tf_core.c                 |   57 +-
 drivers/net/bnxt/tf_core/tf_core.h                 |   57 +-
 drivers/net/bnxt/tf_core/tf_device.c               |    9 +-
 drivers/net/bnxt/tf_core/tf_device.h               |   47 +-
 drivers/net/bnxt/tf_core/tf_device_p4.c            |   69 +-
 drivers/net/bnxt/tf_core/tf_device_p4.h            |    6 +
 drivers/net/bnxt/tf_core/tf_device_p45.h           |  105 +
 drivers/net/bnxt/tf_core/tf_em.h                   |   25 +-
 drivers/net/bnxt/tf_core/tf_em_common.c            |  175 +-
 drivers/net/bnxt/tf_core/tf_em_common.h            |   27 +-
 drivers/net/bnxt/tf_core/tf_em_host.c              |   31 +-
 drivers/net/bnxt/tf_core/tf_global_cfg.c           |    4 +-
 drivers/net/bnxt/tf_core/tf_global_cfg.h           |   42 +-
 drivers/net/bnxt/tf_core/tf_msg.c                  |   13 +-
 drivers/net/bnxt/tf_core/tf_msg.h                  |    4 +-
 drivers/net/bnxt/tf_core/tf_session.h              |   16 +-
 drivers/net/bnxt/tf_core/tf_tbl.h                  |    3 +
 drivers/net/bnxt/tf_core/tfp.c                     |   19 +
 drivers/net/bnxt/tf_core/tfp.h                     |   16 +
 drivers/net/bnxt/tf_ulp/bnxt_tf_common.h           |    4 +-
 drivers/net/bnxt/tf_ulp/bnxt_ulp.c                 |   50 +-
 drivers/net/bnxt/tf_ulp/bnxt_ulp.h                 |   12 +
 drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c            |  129 +-
 drivers/net/bnxt/tf_ulp/ulp_def_rules.c            |   48 +-
 drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c               |  133 +-
 drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h               |   19 +
 drivers/net/bnxt/tf_ulp/ulp_flow_db.c              |  475 +++-
 drivers/net/bnxt/tf_ulp/ulp_flow_db.h              |   46 +
 drivers/net/bnxt/tf_ulp/ulp_mapper.c               |   83 +-
 drivers/net/bnxt/tf_ulp/ulp_mapper.h               |    6 +-
 drivers/net/bnxt/tf_ulp/ulp_rte_parser.c           |   85 +-
 drivers/net/bnxt/tf_ulp/ulp_rte_parser.h           |   12 +
 drivers/net/bnxt/tf_ulp/ulp_template_db_class.c    |  962 +++++---
 drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h     |   42 +-
 drivers/net/bnxt/tf_ulp/ulp_template_db_field.h    |  363 ++-
 .../net/bnxt/tf_ulp/ulp_template_db_stingray_act.c |  116 +-
 .../bnxt/tf_ulp/ulp_template_db_stingray_class.c   | 2493 ++++++++++++++++----
 drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c      |    9 +-
 .../net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c  |  116 +-
 .../bnxt/tf_ulp/ulp_template_db_wh_plus_class.c    | 2489 +++++++++++++++----
 drivers/net/bnxt/tf_ulp/ulp_template_struct.h      |    7 +
 drivers/net/bnxt/tf_ulp/ulp_tun.c                  |  310 +++
 drivers/net/bnxt/tf_ulp/ulp_tun.h                  |   92 +
 drivers/net/bnxt/tf_ulp/ulp_utils.c                |  125 +
 drivers/net/bnxt/tf_ulp/ulp_utils.h                |   48 +-
 53 files changed, 7185 insertions(+), 2037 deletions(-)
 create mode 100644 drivers/net/bnxt/tf_core/tf_device_p45.h
 create mode 100644 drivers/net/bnxt/tf_ulp/ulp_tun.c
 create mode 100644 drivers/net/bnxt/tf_ulp/ulp_tun.h

-- 
2.7.4


^ permalink raw reply	[flat|nested] 32+ messages in thread

* [dpdk-dev] [PATCH 01/14] net/bnxt: device cleanup of FW
  2020-10-17  6:27 [dpdk-dev] [PATCH 00/14] bnxt patches Venkat Duvvuru
@ 2020-10-17  6:27 ` Venkat Duvvuru
  2020-10-17  6:27 ` [dpdk-dev] [PATCH 02/14] net/bnxt: add stingray support Venkat Duvvuru
                   ` (13 subsequent siblings)
  14 siblings, 0 replies; 32+ messages in thread
From: Venkat Duvvuru @ 2020-10-17  6:27 UTC (permalink / raw)
  To: dev; +Cc: Peter Spreadborough

From: Peter Spreadborough <peter.spreadborough@broadcom.com>

- Moved P4 specific code under the P4 directory
- Added P45 skeleton code for SR to build on

Signed-off-by: Peter Spreadborough <peter.spreadborough@broadcom.com>
Reviewed-by: Farah Smith <farah.smith@broadcom.com>
---
 drivers/net/bnxt/hcapi/hcapi_cfa.h       | 39 ++++++++++++++++++++++++--------
 drivers/net/bnxt/tf_core/tf_core.h       |  2 +-
 drivers/net/bnxt/tf_core/tf_device_p45.h | 16 +++++++++++++
 drivers/net/bnxt/tf_core/tf_em.h         |  6 -----
 4 files changed, 46 insertions(+), 17 deletions(-)
 create mode 100644 drivers/net/bnxt/tf_core/tf_device_p45.h

diff --git a/drivers/net/bnxt/hcapi/hcapi_cfa.h b/drivers/net/bnxt/hcapi/hcapi_cfa.h
index c7d87de..aa218d7 100644
--- a/drivers/net/bnxt/hcapi/hcapi_cfa.h
+++ b/drivers/net/bnxt/hcapi/hcapi_cfa.h
@@ -14,7 +14,15 @@
 
 #include "hcapi_cfa_defs.h"
 
+#if CHIP_CFG == SR_A
+#define SUPPORT_CFA_HW_P45  1
+#undef SUPPORT_CFA_HW_P4
+#define SUPPORT_CFA_HW_P4   0
+#elif CHIP_CFG == CMB_A
 #define SUPPORT_CFA_HW_P4  1
+#else
+#error "Chip not supported"
+#endif
 
 #if SUPPORT_CFA_HW_P4 && SUPPORT_CFA_HW_P58 && SUPPORT_CFA_HW_P59
 #define SUPPORT_CFA_HW_ALL  1
@@ -81,17 +89,20 @@ struct hcapi_cfa_key_result {
 /* common CFA register access macros */
 #define CFA_REG(x)		OFFSETOF(cfa_reg_t, cfa_##x)
 
-#ifndef REG_WR
-#define REG_WR(_p, x, y)  (*((uint32_t volatile *)(x)) = (y))
+#ifndef TF_REG_WR
+#define TF_REG_WR(_p, x, y)  (*((uint32_t volatile *)(x)) = (y))
 #endif
-#ifndef REG_RD
-#define REG_RD(_p, x)  (*((uint32_t volatile *)(x)))
+#ifndef TF_REG_RD
+#define TF_REG_RD(_p, x)  (*((uint32_t volatile *)(x)))
+#endif
+#ifndef TF_CFA_REG_RD
+#define TF_CFA_REG_RD(_p, x)	\
+	TF_REG_RD(0, (uint32_t)(_p)->base_addr + CFA_REG(x))
+#endif
+#ifndef TF_CFA_REG_WR
+#define TF_CFA_REG_WR(_p, x, y)	\
+	TF_REG_WR(0, (uint32_t)(_p)->base_addr + CFA_REG(x), y)
 #endif
-#define CFA_REG_RD(_p, x)	\
-	REG_RD(0, (uint32_t)(_p)->base_addr + CFA_REG(x))
-#define CFA_REG_WR(_p, x, y)	\
-	REG_WR(0, (uint32_t)(_p)->base_addr + CFA_REG(x), y)
-
 
 /* Constants used by Resource Manager Registration*/
 #define RM_CLIENT_NAME_MAX_LEN          32
@@ -248,7 +259,15 @@ int hcapi_cfa_p4_mirror_hwop(struct hcapi_cfa_hwop *op,
 int hcapi_cfa_p4_global_cfg_hwop(struct hcapi_cfa_hwop *op,
 				 uint32_t type,
 				 struct hcapi_cfa_data *config);
-#endif /* SUPPORT_CFA_HW_P4 */
+/* SUPPORT_CFA_HW_P4 */
+#elif SUPPORT_CFA_HW_P45
+int hcapi_cfa_p45_mirror_hwop(struct hcapi_cfa_hwop *op,
+			      struct hcapi_cfa_data *mirror);
+int hcapi_cfa_p45_global_cfg_hwop(struct hcapi_cfa_hwop *op,
+				  uint32_t type,
+				  struct hcapi_cfa_data *config);
+/* SUPPORT_CFA_HW_P45 */
+#endif
 /**
  *  HCAPI CFA device HW operation function callback definition
  *  This is standardized function callback hook to install different
diff --git a/drivers/net/bnxt/tf_core/tf_core.h b/drivers/net/bnxt/tf_core/tf_core.h
index db10935..65be8f5 100644
--- a/drivers/net/bnxt/tf_core/tf_core.h
+++ b/drivers/net/bnxt/tf_core/tf_core.h
@@ -10,7 +10,7 @@
 #include <stdlib.h>
 #include <stdbool.h>
 #include <stdio.h>
-#include "hcapi/hcapi_cfa.h"
+#include "hcapi/hcapi_cfa_defs.h"
 #include "tf_project.h"
 
 /**
diff --git a/drivers/net/bnxt/tf_core/tf_device_p45.h b/drivers/net/bnxt/tf_core/tf_device_p45.h
new file mode 100644
index 0000000..2da59d1
--- /dev/null
+++ b/drivers/net/bnxt/tf_core/tf_device_p45.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2019-2020 Broadcom
+ * All rights reserved.
+ */
+
+#ifndef _TF_DEVICE_P45_H_
+#define _TF_DEVICE_P45_H_
+
+#include <cfa_resource_types.h>
+
+#include "tf_core.h"
+#include "tf_rm.h"
+#include "tf_if_tbl.h"
+#include "tf_global_cfg.h"
+
+#endif /* _TF_DEVICE_P45_H_ */
diff --git a/drivers/net/bnxt/tf_core/tf_em.h b/drivers/net/bnxt/tf_core/tf_em.h
index 2a67e47..51b0813 100644
--- a/drivers/net/bnxt/tf_core/tf_em.h
+++ b/drivers/net/bnxt/tf_core/tf_em.h
@@ -9,12 +9,6 @@
 #include "tf_core.h"
 #include "tf_session.h"
 
-
-#define SUPPORT_CFA_HW_P4 1
-#define SUPPORT_CFA_HW_P58 0
-#define SUPPORT_CFA_HW_P59 0
-#define SUPPORT_CFA_HW_ALL 0
-
 #include "hcapi/hcapi_cfa_defs.h"
 
 #define TF_EM_MIN_ENTRIES     (1 << 15) /* 32K */
-- 
2.7.4


^ permalink raw reply	[flat|nested] 32+ messages in thread

* [dpdk-dev] [PATCH 02/14] net/bnxt: add stingray support
  2020-10-17  6:27 [dpdk-dev] [PATCH 00/14] bnxt patches Venkat Duvvuru
  2020-10-17  6:27 ` [dpdk-dev] [PATCH 01/14] net/bnxt: device cleanup of FW Venkat Duvvuru
@ 2020-10-17  6:27 ` Venkat Duvvuru
  2020-10-17  6:27 ` [dpdk-dev] [PATCH 03/14] net/bnxt: changes to support 2 table scopes Venkat Duvvuru
                   ` (12 subsequent siblings)
  14 siblings, 0 replies; 32+ messages in thread
From: Venkat Duvvuru @ 2020-10-17  6:27 UTC (permalink / raw)
  To: dev; +Cc: Jay Ding

From: Jay Ding <jay.ding@broadcom.com>

Add SR support in truflow.

Signed-off-by: Jay Ding <jay.ding@broadcom.com>
Reviewed-by: Farah Smith <farah.smith@broadcom.com>
---
 drivers/net/bnxt/tf_core/cfa_resource_types.h | 95 ++++++++++-----------------
 drivers/net/bnxt/tf_core/tf_core.c            |  3 +-
 drivers/net/bnxt/tf_core/tf_device.c          |  9 ++-
 drivers/net/bnxt/tf_core/tf_device_p4.c       | 25 ++++++-
 drivers/net/bnxt/tf_core/tf_device_p4.h       |  6 ++
 drivers/net/bnxt/tf_core/tf_device_p45.h      | 89 +++++++++++++++++++++++++
 6 files changed, 161 insertions(+), 66 deletions(-)

diff --git a/drivers/net/bnxt/tf_core/cfa_resource_types.h b/drivers/net/bnxt/tf_core/cfa_resource_types.h
index 19838c3..a62063b 100644
--- a/drivers/net/bnxt/tf_core/cfa_resource_types.h
+++ b/drivers/net/bnxt/tf_core/cfa_resource_types.h
@@ -1,6 +1,13 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2020 Broadcom
- * All rights reserved.
+/*
+ * Copyright(c) 2001-2020, Broadcom. All rights reserved. The
+ * term Broadcom refers to Broadcom Inc. and/or its subsidiaries.
+ * Proprietary and Confidential Information.
+ *
+ * This source file is the property of Broadcom Corporation, and
+ * may not be copied or distributed in any isomorphic form without
+ * the prior written consent of Broadcom Corporation.
+ *
+ * DO NOT MODIFY!!! This file is automatically generated.
  */
 
 #ifndef _CFA_RESOURCE_TYPES_H_
@@ -64,79 +71,47 @@
 #define CFA_RESOURCE_TYPE_P59_LAST              CFA_RESOURCE_TYPE_P59_VEB_TCAM
 
 
-/* Multicast Group */
-#define CFA_RESOURCE_TYPE_P58_MCG                 0x0UL
-/* Encap 8 byte record */
-#define CFA_RESOURCE_TYPE_P58_ENCAP_8B            0x1UL
-/* Encap 16 byte record */
-#define CFA_RESOURCE_TYPE_P58_ENCAP_16B           0x2UL
-/* Encap 64 byte record */
-#define CFA_RESOURCE_TYPE_P58_ENCAP_64B           0x3UL
-/* Source Property MAC */
-#define CFA_RESOURCE_TYPE_P58_SP_MAC              0x4UL
-/* Source Property MAC and IPv4 */
-#define CFA_RESOURCE_TYPE_P58_SP_MAC_IPV4         0x5UL
-/* Source Property MAC and IPv6 */
-#define CFA_RESOURCE_TYPE_P58_SP_MAC_IPV6         0x6UL
-/* Network Address Translation Port */
-#define CFA_RESOURCE_TYPE_P58_NAT_PORT            0x7UL
-/* Network Address Translation IPv4 address */
-#define CFA_RESOURCE_TYPE_P58_NAT_IPV4            0x8UL
 /* Meter */
-#define CFA_RESOURCE_TYPE_P58_METER               0x9UL
-/* Flow State */
-#define CFA_RESOURCE_TYPE_P58_FLOW_STATE          0xaUL
-/* Full Action Records */
-#define CFA_RESOURCE_TYPE_P58_FULL_ACTION         0xbUL
-/* Action Record Format 0 */
-#define CFA_RESOURCE_TYPE_P58_FORMAT_0_ACTION     0xcUL
-/* Action Record Ext Format 0 */
-#define CFA_RESOURCE_TYPE_P58_EXT_FORMAT_0_ACTION 0xdUL
-/* Action Record Format 1 */
-#define CFA_RESOURCE_TYPE_P58_FORMAT_1_ACTION     0xeUL
-/* Action Record Format 2 */
-#define CFA_RESOURCE_TYPE_P58_FORMAT_2_ACTION     0xfUL
-/* Action Record Format 3 */
-#define CFA_RESOURCE_TYPE_P58_FORMAT_3_ACTION     0x10UL
-/* Action Record Format 4 */
-#define CFA_RESOURCE_TYPE_P58_FORMAT_4_ACTION     0x11UL
-/* Action Record Format 5 */
-#define CFA_RESOURCE_TYPE_P58_FORMAT_5_ACTION     0x12UL
-/* Action Record Format 6 */
-#define CFA_RESOURCE_TYPE_P58_FORMAT_6_ACTION     0x13UL
+#define CFA_RESOURCE_TYPE_P58_METER              0x0UL
+/* SRAM_Bank_0 */
+#define CFA_RESOURCE_TYPE_P58_SRAM_BANK_0        0x1UL
+/* SRAM_Bank_1 */
+#define CFA_RESOURCE_TYPE_P58_SRAM_BANK_1        0x2UL
+/* SRAM_Bank_2 */
+#define CFA_RESOURCE_TYPE_P58_SRAM_BANK_2        0x3UL
+/* SRAM_Bank_3 */
+#define CFA_RESOURCE_TYPE_P58_SRAM_BANK_3        0x4UL
 /* L2 Context TCAM High priority entries */
-#define CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_HIGH   0x14UL
+#define CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_HIGH  0x5UL
 /* L2 Context TCAM Low priority entries */
-#define CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_LOW    0x15UL
+#define CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_LOW   0x6UL
 /* L2 Context REMAP high priority entries */
-#define CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_HIGH  0x16UL
+#define CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_HIGH 0x7UL
 /* L2 Context REMAP Low priority entries */
-#define CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_LOW   0x17UL
+#define CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_LOW  0x8UL
 /* Profile Func */
-#define CFA_RESOURCE_TYPE_P58_PROF_FUNC           0x18UL
+#define CFA_RESOURCE_TYPE_P58_PROF_FUNC          0x9UL
 /* Profile TCAM */
-#define CFA_RESOURCE_TYPE_P58_PROF_TCAM           0x19UL
+#define CFA_RESOURCE_TYPE_P58_PROF_TCAM          0xaUL
 /* Exact Match Profile Id */
-#define CFA_RESOURCE_TYPE_P58_EM_PROF_ID          0x1aUL
+#define CFA_RESOURCE_TYPE_P58_EM_PROF_ID         0xbUL
 /* Wildcard Profile Id */
-#define CFA_RESOURCE_TYPE_P58_WC_TCAM_PROF_ID     0x1bUL
+#define CFA_RESOURCE_TYPE_P58_WC_TCAM_PROF_ID    0xcUL
 /* Exact Match Record */
-#define CFA_RESOURCE_TYPE_P58_EM_REC              0x1cUL
+#define CFA_RESOURCE_TYPE_P58_EM_REC             0xdUL
 /* Wildcard TCAM */
-#define CFA_RESOURCE_TYPE_P58_WC_TCAM             0x1dUL
+#define CFA_RESOURCE_TYPE_P58_WC_TCAM            0xeUL
 /* Meter profile */
-#define CFA_RESOURCE_TYPE_P58_METER_PROF          0x1eUL
+#define CFA_RESOURCE_TYPE_P58_METER_PROF         0xfUL
 /* Meter */
-#define CFA_RESOURCE_TYPE_P58_MIRROR              0x1fUL
-/* Source Property TCAM */
-#define CFA_RESOURCE_TYPE_P58_SP_TCAM             0x20UL
+#define CFA_RESOURCE_TYPE_P58_MIRROR             0x10UL
 /* Exact Match Flexible Key Builder */
-#define CFA_RESOURCE_TYPE_P58_EM_FKB              0x21UL
+#define CFA_RESOURCE_TYPE_P58_EM_FKB             0x11UL
 /* Wildcard Flexible Key Builder */
-#define CFA_RESOURCE_TYPE_P58_WC_FKB              0x22UL
+#define CFA_RESOURCE_TYPE_P58_WC_FKB             0x12UL
 /* VEB TCAM */
-#define CFA_RESOURCE_TYPE_P58_VEB_TCAM            0x23UL
-#define CFA_RESOURCE_TYPE_P58_LAST               CFA_RESOURCE_TYPE_P58_VEB_TCAM
+#define CFA_RESOURCE_TYPE_P58_VEB_TCAM           0x13UL
+#define CFA_RESOURCE_TYPE_P58_LAST              CFA_RESOURCE_TYPE_P58_VEB_TCAM
 
 
 /* Multicast Group */
diff --git a/drivers/net/bnxt/tf_core/tf_core.c b/drivers/net/bnxt/tf_core/tf_core.c
index 0dbde1d..788335b 100644
--- a/drivers/net/bnxt/tf_core/tf_core.c
+++ b/drivers/net/bnxt/tf_core/tf_core.c
@@ -34,7 +34,8 @@ tf_open_session(struct tf *tfp,
 	 * side. It is assumed that the Firmware will be supported if
 	 * firmware open session succeeds.
 	 */
-	if (parms->device_type != TF_DEVICE_TYPE_WH) {
+	if (parms->device_type != TF_DEVICE_TYPE_WH &&
+	    parms->device_type != TF_DEVICE_TYPE_SR) {
 		TFP_DRV_LOG(ERR,
 			    "Unsupported device type %d\n",
 			    parms->device_type);
diff --git a/drivers/net/bnxt/tf_core/tf_device.c b/drivers/net/bnxt/tf_core/tf_device.c
index 1129440..8389828 100644
--- a/drivers/net/bnxt/tf_core/tf_device.c
+++ b/drivers/net/bnxt/tf_core/tf_device.c
@@ -47,7 +47,6 @@ tf_dev_bind_p4(struct tf *tfp,
 	struct tf_if_tbl_cfg_parms if_tbl_cfg;
 	struct tf_global_cfg_cfg_parms global_cfg;
 
-	dev_handle->type = TF_DEVICE_TYPE_WH;
 	/* Initial function initialization */
 	dev_handle->ops = &tf_dev_ops_p4_init;
 
@@ -90,7 +89,10 @@ tf_dev_bind_p4(struct tf *tfp,
 	 * EEM
 	 */
 	em_cfg.num_elements = TF_EM_TBL_TYPE_MAX;
-	em_cfg.cfg = tf_em_ext_p4;
+	if (dev_handle->type == TF_DEVICE_TYPE_WH)
+		em_cfg.cfg = tf_em_ext_p4;
+	else
+		em_cfg.cfg = tf_em_ext_p45;
 	em_cfg.resources = resources;
 	em_cfg.mem_type = TF_EEM_MEM_TYPE_HOST;
 	rc = tf_em_ext_common_bind(tfp, &em_cfg);
@@ -241,6 +243,8 @@ tf_dev_bind(struct tf *tfp __rte_unused,
 {
 	switch (type) {
 	case TF_DEVICE_TYPE_WH:
+	case TF_DEVICE_TYPE_SR:
+		dev_handle->type = type;
 		return tf_dev_bind_p4(tfp,
 				      shadow_copy,
 				      resources,
@@ -258,6 +262,7 @@ tf_dev_unbind(struct tf *tfp,
 {
 	switch (dev_handle->type) {
 	case TF_DEVICE_TYPE_WH:
+	case TF_DEVICE_TYPE_SR:
 		return tf_dev_unbind_p4(tfp);
 	default:
 		TFP_DRV_LOG(ERR,
diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.c b/drivers/net/bnxt/tf_core/tf_device_p4.c
index fe8dec3..0344565 100644
--- a/drivers/net/bnxt/tf_core/tf_device_p4.c
+++ b/drivers/net/bnxt/tf_core/tf_device_p4.c
@@ -28,13 +28,32 @@
  *   - (-EINVAL) on failure.
  */
 static int
-tf_dev_p4_get_max_types(struct tf *tfp __rte_unused,
+tf_dev_p4_get_max_types(struct tf *tfp,
 			uint16_t *max_types)
 {
-	if (max_types == NULL)
+	struct tf_session *tfs;
+	struct tf_dev_info *dev;
+	int rc;
+
+	if (max_types == NULL || tfp == NULL)
 		return -EINVAL;
 
-	*max_types = CFA_RESOURCE_TYPE_P4_LAST + 1;
+	/* Retrieve the session information */
+	rc = tf_session_get_session(tfp, &tfs);
+	if (rc)
+		return rc;
+
+	/* Retrieve the device information */
+	rc = tf_session_get_device(tfs, &dev);
+	if (rc)
+		return rc;
+
+	if (dev->type == TF_DEVICE_TYPE_WH)
+		*max_types = CFA_RESOURCE_TYPE_P4_LAST + 1;
+	else if (dev->type == TF_DEVICE_TYPE_SR)
+		*max_types = CFA_RESOURCE_TYPE_P45_LAST + 1;
+	else
+		return -ENODEV;
 
 	return 0;
 }
diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.h b/drivers/net/bnxt/tf_core/tf_device_p4.h
index 7e58469..aba28fe 100644
--- a/drivers/net/bnxt/tf_core/tf_device_p4.h
+++ b/drivers/net/bnxt/tf_core/tf_device_p4.h
@@ -83,6 +83,12 @@ struct tf_rm_element_cfg tf_em_ext_p4[TF_EM_TBL_TYPE_MAX] = {
 	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_TBL_SCOPE },
 };
 
+struct tf_rm_element_cfg tf_em_ext_p45[TF_EM_TBL_TYPE_MAX] = {
+	/* CFA_RESOURCE_TYPE_P4_EM_REC */
+	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
+	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_TBL_SCOPE },
+};
+
 struct tf_rm_element_cfg tf_em_int_p4[TF_EM_TBL_TYPE_MAX] = {
 	{ TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_EM_REC },
 	/* CFA_RESOURCE_TYPE_P4_TBL_SCOPE */
diff --git a/drivers/net/bnxt/tf_core/tf_device_p45.h b/drivers/net/bnxt/tf_core/tf_device_p45.h
index 2da59d1..016d6e2 100644
--- a/drivers/net/bnxt/tf_core/tf_device_p45.h
+++ b/drivers/net/bnxt/tf_core/tf_device_p45.h
@@ -13,4 +13,93 @@
 #include "tf_if_tbl.h"
 #include "tf_global_cfg.h"
 
+struct tf_rm_element_cfg tf_ident_p4[TF_IDENT_TYPE_MAX] = {
+	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_L2_CTXT_REMAP_HIGH },
+	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_L2_CTXT_REMAP_LOW },
+	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_PROF_FUNC },
+	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_WC_TCAM_PROF_ID },
+	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_EM_PROF_ID },
+	/* CFA_RESOURCE_TYPE_P45_L2_FUNC */
+	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }
+};
+
+struct tf_rm_element_cfg tf_tcam_p4[TF_TCAM_TBL_TYPE_MAX] = {
+	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_L2_CTXT_TCAM_HIGH },
+	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_L2_CTXT_TCAM_LOW },
+	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_PROF_TCAM },
+	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_WC_TCAM },
+	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_SP_TCAM },
+	/* CFA_RESOURCE_TYPE_P45_CT_RULE_TCAM */
+	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
+	/* CFA_RESOURCE_TYPE_P45_VEB_TCAM */
+	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }
+};
+
+struct tf_rm_element_cfg tf_tbl_p4[TF_TBL_TYPE_MAX] = {
+	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_FULL_ACTION },
+	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_MCG },
+	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_ENCAP_8B },
+	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_ENCAP_16B },
+	/* CFA_RESOURCE_TYPE_P45_ENCAP_32B */
+	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
+	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_ENCAP_64B },
+	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_SP_MAC },
+	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_SP_MAC_IPV4 },
+	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_SP_MAC_IPV6 },
+	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_COUNTER_64B },
+	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_NAT_PORT },
+	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_NAT_PORT },
+	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_NAT_IPV4 },
+	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_METER_PROF },
+	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_METER },
+	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_MIRROR },
+	/* CFA_RESOURCE_TYPE_P45_UPAR */
+	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
+	/* CFA_RESOURCE_TYPE_P45_EPOC */
+	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
+	/* CFA_RESOURCE_TYPE_P45_METADATA */
+	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
+	/* CFA_RESOURCE_TYPE_P45_CT_STATE */
+	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
+	/* CFA_RESOURCE_TYPE_P45_RANGE_PROF */
+	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
+	/* CFA_RESOURCE_TYPE_P45_RANGE_ENTRY */
+	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
+	/* CFA_RESOURCE_TYPE_P45_LAG */
+	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
+	/* CFA_RESOURCE_TYPE_P45_VNIC_SVIF */
+	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
+	/* CFA_RESOURCE_TYPE_P45_EM_FBK */
+	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
+	/* CFA_RESOURCE_TYPE_P45_WC_FKB */
+	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
+	/* CFA_RESOURCE_TYPE_P45_EXT */
+	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }
+};
+
+struct tf_rm_element_cfg tf_em_ext_p4[TF_EM_TBL_TYPE_MAX] = {
+	/* CFA_RESOURCE_TYPE_P45_EM_REC */
+	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
+	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_TBL_SCOPE },
+};
+
+struct tf_rm_element_cfg tf_em_int_p4[TF_EM_TBL_TYPE_MAX] = {
+	{ TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P45_EM_REC },
+	/* CFA_RESOURCE_TYPE_P45_TBL_SCOPE */
+	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
+};
+
+struct tf_if_tbl_cfg tf_if_tbl_p4[TF_IF_TBL_TYPE_MAX] = {
+	{ TF_IF_TBL_CFG, CFA_P4_TBL_PROF_SPIF_DFLT_L2CTXT },
+	{ TF_IF_TBL_CFG, CFA_P4_TBL_PROF_PARIF_DFLT_ACT_REC_PTR },
+	{ TF_IF_TBL_CFG, CFA_P4_TBL_PROF_PARIF_ERR_ACT_REC_PTR },
+	{ TF_IF_TBL_CFG, CFA_P4_TBL_LKUP_PARIF_DFLT_ACT_REC_PTR },
+	{ TF_IF_TBL_CFG_NULL, CFA_IF_TBL_TYPE_INVALID },
+	{ TF_IF_TBL_CFG_NULL, CFA_IF_TBL_TYPE_INVALID }
+};
+
+struct tf_global_cfg_cfg tf_global_cfg_p4[TF_GLOBAL_CFG_TYPE_MAX] = {
+	{ TF_GLOBAL_CFG_CFG_HCAPI, TF_TUNNEL_ENCAP },
+	{ TF_GLOBAL_CFG_CFG_HCAPI, TF_ACTION_BLOCK },
+};
 #endif /* _TF_DEVICE_P45_H_ */
-- 
2.7.4


^ permalink raw reply	[flat|nested] 32+ messages in thread

* [dpdk-dev] [PATCH 03/14] net/bnxt: changes to support 2 table scopes
  2020-10-17  6:27 [dpdk-dev] [PATCH 00/14] bnxt patches Venkat Duvvuru
  2020-10-17  6:27 ` [dpdk-dev] [PATCH 01/14] net/bnxt: device cleanup of FW Venkat Duvvuru
  2020-10-17  6:27 ` [dpdk-dev] [PATCH 02/14] net/bnxt: add stingray support Venkat Duvvuru
@ 2020-10-17  6:27 ` Venkat Duvvuru
  2020-10-17  6:27 ` [dpdk-dev] [PATCH 04/14] net/bnxt: map table scope API Venkat Duvvuru
                   ` (11 subsequent siblings)
  14 siblings, 0 replies; 32+ messages in thread
From: Venkat Duvvuru @ 2020-10-17  6:27 UTC (permalink / raw)
  To: dev; +Cc: Jay Ding

From: Jay Ding <jay.ding@broadcom.com>

This reverts commit 1312374a4e3c1851ae5e0d52cb8788c5b5e76fe0.

Signed-off-by: Jay Ding <jay.ding@broadcom.com>
Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com>
---
 drivers/net/bnxt/tf_core/tf_em_common.c | 85 +--------------------------------
 drivers/net/bnxt/tf_core/tf_em_common.h | 27 +----------
 drivers/net/bnxt/tf_core/tf_em_host.c   | 23 +++++++--
 3 files changed, 21 insertions(+), 114 deletions(-)

diff --git a/drivers/net/bnxt/tf_core/tf_em_common.c b/drivers/net/bnxt/tf_core/tf_em_common.c
index 0d8b908..0f4b121 100644
--- a/drivers/net/bnxt/tf_core/tf_em_common.c
+++ b/drivers/net/bnxt/tf_core/tf_em_common.c
@@ -44,28 +44,6 @@ static enum tf_mem_type mem_type;
 /** Table scope array */
 struct tf_tbl_scope_cb tbl_scopes[TF_NUM_TBL_SCOPE];
 
-/** Table scope reversal table
- *
- * Table scope are allocated from 15 to 0 within HCAPI RM.  Because of the
- * association between PFs and legacy table scopes, reverse table scope ids.
- * 15 indicates 0, 14 indicates 1, etc... The application will only see the 0
- * based number.  The firmware will only use the 0 based number.  Only HCAPI RM
- * and Truflow RM believe the number is 15.  When HCAPI RM support allocation
- * from low to high is supported, this adjust function can be removed.
- */
-const uint32_t tbl_scope_reverse[TF_NUM_TBL_SCOPE] = {
-	15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0 };
-
-static uint32_t
-tf_tbl_scope_adjust(uint32_t tbl_scope_id)
-{
-	if (tbl_scope_id < TF_NUM_TBL_SCOPE)
-		return tbl_scope_reverse[tbl_scope_id];
-	else
-		return TF_TBL_SCOPE_INVALID;
-};
-
-
 /* API defined in tf_em.h */
 struct tf_tbl_scope_cb *
 tbl_scope_cb_find(uint32_t tbl_scope_id)
@@ -73,17 +51,11 @@ tbl_scope_cb_find(uint32_t tbl_scope_id)
 	int i;
 	struct tf_rm_is_allocated_parms parms = { 0 };
 	int allocated;
-	uint32_t rm_tbl_scope_id;
-
-	rm_tbl_scope_id = tf_tbl_scope_adjust(tbl_scope_id);
-
-	if (rm_tbl_scope_id == TF_TBL_SCOPE_INVALID)
-		return NULL;
 
 	/* Check that id is valid */
 	parms.rm_db = eem_db[TF_DIR_RX];
 	parms.db_index = TF_EM_TBL_TYPE_TBL_SCOPE;
-	parms.index = rm_tbl_scope_id;
+	parms.index = tbl_scope_id;
 	parms.allocated = &allocated;
 
 	i = tf_rm_is_allocated(&parms);
@@ -99,61 +71,6 @@ tbl_scope_cb_find(uint32_t tbl_scope_id)
 	return NULL;
 }
 
-int tf_tbl_scope_alloc(uint32_t *tbl_scope_id)
-{
-	int rc;
-	struct tf_rm_allocate_parms parms = { 0 };
-	uint32_t rm_tbl_scope_id;
-	uint32_t usr_tbl_scope_id = TF_TBL_SCOPE_INVALID;
-
-	/* Get Table Scope control block from the session pool */
-	parms.rm_db = eem_db[TF_DIR_RX];
-	parms.db_index = TF_EM_TBL_TYPE_TBL_SCOPE;
-	parms.index = &rm_tbl_scope_id;
-
-	rc = tf_rm_allocate(&parms);
-	if (rc) {
-		TFP_DRV_LOG(ERR,
-			    "Failed to allocate table scope rc:%s\n",
-			    strerror(-rc));
-		return rc;
-	}
-
-	usr_tbl_scope_id = tf_tbl_scope_adjust(rm_tbl_scope_id);
-
-	if (usr_tbl_scope_id == TF_TBL_SCOPE_INVALID) {
-		TFP_DRV_LOG(ERR,
-			    "Invalid table scope allocated id:%d\n",
-			    (int)rm_tbl_scope_id);
-		return -EINVAL;
-	}
-	*tbl_scope_id = usr_tbl_scope_id;
-	return 0;
-};
-
-int tf_tbl_scope_free(uint32_t tbl_scope_id)
-{
-	struct tf_rm_free_parms parms = { 0 };
-	uint32_t rm_tbl_scope_id;
-	uint32_t rc;
-
-	rm_tbl_scope_id = tf_tbl_scope_adjust(tbl_scope_id);
-
-	if (rm_tbl_scope_id == TF_TBL_SCOPE_INVALID) {
-		TFP_DRV_LOG(ERR,
-			    "Invalid table scope allocated id:%d\n",
-			    (int)tbl_scope_id);
-		return -EINVAL;
-	}
-
-	parms.rm_db = eem_db[TF_DIR_RX];
-	parms.db_index = TF_EM_TBL_TYPE_TBL_SCOPE;
-	parms.index = rm_tbl_scope_id;
-
-	rc = tf_rm_free(&parms);
-	return rc;
-};
-
 int
 tf_create_tbl_pool_external(enum tf_dir dir,
 			    struct tf_tbl_scope_cb *tbl_scope_cb,
diff --git a/drivers/net/bnxt/tf_core/tf_em_common.h b/drivers/net/bnxt/tf_core/tf_em_common.h
index f71a487..fa313c4 100644
--- a/drivers/net/bnxt/tf_core/tf_em_common.h
+++ b/drivers/net/bnxt/tf_core/tf_em_common.h
@@ -9,6 +9,7 @@
 #include "tf_core.h"
 #include "tf_session.h"
 
+
 /**
  * Function to search for table scope control block structure
  * with specified table scope ID.
@@ -23,32 +24,6 @@
 struct tf_tbl_scope_cb *tbl_scope_cb_find(uint32_t tbl_scope_id);
 
 /**
- * Table Scope Allocate
- *
- * Allocate a table scope
- *
- * [in/out] pointer to tbl_scope_id
- *
- * Returns:
- *  0 - success
- *  -EINVAL - error
- */
-int tf_tbl_scope_alloc(uint32_t *tbl_scope_id);
-
-/**
- * Table Scope Free
- *
- * Free a table scope
- *
- * [in] tbl_scope_id to free
- *
- * Returns:
- *  0 - success
- *  -EINVAL - error
- */
-int tf_tbl_scope_free(uint32_t tbl_scope_id);
-
-/**
  * Create and initialize a stack to use for action entries
  *
  * [in] dir
diff --git a/drivers/net/bnxt/tf_core/tf_em_host.c b/drivers/net/bnxt/tf_core/tf_em_host.c
index cfcb12f..b5db94f 100644
--- a/drivers/net/bnxt/tf_core/tf_em_host.c
+++ b/drivers/net/bnxt/tf_core/tf_em_host.c
@@ -374,8 +374,14 @@ tf_em_ext_alloc(struct tf *tfp, struct tf_alloc_tbl_scope_parms *parms)
 	struct tf_tbl_scope_cb *tbl_scope_cb;
 	struct hcapi_cfa_em_table *em_tables;
 	struct tf_free_tbl_scope_parms free_parms;
-
-	rc = tf_tbl_scope_alloc(&parms->tbl_scope_id);
+	struct tf_rm_allocate_parms aparms = { 0 };
+	struct tf_rm_free_parms fparms = { 0 };
+
+	/* Get Table Scope control block from the session pool */
+	aparms.rm_db = eem_db[TF_DIR_RX];
+	aparms.db_index = TF_EM_TBL_TYPE_TBL_SCOPE;
+	aparms.index = (uint32_t *)&parms->tbl_scope_id;
+	rc = tf_rm_allocate(&aparms);
 	if (rc) {
 		TFP_DRV_LOG(ERR,
 			    "Failed to allocate table scope\n");
@@ -472,7 +478,11 @@ tf_em_ext_alloc(struct tf *tfp, struct tf_alloc_tbl_scope_parms *parms)
 	return -EINVAL;
 
 cleanup:
-	tf_tbl_scope_free(parms->tbl_scope_id);
+	/* Free Table control block */
+	fparms.rm_db = eem_db[TF_DIR_RX];
+	fparms.db_index = TF_EM_TBL_TYPE_TBL_SCOPE;
+	fparms.index = parms->tbl_scope_id;
+	tf_rm_free(&fparms);
 	return -EINVAL;
 }
 
@@ -483,6 +493,7 @@ tf_em_ext_free(struct tf *tfp,
 	int rc = 0;
 	enum tf_dir  dir;
 	struct tf_tbl_scope_cb *tbl_scope_cb;
+	struct tf_rm_free_parms aparms = { 0 };
 
 	tbl_scope_cb = tbl_scope_cb_find(parms->tbl_scope_id);
 
@@ -491,7 +502,11 @@ tf_em_ext_free(struct tf *tfp,
 		return -EINVAL;
 	}
 
-	rc = tf_tbl_scope_free(parms->tbl_scope_id);
+	/* Free Table control block */
+	aparms.rm_db = eem_db[TF_DIR_RX];
+	aparms.db_index = TF_EM_TBL_TYPE_TBL_SCOPE;
+	aparms.index = parms->tbl_scope_id;
+	rc = tf_rm_free(&aparms);
 	if (rc) {
 		TFP_DRV_LOG(ERR,
 			    "Failed to free table scope\n");
-- 
2.7.4


^ permalink raw reply	[flat|nested] 32+ messages in thread

* [dpdk-dev] [PATCH 04/14] net/bnxt: map table scope API
  2020-10-17  6:27 [dpdk-dev] [PATCH 00/14] bnxt patches Venkat Duvvuru
                   ` (2 preceding siblings ...)
  2020-10-17  6:27 ` [dpdk-dev] [PATCH 03/14] net/bnxt: changes to support 2 table scopes Venkat Duvvuru
@ 2020-10-17  6:27 ` Venkat Duvvuru
  2020-10-17  6:28 ` [dpdk-dev] [PATCH 05/14] net/bnxt: table scope to PF Mapping for SR and Wh+ Venkat Duvvuru
                   ` (10 subsequent siblings)
  14 siblings, 0 replies; 32+ messages in thread
From: Venkat Duvvuru @ 2020-10-17  6:27 UTC (permalink / raw)
  To: dev; +Cc: Farah Smith

From: Farah Smith <farah.smith@broadcom.com>

New API to map a PARIF to an EEM table scope (set of rx and tx EEM
base addresses).  Uses HWRM_TF_GLOBAL_CFG_SET HWRM to configure.
Adjustments to tf_global_cfg_set() to reduce overhead and nominal
name clarification.

Signed-off-by: Farah Smith <farah.smith@broadcom.com>
Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com>
---
 drivers/net/bnxt/tf_core/tf_core.c       | 54 +++++++++++++++-----
 drivers/net/bnxt/tf_core/tf_core.h       | 55 +++++++++++++++++---
 drivers/net/bnxt/tf_core/tf_device.h     | 43 +++++++++++++++-
 drivers/net/bnxt/tf_core/tf_device_p4.c  | 44 ++++++++++++++++
 drivers/net/bnxt/tf_core/tf_em.h         | 19 ++++++-
 drivers/net/bnxt/tf_core/tf_em_common.c  | 88 ++++++++++++++++++++++++++++++++
 drivers/net/bnxt/tf_core/tf_global_cfg.c |  4 +-
 drivers/net/bnxt/tf_core/tf_global_cfg.h | 42 ++++-----------
 drivers/net/bnxt/tf_core/tf_msg.c        | 13 ++++-
 drivers/net/bnxt/tf_core/tf_msg.h        |  4 +-
 10 files changed, 304 insertions(+), 62 deletions(-)

diff --git a/drivers/net/bnxt/tf_core/tf_core.c b/drivers/net/bnxt/tf_core/tf_core.c
index 788335b..0f49a00 100644
--- a/drivers/net/bnxt/tf_core/tf_core.c
+++ b/drivers/net/bnxt/tf_core/tf_core.c
@@ -303,7 +303,6 @@ int tf_get_global_cfg(struct tf *tfp,
 	int rc = 0;
 	struct tf_session *tfs;
 	struct tf_dev_info *dev;
-	struct tf_dev_global_cfg_parms gparms = { 0 };
 
 	TF_CHECK_PARMS2(tfp, parms);
 
@@ -342,12 +341,7 @@ int tf_get_global_cfg(struct tf *tfp,
 		return -EOPNOTSUPP;
 	}
 
-	gparms.dir = parms->dir;
-	gparms.type = parms->type;
-	gparms.offset = parms->offset;
-	gparms.config = parms->config;
-	gparms.config_sz_in_bytes = parms->config_sz_in_bytes;
-	rc = dev->ops->tf_dev_get_global_cfg(tfp, &gparms);
+	rc = dev->ops->tf_dev_get_global_cfg(tfp, parms);
 	if (rc) {
 		TFP_DRV_LOG(ERR,
 			    "%s: Global Cfg get failed, rc:%s\n",
@@ -371,7 +365,6 @@ int tf_set_global_cfg(struct tf *tfp,
 	int rc = 0;
 	struct tf_session *tfs;
 	struct tf_dev_info *dev;
-	struct tf_dev_global_cfg_parms gparms = { 0 };
 
 	TF_CHECK_PARMS2(tfp, parms);
 
@@ -410,12 +403,7 @@ int tf_set_global_cfg(struct tf *tfp,
 		return -EOPNOTSUPP;
 	}
 
-	gparms.dir = parms->dir;
-	gparms.type = parms->type;
-	gparms.offset = parms->offset;
-	gparms.config = parms->config;
-	gparms.config_sz_in_bytes = parms->config_sz_in_bytes;
-	rc = dev->ops->tf_dev_set_global_cfg(tfp, &gparms);
+	rc = dev->ops->tf_dev_set_global_cfg(tfp, parms);
 	if (rc) {
 		TFP_DRV_LOG(ERR,
 			    "%s: Global Cfg set failed, rc:%s\n",
@@ -1352,6 +1340,44 @@ tf_alloc_tbl_scope(struct tf *tfp,
 
 	return rc;
 }
+int
+tf_map_tbl_scope(struct tf *tfp,
+		   struct tf_map_tbl_scope_parms *parms)
+{
+	struct tf_session *tfs;
+	struct tf_dev_info *dev;
+	int rc;
+
+	TF_CHECK_PARMS2(tfp, parms);
+
+	/* Retrieve the session information */
+	rc = tf_session_get_session(tfp, &tfs);
+	if (rc) {
+		TFP_DRV_LOG(ERR,
+			    "Failed to lookup session, rc:%s\n",
+			    strerror(-rc));
+		return rc;
+	}
+
+	/* Retrieve the device information */
+	rc = tf_session_get_device(tfs, &dev);
+	if (rc) {
+		TFP_DRV_LOG(ERR,
+			    "Failed to lookup device, rc:%s\n",
+			    strerror(-rc));
+		return rc;
+	}
+
+	if (dev->ops->tf_dev_map_tbl_scope != NULL) {
+		rc = dev->ops->tf_dev_map_tbl_scope(tfp, parms);
+	} else {
+		TFP_DRV_LOG(ERR,
+			    "Map table scope not supported by device\n");
+		return -EINVAL;
+	}
+
+	return rc;
+}
 
 int
 tf_free_tbl_scope(struct tf *tfp,
diff --git a/drivers/net/bnxt/tf_core/tf_core.h b/drivers/net/bnxt/tf_core/tf_core.h
index 65be8f5..fa8ab52 100644
--- a/drivers/net/bnxt/tf_core/tf_core.h
+++ b/drivers/net/bnxt/tf_core/tf_core.h
@@ -898,7 +898,9 @@ struct tf_alloc_tbl_scope_parms {
 	 */
 	uint32_t tbl_scope_id;
 };
-
+/**
+ * tf_free_tbl_scope_parms definition
+ */
 struct tf_free_tbl_scope_parms {
 	/**
 	 * [in] table scope identifier
@@ -907,6 +909,21 @@ struct tf_free_tbl_scope_parms {
 };
 
 /**
+ * tf_map_tbl_scope_parms definition
+ */
+struct tf_map_tbl_scope_parms {
+	/**
+	 * [in] table scope identifier
+	 */
+	uint32_t tbl_scope_id;
+	/**
+	 * [in] Which parifs are associated with this table scope.  Bit 0
+	 *      indicates parif 0.
+	 */
+	uint16_t parif_bitmask;
+};
+
+/**
  * allocate a table scope
  *
  * On SR2 Firmware will allocate a scope ID.  On other devices, the scope
@@ -915,13 +932,13 @@ struct tf_free_tbl_scope_parms {
  * device constraints based upon calculations using either the number of flows
  * requested or the size of memory indicated.  Other parameters passed in
  * determine the configuration (maximum key size, maximum external action record
- * size.
+ * size).
  *
- * This API will allocate the table region in
- * DRAM, program the PTU page table entries, and program the number of static
- * buckets (if SR2) in the RX and TX CFAs.  Buckets are assumed to start at
- * 0 in the EM memory for the scope.  Upon successful completion of this API,
- * hash tables are fully initialized and ready for entries to be inserted.
+ * This API will allocate the table region in DRAM, program the PTU page table
+ * entries, and program the number of static buckets (if SR2) in the RX and TX
+ * CFAs.  Buckets are assumed to start at 0 in the EM memory for the scope.
+ * Upon successful completion of this API, hash tables are fully initialized and
+ * ready for entries to be inserted.
  *
  * A single API is used to allocate a common table scope identifier in both
  * receive and transmit CFA. The scope identifier is common due to nature of
@@ -944,7 +961,25 @@ struct tf_free_tbl_scope_parms {
 int tf_alloc_tbl_scope(struct tf *tfp,
 		       struct tf_alloc_tbl_scope_parms *parms);
 
+/**
+ * map a table scope (legacy device only Wh+/SR)
+ *
+ * Map a table scope to one or more partition interfaces (parifs).
+ * The parif can be remapped in the L2 context lookup for legacy devices.  This
+ * API allows a number of parifs to be mapped to the same table scope.  On
+ * legacy devices a table scope identifies one of 16 sets of EEM table base
+ * addresses and is associated with a PF communication channel.  The associated
+ * PF must be configured for the table scope to operate.
+ *
+ * An L2 context TCAM lookup returns a remapped parif value used to
+ * index into the set of 16 parif_to_pf registers which are used to map to one
+ * of the 16 table scopes.  This API allows the user to map the parifs in the
+ * mask to the previously allocated table scope (EEM table).
 
+ * Returns success or failure code.
+ */
+int tf_map_tbl_scope(struct tf *tfp,
+		      struct tf_map_tbl_scope_parms *parms);
 /**
  * free a table scope
  *
@@ -1909,6 +1944,12 @@ struct tf_global_cfg_parms {
 	 */
 	uint8_t *config;
 	/**
+	 * [in] Configuration mask
+	 * set - Read, Modify with mask and Write
+	 * get - unused
+	 */
+	uint8_t *config_mask;
+	/**
 	 * [in] struct containing size
 	 */
 	uint16_t config_sz_in_bytes;
diff --git a/drivers/net/bnxt/tf_core/tf_device.h b/drivers/net/bnxt/tf_core/tf_device.h
index fce7f25..cf7c36e 100644
--- a/drivers/net/bnxt/tf_core/tf_device.h
+++ b/drivers/net/bnxt/tf_core/tf_device.h
@@ -573,6 +573,45 @@ struct tf_dev_ops {
 	 */
 	int (*tf_dev_alloc_tbl_scope)(struct tf *tfp,
 				      struct tf_alloc_tbl_scope_parms *parms);
+	/**
+	 * Map EEM parif
+	 *
+	 * [in] tfp
+	 *   Pointer to TF handle
+	 *
+	 * [in] parms
+	 *   Pointer to table scope map parameters
+	 *
+	 * [in/out] pointer to the parif_2_pf data to be updated
+	 *
+	 * [in/out] pointer to the parif_2_pf mask to be updated
+	 *
+	 * [in] sz_in_bytes - number of bytes to be written
+	 *
+	 *    returns:
+	 *    0       - Success
+	 *    -EINVAL - Error
+	 */
+	int (*tf_dev_map_parif)(struct tf *tfp,
+				struct tf_map_tbl_scope_parms *parms,
+				uint8_t *data,
+				uint8_t *mask,
+				uint16_t sz_in_bytes);
+	/**
+	 * Map EEM table scope
+	 *
+	 * [in] tfp
+	 *   Pointer to TF handle
+	 *
+	 * [in] parms
+	 *   Pointer to table scope map parameters
+	 *
+	 *    returns:
+	 *    0       - Success
+	 *    -EINVAL - Error
+	 */
+	int (*tf_dev_map_tbl_scope)(struct tf *tfp,
+				    struct tf_map_tbl_scope_parms *parms);
 
 	/**
 	 * Free EEM table scope
@@ -642,7 +681,7 @@ struct tf_dev_ops {
 	 *    -EINVAL - Error
 	 */
 	int (*tf_dev_set_global_cfg)(struct tf *tfp,
-				     struct tf_dev_global_cfg_parms *parms);
+				     struct tf_global_cfg_parms *parms);
 
 	/**
 	 * Get global cfg
@@ -658,7 +697,7 @@ struct tf_dev_ops {
 	 *    -EINVAL - Error
 	 */
 	int (*tf_dev_get_global_cfg)(struct tf *tfp,
-				     struct tf_dev_global_cfg_parms *parms);
+				     struct tf_global_cfg_parms *parms);
 };
 
 /**
diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.c b/drivers/net/bnxt/tf_core/tf_device_p4.c
index 0344565..07c8d02 100644
--- a/drivers/net/bnxt/tf_core/tf_device_p4.c
+++ b/drivers/net/bnxt/tf_core/tf_device_p4.c
@@ -12,6 +12,10 @@
 #include "tf_tcam.h"
 #include "tf_em.h"
 #include "tf_if_tbl.h"
+#include "tfp.h"
+
+#define TF_DEV_P4_PARIF_MAX 16
+#define TF_DEV_P4_PF_MASK 0xfUL
 
 /**
  * Device specific function that retrieves the MAX number of HCAPI
@@ -97,6 +101,42 @@ tf_dev_p4_get_tcam_slice_info(struct tf *tfp __rte_unused,
 	return 0;
 }
 
+static int
+tf_dev_p4_map_parif(struct tf *tfp __rte_unused,
+		    struct tf_map_tbl_scope_parms *parms,
+		    uint8_t *data,
+		    uint8_t *mask,
+		    uint16_t sz_in_bytes)
+{
+	uint32_t parif_pf[2] = { 0 };
+	uint32_t parif_pf_mask[2] = { 0 };
+	uint32_t parif;
+	uint32_t shift;
+	uint32_t scope_id = (uint32_t)(parms->tbl_scope_id);
+
+	if (sz_in_bytes != sizeof(uint64_t))
+		return -ENOTSUP;
+
+	for (parif = 0; parif < TF_DEV_P4_PARIF_MAX; parif++) {
+		if (parms->parif_bitmask & (1UL << parif)) {
+			if (parif < 8) {
+				shift = 4 * parif;
+				parif_pf_mask[0] |= TF_DEV_P4_PF_MASK << shift;
+				parif_pf[0] |= scope_id << shift;
+			} else {
+				shift = 4 * (parif - 8);
+				parif_pf_mask[1] |= TF_DEV_P4_PF_MASK << shift;
+				parif_pf[1] |= scope_id << shift;
+			}
+		}
+	}
+	tfp_memcpy(data, parif_pf, sz_in_bytes);
+	tfp_memcpy(mask, parif_pf_mask, sz_in_bytes);
+
+	return 0;
+}
+
+
 /**
  * Truflow P4 device specific functions
  */
@@ -125,6 +165,8 @@ const struct tf_dev_ops tf_dev_ops_p4_init = {
 	.tf_dev_insert_ext_em_entry = NULL,
 	.tf_dev_delete_ext_em_entry = NULL,
 	.tf_dev_alloc_tbl_scope = NULL,
+	.tf_dev_map_tbl_scope = NULL,
+	.tf_dev_map_parif = NULL,
 	.tf_dev_free_tbl_scope = NULL,
 	.tf_dev_set_if_tbl = NULL,
 	.tf_dev_get_if_tbl = NULL,
@@ -160,6 +202,8 @@ const struct tf_dev_ops tf_dev_ops_p4 = {
 	.tf_dev_insert_ext_em_entry = tf_em_insert_ext_entry,
 	.tf_dev_delete_ext_em_entry = tf_em_delete_ext_entry,
 	.tf_dev_alloc_tbl_scope = tf_em_ext_common_alloc,
+	.tf_dev_map_tbl_scope = tf_em_ext_map_tbl_scope,
+	.tf_dev_map_parif = tf_dev_p4_map_parif,
 	.tf_dev_free_tbl_scope = tf_em_ext_common_free,
 	.tf_dev_set_if_tbl = tf_if_tbl_set,
 	.tf_dev_get_if_tbl = tf_if_tbl_get,
diff --git a/drivers/net/bnxt/tf_core/tf_em.h b/drivers/net/bnxt/tf_core/tf_em.h
index 51b0813..8820b28 100644
--- a/drivers/net/bnxt/tf_core/tf_em.h
+++ b/drivers/net/bnxt/tf_core/tf_em.h
@@ -358,7 +358,7 @@ int tf_em_ext_free(struct tf *tfp,
 		   struct tf_free_tbl_scope_parms *parms);
 
 /**
- * Common free for external EEM using host or system memory
+ * Common free table scope for external EEM using host or system memory
  *
  * [in] tfp
  *   Pointer to TruFlow handle
@@ -374,7 +374,7 @@ int tf_em_ext_common_free(struct tf *tfp,
 			  struct tf_free_tbl_scope_parms *parms);
 
 /**
- * Common alloc for external EEM using host or system memory
+ * Common alloc table scope for external EEM using host or system memory
  *
  * [in] tfp
  *   Pointer to TruFlow handle
@@ -388,6 +388,21 @@ int tf_em_ext_common_free(struct tf *tfp,
  */
 int tf_em_ext_common_alloc(struct tf *tfp,
 			   struct tf_alloc_tbl_scope_parms *parms);
+/**
+ * Map a set of parifs to a set of EEM base addresses (table scope)
+ *
+ * [in] tfp
+ *   Pointer to TruFlow handle
+ *
+ * [in] parms
+ *   Pointer to input parameters
+ *
+ * Returns:
+ *   0       - Success
+ *   -EINVAL - Parameter error
+ */
+int tf_em_ext_map_tbl_scope(struct tf *tfp,
+			    struct tf_map_tbl_scope_parms *parms);
 
 /**
  * Allocate External Tbl entry from the scope pool.
diff --git a/drivers/net/bnxt/tf_core/tf_em_common.c b/drivers/net/bnxt/tf_core/tf_em_common.c
index 0f4b121..c4f3de0 100644
--- a/drivers/net/bnxt/tf_core/tf_em_common.c
+++ b/drivers/net/bnxt/tf_core/tf_em_common.c
@@ -1046,3 +1046,91 @@ tf_em_ext_common_free(struct tf *tfp,
 {
 	return tf_em_ext_free(tfp, parms);
 }
+
+int tf_em_ext_map_tbl_scope(struct tf *tfp,
+			    struct tf_map_tbl_scope_parms *parms)
+{
+	int rc = 0;
+	struct tf_session *tfs;
+	struct tf_tbl_scope_cb *tbl_scope_cb;
+	struct tf_global_cfg_parms gcfg_parms = { 0 };
+	struct tfp_calloc_parms aparms;
+	uint32_t *data, *mask;
+	uint32_t sz_in_bytes = 8;
+	struct tf_dev_info *dev;
+
+	tbl_scope_cb = tbl_scope_cb_find(parms->tbl_scope_id);
+
+	if (tbl_scope_cb == NULL) {
+		TFP_DRV_LOG(ERR, "Invalid tbl_scope_cb tbl_scope_id(%d)\n",
+			    parms->tbl_scope_id);
+		return -EINVAL;
+	}
+
+	/* Retrieve the session information */
+	rc = tf_session_get_session_internal(tfp, &tfs);
+	if (rc)
+		return rc;
+
+	/* Retrieve the device information */
+	rc = tf_session_get_device(tfs, &dev);
+	if (rc)
+		return rc;
+
+	if (dev->ops->tf_dev_map_tbl_scope == NULL) {
+		rc = -EOPNOTSUPP;
+		TFP_DRV_LOG(ERR,
+			    "Map table scope operation not supported, rc:%s\n",
+			    strerror(-rc));
+		return rc;
+	}
+
+	aparms.nitems = 2;
+	aparms.size = sizeof(uint32_t);
+	aparms.alignment = 0;
+
+	if (tfp_calloc(&aparms) != 0) {
+		TFP_DRV_LOG(ERR, "Map tbl scope alloc data error %s\n",
+			    strerror(ENOMEM));
+		return -ENOMEM;
+	}
+	data = aparms.mem_va;
+
+	if (tfp_calloc(&aparms) != 0) {
+		TFP_DRV_LOG(ERR, "Map tbl scope alloc mask error %s\n",
+			    strerror(ENOMEM));
+		rc = -ENOMEM;
+		goto clean;
+	}
+	mask = aparms.mem_va;
+
+	rc = dev->ops->tf_dev_map_parif(tfp, parms, (uint8_t *)data,
+					(uint8_t *)mask, sz_in_bytes);
+
+	if (rc) {
+		TFP_DRV_LOG(ERR,
+			    "Map table scope config failure, rc:%s\n",
+			    strerror(-rc));
+		goto cleaner;
+	}
+
+	gcfg_parms.type = TF_GLOBAL_CFG_INTERNAL_PARIF_2_PF;
+	gcfg_parms.offset = 0;
+	gcfg_parms.config = (uint8_t *)data;
+	gcfg_parms.config_mask = (uint8_t *)mask;
+	gcfg_parms.config_sz_in_bytes = sizeof(uint64_t);
+
+
+	rc = tf_msg_set_global_cfg(tfp, &gcfg_parms);
+	if (rc) {
+		TFP_DRV_LOG(ERR,
+			    "Map tbl scope, set failed, rc:%s\n",
+			    strerror(-rc));
+	}
+cleaner:
+	tfp_free(mask);
+clean:
+	tfp_free(data);
+
+	return rc;
+}
diff --git a/drivers/net/bnxt/tf_core/tf_global_cfg.c b/drivers/net/bnxt/tf_core/tf_global_cfg.c
index 4ed4039..ebd1a86 100644
--- a/drivers/net/bnxt/tf_core/tf_global_cfg.c
+++ b/drivers/net/bnxt/tf_core/tf_global_cfg.c
@@ -113,7 +113,7 @@ tf_global_cfg_unbind(struct tf *tfp __rte_unused)
 
 int
 tf_global_cfg_set(struct tf *tfp,
-		  struct tf_dev_global_cfg_parms *parms)
+		  struct tf_global_cfg_parms *parms)
 {
 	int rc;
 	struct tf_global_cfg_get_hcapi_parms hparms;
@@ -156,7 +156,7 @@ tf_global_cfg_set(struct tf *tfp,
 
 int
 tf_global_cfg_get(struct tf *tfp,
-		  struct tf_dev_global_cfg_parms *parms)
+		  struct tf_global_cfg_parms *parms)
 
 {
 	int rc;
diff --git a/drivers/net/bnxt/tf_core/tf_global_cfg.h b/drivers/net/bnxt/tf_core/tf_global_cfg.h
index 5c73bb1..685f38d 100644
--- a/drivers/net/bnxt/tf_core/tf_global_cfg.h
+++ b/drivers/net/bnxt/tf_core/tf_global_cfg.h
@@ -13,7 +13,15 @@
  * The global cfg module provides processing of global cfg types.
  */
 
-struct tf;
+/* struct tf; */
+
+/* Internal type not available to user
+ * but available internally within Truflow
+ */
+enum tf_global_config_internal_type {
+	TF_GLOBAL_CFG_INTERNAL_PARIF_2_PF = TF_GLOBAL_CFG_TYPE_MAX,
+	TF_GLOBAL_CFG_INTERNAL_TYPE_MAX
+};
 
 /**
  * Global cfg configuration enumeration.
@@ -62,34 +70,6 @@ struct tf_global_cfg_cfg_parms {
 };
 
 /**
- * global cfg parameters
- */
-struct tf_dev_global_cfg_parms {
-	/**
-	 * [in] Receive or transmit direction
-	 */
-	enum tf_dir dir;
-	/**
-	 * [in] Global config type
-	 */
-	enum tf_global_config_type type;
-	/**
-	 * [in] Offset @ the type
-	 */
-	uint32_t offset;
-	/**
-	 * [in/out] Value of the configuration
-	 * set - Read, Modify and Write
-	 * get - Read the full configuration
-	 */
-	uint8_t *config;
-	/**
-	 * [in] struct containing size
-	 */
-	uint16_t config_sz_in_bytes;
-};
-
-/**
  * @page global cfg
  *
  * @ref tf_global_cfg_bind
@@ -149,7 +129,7 @@ tf_global_cfg_unbind(struct tf *tfp);
  *   - (-EINVAL) on failure.
  */
 int tf_global_cfg_set(struct tf *tfp,
-		      struct tf_dev_global_cfg_parms *parms);
+		      struct tf_global_cfg_parms *parms);
 
 /**
  * Get global configuration
@@ -165,6 +145,6 @@ int tf_global_cfg_set(struct tf *tfp,
  *   - (-EINVAL) on failure.
  */
 int tf_global_cfg_get(struct tf *tfp,
-		      struct tf_dev_global_cfg_parms *parms);
+		      struct tf_global_cfg_parms *parms);
 
 #endif /* TF_GLOBAL_CFG_H */
diff --git a/drivers/net/bnxt/tf_core/tf_msg.c b/drivers/net/bnxt/tf_core/tf_msg.c
index 7c2ad17..5615eed 100644
--- a/drivers/net/bnxt/tf_core/tf_msg.c
+++ b/drivers/net/bnxt/tf_core/tf_msg.c
@@ -1075,7 +1075,7 @@ tf_msg_get_tbl_entry(struct tf *tfp,
 
 int
 tf_msg_get_global_cfg(struct tf *tfp,
-		      struct tf_dev_global_cfg_parms *params)
+		      struct tf_global_cfg_parms *params)
 {
 	int rc = 0;
 	struct tfp_send_msg_parms parms = { 0 };
@@ -1133,7 +1133,7 @@ tf_msg_get_global_cfg(struct tf *tfp,
 
 int
 tf_msg_set_global_cfg(struct tf *tfp,
-		      struct tf_dev_global_cfg_parms *params)
+		      struct tf_global_cfg_parms *params)
 {
 	int rc = 0;
 	struct tfp_send_msg_parms parms = { 0 };
@@ -1173,6 +1173,15 @@ tf_msg_set_global_cfg(struct tf *tfp,
 
 	tfp_memcpy(req.data, params->config,
 		   params->config_sz_in_bytes);
+
+	/* Only set mask if pointer is provided
+	 */
+	if (params->config_mask) {
+		tfp_memcpy(req.data + params->config_sz_in_bytes,
+			   params->config_mask,
+			   params->config_sz_in_bytes);
+	}
+
 	req.size = tfp_cpu_to_le_32(params->config_sz_in_bytes);
 
 	parms.tf_type = HWRM_TF_GLOBAL_CFG_SET;
diff --git a/drivers/net/bnxt/tf_core/tf_msg.h b/drivers/net/bnxt/tf_core/tf_msg.h
index 195710e..72bf850 100644
--- a/drivers/net/bnxt/tf_core/tf_msg.h
+++ b/drivers/net/bnxt/tf_core/tf_msg.h
@@ -462,7 +462,7 @@ int tf_msg_get_tbl_entry(struct tf *tfp,
  *   0 on Success else internal Truflow error
  */
 int tf_msg_get_global_cfg(struct tf *tfp,
-			  struct tf_dev_global_cfg_parms *params);
+			  struct tf_global_cfg_parms *params);
 
 /**
  * Sends global cfg update request to Firmware
@@ -477,7 +477,7 @@ int tf_msg_get_global_cfg(struct tf *tfp,
  *   0 on Success else internal Truflow error
  */
 int tf_msg_set_global_cfg(struct tf *tfp,
-			  struct tf_dev_global_cfg_parms *params);
+			  struct tf_global_cfg_parms *params);
 
 /**
  * Sends bulk get message of a Table Type element to the firmware.
-- 
2.7.4


^ permalink raw reply	[flat|nested] 32+ messages in thread

* [dpdk-dev] [PATCH 05/14] net/bnxt: table scope to PF Mapping for SR and Wh+
  2020-10-17  6:27 [dpdk-dev] [PATCH 00/14] bnxt patches Venkat Duvvuru
                   ` (3 preceding siblings ...)
  2020-10-17  6:27 ` [dpdk-dev] [PATCH 04/14] net/bnxt: map table scope API Venkat Duvvuru
@ 2020-10-17  6:28 ` Venkat Duvvuru
  2020-10-17  6:28 ` [dpdk-dev] [PATCH 06/14] net/bnxt: add build option for EM slot allocation Venkat Duvvuru
                   ` (9 subsequent siblings)
  14 siblings, 0 replies; 32+ messages in thread
From: Venkat Duvvuru @ 2020-10-17  6:28 UTC (permalink / raw)
  To: dev; +Cc: Farah Smith

From: Farah Smith <farah.smith@broadcom.com>

Legacy devices require PF set of base addresses for EEM operation.
A table scope id is a logical construct and is mapped to the PF
associated with the communications channel used.
In the case of a VF, the parent PF is used.

Signed-off-by: Farah Smith <farah.smith@broadcom.com>
Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com>
---
 drivers/net/bnxt/tf_core/tf_device.h    | 10 +++++++---
 drivers/net/bnxt/tf_core/tf_device_p4.c | 10 +++++-----
 drivers/net/bnxt/tf_core/tf_em_common.c |  6 ++++--
 drivers/net/bnxt/tf_core/tf_em_host.c   |  8 ++++++++
 drivers/net/bnxt/tf_core/tf_tbl.h       |  3 +++
 drivers/net/bnxt/tf_core/tfp.c          | 19 +++++++++++++++++++
 drivers/net/bnxt/tf_core/tfp.h          | 16 ++++++++++++++++
 7 files changed, 62 insertions(+), 10 deletions(-)

diff --git a/drivers/net/bnxt/tf_core/tf_device.h b/drivers/net/bnxt/tf_core/tf_device.h
index cf7c36e..b5fc695 100644
--- a/drivers/net/bnxt/tf_core/tf_device.h
+++ b/drivers/net/bnxt/tf_core/tf_device.h
@@ -579,8 +579,11 @@ struct tf_dev_ops {
 	 * [in] tfp
 	 *   Pointer to TF handle
 	 *
-	 * [in] parms
-	 *   Pointer to table scope map parameters
+	 * [in] pf
+	 * PF associated with the table scope
+	 *
+	 * [in] parif_bitmask
+	 * Bitmask of PARIFs to enable
 	 *
 	 * [in/out] pointer to the parif_2_pf data to be updated
 	 *
@@ -593,7 +596,8 @@ struct tf_dev_ops {
 	 *    -EINVAL - Error
 	 */
 	int (*tf_dev_map_parif)(struct tf *tfp,
-				struct tf_map_tbl_scope_parms *parms,
+				uint16_t parif_bitmask,
+				uint16_t pf,
 				uint8_t *data,
 				uint8_t *mask,
 				uint16_t sz_in_bytes);
diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.c b/drivers/net/bnxt/tf_core/tf_device_p4.c
index 07c8d02..b35e65a 100644
--- a/drivers/net/bnxt/tf_core/tf_device_p4.c
+++ b/drivers/net/bnxt/tf_core/tf_device_p4.c
@@ -103,7 +103,8 @@ tf_dev_p4_get_tcam_slice_info(struct tf *tfp __rte_unused,
 
 static int
 tf_dev_p4_map_parif(struct tf *tfp __rte_unused,
-		    struct tf_map_tbl_scope_parms *parms,
+		    uint16_t parif_bitmask,
+		    uint16_t pf,
 		    uint8_t *data,
 		    uint8_t *mask,
 		    uint16_t sz_in_bytes)
@@ -112,21 +113,20 @@ tf_dev_p4_map_parif(struct tf *tfp __rte_unused,
 	uint32_t parif_pf_mask[2] = { 0 };
 	uint32_t parif;
 	uint32_t shift;
-	uint32_t scope_id = (uint32_t)(parms->tbl_scope_id);
 
 	if (sz_in_bytes != sizeof(uint64_t))
 		return -ENOTSUP;
 
 	for (parif = 0; parif < TF_DEV_P4_PARIF_MAX; parif++) {
-		if (parms->parif_bitmask & (1UL << parif)) {
+		if (parif_bitmask & (1UL << parif)) {
 			if (parif < 8) {
 				shift = 4 * parif;
 				parif_pf_mask[0] |= TF_DEV_P4_PF_MASK << shift;
-				parif_pf[0] |= scope_id << shift;
+				parif_pf[0] |= pf << shift;
 			} else {
 				shift = 4 * (parif - 8);
 				parif_pf_mask[1] |= TF_DEV_P4_PF_MASK << shift;
-				parif_pf[1] |= scope_id << shift;
+				parif_pf[1] |= pf << shift;
 			}
 		}
 	}
diff --git a/drivers/net/bnxt/tf_core/tf_em_common.c b/drivers/net/bnxt/tf_core/tf_em_common.c
index c4f3de0..c975bca 100644
--- a/drivers/net/bnxt/tf_core/tf_em_common.c
+++ b/drivers/net/bnxt/tf_core/tf_em_common.c
@@ -1104,8 +1104,10 @@ int tf_em_ext_map_tbl_scope(struct tf *tfp,
 	}
 	mask = aparms.mem_va;
 
-	rc = dev->ops->tf_dev_map_parif(tfp, parms, (uint8_t *)data,
-					(uint8_t *)mask, sz_in_bytes);
+	rc = dev->ops->tf_dev_map_parif(tfp, parms->parif_bitmask,
+					tbl_scope_cb->pf,
+					(uint8_t *)data, (uint8_t *)mask,
+					sz_in_bytes);
 
 	if (rc) {
 		TFP_DRV_LOG(ERR,
diff --git a/drivers/net/bnxt/tf_core/tf_em_host.c b/drivers/net/bnxt/tf_core/tf_em_host.c
index b5db94f..a106bdf 100644
--- a/drivers/net/bnxt/tf_core/tf_em_host.c
+++ b/drivers/net/bnxt/tf_core/tf_em_host.c
@@ -392,6 +392,14 @@ tf_em_ext_alloc(struct tf *tfp, struct tf_alloc_tbl_scope_parms *parms)
 	tbl_scope_cb->index = parms->tbl_scope_id;
 	tbl_scope_cb->tbl_scope_id = parms->tbl_scope_id;
 
+	rc = tfp_get_pf(tfp, &tbl_scope_cb->pf);
+	if (rc) {
+		TFP_DRV_LOG(ERR,
+			    "EEM: PF query error rc:%s\n",
+			    strerror(-rc));
+		goto cleanup;
+	}
+
 	for (dir = 0; dir < TF_DIR_MAX; dir++) {
 		rc = tf_msg_em_qcaps(tfp,
 				     dir,
diff --git a/drivers/net/bnxt/tf_core/tf_tbl.h b/drivers/net/bnxt/tf_core/tf_tbl.h
index 2a5d24c..230338c 100644
--- a/drivers/net/bnxt/tf_core/tf_tbl.h
+++ b/drivers/net/bnxt/tf_core/tf_tbl.h
@@ -38,6 +38,9 @@ struct tf_em_caps {
  */
 struct tf_tbl_scope_cb {
 	uint32_t tbl_scope_id;
+       /** The pf or parent pf of the vf used for table scope creation
+	*/
+	uint16_t pf;
 	int index;
 	struct hcapi_cfa_em_ctx_mem_info em_ctx_info[TF_DIR_MAX];
 	struct tf_em_caps em_caps[TF_DIR_MAX];
diff --git a/drivers/net/bnxt/tf_core/tfp.c b/drivers/net/bnxt/tf_core/tfp.c
index 426a182..0f6d63c 100644
--- a/drivers/net/bnxt/tf_core/tfp.c
+++ b/drivers/net/bnxt/tf_core/tfp.c
@@ -178,3 +178,22 @@ tfp_get_fid(struct tf *tfp, uint16_t *fw_fid)
 
 	return 0;
 }
+
+int
+tfp_get_pf(struct tf *tfp, uint16_t *pf)
+{
+	struct bnxt *bp = NULL;
+
+	if (tfp == NULL || pf == NULL)
+		return -EINVAL;
+
+	bp = container_of(tfp, struct bnxt, tfp);
+	if (BNXT_VF(bp) && bp->parent) {
+		*pf = bp->parent->fid - 1;
+		return 0;
+	} else if (BNXT_PF(bp)) {
+		*pf = bp->fw_fid - 1;
+		return 0;
+	}
+	return -EINVAL;
+}
diff --git a/drivers/net/bnxt/tf_core/tfp.h b/drivers/net/bnxt/tf_core/tfp.h
index 421a7d9..551b9c5 100644
--- a/drivers/net/bnxt/tf_core/tfp.h
+++ b/drivers/net/bnxt/tf_core/tfp.h
@@ -268,4 +268,20 @@ int tfp_get_fid(struct tf *tfp, uint16_t *fw_fid);
  */
 int tfp_get_fid(struct tf *tfp, uint16_t *fw_fid);
 
+/**
+ * Get the PF associated with the fw communications channel.
+ *
+ * [in] session
+ *   Pointer to session handle
+ *
+ * [out] pf
+ *   Pointer to the pf id
+ *
+ * Returns:
+ *   0       - Success
+ *   -EINVAL - Failure
+ *
+ */
+int tfp_get_pf(struct tf *tfp, uint16_t *pf);
+
 #endif /* _TFP_H_ */
-- 
2.7.4


^ permalink raw reply	[flat|nested] 32+ messages in thread

* [dpdk-dev] [PATCH 06/14] net/bnxt: add build option for EM slot allocation
  2020-10-17  6:27 [dpdk-dev] [PATCH 00/14] bnxt patches Venkat Duvvuru
                   ` (4 preceding siblings ...)
  2020-10-17  6:28 ` [dpdk-dev] [PATCH 05/14] net/bnxt: table scope to PF Mapping for SR and Wh+ Venkat Duvvuru
@ 2020-10-17  6:28 ` Venkat Duvvuru
  2020-10-17  6:28 ` [dpdk-dev] [PATCH 07/14] net/bnxt: update SR ULP resource counts Venkat Duvvuru
                   ` (8 subsequent siblings)
  14 siblings, 0 replies; 32+ messages in thread
From: Venkat Duvvuru @ 2020-10-17  6:28 UTC (permalink / raw)
  To: dev; +Cc: Peter Spreadborough

From: Peter Spreadborough <peter.spreadborough@broadcom.com>

- Add build option to select either 2 or 4 slot EM entries.
- The default is 4 slot entries.

Signed-off-by: Peter Spreadborough <peter.spreadborough@broadcom.com>
Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com>
---
 drivers/net/bnxt/tf_core/tf_session.h | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/net/bnxt/tf_core/tf_session.h b/drivers/net/bnxt/tf_core/tf_session.h
index aa7a278..6a5c894 100644
--- a/drivers/net/bnxt/tf_core/tf_session.h
+++ b/drivers/net/bnxt/tf_core/tf_session.h
@@ -33,16 +33,16 @@
 #define TF_SESSION_ID_INVALID     0xFFFFFFFF /** Invalid Session ID define */
 
 /**
- * Number of EM entries. Static for now will be removed
- * when parameter added at a later date. At this stage we
- * are using fixed size entries so that each stack entry
- * represents 4 RT (f/n)blocks. So we take the total block
- * allocation for truflow and divide that by 4.
+ * At this stage we are using fixed size entries so that each
+ * stack entry represents either 2 or 4 RT (f/n)blocks. So we
+ * take the total block allocation for truflow and divide that
+ * by either 2 or 4.
  */
-#define TF_SESSION_TOTAL_FN_BLOCKS (1024 * 8) /* 8K blocks */
+#ifdef TF_EM_ENTRY_IPV4_ONLY
+#define TF_SESSION_EM_ENTRY_SIZE 2 /* 2 blocks per entry */
+#else
 #define TF_SESSION_EM_ENTRY_SIZE 4 /* 4 blocks per entry */
-#define TF_SESSION_EM_POOL_SIZE \
-	(TF_SESSION_TOTAL_FN_BLOCKS / TF_SESSION_EM_ENTRY_SIZE)
+#endif
 
 /**
  * Session
-- 
2.7.4


^ permalink raw reply	[flat|nested] 32+ messages in thread

* [dpdk-dev] [PATCH 07/14] net/bnxt: update SR ULP resource counts
  2020-10-17  6:27 [dpdk-dev] [PATCH 00/14] bnxt patches Venkat Duvvuru
                   ` (5 preceding siblings ...)
  2020-10-17  6:28 ` [dpdk-dev] [PATCH 06/14] net/bnxt: add build option for EM slot allocation Venkat Duvvuru
@ 2020-10-17  6:28 ` Venkat Duvvuru
  2020-10-17  6:28 ` [dpdk-dev] [PATCH 08/14] net/bnxt: fix infinite loop in flow query count API Venkat Duvvuru
                   ` (7 subsequent siblings)
  14 siblings, 0 replies; 32+ messages in thread
From: Venkat Duvvuru @ 2020-10-17  6:28 UTC (permalink / raw)
  To: dev; +Cc: Farah Smith

From: Farah Smith <farah.smith@broadcom.com>

Updated the SR ULP requested resource counts to reflect
those available after AFM resources are accounted for.

Signed-off-by: Farah Smith <farah.smith@broadcom.com>
Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com>
---
 drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 40 +++++++++++++++++++-------------------
 1 file changed, 20 insertions(+), 20 deletions(-)

diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
index b22929a..d753b5a 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
@@ -153,11 +153,11 @@ bnxt_ulp_tf_session_resources_get(struct bnxt *bp,
 	case BNXT_ULP_DEVICE_ID_STINGRAY:
 		/** RX **/
 		/* Identifiers */
-		res->ident_cnt[TF_DIR_RX].cnt[TF_IDENT_TYPE_L2_CTXT_HIGH] = 100;
+		res->ident_cnt[TF_DIR_RX].cnt[TF_IDENT_TYPE_L2_CTXT_HIGH] = 315;
 		res->ident_cnt[TF_DIR_RX].cnt[TF_IDENT_TYPE_L2_CTXT_LOW] = 6;
-		res->ident_cnt[TF_DIR_RX].cnt[TF_IDENT_TYPE_WC_PROF] = 10;
-		res->ident_cnt[TF_DIR_RX].cnt[TF_IDENT_TYPE_PROF_FUNC] = 10;
-		res->ident_cnt[TF_DIR_RX].cnt[TF_IDENT_TYPE_EM_PROF] = 10;
+		res->ident_cnt[TF_DIR_RX].cnt[TF_IDENT_TYPE_WC_PROF] = 192;
+		res->ident_cnt[TF_DIR_RX].cnt[TF_IDENT_TYPE_PROF_FUNC] = 64;
+		res->ident_cnt[TF_DIR_RX].cnt[TF_IDENT_TYPE_EM_PROF] = 192;
 
 		/* Table Types */
 		res->tbl_cnt[TF_DIR_RX].cnt[TF_TBL_TYPE_FULL_ACT_RECORD] = 8192;
@@ -170,28 +170,28 @@ bnxt_ulp_tf_session_resources_get(struct bnxt *bp,
 
 		/* TCAMs */
 		res->tcam_cnt[TF_DIR_RX].cnt[TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH] =
-			100;
+			315;
 		res->tcam_cnt[TF_DIR_RX].cnt[TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW] =
 			6;
-		res->tcam_cnt[TF_DIR_RX].cnt[TF_TCAM_TBL_TYPE_PROF_TCAM] = 100;
-		res->tcam_cnt[TF_DIR_RX].cnt[TF_TCAM_TBL_TYPE_WC_TCAM] = 0;
+		res->tcam_cnt[TF_DIR_RX].cnt[TF_TCAM_TBL_TYPE_PROF_TCAM] = 960;
+		res->tcam_cnt[TF_DIR_RX].cnt[TF_TCAM_TBL_TYPE_WC_TCAM] = 112;
 
 		/* EM */
-		res->em_cnt[TF_DIR_RX].cnt[TF_EM_TBL_TYPE_EM_RECORD] = 13168;
+		res->em_cnt[TF_DIR_RX].cnt[TF_EM_TBL_TYPE_EM_RECORD] = 13200;
 
 		/* EEM */
 		res->em_cnt[TF_DIR_RX].cnt[TF_EM_TBL_TYPE_TBL_SCOPE] = 1;
 
 		/* SP */
-		res->tbl_cnt[TF_DIR_RX].cnt[TF_TBL_TYPE_ACT_SP_SMAC] = 255;
+		res->tbl_cnt[TF_DIR_RX].cnt[TF_TBL_TYPE_ACT_SP_SMAC] = 256;
 
 		/** TX **/
 		/* Identifiers */
-		res->ident_cnt[TF_DIR_TX].cnt[TF_IDENT_TYPE_L2_CTXT_HIGH] = 100;
-		res->ident_cnt[TF_DIR_TX].cnt[TF_IDENT_TYPE_L2_CTXT_LOW] = 100;
-		res->ident_cnt[TF_DIR_TX].cnt[TF_IDENT_TYPE_WC_PROF] = 10;
-		res->ident_cnt[TF_DIR_TX].cnt[TF_IDENT_TYPE_PROF_FUNC] = 10;
-		res->ident_cnt[TF_DIR_TX].cnt[TF_IDENT_TYPE_EM_PROF] = 10;
+		res->ident_cnt[TF_DIR_TX].cnt[TF_IDENT_TYPE_L2_CTXT_HIGH] = 292;
+		res->ident_cnt[TF_DIR_TX].cnt[TF_IDENT_TYPE_L2_CTXT_LOW] = 127;
+		res->ident_cnt[TF_DIR_TX].cnt[TF_IDENT_TYPE_WC_PROF] = 192;
+		res->ident_cnt[TF_DIR_TX].cnt[TF_IDENT_TYPE_PROF_FUNC] = 64;
+		res->ident_cnt[TF_DIR_TX].cnt[TF_IDENT_TYPE_EM_PROF] = 192;
 
 		/* Table Types */
 		res->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_FULL_ACT_RECORD] = 8192;
@@ -199,17 +199,17 @@ bnxt_ulp_tf_session_resources_get(struct bnxt *bp,
 		res->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_ACT_MODIFY_IPV4] = 1023;
 
 		/* ENCAP */
-		res->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_ACT_ENCAP_64B] = 511;
+		res->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_ACT_ENCAP_64B] = 367;
 		res->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_ACT_ENCAP_16B] = 223;
 		res->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_ACT_ENCAP_8B] = 255;
 
 		/* TCAMs */
 		res->tcam_cnt[TF_DIR_TX].cnt[TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH] =
-			100;
+			292;
 		res->tcam_cnt[TF_DIR_TX].cnt[TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW] =
-			100;
-		res->tcam_cnt[TF_DIR_TX].cnt[TF_TCAM_TBL_TYPE_PROF_TCAM] = 100;
-		res->tcam_cnt[TF_DIR_TX].cnt[TF_TCAM_TBL_TYPE_WC_TCAM] = 0;
+			127;
+		res->tcam_cnt[TF_DIR_TX].cnt[TF_TCAM_TBL_TYPE_PROF_TCAM] = 960;
+		res->tcam_cnt[TF_DIR_TX].cnt[TF_TCAM_TBL_TYPE_WC_TCAM] = 928;
 
 		/* EM */
 		res->em_cnt[TF_DIR_TX].cnt[TF_EM_TBL_TYPE_EM_RECORD] = 15232;
@@ -219,7 +219,7 @@ bnxt_ulp_tf_session_resources_get(struct bnxt *bp,
 
 		/* SP */
 		res->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = 488;
-		res->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = 511;
+		res->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = 512;
 		break;
 	default:
 		return -EINVAL;
-- 
2.7.4


^ permalink raw reply	[flat|nested] 32+ messages in thread

* [dpdk-dev] [PATCH 08/14] net/bnxt: fix infinite loop in flow query count API
  2020-10-17  6:27 [dpdk-dev] [PATCH 00/14] bnxt patches Venkat Duvvuru
                   ` (6 preceding siblings ...)
  2020-10-17  6:28 ` [dpdk-dev] [PATCH 07/14] net/bnxt: update SR ULP resource counts Venkat Duvvuru
@ 2020-10-17  6:28 ` Venkat Duvvuru
  2020-10-17  6:28 ` [dpdk-dev] [PATCH 09/14] net/bnxt: add support for parent flow accumulation counters Venkat Duvvuru
                   ` (6 subsequent siblings)
  14 siblings, 0 replies; 32+ messages in thread
From: Venkat Duvvuru @ 2020-10-17  6:28 UTC (permalink / raw)
  To: dev; +Cc: Somnath Kotur

From: Somnath Kotur <somnath.kotur@broadcom.com>

`nxt_resource_idx` could be zero in some cases which is invalid and
should be part of the while loop condition. Also synchronize access to
the flow db using the fdb_lock

Fixes: 306c2d28e247 ("net/bnxt: support count action in flow query")

Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
Reviewed-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
Reviewed-by: Ajit Kumar Khaparde <ajit.khaparde@broadcom.com>
---
 drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c | 51 +++++++++++++++++++-----------------
 1 file changed, 27 insertions(+), 24 deletions(-)

diff --git a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c
index 051ebac..41736a8 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c
@@ -559,6 +559,9 @@ int ulp_fc_mgr_query_count_get(struct bnxt_ulp_context *ctxt,
 	if (!ulp_fc_info)
 		return -ENODEV;
 
+	if (bnxt_ulp_cntxt_acquire_fdb_lock(ctxt))
+		return -EIO;
+
 	do {
 		rc = ulp_flow_db_resource_get(ctxt,
 					      BNXT_ULP_FDB_TYPE_REGULAR,
@@ -575,35 +578,35 @@ int ulp_fc_mgr_query_count_get(struct bnxt_ulp_context *ctxt,
 			break;
 		}
 
-	} while (!rc);
+	} while (!rc && nxt_resource_index);
+
+	bnxt_ulp_cntxt_release_fdb_lock(ctxt);
 
-	if (rc)
+	if (rc || !found_cntr_resource)
 		return rc;
 
-	if (found_cntr_resource) {
-		dir = params.direction;
-		hw_cntr_id = params.resource_hndl;
-		sw_cntr_idx = hw_cntr_id -
-				ulp_fc_info->shadow_hw_tbl[dir].start_idx;
-		sw_acc_tbl_entry = &ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx];
-		if (params.resource_sub_type ==
+	dir = params.direction;
+	hw_cntr_id = params.resource_hndl;
+	sw_cntr_idx = hw_cntr_id -
+		ulp_fc_info->shadow_hw_tbl[dir].start_idx;
+	sw_acc_tbl_entry = &ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx];
+	if (params.resource_sub_type ==
 			BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT) {
-			pthread_mutex_lock(&ulp_fc_info->fc_lock);
-			if (sw_acc_tbl_entry->pkt_count) {
-				count->hits_set = 1;
-				count->bytes_set = 1;
-				count->hits = sw_acc_tbl_entry->pkt_count;
-				count->bytes = sw_acc_tbl_entry->byte_count;
-			}
-			if (count->reset) {
-				sw_acc_tbl_entry->pkt_count = 0;
-				sw_acc_tbl_entry->byte_count = 0;
-			}
-			pthread_mutex_unlock(&ulp_fc_info->fc_lock);
-		} else {
-			/* TBD: Handle External counters */
-			rc = -EINVAL;
+		pthread_mutex_lock(&ulp_fc_info->fc_lock);
+		if (sw_acc_tbl_entry->pkt_count) {
+			count->hits_set = 1;
+			count->bytes_set = 1;
+			count->hits = sw_acc_tbl_entry->pkt_count;
+			count->bytes = sw_acc_tbl_entry->byte_count;
 		}
+		if (count->reset) {
+			sw_acc_tbl_entry->pkt_count = 0;
+			sw_acc_tbl_entry->byte_count = 0;
+		}
+		pthread_mutex_unlock(&ulp_fc_info->fc_lock);
+	} else {
+		/* TBD: Handle External counters */
+		rc = -EINVAL;
 	}
 
 	return rc;
-- 
2.7.4


^ permalink raw reply	[flat|nested] 32+ messages in thread

* [dpdk-dev] [PATCH 09/14] net/bnxt: add support for parent flow accumulation counters
  2020-10-17  6:27 [dpdk-dev] [PATCH 00/14] bnxt patches Venkat Duvvuru
                   ` (7 preceding siblings ...)
  2020-10-17  6:28 ` [dpdk-dev] [PATCH 08/14] net/bnxt: fix infinite loop in flow query count API Venkat Duvvuru
@ 2020-10-17  6:28 ` Venkat Duvvuru
  2020-10-17  6:28 ` [dpdk-dev] [PATCH 10/14] net/bnxt: use cfa pair alloc for configuring reps Venkat Duvvuru
                   ` (5 subsequent siblings)
  14 siblings, 0 replies; 32+ messages in thread
From: Venkat Duvvuru @ 2020-10-17  6:28 UTC (permalink / raw)
  To: dev; +Cc: Kishore Padmanabha

From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>

Added support for parent flow accumulation counters, the child flow
counters are aggregated to get the parent flow counter details.

Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Shahaji Bhosle <shahaji.bhosle@broadcom.com>
---
 drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c           |  92 +++++-
 drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h           |  19 ++
 drivers/net/bnxt/tf_ulp/ulp_flow_db.c          | 382 ++++++++++++++++++++-----
 drivers/net/bnxt/tf_ulp/ulp_flow_db.h          |  44 +++
 drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h |   3 +-
 5 files changed, 447 insertions(+), 93 deletions(-)

diff --git a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c
index 41736a8..734b419 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c
@@ -21,13 +21,13 @@ static int
 ulp_fc_mgr_shadow_mem_alloc(struct hw_fc_mem_info *parms, int size)
 {
 	/* Allocate memory*/
-	if (parms == NULL)
+	if (!parms)
 		return -EINVAL;
 
 	parms->mem_va = rte_zmalloc("ulp_fc_info",
 				    RTE_CACHE_LINE_ROUNDUP(size),
 				    4096);
-	if (parms->mem_va == NULL) {
+	if (!parms->mem_va) {
 		BNXT_TF_DBG(ERR, "Allocate failed mem_va\n");
 		return -ENOMEM;
 	}
@@ -149,7 +149,6 @@ ulp_fc_mgr_deinit(struct bnxt_ulp_context *ctxt)
 	for (i = 0; i < TF_DIR_MAX; i++)
 		ulp_fc_mgr_shadow_mem_free(&ulp_fc_info->shadow_hw_tbl[i]);
 
-
 	rte_free(ulp_fc_info);
 
 	/* Safe to ignore on deinit */
@@ -254,7 +253,7 @@ ulp_bulk_get_flow_stats(struct tf *tfp,
 	stats = (uint64_t *)fc_info->shadow_hw_tbl[dir].mem_va;
 	parms.physical_mem_addr = (uintptr_t)fc_info->shadow_hw_tbl[dir].mem_pa;
 
-	if (stats == NULL) {
+	if (!stats) {
 		PMD_DRV_LOG(ERR,
 			    "BULK: Memory not initialized id:0x%x dir:%d\n",
 			    parms.starting_idx, dir);
@@ -274,7 +273,8 @@ ulp_bulk_get_flow_stats(struct tf *tfp,
 		sw_acc_tbl_entry = &fc_info->sw_acc_tbl[dir][i];
 		if (!sw_acc_tbl_entry->valid)
 			continue;
-		sw_acc_tbl_entry->pkt_count += FLOW_CNTR_PKTS(stats[i], dparms);
+		sw_acc_tbl_entry->pkt_count += FLOW_CNTR_PKTS(stats[i],
+							      dparms);
 		sw_acc_tbl_entry->byte_count += FLOW_CNTR_BYTES(stats[i],
 								dparms);
 	}
@@ -282,7 +282,8 @@ ulp_bulk_get_flow_stats(struct tf *tfp,
 	return rc;
 }
 
-static int ulp_get_single_flow_stat(struct tf *tfp,
+static int ulp_get_single_flow_stat(struct bnxt_ulp_context *ctxt,
+				    struct tf *tfp,
 				    struct bnxt_ulp_fc_info *fc_info,
 				    enum tf_dir dir,
 				    uint32_t hw_cntr_id,
@@ -291,7 +292,7 @@ static int ulp_get_single_flow_stat(struct tf *tfp,
 	int rc = 0;
 	struct tf_get_tbl_entry_parms parms = { 0 };
 	enum tf_tbl_type stype = TF_TBL_TYPE_ACT_STATS_64;  /* TBD:Template? */
-	struct sw_acc_counter *sw_acc_tbl_entry = NULL;
+	struct sw_acc_counter *sw_acc_tbl_entry = NULL, *t_sw;
 	uint64_t stats = 0;
 	uint32_t sw_cntr_indx = 0;
 
@@ -318,6 +319,18 @@ static int ulp_get_single_flow_stat(struct tf *tfp,
 	sw_acc_tbl_entry->pkt_count = FLOW_CNTR_PKTS(stats, dparms);
 	sw_acc_tbl_entry->byte_count = FLOW_CNTR_BYTES(stats, dparms);
 
+	/* Update the parent counters if it is child flow */
+	if (sw_acc_tbl_entry->parent_flow_id) {
+		/* Update the parent counters */
+		t_sw = sw_acc_tbl_entry;
+		if (ulp_flow_db_parent_flow_count_update(ctxt,
+							 t_sw->parent_flow_id,
+							 t_sw->pkt_count,
+							 t_sw->byte_count)) {
+			PMD_DRV_LOG(ERR, "Error updating parent counters\n");
+		}
+	}
+
 	return rc;
 }
 
@@ -384,13 +397,17 @@ ulp_fc_mgr_alarm_cb(void *arg)
 			break;
 	}
 	*/
+
+	/* reset the parent accumulation counters before accumulation if any */
+	ulp_flow_db_parent_flow_count_reset(ctxt);
+
 	num_entries = dparms->flow_count_db_entries / 2;
 	for (i = 0; i < TF_DIR_MAX; i++) {
 		for (j = 0; j < num_entries; j++) {
 			if (!ulp_fc_info->sw_acc_tbl[i][j].valid)
 				continue;
 			hw_cntr_id = ulp_fc_info->sw_acc_tbl[i][j].hw_cntr_id;
-			rc = ulp_get_single_flow_stat(tfp, ulp_fc_info, i,
+			rc = ulp_get_single_flow_stat(ctxt, tfp, ulp_fc_info, i,
 						      hw_cntr_id, dparms);
 			if (rc)
 				break;
@@ -573,11 +590,12 @@ int ulp_fc_mgr_query_count_get(struct bnxt_ulp_context *ctxt,
 		     (params.resource_sub_type ==
 		      BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT ||
 		      params.resource_sub_type ==
-		      BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_EXT_COUNT)) {
+		      BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_EXT_COUNT ||
+		      params.resource_sub_type ==
+		      BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT_ACC)) {
 			found_cntr_resource = true;
 			break;
 		}
-
 	} while (!rc && nxt_resource_index);
 
 	bnxt_ulp_cntxt_release_fdb_lock(ctxt);
@@ -587,12 +605,12 @@ int ulp_fc_mgr_query_count_get(struct bnxt_ulp_context *ctxt,
 
 	dir = params.direction;
 	hw_cntr_id = params.resource_hndl;
-	sw_cntr_idx = hw_cntr_id -
-		ulp_fc_info->shadow_hw_tbl[dir].start_idx;
-	sw_acc_tbl_entry = &ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx];
 	if (params.resource_sub_type ==
 			BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT) {
 		pthread_mutex_lock(&ulp_fc_info->fc_lock);
+		sw_cntr_idx = hw_cntr_id -
+			ulp_fc_info->shadow_hw_tbl[dir].start_idx;
+		sw_acc_tbl_entry = &ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx];
 		if (sw_acc_tbl_entry->pkt_count) {
 			count->hits_set = 1;
 			count->bytes_set = 1;
@@ -604,6 +622,15 @@ int ulp_fc_mgr_query_count_get(struct bnxt_ulp_context *ctxt,
 			sw_acc_tbl_entry->byte_count = 0;
 		}
 		pthread_mutex_unlock(&ulp_fc_info->fc_lock);
+	} else if (params.resource_sub_type ==
+			BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT_ACC) {
+		/* Get the stats from the parent child table */
+		ulp_flow_db_parent_flow_count_get(ctxt,
+						  flow_id,
+						  &count->hits,
+						  &count->bytes);
+		count->hits_set = 1;
+		count->bytes_set = 1;
 	} else {
 		/* TBD: Handle External counters */
 		rc = -EINVAL;
@@ -611,3 +638,42 @@ int ulp_fc_mgr_query_count_get(struct bnxt_ulp_context *ctxt,
 
 	return rc;
 }
+
+/*
+ * Set the parent flow if it is SW accumulation counter entry.
+ *
+ * ctxt [in] The ulp context for the flow counter manager
+ *
+ * dir [in] The direction of the flow
+ *
+ * hw_cntr_id [in] The HW flow counter ID
+ *
+ * fid [in] parent flow id
+ *
+ */
+int32_t ulp_fc_mgr_cntr_parent_flow_set(struct bnxt_ulp_context *ctxt,
+					enum tf_dir dir,
+					uint32_t hw_cntr_id,
+					uint32_t fid)
+{
+	struct bnxt_ulp_fc_info *ulp_fc_info;
+	uint32_t sw_cntr_idx;
+	int32_t rc = 0;
+
+	ulp_fc_info = bnxt_ulp_cntxt_ptr2_fc_info_get(ctxt);
+	if (!ulp_fc_info)
+		return -EIO;
+
+	pthread_mutex_lock(&ulp_fc_info->fc_lock);
+	sw_cntr_idx = hw_cntr_id - ulp_fc_info->shadow_hw_tbl[dir].start_idx;
+	if (ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].valid) {
+		ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].parent_flow_id = fid;
+	} else {
+		BNXT_TF_DBG(ERR, "Failed to set parent flow id %x:%x\n",
+			    hw_cntr_id, fid);
+		rc = -ENOENT;
+	}
+	pthread_mutex_unlock(&ulp_fc_info->fc_lock);
+
+	return rc;
+}
diff --git a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h
index 0cb880d..de4d3df 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h
@@ -26,6 +26,7 @@ struct sw_acc_counter {
 	uint64_t byte_count;
 	bool	valid;
 	uint32_t hw_cntr_id;
+	uint32_t parent_flow_id;
 };
 
 struct hw_fc_mem_info {
@@ -163,4 +164,22 @@ bool ulp_fc_mgr_thread_isstarted(struct bnxt_ulp_context *ctxt);
 int ulp_fc_mgr_query_count_get(struct bnxt_ulp_context *ulp_ctx,
 			       uint32_t flow_id,
 			       struct rte_flow_query_count *count);
+
+/*
+ * Set the parent flow if in the SW accumulator table entry
+ *
+ * ctxt [in] The ulp context for the flow counter manager
+ *
+ * dir [in] The direction of the flow
+ *
+ * hw_cntr_id [in] The HW flow counter ID
+ *
+ * fid [in] parent flow id
+ *
+ */
+int32_t ulp_fc_mgr_cntr_parent_flow_set(struct bnxt_ulp_context *ctxt,
+					enum tf_dir dir,
+					uint32_t hw_cntr_id,
+					uint32_t fid);
+
 #endif /* _ULP_FC_MGR_H_ */
diff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c
index 3be7489..8780c01 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c
@@ -1058,12 +1058,12 @@ ulp_flow_db_validate_flow_func(struct bnxt_ulp_context *ulp_ctx,
  * the first match.
  */
 static int32_t
-ulp_flow_db_resource_hndl_get(struct bnxt_ulp_context *ulp_ctx,
-			      enum bnxt_ulp_fdb_type flow_type,
-			      uint32_t flow_id,
-			      uint32_t resource_func,
-			      uint32_t res_subtype,
-			      uint64_t *res_hndl)
+ulp_flow_db_resource_params_get(struct bnxt_ulp_context *ulp_ctx,
+				enum bnxt_ulp_fdb_type flow_type,
+				uint32_t flow_id,
+				uint32_t resource_func,
+				uint32_t res_subtype,
+				struct ulp_flow_db_res_params *params)
 {
 	struct bnxt_ulp_flow_db *flow_db;
 	struct bnxt_ulp_flow_tbl *flow_tbl;
@@ -1076,6 +1076,11 @@ ulp_flow_db_resource_hndl_get(struct bnxt_ulp_context *ulp_ctx,
 		return -EINVAL;
 	}
 
+	if (!params) {
+		BNXT_TF_DBG(ERR, "invalid argument\n");
+		return -EINVAL;
+	}
+
 	if (flow_type > BNXT_ULP_FDB_TYPE_DEFAULT) {
 		BNXT_TF_DBG(ERR, "Invalid flow type\n");
 		return -EINVAL;
@@ -1096,12 +1101,14 @@ ulp_flow_db_resource_hndl_get(struct bnxt_ulp_context *ulp_ctx,
 	}
 	/* Iterate the resource to get the resource handle */
 	res_id =  flow_id;
+	memset(params, 0, sizeof(struct ulp_flow_db_res_params));
 	while (res_id) {
 		fid_res = &flow_tbl->flow_resources[res_id];
 		if (ulp_flow_db_resource_func_get(fid_res) == resource_func) {
 			if (resource_func & ULP_FLOW_DB_RES_FUNC_NEED_LOWER) {
 				if (res_subtype == fid_res->resource_sub_type) {
-					*res_hndl = fid_res->resource_hndl;
+					ulp_flow_db_res_info_to_params(fid_res,
+								       params);
 					return 0;
 				}
 
@@ -1109,7 +1116,8 @@ ulp_flow_db_resource_hndl_get(struct bnxt_ulp_context *ulp_ctx,
 				   BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE ||
 				   resource_func ==
 				   BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE) {
-				*res_hndl = fid_res->resource_em_handle;
+				ulp_flow_db_res_info_to_params(fid_res,
+							       params);
 				return 0;
 			}
 		}
@@ -1134,23 +1142,51 @@ ulp_default_flow_db_cfa_action_get(struct bnxt_ulp_context *ulp_ctx,
 				   uint16_t *cfa_action)
 {
 	uint8_t sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_VFR_CFA_ACTION;
-	uint64_t hndl;
+	struct ulp_flow_db_res_params params;
 	int32_t rc;
 
-	rc = ulp_flow_db_resource_hndl_get(ulp_ctx,
-					   BNXT_ULP_FDB_TYPE_DEFAULT,
-					   flow_id,
-					   BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
-					   sub_type, &hndl);
+	rc = ulp_flow_db_resource_params_get(ulp_ctx,
+					     BNXT_ULP_FDB_TYPE_DEFAULT,
+					     flow_id,
+					     BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+					     sub_type, &params);
 	if (rc) {
 		BNXT_TF_DBG(ERR, "CFA Action ptr not found for flow id %u\n",
 			    flow_id);
 		return -ENOENT;
 	}
-	*cfa_action = hndl;
+	*cfa_action = params.resource_hndl;
 	return 0;
 }
 
+/* internal validation function for parent flow tbl */
+static struct bnxt_ulp_flow_db *
+ulp_flow_db_parent_arg_validation(struct bnxt_ulp_context *ulp_ctxt,
+				  uint32_t fid)
+{
+	struct bnxt_ulp_flow_db *flow_db;
+
+	flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);
+	if (!flow_db) {
+		BNXT_TF_DBG(ERR, "Invalid Arguments\n");
+		return NULL;
+	}
+
+	/* check for max flows */
+	if (fid >= flow_db->flow_tbl.num_flows || !fid) {
+		BNXT_TF_DBG(ERR, "Invalid flow index\n");
+		return NULL;
+	}
+
+	/* No support for parent child db then just exit */
+	if (!flow_db->parent_child_db.entries_count) {
+		BNXT_TF_DBG(ERR, "parent child db not supported\n");
+		return NULL;
+	}
+
+	return flow_db;
+}
+
 /*
  * Allocate the entry in the parent-child database
  *
@@ -1167,26 +1203,15 @@ ulp_flow_db_parent_flow_alloc(struct bnxt_ulp_context *ulp_ctxt,
 	struct ulp_fdb_parent_child_db *p_pdb;
 	uint32_t idx, free_idx = 0;
 
-	flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);
+	/* validate the arguments */
+	flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, fid);
 	if (!flow_db) {
-		BNXT_TF_DBG(ERR, "Invalid Arguments\n");
-		return -EINVAL;
-	}
-
-	/* check for max flows */
-	if (fid >= flow_db->flow_tbl.num_flows || !fid) {
-		BNXT_TF_DBG(ERR, "Invalid flow index\n");
-		return -EINVAL;
-	}
-
-	/* No support for parent child db then just exit */
-	if (!flow_db->parent_child_db.entries_count) {
-		BNXT_TF_DBG(ERR, "parent child db not supported\n");
+		BNXT_TF_DBG(ERR, "parent child db validation failed\n");
 		return -EINVAL;
 	}
 
 	p_pdb = &flow_db->parent_child_db;
-	for (idx = 0; idx <= p_pdb->entries_count; idx++) {
+	for (idx = 0; idx < p_pdb->entries_count; idx++) {
 		if (p_pdb->parent_flow_tbl[idx].parent_fid == fid) {
 			BNXT_TF_DBG(ERR, "fid is already allocated\n");
 			return -EINVAL;
@@ -1222,26 +1247,15 @@ ulp_flow_db_parent_flow_free(struct bnxt_ulp_context *ulp_ctxt,
 	struct ulp_fdb_parent_child_db *p_pdb;
 	uint32_t idx;
 
-	flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);
+	/* validate the arguments */
+	flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, fid);
 	if (!flow_db) {
-		BNXT_TF_DBG(ERR, "Invalid Arguments\n");
-		return -EINVAL;
-	}
-
-	/* check for max flows */
-	if (fid >= flow_db->flow_tbl.num_flows || !fid) {
-		BNXT_TF_DBG(ERR, "Invalid flow index\n");
-		return -EINVAL;
-	}
-
-	/* No support for parent child db then just exit */
-	if (!flow_db->parent_child_db.entries_count) {
-		BNXT_TF_DBG(ERR, "parent child db not supported\n");
+		BNXT_TF_DBG(ERR, "parent child db validation failed\n");
 		return -EINVAL;
 	}
 
 	p_pdb = &flow_db->parent_child_db;
-	for (idx = 0; idx <= p_pdb->entries_count; idx++) {
+	for (idx = 0; idx < p_pdb->entries_count; idx++) {
 		if (p_pdb->parent_flow_tbl[idx].parent_fid == fid) {
 			/* free the contents */
 			p_pdb->parent_flow_tbl[idx].parent_fid = 0;
@@ -1275,15 +1289,10 @@ ulp_flow_db_parent_child_flow_set(struct bnxt_ulp_context *ulp_ctxt,
 	uint32_t idx, a_idx;
 	uint64_t *t;
 
-	flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);
+	/* validate the arguments */
+	flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, parent_fid);
 	if (!flow_db) {
-		BNXT_TF_DBG(ERR, "Invalid Arguments\n");
-		return -EINVAL;
-	}
-
-	/* check for fid validity */
-	if (parent_fid >= flow_db->flow_tbl.num_flows || !parent_fid) {
-		BNXT_TF_DBG(ERR, "Invalid parent flow index %x\n", parent_fid);
+		BNXT_TF_DBG(ERR, "parent child db validation failed\n");
 		return -EINVAL;
 	}
 
@@ -1293,15 +1302,9 @@ ulp_flow_db_parent_child_flow_set(struct bnxt_ulp_context *ulp_ctxt,
 		return -EINVAL;
 	}
 
-	/* No support for parent child db then just exit */
-	if (!flow_db->parent_child_db.entries_count) {
-		BNXT_TF_DBG(ERR, "parent child db not supported\n");
-		return -EINVAL;
-	}
-
 	p_pdb = &flow_db->parent_child_db;
 	a_idx = child_fid / ULP_INDEX_BITMAP_SIZE;
-	for (idx = 0; idx <= p_pdb->entries_count; idx++) {
+	for (idx = 0; idx < p_pdb->entries_count; idx++) {
 		if (p_pdb->parent_flow_tbl[idx].parent_fid == parent_fid) {
 			t = p_pdb->parent_flow_tbl[idx].child_fid_bitset;
 			if (set_flag)
@@ -1334,26 +1337,15 @@ ulp_flow_db_parent_flow_idx_get(struct bnxt_ulp_context *ulp_ctxt,
 	struct ulp_fdb_parent_child_db *p_pdb;
 	uint32_t idx;
 
-	flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);
+	/* validate the arguments */
+	flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, parent_fid);
 	if (!flow_db) {
-		BNXT_TF_DBG(ERR, "Invalid Arguments\n");
-		return -EINVAL;
-	}
-
-	/* check for fid validity */
-	if (parent_fid >= flow_db->flow_tbl.num_flows || !parent_fid) {
-		BNXT_TF_DBG(ERR, "Invalid parent flow index %x\n", parent_fid);
-		return -EINVAL;
-	}
-
-	/* No support for parent child db then just exit */
-	if (!flow_db->parent_child_db.entries_count) {
-		BNXT_TF_DBG(ERR, "parent child db not supported\n");
+		BNXT_TF_DBG(ERR, "parent child db validation failed\n");
 		return -EINVAL;
 	}
 
 	p_pdb = &flow_db->parent_child_db;
-	for (idx = 0; idx <= p_pdb->entries_count; idx++) {
+	for (idx = 0; idx < p_pdb->entries_count; idx++) {
 		if (p_pdb->parent_flow_tbl[idx].parent_fid == parent_fid) {
 			*parent_idx = idx;
 			return 0;
@@ -1426,6 +1418,73 @@ ulp_flow_db_parent_child_flow_next_entry_get(struct bnxt_ulp_flow_db *flow_db,
 }
 
 /*
+ * Set the counter accumulation in the parent flow
+ *
+ * ulp_ctxt [in] Ptr to ulp_context
+ * parent_idx [in] The parent index of the parent flow entry
+ *
+ * returns index on success and negative on failure.
+ */
+static int32_t
+ulp_flow_db_parent_flow_count_accum_set(struct bnxt_ulp_context *ulp_ctxt,
+					uint32_t parent_idx)
+{
+	struct bnxt_ulp_flow_db *flow_db;
+	struct ulp_fdb_parent_child_db *p_pdb;
+
+	flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);
+	if (!flow_db) {
+		BNXT_TF_DBG(ERR, "Invalid Arguments\n");
+		return -EINVAL;
+	}
+
+	/* check for parent idx validity */
+	p_pdb = &flow_db->parent_child_db;
+	if (parent_idx >= p_pdb->entries_count ||
+	    !p_pdb->parent_flow_tbl[parent_idx].parent_fid) {
+		BNXT_TF_DBG(ERR, "Invalid parent flow index %x\n", parent_idx);
+		return -EINVAL;
+	}
+
+	p_pdb->parent_flow_tbl[parent_idx].counter_acc = 1;
+	return 0;
+}
+
+/*
+ * Get the counter accumulation in the parent flow
+ *
+ * ulp_ctxt [in] Ptr to ulp_context
+ * parent_fid [in] The flow id of the parent flow entry
+ *
+ * returns 0 if counter accum is set else -1.
+ */
+static int32_t
+ulp_flow_db_parent_flow_count_accum_get(struct bnxt_ulp_context *ulp_ctxt,
+					uint32_t parent_fid)
+{
+	struct bnxt_ulp_flow_db *flow_db;
+	struct ulp_fdb_parent_child_db *p_pdb;
+	uint32_t idx;
+
+	/* validate the arguments */
+	flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, parent_fid);
+	if (!flow_db) {
+		BNXT_TF_DBG(ERR, "parent child db validation failed\n");
+		return -EINVAL;
+	}
+
+	p_pdb = &flow_db->parent_child_db;
+	for (idx = 0; idx < p_pdb->entries_count; idx++) {
+		if (p_pdb->parent_flow_tbl[idx].parent_fid == parent_fid) {
+			if (p_pdb->parent_flow_tbl[idx].counter_acc)
+				return 0;
+			break;
+		}
+	}
+	return -1;
+}
+
+/*
  * Orphan the child flow entry
  * This is called only for child flows that have
  * BNXT_ULP_RESOURCE_FUNC_CHILD_FLOW resource
@@ -1498,6 +1557,8 @@ int32_t
 ulp_flow_db_parent_flow_create(struct bnxt_ulp_mapper_parms *parms)
 {
 	struct ulp_flow_db_res_params fid_parms;
+	uint32_t sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT_ACC;
+	struct ulp_flow_db_res_params res_params;
 	int32_t fid_idx;
 
 	/* create the child flow entry in parent flow table */
@@ -1519,6 +1580,22 @@ ulp_flow_db_parent_flow_create(struct bnxt_ulp_mapper_parms *parms)
 			    parms->fid);
 		return -1;
 	}
+
+	/* check of the flow has internal counter accumulation enabled */
+	if (!ulp_flow_db_resource_params_get(parms->ulp_ctx,
+					     BNXT_ULP_FDB_TYPE_REGULAR,
+					     parms->fid,
+					     BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+					     sub_type,
+					     &res_params)) {
+		/* Enable the counter accumulation in parent entry */
+		if (ulp_flow_db_parent_flow_count_accum_set(parms->ulp_ctx,
+							    fid_idx)) {
+			BNXT_TF_DBG(ERR, "Error in setting counter acc %x\n",
+				    parms->fid);
+			return -1;
+		}
+	}
 	return 0;
 }
 
@@ -1533,6 +1610,10 @@ int32_t
 ulp_flow_db_child_flow_create(struct bnxt_ulp_mapper_parms *parms)
 {
 	struct ulp_flow_db_res_params fid_parms;
+	uint32_t sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT;
+	enum bnxt_ulp_resource_func res_fun;
+	struct ulp_flow_db_res_params res_p;
+	uint32_t parent_fid = parms->parent_fid;
 	int32_t rc;
 
 	/* create the parent flow entry in parent flow table */
@@ -1541,7 +1622,7 @@ ulp_flow_db_child_flow_create(struct bnxt_ulp_mapper_parms *parms)
 					       parms->fid, 1);
 	if (rc) {
 		BNXT_TF_DBG(ERR, "Error in setting child fid %x\n", parms->fid);
-		return -1;
+		return rc;
 	}
 
 	/* Add the parent details in the resource list of the flow */
@@ -1549,11 +1630,154 @@ ulp_flow_db_child_flow_create(struct bnxt_ulp_mapper_parms *parms)
 	fid_parms.resource_func	= BNXT_ULP_RESOURCE_FUNC_CHILD_FLOW;
 	fid_parms.resource_hndl	= parms->parent_fid;
 	fid_parms.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO;
-	if (ulp_flow_db_resource_add(parms->ulp_ctx, BNXT_ULP_FDB_TYPE_REGULAR,
-				     parms->fid, &fid_parms)) {
+	rc  = ulp_flow_db_resource_add(parms->ulp_ctx,
+				       BNXT_ULP_FDB_TYPE_REGULAR,
+				       parms->fid, &fid_parms);
+	if (rc) {
 		BNXT_TF_DBG(ERR, "Error in adding flow res for fid %x\n",
 			    parms->fid);
-		return -1;
+		return rc;
+	}
+
+	/* check if accumulation count is set for parent flow */
+	rc = ulp_flow_db_parent_flow_count_accum_get(parms->ulp_ctx,
+						     parms->parent_fid);
+	if (!rc) {
+		/* check if internal count action included for this flow.*/
+		res_fun = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE;
+		rc = ulp_flow_db_resource_params_get(parms->ulp_ctx,
+						     BNXT_ULP_FDB_TYPE_REGULAR,
+						     parms->fid,
+						     res_fun,
+						     sub_type,
+						     &res_p);
+		if (!rc) {
+			/* update the counter manager to include parent fid */
+			if (ulp_fc_mgr_cntr_parent_flow_set(parms->ulp_ctx,
+							    res_p.direction,
+							    res_p.resource_hndl,
+							    parent_fid)) {
+				BNXT_TF_DBG(ERR, "Error in setting child %x\n",
+					    parms->fid);
+				return -1;
+			}
+		}
 	}
+	/* return success */
 	return 0;
 }
+
+/*
+ * Update the parent counters
+ *
+ * ulp_ctxt [in] Ptr to ulp_context
+ * parent_fid [in] The flow id of the parent flow entry
+ * packet_count [in] - packet count
+ * byte_count [in] - byte count
+ *
+ * returns 0 on success
+ */
+int32_t
+ulp_flow_db_parent_flow_count_update(struct bnxt_ulp_context *ulp_ctxt,
+				     uint32_t parent_fid,
+				     uint64_t packet_count,
+				     uint64_t byte_count)
+{
+	struct bnxt_ulp_flow_db *flow_db;
+	struct ulp_fdb_parent_child_db *p_pdb;
+	uint32_t idx;
+
+	/* validate the arguments */
+	flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, parent_fid);
+	if (!flow_db) {
+		BNXT_TF_DBG(ERR, "parent child db validation failed\n");
+		return -EINVAL;
+	}
+
+	p_pdb = &flow_db->parent_child_db;
+	for (idx = 0; idx < p_pdb->entries_count; idx++) {
+		if (p_pdb->parent_flow_tbl[idx].parent_fid == parent_fid) {
+			if (p_pdb->parent_flow_tbl[idx].counter_acc) {
+				p_pdb->parent_flow_tbl[idx].pkt_count +=
+					packet_count;
+				p_pdb->parent_flow_tbl[idx].byte_count +=
+					byte_count;
+			}
+			return 0;
+		}
+	}
+	return -ENOENT;
+}
+
+/*
+ * Get the parent accumulation counters
+ *
+ * ulp_ctxt [in] Ptr to ulp_context
+ * parent_fid [in] The flow id of the parent flow entry
+ * packet_count [out] - packet count
+ * byte_count [out] - byte count
+ *
+ * returns 0 on success
+ */
+int32_t
+ulp_flow_db_parent_flow_count_get(struct bnxt_ulp_context *ulp_ctxt,
+				  uint32_t parent_fid,
+				  uint64_t *packet_count,
+				  uint64_t *byte_count)
+{
+	struct bnxt_ulp_flow_db *flow_db;
+	struct ulp_fdb_parent_child_db *p_pdb;
+	uint32_t idx;
+
+	/* validate the arguments */
+	flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, parent_fid);
+	if (!flow_db) {
+		BNXT_TF_DBG(ERR, "parent child db validation failed\n");
+		return -EINVAL;
+	}
+
+	p_pdb = &flow_db->parent_child_db;
+	for (idx = 0; idx < p_pdb->entries_count; idx++) {
+		if (p_pdb->parent_flow_tbl[idx].parent_fid == parent_fid) {
+			if (p_pdb->parent_flow_tbl[idx].counter_acc) {
+				*packet_count =
+					p_pdb->parent_flow_tbl[idx].pkt_count;
+				*byte_count =
+					p_pdb->parent_flow_tbl[idx].byte_count;
+			}
+			return 0;
+		}
+	}
+	return -ENOENT;
+}
+
+/*
+ * reset the parent accumulation counters
+ *
+ * ulp_ctxt [in] Ptr to ulp_context
+ *
+ * returns none
+ */
+void
+ulp_flow_db_parent_flow_count_reset(struct bnxt_ulp_context *ulp_ctxt)
+{
+	struct bnxt_ulp_flow_db *flow_db;
+	struct ulp_fdb_parent_child_db *p_pdb;
+	uint32_t idx;
+
+	/* validate the arguments */
+	flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, 1);
+	if (!flow_db) {
+		BNXT_TF_DBG(ERR, "parent child db validation failed\n");
+		return;
+	}
+
+	p_pdb = &flow_db->parent_child_db;
+	for (idx = 0; idx < p_pdb->entries_count; idx++) {
+		if (p_pdb->parent_flow_tbl[idx].parent_fid &&
+		    p_pdb->parent_flow_tbl[idx].counter_acc) {
+			p_pdb->parent_flow_tbl[idx].pkt_count = 0;
+			p_pdb->parent_flow_tbl[idx].byte_count = 0;
+		}
+	}
+}
diff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.h b/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
index 95fd199..10e69ba 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
@@ -56,6 +56,9 @@ struct bnxt_ulp_flow_tbl {
 /* Structure to maintain parent-child flow relationships */
 struct ulp_fdb_parent_info {
 	uint32_t	parent_fid;
+	uint32_t	counter_acc;
+	uint64_t	pkt_count;
+	uint64_t	byte_count;
 	uint64_t	*child_fid_bitset;
 };
 
@@ -356,4 +359,45 @@ ulp_flow_db_parent_flow_create(struct bnxt_ulp_mapper_parms *parms);
 int32_t
 ulp_flow_db_child_flow_create(struct bnxt_ulp_mapper_parms *parms);
 
+/*
+ * Update the parent counters
+ *
+ * ulp_ctxt [in] Ptr to ulp_context
+ * parent_fid [in] The flow id of the parent flow entry
+ * packet_count [in] - packet count
+ * byte_count [in] - byte count
+ *
+ * returns 0 on success
+ */
+int32_t
+ulp_flow_db_parent_flow_count_update(struct bnxt_ulp_context *ulp_ctxt,
+				     uint32_t parent_fid,
+				     uint64_t packet_count,
+				     uint64_t byte_count);
+/*
+ * Get the parent accumulation counters
+ *
+ * ulp_ctxt [in] Ptr to ulp_context
+ * parent_fid [in] The flow id of the parent flow entry
+ * packet_count [out] - packet count
+ * byte_count [out] - byte count
+ *
+ * returns 0 on success
+ */
+int32_t
+ulp_flow_db_parent_flow_count_get(struct bnxt_ulp_context *ulp_ctxt,
+				  uint32_t parent_fid,
+				  uint64_t *packet_count,
+				  uint64_t *byte_count);
+
+/*
+ * reset the parent accumulation counters
+ *
+ * ulp_ctxt [in] Ptr to ulp_context
+ *
+ * returns none
+ */
+void
+ulp_flow_db_parent_flow_count_reset(struct bnxt_ulp_context *ulp_ctxt);
+
 #endif /* _ULP_FLOW_DB_H_ */
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
index 168e308..6dade9a 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
@@ -332,7 +332,8 @@ enum bnxt_ulp_resource_sub_type {
 	BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL = 0,
 	BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_VFR_CFA_ACTION = 1,
 	BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT = 2,
-	BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_EXT_COUNT = 3,
+	BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT_ACC = 3,
+	BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_EXT_COUNT = 4,
 	BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM = 0,
 	BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM = 1
 };
-- 
2.7.4


^ permalink raw reply	[flat|nested] 32+ messages in thread

* [dpdk-dev] [PATCH 10/14] net/bnxt: use cfa pair alloc for configuring reps
  2020-10-17  6:27 [dpdk-dev] [PATCH 00/14] bnxt patches Venkat Duvvuru
                   ` (8 preceding siblings ...)
  2020-10-17  6:28 ` [dpdk-dev] [PATCH 09/14] net/bnxt: add support for parent flow accumulation counters Venkat Duvvuru
@ 2020-10-17  6:28 ` Venkat Duvvuru
  2020-10-17  6:28 ` [dpdk-dev] [PATCH 11/14] net/bnxt: add mapper support for wildcard TCAM entry Venkat Duvvuru
                   ` (4 subsequent siblings)
  14 siblings, 0 replies; 32+ messages in thread
From: Venkat Duvvuru @ 2020-10-17  6:28 UTC (permalink / raw)
  To: dev; +Cc: Somnath Kotur

From: Somnath Kotur <somnath.kotur@broadcom.com>

Instead of vfr_alloc for Wh+ and pair_alloc for Stingray, converge
to cfa_pair_alloc/free for both and set the cmd request structure
bits accordingly.
As part of this, remove the old vfr_alloc cmd definitions as FW has
deprecated support for them

Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
Reviewed-by: Shahaji Bhosle <shahaji.bhosle@broadcom.com>
Reviewed-by: Ajit Kumar Khaparde <ajit.khaparde@broadcom.com>
---
 drivers/net/bnxt/bnxt.h        |  6 ++++-
 drivers/net/bnxt/bnxt_ethdev.c |  2 ++
 drivers/net/bnxt/bnxt_hwrm.c   | 60 +++++-------------------------------------
 drivers/net/bnxt/bnxt_hwrm.h   |  2 --
 drivers/net/bnxt/bnxt_reps.c   | 18 ++++++-------
 5 files changed, 21 insertions(+), 67 deletions(-)

diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h
index a951bca..5717819 100644
--- a/drivers/net/bnxt/bnxt.h
+++ b/drivers/net/bnxt/bnxt.h
@@ -836,12 +836,14 @@ struct bnxt_representor {
 #define BNXT_REP_Q_F2R_VALID		BIT(2)
 #define BNXT_REP_FC_R2F_VALID		BIT(3)
 #define BNXT_REP_FC_F2R_VALID		BIT(4)
+#define BNXT_REP_BASED_PF_VALID		BIT(5)
 	uint32_t		flags;
 	uint16_t		fw_fid;
 #define	BNXT_DFLT_VNIC_ID_INVALID	0xFFFF
 	uint16_t		dflt_vnic_id;
 	uint16_t		svif;
 	uint16_t		vfr_tx_cfa_action;
+	uint8_t			parent_pf_idx; /* Logical PF index */
 	uint32_t		dpdk_port_id;
 	uint32_t		rep_based_pf;
 	uint8_t			rep_q_r2f;
@@ -863,7 +865,9 @@ struct bnxt_representor {
 	uint64_t                rx_drop_bytes[BNXT_MAX_VF_REP_RINGS];
 };
 
-#define BNXT_REP_PF(vfr_bp)	((vfr_bp)->flags & BNXT_REP_IS_PF)
+#define BNXT_REP_PF(vfr_bp)		((vfr_bp)->flags & BNXT_REP_IS_PF)
+#define BNXT_REP_BASED_PF(vfr_bp)	\
+		((vfr_bp)->flags & BNXT_REP_BASED_PF_VALID)
 
 struct bnxt_vf_rep_tx_queue {
 	struct bnxt_tx_queue *txq;
diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
index 8dd4ec3..35491d8 100644
--- a/drivers/net/bnxt/bnxt_ethdev.c
+++ b/drivers/net/bnxt/bnxt_ethdev.c
@@ -5762,6 +5762,8 @@ bnxt_parse_devarg_rep_based_pf(__rte_unused const char *key,
 	}
 
 	vfr_bp->rep_based_pf = rep_based_pf;
+	vfr_bp->flags |= BNXT_REP_BASED_PF_VALID;
+
 	PMD_DRV_LOG(INFO, "rep-based-pf = %d\n", vfr_bp->rep_based_pf);
 
 	return 0;
diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c
index 361f995..8470212 100644
--- a/drivers/net/bnxt/bnxt_hwrm.c
+++ b/drivers/net/bnxt/bnxt_hwrm.c
@@ -5671,55 +5671,6 @@ int bnxt_hwrm_cfa_counter_qstats(struct bnxt *bp,
 	return 0;
 }
 
-int bnxt_hwrm_cfa_vfr_alloc(struct bnxt *bp, uint16_t vf_idx)
-{
-	struct hwrm_cfa_vfr_alloc_output *resp = bp->hwrm_cmd_resp_addr;
-	struct hwrm_cfa_vfr_alloc_input req = {0};
-	int rc;
-
-	if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
-		PMD_DRV_LOG(DEBUG,
-			    "Not a PF or trusted VF. Command not supported\n");
-		return 0;
-	}
-
-	HWRM_PREP(&req, HWRM_CFA_VFR_ALLOC, BNXT_USE_CHIMP_MB);
-	req.vf_id = rte_cpu_to_le_16(vf_idx);
-	snprintf(req.vfr_name, sizeof(req.vfr_name), "%svfr%d",
-		 bp->eth_dev->data->name, vf_idx);
-
-	rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
-	HWRM_CHECK_RESULT();
-
-	HWRM_UNLOCK();
-	PMD_DRV_LOG(DEBUG, "VFR %d allocated\n", vf_idx);
-	return rc;
-}
-
-int bnxt_hwrm_cfa_vfr_free(struct bnxt *bp, uint16_t vf_idx)
-{
-	struct hwrm_cfa_vfr_free_output *resp = bp->hwrm_cmd_resp_addr;
-	struct hwrm_cfa_vfr_free_input req = {0};
-	int rc;
-
-	if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
-		PMD_DRV_LOG(DEBUG,
-			    "Not a PF or trusted VF. Command not supported\n");
-		return 0;
-	}
-
-	HWRM_PREP(&req, HWRM_CFA_VFR_FREE, BNXT_USE_CHIMP_MB);
-	req.vf_id = rte_cpu_to_le_16(vf_idx);
-	snprintf(req.vfr_name, sizeof(req.vfr_name), "%svfr%d",
-		 bp->eth_dev->data->name, vf_idx);
-
-	rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
-	HWRM_CHECK_RESULT();
-	HWRM_UNLOCK();
-	PMD_DRV_LOG(DEBUG, "VFR %d freed\n", vf_idx);
-	return rc;
-}
-
 int bnxt_hwrm_first_vf_id_query(struct bnxt *bp, uint16_t fid,
 				uint16_t *first_vf_id)
 {
@@ -5760,8 +5711,9 @@ int bnxt_hwrm_cfa_pair_alloc(struct bnxt *bp, struct bnxt_representor *rep_bp)
 	snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d",
 		 bp->eth_dev->data->name, rep_bp->vf_id);
 
-	req.pf_b_id = rte_cpu_to_le_32(rep_bp->rep_based_pf);
-	req.vf_b_id = rte_cpu_to_le_16(rep_bp->vf_id);
+	req.pf_b_id = rep_bp->parent_pf_idx;
+	req.vf_b_id = BNXT_REP_PF(rep_bp) ? rte_cpu_to_le_16(((uint16_t)-1)) :
+						rte_cpu_to_le_16(rep_bp->vf_id);
 	req.vf_a_id = rte_cpu_to_le_16(bp->fw_fid);
 	req.host_b_id = 1; /* TBD - Confirm if this is OK */
 
@@ -5803,10 +5755,10 @@ int bnxt_hwrm_cfa_pair_free(struct bnxt *bp, struct bnxt_representor *rep_bp)
 	HWRM_PREP(&req, HWRM_CFA_PAIR_FREE, BNXT_USE_CHIMP_MB);
 	snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d",
 		 bp->eth_dev->data->name, rep_bp->vf_id);
-	req.pf_b_id = rte_cpu_to_le_32(rep_bp->rep_based_pf);
-	req.vf_id = rte_cpu_to_le_16(rep_bp->vf_id);
+	req.pf_b_id = rep_bp->parent_pf_idx;
 	req.pair_mode = HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW;
-
+	req.vf_id = BNXT_REP_PF(rep_bp) ? rte_cpu_to_le_16(((uint16_t)-1)) :
+						rte_cpu_to_le_16(rep_bp->vf_id);
 	rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 	HWRM_CHECK_RESULT();
 	HWRM_UNLOCK();
diff --git a/drivers/net/bnxt/bnxt_hwrm.h b/drivers/net/bnxt/bnxt_hwrm.h
index a7fa7f6..23ca6ab 100644
--- a/drivers/net/bnxt/bnxt_hwrm.h
+++ b/drivers/net/bnxt/bnxt_hwrm.h
@@ -297,8 +297,6 @@ int bnxt_hwrm_port_phy_qcaps(struct bnxt *bp);
 int bnxt_hwrm_oem_cmd(struct bnxt *bp, uint32_t entry_num);
 int bnxt_clear_one_vnic_filter(struct bnxt *bp,
 			       struct bnxt_filter_info *filter);
-int bnxt_hwrm_cfa_vfr_alloc(struct bnxt *bp, uint16_t vf_idx);
-int bnxt_hwrm_cfa_vfr_free(struct bnxt *bp, uint16_t vf_idx);
 void bnxt_hwrm_free_vf_info(struct bnxt *bp);
 int bnxt_hwrm_first_vf_id_query(struct bnxt *bp, uint16_t fid,
 				uint16_t *first_vf_id);
diff --git a/drivers/net/bnxt/bnxt_reps.c b/drivers/net/bnxt/bnxt_reps.c
index 74a76fc..957021d 100644
--- a/drivers/net/bnxt/bnxt_reps.c
+++ b/drivers/net/bnxt/bnxt_reps.c
@@ -215,8 +215,9 @@ int bnxt_representor_init(struct rte_eth_dev *eth_dev, void *params)
 		    "Switch domain id %d: Representor Device %d init done\n",
 		    vf_rep_bp->switch_domain_id, vf_rep_bp->vf_id);
 
-	if (vf_rep_bp->rep_based_pf) {
+	if (BNXT_REP_BASED_PF(vf_rep_bp)) {
 		vf_rep_bp->fw_fid = vf_rep_bp->rep_based_pf + 1;
+		vf_rep_bp->parent_pf_idx = vf_rep_bp->rep_based_pf;
 		if (!(BNXT_REP_PF(vf_rep_bp))) {
 			/* VF representor for the remote PF,get first_vf_id */
 			rc = bnxt_hwrm_first_vf_id_query(parent_bp,
@@ -236,6 +237,10 @@ int bnxt_representor_init(struct rte_eth_dev *eth_dev, void *params)
 		}
 	}  else {
 		vf_rep_bp->fw_fid = rep_params->vf_id + parent_bp->first_vf_id;
+		if (BNXT_VF_IS_TRUSTED(parent_bp))
+			vf_rep_bp->parent_pf_idx = parent_bp->parent->fid - 1;
+		else
+			vf_rep_bp->parent_pf_idx = parent_bp->fw_fid - 1;
 	}
 
 	PMD_DRV_LOG(INFO, "vf_rep->fw_fid = %d\n", vf_rep_bp->fw_fid);
@@ -329,11 +334,7 @@ static int bnxt_tf_vfr_alloc(struct rte_eth_dev *vfr_ethdev)
 	/* update the port id so you can backtrack to ethdev */
 	vfr->dpdk_port_id = vfr_ethdev->data->port_id;
 
-	if (BNXT_STINGRAY(parent_bp)) {
-		rc = bnxt_hwrm_cfa_pair_alloc(parent_bp, vfr);
-	} else {
-		rc = bnxt_hwrm_cfa_vfr_alloc(parent_bp, vfr->vf_id);
-	}
+	rc = bnxt_hwrm_cfa_pair_alloc(parent_bp, vfr);
 	if (rc) {
 		BNXT_TF_DBG(ERR, "Failed in hwrm vfr alloc vfr:%u rc=%d\n",
 			    vfr->vf_id, rc);
@@ -468,10 +469,7 @@ static int bnxt_vfr_free(struct bnxt_representor *vfr)
 		    vfr->vf_id);
 	vfr->vfr_tx_cfa_action = 0;
 
-	if (BNXT_STINGRAY(parent_bp))
-		rc = bnxt_hwrm_cfa_pair_free(parent_bp, vfr);
-	else
-		rc = bnxt_hwrm_cfa_vfr_free(parent_bp, vfr->vf_id);
+	rc = bnxt_hwrm_cfa_pair_free(parent_bp, vfr);
 
 	return rc;
 }
-- 
2.7.4


^ permalink raw reply	[flat|nested] 32+ messages in thread

* [dpdk-dev] [PATCH 11/14] net/bnxt: add mapper support for wildcard TCAM entry
  2020-10-17  6:27 [dpdk-dev] [PATCH 00/14] bnxt patches Venkat Duvvuru
                   ` (9 preceding siblings ...)
  2020-10-17  6:28 ` [dpdk-dev] [PATCH 10/14] net/bnxt: use cfa pair alloc for configuring reps Venkat Duvvuru
@ 2020-10-17  6:28 ` Venkat Duvvuru
  2020-10-17  6:28 ` [dpdk-dev] [PATCH 12/14] net/bnxt: refactor flow id allocation Venkat Duvvuru
                   ` (3 subsequent siblings)
  14 siblings, 0 replies; 32+ messages in thread
From: Venkat Duvvuru @ 2020-10-17  6:28 UTC (permalink / raw)
  To: dev; +Cc: Kishore Padmanabha

From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>

Added support for the key and mask fields encoding for the
wildcard tcam entry.

Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Michael Baucom <michael.baucom@broadcom.com>
---
 drivers/net/bnxt/tf_ulp/ulp_mapper.c |  47 +++++++++++--
 drivers/net/bnxt/tf_ulp/ulp_utils.c  | 125 +++++++++++++++++++++++++++++++++++
 drivers/net/bnxt/tf_ulp/ulp_utils.h  |  48 +++++++++++++-
 3 files changed, 212 insertions(+), 8 deletions(-)

diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
index b74cb92..27b4780 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
@@ -1497,6 +1497,29 @@ ulp_mapper_tcam_tbl_entry_write(struct bnxt_ulp_mapper_parms *parms,
 	return rc;
 }
 
+#define BNXT_ULP_WC_TCAM_SLICE_SIZE 80
+/* internal function to post process the key/mask blobs for wildcard tcam tbl */
+static void ulp_mapper_wc_tcam_tbl_post_process(struct ulp_blob *blob,
+						uint32_t len)
+{
+	uint8_t mode[2] = {0x0, 0x0};
+	uint32_t mode_len = len / BNXT_ULP_WC_TCAM_SLICE_SIZE;
+	uint32_t size, idx;
+
+	/* Add the mode bits to the key and mask*/
+	if (mode_len == 2)
+		mode[1] = 2;
+	else if (mode_len > 2)
+		mode[1] = 3;
+
+	size = BNXT_ULP_WC_TCAM_SLICE_SIZE + ULP_BYTE_2_BITS(sizeof(mode));
+	for (idx = 0; idx < mode_len; idx++)
+		ulp_blob_insert(blob, (size * idx), mode,
+				ULP_BYTE_2_BITS(sizeof(mode)));
+	ulp_blob_perform_64B_word_swap(blob);
+	ulp_blob_perform_64B_byte_swap(blob);
+}
+
 static int32_t
 ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms,
 			    struct bnxt_ulp_mapper_tbl_info *tbl)
@@ -1533,9 +1556,9 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms,
 		return -EINVAL;
 	}
 
-	if (!ulp_blob_init(&key, tbl->key_bit_size,
+	if (!ulp_blob_init(&key, tbl->blob_key_bit_size,
 			   parms->device_params->byte_order) ||
-	    !ulp_blob_init(&mask, tbl->key_bit_size,
+	    !ulp_blob_init(&mask, tbl->blob_key_bit_size,
 			   parms->device_params->byte_order) ||
 	    !ulp_blob_init(&data, tbl->result_bit_size,
 			   parms->device_params->byte_order) ||
@@ -1545,6 +1568,11 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms,
 		return -EINVAL;
 	}
 
+	if (tbl->resource_type == TF_TCAM_TBL_TYPE_WC_TCAM) {
+		key.byte_order = BNXT_ULP_BYTE_ORDER_BE;
+		mask.byte_order = BNXT_ULP_BYTE_ORDER_BE;
+	}
+
 	/* create the key/mask */
 	/*
 	 * NOTE: The WC table will require some kind of flag to handle the
@@ -1570,6 +1598,11 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms,
 		}
 	}
 
+	if (tbl->resource_type == TF_TCAM_TBL_TYPE_WC_TCAM) {
+		ulp_mapper_wc_tcam_tbl_post_process(&key, tbl->key_bit_size);
+		ulp_mapper_wc_tcam_tbl_post_process(&mask, tbl->key_bit_size);
+	}
+
 	if (tbl->srch_b4_alloc == BNXT_ULP_SEARCH_BEFORE_ALLOC_NO) {
 		/*
 		 * No search for re-use is requested, so simply allocate the
@@ -1578,18 +1611,18 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms,
 		aparms.dir		= tbl->direction;
 		aparms.tcam_tbl_type	= tbl->resource_type;
 		aparms.search_enable	= tbl->srch_b4_alloc;
-		aparms.key_sz_in_bits	= tbl->key_bit_size;
 		aparms.key		= ulp_blob_data_get(&key, &tmplen);
-		if (tbl->key_bit_size != tmplen) {
+		aparms.key_sz_in_bits	= tmplen;
+		if (tbl->blob_key_bit_size != tmplen) {
 			BNXT_TF_DBG(ERR, "Key len (%d) != Expected (%d)\n",
-				    tmplen, tbl->key_bit_size);
+				    tmplen, tbl->blob_key_bit_size);
 			return -EINVAL;
 		}
 
 		aparms.mask		= ulp_blob_data_get(&mask, &tmplen);
-		if (tbl->key_bit_size != tmplen) {
+		if (tbl->blob_key_bit_size != tmplen) {
 			BNXT_TF_DBG(ERR, "Mask len (%d) != Expected (%d)\n",
-				    tmplen, tbl->key_bit_size);
+				    tmplen, tbl->blob_key_bit_size);
 			return -EINVAL;
 		}
 
diff --git a/drivers/net/bnxt/tf_ulp/ulp_utils.c b/drivers/net/bnxt/tf_ulp/ulp_utils.c
index 24474e2..a13a3bb 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_utils.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_utils.c
@@ -274,6 +274,69 @@ ulp_blob_push(struct ulp_blob *blob,
 }
 
 /*
+ * Insert data into the binary blob at the given offset.
+ *
+ * blob [in] The blob that data is added to.  The blob must
+ * be initialized prior to pushing data.
+ *
+ * offset [in] The offset where the data needs to be inserted.
+ *
+ * data [in/out] A pointer to bytes to be added to the blob.
+ *
+ * datalen [in] The number of bits to be added to the blob.
+ *
+ * The offset of the data is updated after each push of data.
+ * NULL returned on error.
+ */
+uint32_t
+ulp_blob_insert(struct ulp_blob *blob, uint32_t offset,
+		uint8_t *data, uint32_t datalen)
+{
+	uint32_t rc;
+	uint8_t local_data[BNXT_ULP_FLMP_BLOB_SIZE];
+	uint16_t mov_len;
+
+	/* validate the arguments */
+	if (!blob || datalen > (uint32_t)(blob->bitlen - blob->write_idx) ||
+	    offset > blob->write_idx) {
+		BNXT_TF_DBG(ERR, "invalid argument\n");
+		return 0; /* failure */
+	}
+
+	mov_len = blob->write_idx - offset;
+	/* If offset and data len are not 8 bit aligned then return error */
+	if (ULP_BITS_IS_BYTE_NOT_ALIGNED(offset) ||
+	    ULP_BITS_IS_BYTE_NOT_ALIGNED(datalen)) {
+		BNXT_TF_DBG(ERR, "invalid argument, not aligned\n");
+		return 0; /* failure */
+	}
+
+	/* copy the data so we can move the data */
+	memcpy(local_data, &blob->data[ULP_BITS_2_BYTE_NR(offset)],
+	       ULP_BITS_2_BYTE(mov_len));
+	blob->write_idx = offset;
+	if (blob->byte_order == BNXT_ULP_BYTE_ORDER_BE)
+		rc = ulp_bs_push_msb(blob->data,
+				     blob->write_idx,
+				     datalen,
+				     data);
+	else
+		rc = ulp_bs_push_lsb(blob->data,
+				     blob->write_idx,
+				     datalen,
+				     data);
+	if (!rc) {
+		BNXT_TF_DBG(ERR, "Failed ro write blob\n");
+		return 0;
+	}
+	/* copy the previously stored data */
+	memcpy(&blob->data[ULP_BITS_2_BYTE_NR(offset + datalen)], local_data,
+	       ULP_BITS_2_BYTE(mov_len));
+	blob->write_idx += (mov_len + datalen);
+	return datalen;
+}
+
+/*
  * Add data to the binary blob at the current offset.
  *
  * blob [in] The blob that data is added to.  The blob must
@@ -604,6 +667,68 @@ ulp_blob_perform_byte_reverse(struct ulp_blob *blob)
 }
 
 /*
+ * Perform the blob buffer 64 bit word swap.
+ * This api makes the first 4 bytes the last in
+ * a given 64 bit value and vice-versa.
+ *
+ * blob [in] The blob's data to be used for swap.
+ *
+ * returns void.
+ */
+void
+ulp_blob_perform_64B_word_swap(struct ulp_blob *blob)
+{
+	uint32_t i, j, num;
+	uint8_t xchar;
+	uint32_t word_size = ULP_64B_IN_BYTES / 2;
+
+	/* validate the arguments */
+	if (!blob) {
+		BNXT_TF_DBG(ERR, "invalid argument\n");
+		return; /* failure */
+	}
+	num = ULP_BITS_2_BYTE(blob->write_idx);
+	for (i = 0; i < num; i = i + ULP_64B_IN_BYTES) {
+		for (j = 0; j < word_size; j++) {
+			xchar = blob->data[i + j];
+			blob->data[i + j] = blob->data[i + j + word_size];
+			blob->data[i + j + word_size] = xchar;
+		}
+	}
+}
+
+/*
+ * Perform the blob buffer 64 bit byte swap.
+ * This api makes the first byte the last in
+ * a given 64 bit value and vice-versa.
+ *
+ * blob [in] The blob's data to be used for swap.
+ *
+ * returns void.
+ */
+void
+ulp_blob_perform_64B_byte_swap(struct ulp_blob *blob)
+{
+	uint32_t i, j, num;
+	uint8_t xchar;
+	uint32_t offset = ULP_64B_IN_BYTES - 1;
+
+	/* validate the arguments */
+	if (!blob) {
+		BNXT_TF_DBG(ERR, "invalid argument\n");
+		return; /* failure */
+	}
+	num = ULP_BITS_2_BYTE(blob->write_idx);
+	for (i = 0; i < num; i = i + ULP_64B_IN_BYTES) {
+		for (j = 0; j < (ULP_64B_IN_BYTES / 2); j++) {
+			xchar = blob->data[i + j];
+			blob->data[i + j] = blob->data[i + offset - j];
+			blob->data[i + offset - j] = xchar;
+		}
+	}
+}
+
+/*
  * Read data from the operand
  *
  * operand [in] A pointer to a 16 Byte operand
diff --git a/drivers/net/bnxt/tf_ulp/ulp_utils.h b/drivers/net/bnxt/tf_ulp/ulp_utils.h
index 898e851..749ac06 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_utils.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_utils.h
@@ -12,7 +12,7 @@
 #define ULP_BUFFER_ALIGN_8_BYTE		8
 #define ULP_BUFFER_ALIGN_16_BYTE	16
 #define ULP_BUFFER_ALIGN_64_BYTE	64
-
+#define ULP_64B_IN_BYTES		8
 /*
  * Macros for bitmap sets and gets
  * These macros can be used if the val are power of 2.
@@ -57,6 +57,9 @@
 /* Macro to round off to next multiple of 8*/
 #define ULP_BYTE_ROUND_OFF_8(x)	(((x) + 7) & ~7)
 
+/* Macro to check bits are byte aligned */
+#define ULP_BITS_IS_BYTE_NOT_ALIGNED(x)	((x) % 8)
+
 /* Macros to read the computed fields */
 #define ULP_COMP_FLD_IDX_RD(params, idx) \
 	rte_be_to_cpu_32((params)->comp_fld[(idx)])
@@ -168,6 +171,25 @@ ulp_blob_push(struct ulp_blob *blob,
 	      uint32_t datalen);
 
 /*
+ * Insert data into the binary blob at the given offset.
+ *
+ * blob [in] The blob that data is added to.  The blob must
+ * be initialized prior to pushing data.
+ *
+ * offset [in] The offset where the data needs to be inserted.
+ *
+ * data [in/out] A pointer to bytes to be added to the blob.
+ *
+ * datalen [in] The number of bits to be added to the blob.
+ *
+ * The offset of the data is updated after each push of data.
+ * NULL returned on error.
+ */
+uint32_t
+ulp_blob_insert(struct ulp_blob *blob, uint32_t offset,
+		uint8_t *data, uint32_t datalen);
+
+/*
  * Add data to the binary blob at the current offset.
  *
  * blob [in] The blob that data is added to.  The blob must
@@ -300,6 +322,30 @@ void
 ulp_blob_perform_byte_reverse(struct ulp_blob *blob);
 
 /*
+ * Perform the blob buffer 64 bit word swap.
+ * This api makes the first 4 bytes the last in
+ * a given 64 bit value and vice-versa.
+ *
+ * blob [in] The blob's data to be used for swap.
+ *
+ * returns void.
+ */
+void
+ulp_blob_perform_64B_word_swap(struct ulp_blob *blob);
+
+/*
+ * Perform the blob buffer 64 bit byte swap.
+ * This api makes the first byte the last in
+ * a given 64 bit value and vice-versa.
+ *
+ * blob [in] The blob's data to be used for swap.
+ *
+ * returns void.
+ */
+void
+ulp_blob_perform_64B_byte_swap(struct ulp_blob *blob);
+
+/*
  * Read data from the operand
  *
  * operand [in] A pointer to a 16 Byte operand
-- 
2.7.4


^ permalink raw reply	[flat|nested] 32+ messages in thread

* [dpdk-dev] [PATCH 12/14] net/bnxt: refactor flow id allocation
  2020-10-17  6:27 [dpdk-dev] [PATCH 00/14] bnxt patches Venkat Duvvuru
                   ` (10 preceding siblings ...)
  2020-10-17  6:28 ` [dpdk-dev] [PATCH 11/14] net/bnxt: add mapper support for wildcard TCAM entry Venkat Duvvuru
@ 2020-10-17  6:28 ` Venkat Duvvuru
  2020-10-17  6:28 ` [dpdk-dev] [PATCH 13/14] net/bnxt: add support for VXLAN decap templates Venkat Duvvuru
                   ` (2 subsequent siblings)
  14 siblings, 0 replies; 32+ messages in thread
From: Venkat Duvvuru @ 2020-10-17  6:28 UTC (permalink / raw)
  To: dev; +Cc: Venkat Duvvuru

Currently, the flow id is allocated inside ulp_mapper_flow_create.
However with vxlan decap feature if F2 flow comes before F1 flow
then F2 is cached and not really installed in the hardware which
means the code will return without calling ulp_mapper_flow_create.
But, ULP has to still return valid flow id to the stack.
Hence, move the flow id allocation outside ulp_mapper_flow_create.

Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
Reviewed-by: Somnath Kotur <somnath.kotur@broadcom.com>
---
 drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c  | 109 ++++++++++++++++++++++---------
 drivers/net/bnxt/tf_ulp/ulp_def_rules.c  |  48 ++++++++++++--
 drivers/net/bnxt/tf_ulp/ulp_mapper.c     |  35 +---------
 drivers/net/bnxt/tf_ulp/ulp_mapper.h     |   4 +-
 drivers/net/bnxt/tf_ulp/ulp_rte_parser.h |   9 +++
 5 files changed, 132 insertions(+), 73 deletions(-)

diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
index c7b2982..47fbaba 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
@@ -74,6 +74,29 @@ bnxt_ulp_set_dir_attributes(struct ulp_rte_parser_params *params,
 		params->dir_attr |= BNXT_ULP_FLOW_ATTR_TRANSFER;
 }
 
+void
+bnxt_ulp_init_mapper_params(struct bnxt_ulp_mapper_create_parms *mapper_cparms,
+			    struct ulp_rte_parser_params *params,
+			    uint32_t priority, uint32_t class_id,
+			    uint32_t act_tmpl, uint16_t func_id,
+			    uint32_t fid,
+			    enum bnxt_ulp_fdb_type flow_type)
+{
+	mapper_cparms->app_priority = priority;
+	mapper_cparms->dir_attr = params->dir_attr;
+
+	mapper_cparms->class_tid = class_id;
+	mapper_cparms->act_tid = act_tmpl;
+	mapper_cparms->func_id = func_id;
+	mapper_cparms->hdr_bitmap = &params->hdr_bitmap;
+	mapper_cparms->hdr_field = params->hdr_field;
+	mapper_cparms->comp_fld = params->comp_fld;
+	mapper_cparms->act = &params->act_bitmap;
+	mapper_cparms->act_prop = &params->act_prop;
+	mapper_cparms->flow_type = flow_type;
+	mapper_cparms->flow_id = fid;
+}
+
 /* Function to create the rte flow. */
 static struct rte_flow *
 bnxt_ulp_flow_create(struct rte_eth_dev *dev,
@@ -85,22 +108,23 @@ bnxt_ulp_flow_create(struct rte_eth_dev *dev,
 	struct bnxt_ulp_mapper_create_parms mapper_cparms = { 0 };
 	struct ulp_rte_parser_params params;
 	struct bnxt_ulp_context *ulp_ctx;
+	int rc, ret = BNXT_TF_RC_ERROR;
 	uint32_t class_id, act_tmpl;
 	struct rte_flow *flow_id;
+	uint16_t func_id;
 	uint32_t fid;
-	int ret = BNXT_TF_RC_ERROR;
 
 	if (bnxt_ulp_flow_validate_args(attr,
 					pattern, actions,
 					error) == BNXT_TF_RC_ERROR) {
 		BNXT_TF_DBG(ERR, "Invalid arguments being passed\n");
-		goto parse_error;
+		goto parse_err1;
 	}
 
 	ulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(dev);
 	if (!ulp_ctx) {
 		BNXT_TF_DBG(ERR, "ULP context is not initialized\n");
-		goto parse_error;
+		goto parse_err1;
 	}
 
 	/* Initialize the parser params */
@@ -116,56 +140,72 @@ bnxt_ulp_flow_create(struct rte_eth_dev *dev,
 	ULP_COMP_FLD_IDX_WR(&params, BNXT_ULP_CF_IDX_SVIF_FLAG,
 			    BNXT_ULP_INVALID_SVIF_VAL);
 
+	/* Get the function id */
+	if (ulp_port_db_port_func_id_get(ulp_ctx,
+					 dev->data->port_id,
+					 &func_id)) {
+		BNXT_TF_DBG(ERR, "conversion of port to func id failed\n");
+		goto parse_err1;
+	}
+
+	/* Protect flow creation */
+	if (bnxt_ulp_cntxt_acquire_fdb_lock(ulp_ctx)) {
+		BNXT_TF_DBG(ERR, "Flow db lock acquire failed\n");
+		goto parse_err1;
+	}
+
+	/* Allocate a Flow ID for attaching all resources for the flow to.
+	 * Once allocated, all errors have to walk the list of resources and
+	 * free each of them.
+	 */
+	rc = ulp_flow_db_fid_alloc(ulp_ctx, BNXT_ULP_FDB_TYPE_REGULAR,
+				   func_id, &fid);
+	if (rc) {
+		BNXT_TF_DBG(ERR, "Unable to allocate flow table entry\n");
+		goto parse_err2;
+	}
+
 	/* Parse the rte flow pattern */
 	ret = bnxt_ulp_rte_parser_hdr_parse(pattern, &params);
 	if (ret != BNXT_TF_RC_SUCCESS)
-		goto parse_error;
+		goto parse_err3;
 
 	/* Parse the rte flow action */
 	ret = bnxt_ulp_rte_parser_act_parse(actions, &params);
 	if (ret != BNXT_TF_RC_SUCCESS)
-		goto parse_error;
+		goto parse_err3;
 
 	/* Perform the rte flow post process */
 	ret = bnxt_ulp_rte_parser_post_process(&params);
 	if (ret != BNXT_TF_RC_SUCCESS)
-		goto parse_error;
+		goto parse_err3;
 
 	ret = ulp_matcher_pattern_match(&params, &class_id);
 	if (ret != BNXT_TF_RC_SUCCESS)
-		goto parse_error;
+		goto parse_err3;
 
 	ret = ulp_matcher_action_match(&params, &act_tmpl);
 	if (ret != BNXT_TF_RC_SUCCESS)
-		goto parse_error;
+		goto parse_err3;
 
-	mapper_cparms.app_priority = attr->priority;
-	mapper_cparms.hdr_bitmap = &params.hdr_bitmap;
-	mapper_cparms.hdr_field = params.hdr_field;
-	mapper_cparms.comp_fld = params.comp_fld;
-	mapper_cparms.act = &params.act_bitmap;
-	mapper_cparms.act_prop = &params.act_prop;
-	mapper_cparms.class_tid = class_id;
-	mapper_cparms.act_tid = act_tmpl;
-	mapper_cparms.flow_type = BNXT_ULP_FDB_TYPE_REGULAR;
+	bnxt_ulp_init_mapper_params(&mapper_cparms, &params, attr->priority,
+				    class_id, act_tmpl, func_id, fid,
+				    BNXT_ULP_FDB_TYPE_REGULAR);
+	/* Call the ulp mapper to create the flow in the hardware. */
+	ret = ulp_mapper_flow_create(ulp_ctx, &mapper_cparms);
+	if (ret)
+		goto parse_err3;
 
-	/* Get the function id */
-	if (ulp_port_db_port_func_id_get(ulp_ctx,
-					 dev->data->port_id,
-					 &mapper_cparms.func_id)) {
-		BNXT_TF_DBG(ERR, "conversion of port to func id failed\n");
-		goto parse_error;
-	}
-	mapper_cparms.dir_attr = params.dir_attr;
+	bnxt_ulp_cntxt_release_fdb_lock(ulp_ctx);
 
-	/* Call the ulp mapper to create the flow in the hardware. */
-	ret = ulp_mapper_flow_create(ulp_ctx, &mapper_cparms, &fid);
-	if (!ret) {
-		flow_id = (struct rte_flow *)((uintptr_t)fid);
-		return flow_id;
-	}
+	flow_id = (struct rte_flow *)((uintptr_t)fid);
+	return flow_id;
 
-parse_error:
+parse_err3:
+	ulp_flow_db_fid_free(ulp_ctx, BNXT_ULP_FDB_TYPE_REGULAR, fid);
+parse_err2:
+	bnxt_ulp_cntxt_release_fdb_lock(ulp_ctx);
+parse_err1:
 	rte_flow_error_set(error, ret, RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
 			   "Failed to create flow.");
 	return NULL;
@@ -281,6 +321,10 @@ bnxt_ulp_flow_destroy(struct rte_eth_dev *dev,
 		return -EINVAL;
 	}
 
+	if (bnxt_ulp_cntxt_acquire_fdb_lock(ulp_ctx)) {
+		BNXT_TF_DBG(ERR, "Flow db lock acquire failed\n");
+		return -EINVAL;
+	}
 	ret = ulp_mapper_flow_destroy(ulp_ctx, BNXT_ULP_FDB_TYPE_REGULAR,
 				      flow_id);
 	if (ret) {
@@ -290,6 +334,7 @@ bnxt_ulp_flow_destroy(struct rte_eth_dev *dev,
 					   RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
 					   "Failed to destroy flow.");
 	}
+	bnxt_ulp_cntxt_release_fdb_lock(ulp_ctx);
 
 	return ret;
 }
diff --git a/drivers/net/bnxt/tf_ulp/ulp_def_rules.c b/drivers/net/bnxt/tf_ulp/ulp_def_rules.c
index c36d4d4..ec504fc 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_def_rules.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_def_rules.c
@@ -304,8 +304,8 @@ ulp_default_flow_create(struct rte_eth_dev *eth_dev,
 	struct ulp_rte_act_prop		act_prop;
 	struct ulp_rte_act_bitmap	act = { 0 };
 	struct bnxt_ulp_context		*ulp_ctx;
-	uint32_t type, ulp_flags = 0;
-	int rc;
+	uint32_t type, ulp_flags = 0, fid;
+	int rc = 0;
 
 	memset(&mapper_params, 0, sizeof(mapper_params));
 	memset(hdr_field, 0, sizeof(hdr_field));
@@ -316,6 +316,8 @@ ulp_default_flow_create(struct rte_eth_dev *eth_dev,
 	mapper_params.act = &act;
 	mapper_params.act_prop = &act_prop;
 	mapper_params.comp_fld = comp_fld;
+	mapper_params.class_tid = ulp_class_tid;
+	mapper_params.flow_type = BNXT_ULP_FDB_TYPE_DEFAULT;
 
 	ulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(eth_dev);
 	if (!ulp_ctx) {
@@ -350,16 +352,43 @@ ulp_default_flow_create(struct rte_eth_dev *eth_dev,
 		type = param_list->type;
 	}
 
-	mapper_params.class_tid = ulp_class_tid;
-	mapper_params.flow_type = BNXT_ULP_FDB_TYPE_DEFAULT;
+	/* Get the function id */
+	if (ulp_port_db_port_func_id_get(ulp_ctx,
+					 eth_dev->data->port_id,
+					 &mapper_params.func_id)) {
+		BNXT_TF_DBG(ERR, "conversion of port to func id failed\n");
+		goto err1;
+	}
+
+	/* Protect flow creation */
+	if (bnxt_ulp_cntxt_acquire_fdb_lock(ulp_ctx)) {
+		BNXT_TF_DBG(ERR, "Flow db lock acquire failed\n");
+		goto err1;
+	}
 
-	rc = ulp_mapper_flow_create(ulp_ctx, &mapper_params, flow_id);
+	rc = ulp_flow_db_fid_alloc(ulp_ctx, BNXT_ULP_FDB_TYPE_DEFAULT,
+				   mapper_params.func_id, &fid);
 	if (rc) {
-		BNXT_TF_DBG(ERR, "Failed to create default flow.\n");
-		return rc;
+		BNXT_TF_DBG(ERR, "Unable to allocate flow table entry\n");
+		goto err2;
 	}
 
+	mapper_params.flow_id = fid;
+	rc = ulp_mapper_flow_create(ulp_ctx, &mapper_params);
+	if (rc)
+		goto err3;
+
+	bnxt_ulp_cntxt_release_fdb_lock(ulp_ctx);
+	*flow_id = fid;
 	return 0;
+
+err3:
+	ulp_flow_db_fid_free(ulp_ctx, BNXT_ULP_FDB_TYPE_DEFAULT, fid);
+err2:
+	bnxt_ulp_cntxt_release_fdb_lock(ulp_ctx);
+err1:
+	BNXT_TF_DBG(ERR, "Failed to create default flow.\n");
+	return rc;
 }
 
 /*
@@ -391,10 +420,15 @@ ulp_default_flow_destroy(struct rte_eth_dev *eth_dev, uint32_t flow_id)
 		return rc;
 	}
 
+	if (bnxt_ulp_cntxt_acquire_fdb_lock(ulp_ctx)) {
+		BNXT_TF_DBG(ERR, "Flow db lock acquire failed\n");
+		return -EINVAL;
+	}
 	rc = ulp_mapper_flow_destroy(ulp_ctx, BNXT_ULP_FDB_TYPE_DEFAULT,
 				     flow_id);
 	if (rc)
 		BNXT_TF_DBG(ERR, "Failed to destroy flow.\n");
+	bnxt_ulp_cntxt_release_fdb_lock(ulp_ctx);
 
 	return rc;
 }
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
index 27b4780..d5c129b 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
@@ -2723,15 +2723,9 @@ ulp_mapper_flow_destroy(struct bnxt_ulp_context *ulp_ctx,
 		BNXT_TF_DBG(ERR, "Invalid parms, unable to free flow\n");
 		return -EINVAL;
 	}
-	if (bnxt_ulp_cntxt_acquire_fdb_lock(ulp_ctx)) {
-		BNXT_TF_DBG(ERR, "Flow db lock acquire failed\n");
-		return -EINVAL;
-	}
 
 	rc = ulp_mapper_resources_free(ulp_ctx, flow_type, fid);
-	bnxt_ulp_cntxt_release_fdb_lock(ulp_ctx);
 	return rc;
-
 }
 
 /* Function to handle the default global templates that are allocated during
@@ -2795,8 +2789,7 @@ ulp_mapper_glb_template_table_init(struct bnxt_ulp_context *ulp_ctx)
  */
 int32_t
 ulp_mapper_flow_create(struct bnxt_ulp_context *ulp_ctx,
-		       struct bnxt_ulp_mapper_create_parms *cparms,
-		       uint32_t *flowid)
+		       struct bnxt_ulp_mapper_create_parms *cparms)
 {
 	struct bnxt_ulp_mapper_parms parms;
 	struct ulp_regfile regfile;
@@ -2821,6 +2814,7 @@ ulp_mapper_flow_create(struct bnxt_ulp_context *ulp_ctx,
 	parms.flow_type = cparms->flow_type;
 	parms.parent_flow = cparms->parent_flow;
 	parms.parent_fid = cparms->parent_fid;
+	parms.fid = cparms->flow_id;
 
 	/* Get the device id from the ulp context */
 	if (bnxt_ulp_cntxt_dev_id_get(ulp_ctx, &parms.dev_id)) {
@@ -2861,26 +2855,7 @@ ulp_mapper_flow_create(struct bnxt_ulp_context *ulp_ctx,
 		return -EINVAL;
 	}
 
-	/* Protect flow creation */
-	if (bnxt_ulp_cntxt_acquire_fdb_lock(ulp_ctx)) {
-		BNXT_TF_DBG(ERR, "Flow db lock acquire failed\n");
-		return -EINVAL;
-	}
-
-	/* Allocate a Flow ID for attaching all resources for the flow to.
-	 * Once allocated, all errors have to walk the list of resources and
-	 * free each of them.
-	 */
-	rc = ulp_flow_db_fid_alloc(ulp_ctx,
-				   parms.flow_type,
-				   cparms->func_id,
-				   &parms.fid);
-	if (rc) {
-		BNXT_TF_DBG(ERR, "Unable to allocate flow table entry\n");
-		bnxt_ulp_cntxt_release_fdb_lock(ulp_ctx);
-		return rc;
-	}
-
+	/* Process the action template list from the selected action table*/
 	if (parms.act_tid) {
 		parms.tmpl_type = BNXT_ULP_TEMPLATE_TYPE_ACTION;
 		/* Process the action template tables */
@@ -2911,13 +2886,9 @@ ulp_mapper_flow_create(struct bnxt_ulp_context *ulp_ctx,
 			goto flow_error;
 	}
 
-	*flowid = parms.fid;
-	bnxt_ulp_cntxt_release_fdb_lock(ulp_ctx);
-
 	return rc;
 
 flow_error:
-	bnxt_ulp_cntxt_release_fdb_lock(ulp_ctx);
 	/* Free all resources that were allocated during flow creation */
 	trc = ulp_mapper_flow_destroy(ulp_ctx, BNXT_ULP_FDB_TYPE_REGULAR,
 				      parms.fid);
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.h b/drivers/net/bnxt/tf_ulp/ulp_mapper.h
index 542e41e..0595d15 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.h
@@ -93,6 +93,7 @@ struct bnxt_ulp_mapper_create_parms {
 	uint32_t			dir_attr;
 	enum bnxt_ulp_fdb_type		flow_type;
 
+	uint32_t			flow_id;
 	/* if set then create it as a child flow with parent as parent_fid */
 	uint32_t			parent_fid;
 	/* if set then create a parent flow */
@@ -113,8 +114,7 @@ ulp_mapper_deinit(struct bnxt_ulp_context *ulp_ctx);
  */
 int32_t
 ulp_mapper_flow_create(struct bnxt_ulp_context	*ulp_ctx,
-		       struct bnxt_ulp_mapper_create_parms *parms,
-		       uint32_t *flowid);
+		       struct bnxt_ulp_mapper_create_parms *parms);
 
 /* Function that frees all resources associated with the flow. */
 int32_t
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
index 41f3df9..bb5a8a4 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
@@ -11,6 +11,7 @@
 #include <rte_flow_driver.h>
 #include "ulp_template_db_enum.h"
 #include "ulp_template_struct.h"
+#include "ulp_mapper.h"
 
 /* defines to be used in the tunnel header parsing */
 #define BNXT_ULP_ENCAP_IPV4_VER_HLEN_TOS	2
@@ -34,6 +35,14 @@
 #define	BNXT_ULP_PARSER_IPV6_TC			0x0ff00000
 #define	BNXT_ULP_PARSER_IPV6_FLOW_LABEL		0x000fffff
 
+void
+bnxt_ulp_init_mapper_params(struct bnxt_ulp_mapper_create_parms *mapper_cparms,
+			    struct ulp_rte_parser_params *params,
+			    uint32_t priority, uint32_t class_id,
+			    uint32_t act_tmpl, uint16_t func_id,
+			    uint32_t flow_id,
+			    enum bnxt_ulp_fdb_type flow_type);
+
 /* Function to handle the parsing of the RTE port id. */
 int32_t
 ulp_rte_parser_implicit_match_port_process(struct ulp_rte_parser_params *param);
-- 
2.7.4


^ permalink raw reply	[flat|nested] 32+ messages in thread

* [dpdk-dev] [PATCH 13/14] net/bnxt: add support for VXLAN decap templates
  2020-10-17  6:27 [dpdk-dev] [PATCH 00/14] bnxt patches Venkat Duvvuru
                   ` (11 preceding siblings ...)
  2020-10-17  6:28 ` [dpdk-dev] [PATCH 12/14] net/bnxt: refactor flow id allocation Venkat Duvvuru
@ 2020-10-17  6:28 ` Venkat Duvvuru
  2020-10-17  6:28 ` [dpdk-dev] [PATCH 14/14] net/bnxt: add VXLAN decap offload support Venkat Duvvuru
  2020-10-20 21:55 ` [dpdk-dev] [PATCH v2 00/11] bnxt fixes and enhancements to TRUFLOW support Ajit Khaparde
  14 siblings, 0 replies; 32+ messages in thread
From: Venkat Duvvuru @ 2020-10-17  6:28 UTC (permalink / raw)
  To: dev; +Cc: Venkat Duvvuru

outer tunnel & inner tunnel flow templates are added.

Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
Reviewed-by: Michael Baucom <michael.baucom@broadcom.com>
---
 drivers/net/bnxt/tf_ulp/ulp_rte_parser.c           |   10 +
 drivers/net/bnxt/tf_ulp/ulp_rte_parser.h           |    5 +
 drivers/net/bnxt/tf_ulp/ulp_template_db_class.c    |  962 +++++---
 drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h     |   35 +-
 drivers/net/bnxt/tf_ulp/ulp_template_db_field.h    |  363 ++-
 .../net/bnxt/tf_ulp/ulp_template_db_stingray_act.c |  116 +-
 .../bnxt/tf_ulp/ulp_template_db_stingray_class.c   | 2493 ++++++++++++++++----
 drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c      |    9 +-
 .../net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c  |  116 +-
 .../bnxt/tf_ulp/ulp_template_db_wh_plus_class.c    | 2489 +++++++++++++++----
 10 files changed, 5127 insertions(+), 1471 deletions(-)

diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
index 770fec5..42021ae 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
@@ -2110,3 +2110,13 @@ ulp_rte_dec_ttl_act_handler(const struct rte_flow_action *act __rte_unused,
 	ULP_BITMAP_SET(params->act_bitmap.bits, BNXT_ULP_ACTION_BIT_DEC_TTL);
 	return BNXT_TF_RC_SUCCESS;
 }
+
+/* Function to handle the parsing of RTE Flow action JUMP */
+int32_t
+ulp_rte_jump_act_handler(const struct rte_flow_action *action_item __rte_unused,
+			    struct ulp_rte_parser_params *params)
+{
+	/* Update the act_bitmap with dec ttl */
+	ULP_BITMAP_SET(params->act_bitmap.bits, BNXT_ULP_ACTION_BIT_JUMP);
+	return BNXT_TF_RC_SUCCESS;
+}
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
index bb5a8a4..a71aabe 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
@@ -233,4 +233,9 @@ int32_t
 ulp_rte_dec_ttl_act_handler(const struct rte_flow_action *action_item,
 			    struct ulp_rte_parser_params *params);
 
+/* Function to handle the parsing of RTE Flow action JUMP .*/
+int32_t
+ulp_rte_jump_act_handler(const struct rte_flow_action *action_item,
+			 struct ulp_rte_parser_params *params);
+
 #endif /* _ULP_RTE_PARSER_H_ */
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c
index c348abe..fdb26da 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c
@@ -157,58 +157,74 @@ uint16_t ulp_class_sig_tbl[BNXT_ULP_CLASS_SIG_TBL_MAX_SZ] = {
 	[BNXT_ULP_CLASS_HID_05b9] = 146,
 	[BNXT_ULP_CLASS_HID_0371] = 147,
 	[BNXT_ULP_CLASS_HID_00e1] = 148,
-	[BNXT_ULP_CLASS_HID_048b] = 149,
-	[BNXT_ULP_CLASS_HID_0749] = 150,
-	[BNXT_ULP_CLASS_HID_05f1] = 151,
-	[BNXT_ULP_CLASS_HID_04b7] = 152,
-	[BNXT_ULP_CLASS_HID_049b] = 153,
-	[BNXT_ULP_CLASS_HID_0759] = 154,
-	[BNXT_ULP_CLASS_HID_05e1] = 155,
-	[BNXT_ULP_CLASS_HID_04a7] = 156,
-	[BNXT_ULP_CLASS_HID_0301] = 157,
-	[BNXT_ULP_CLASS_HID_07f9] = 158,
-	[BNXT_ULP_CLASS_HID_0397] = 159,
-	[BNXT_ULP_CLASS_HID_068f] = 160,
-	[BNXT_ULP_CLASS_HID_02f1] = 161,
-	[BNXT_ULP_CLASS_HID_0609] = 162,
-	[BNXT_ULP_CLASS_HID_0267] = 163,
-	[BNXT_ULP_CLASS_HID_077f] = 164,
-	[BNXT_ULP_CLASS_HID_01e1] = 165,
-	[BNXT_ULP_CLASS_HID_0329] = 166,
-	[BNXT_ULP_CLASS_HID_01c1] = 167,
-	[BNXT_ULP_CLASS_HID_0309] = 168,
-	[BNXT_ULP_CLASS_HID_01d1] = 169,
-	[BNXT_ULP_CLASS_HID_0319] = 170,
-	[BNXT_ULP_CLASS_HID_01e2] = 171,
-	[BNXT_ULP_CLASS_HID_032a] = 172,
-	[BNXT_ULP_CLASS_HID_0650] = 173,
-	[BNXT_ULP_CLASS_HID_0198] = 174,
-	[BNXT_ULP_CLASS_HID_01c2] = 175,
-	[BNXT_ULP_CLASS_HID_030a] = 176,
-	[BNXT_ULP_CLASS_HID_0670] = 177,
-	[BNXT_ULP_CLASS_HID_01b8] = 178,
-	[BNXT_ULP_CLASS_HID_01d2] = 179,
-	[BNXT_ULP_CLASS_HID_031a] = 180,
-	[BNXT_ULP_CLASS_HID_0660] = 181,
-	[BNXT_ULP_CLASS_HID_01a8] = 182,
-	[BNXT_ULP_CLASS_HID_01dd] = 183,
-	[BNXT_ULP_CLASS_HID_0315] = 184,
-	[BNXT_ULP_CLASS_HID_003d] = 185,
-	[BNXT_ULP_CLASS_HID_02f5] = 186,
-	[BNXT_ULP_CLASS_HID_01cd] = 187,
-	[BNXT_ULP_CLASS_HID_0305] = 188,
-	[BNXT_ULP_CLASS_HID_01de] = 189,
-	[BNXT_ULP_CLASS_HID_0316] = 190,
-	[BNXT_ULP_CLASS_HID_066c] = 191,
-	[BNXT_ULP_CLASS_HID_01a4] = 192,
-	[BNXT_ULP_CLASS_HID_003e] = 193,
-	[BNXT_ULP_CLASS_HID_02f6] = 194,
-	[BNXT_ULP_CLASS_HID_078c] = 195,
-	[BNXT_ULP_CLASS_HID_0044] = 196,
-	[BNXT_ULP_CLASS_HID_01ce] = 197,
-	[BNXT_ULP_CLASS_HID_0306] = 198,
-	[BNXT_ULP_CLASS_HID_067c] = 199,
-	[BNXT_ULP_CLASS_HID_01b4] = 200
+	[BNXT_ULP_CLASS_HID_0000] = 149,
+	[BNXT_ULP_CLASS_HID_00ce] = 150,
+	[BNXT_ULP_CLASS_HID_01b6] = 151,
+	[BNXT_ULP_CLASS_HID_0074] = 152,
+	[BNXT_ULP_CLASS_HID_00fe] = 153,
+	[BNXT_ULP_CLASS_HID_03bc] = 154,
+	[BNXT_ULP_CLASS_HID_0206] = 155,
+	[BNXT_ULP_CLASS_HID_02c4] = 156,
+	[BNXT_ULP_CLASS_HID_055a] = 157,
+	[BNXT_ULP_CLASS_HID_045a] = 158,
+	[BNXT_ULP_CLASS_HID_061a] = 159,
+	[BNXT_ULP_CLASS_HID_051a] = 160,
+	[BNXT_ULP_CLASS_HID_074a] = 161,
+	[BNXT_ULP_CLASS_HID_004e] = 162,
+	[BNXT_ULP_CLASS_HID_040a] = 163,
+	[BNXT_ULP_CLASS_HID_010e] = 164,
+	[BNXT_ULP_CLASS_HID_048b] = 165,
+	[BNXT_ULP_CLASS_HID_0749] = 166,
+	[BNXT_ULP_CLASS_HID_05f1] = 167,
+	[BNXT_ULP_CLASS_HID_04b7] = 168,
+	[BNXT_ULP_CLASS_HID_049b] = 169,
+	[BNXT_ULP_CLASS_HID_0759] = 170,
+	[BNXT_ULP_CLASS_HID_05e1] = 171,
+	[BNXT_ULP_CLASS_HID_04a7] = 172,
+	[BNXT_ULP_CLASS_HID_0301] = 173,
+	[BNXT_ULP_CLASS_HID_07f9] = 174,
+	[BNXT_ULP_CLASS_HID_0397] = 175,
+	[BNXT_ULP_CLASS_HID_068f] = 176,
+	[BNXT_ULP_CLASS_HID_02f1] = 177,
+	[BNXT_ULP_CLASS_HID_0609] = 178,
+	[BNXT_ULP_CLASS_HID_0267] = 179,
+	[BNXT_ULP_CLASS_HID_077f] = 180,
+	[BNXT_ULP_CLASS_HID_01e1] = 181,
+	[BNXT_ULP_CLASS_HID_0329] = 182,
+	[BNXT_ULP_CLASS_HID_01c1] = 183,
+	[BNXT_ULP_CLASS_HID_0309] = 184,
+	[BNXT_ULP_CLASS_HID_01d1] = 185,
+	[BNXT_ULP_CLASS_HID_0319] = 186,
+	[BNXT_ULP_CLASS_HID_01e2] = 187,
+	[BNXT_ULP_CLASS_HID_032a] = 188,
+	[BNXT_ULP_CLASS_HID_0650] = 189,
+	[BNXT_ULP_CLASS_HID_0198] = 190,
+	[BNXT_ULP_CLASS_HID_01c2] = 191,
+	[BNXT_ULP_CLASS_HID_030a] = 192,
+	[BNXT_ULP_CLASS_HID_0670] = 193,
+	[BNXT_ULP_CLASS_HID_01b8] = 194,
+	[BNXT_ULP_CLASS_HID_01d2] = 195,
+	[BNXT_ULP_CLASS_HID_031a] = 196,
+	[BNXT_ULP_CLASS_HID_0660] = 197,
+	[BNXT_ULP_CLASS_HID_01a8] = 198,
+	[BNXT_ULP_CLASS_HID_01dd] = 199,
+	[BNXT_ULP_CLASS_HID_0315] = 200,
+	[BNXT_ULP_CLASS_HID_003d] = 201,
+	[BNXT_ULP_CLASS_HID_02f5] = 202,
+	[BNXT_ULP_CLASS_HID_01cd] = 203,
+	[BNXT_ULP_CLASS_HID_0305] = 204,
+	[BNXT_ULP_CLASS_HID_01de] = 205,
+	[BNXT_ULP_CLASS_HID_0316] = 206,
+	[BNXT_ULP_CLASS_HID_066c] = 207,
+	[BNXT_ULP_CLASS_HID_01a4] = 208,
+	[BNXT_ULP_CLASS_HID_003e] = 209,
+	[BNXT_ULP_CLASS_HID_02f6] = 210,
+	[BNXT_ULP_CLASS_HID_078c] = 211,
+	[BNXT_ULP_CLASS_HID_0044] = 212,
+	[BNXT_ULP_CLASS_HID_01ce] = 213,
+	[BNXT_ULP_CLASS_HID_0306] = 214,
+	[BNXT_ULP_CLASS_HID_067c] = 215,
+	[BNXT_ULP_CLASS_HID_01b4] = 216
 };
 
 struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
@@ -2831,305 +2847,617 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.wc_pri = 23
 	},
 	[149] = {
-	.class_hid = BNXT_ULP_CLASS_HID_048b,
+	.class_hid = BNXT_ULP_CLASS_HID_0000,
 	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_F1 |
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
 		BNXT_ULP_HDR_BIT_O_UDP |
-		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
+		BNXT_ULP_HF18_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF18_BITMASK_O_ETH_SMAC |
 		BNXT_ULP_HF18_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF18_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF18_BITMASK_O_IPV4_DST_ADDR |
 		BNXT_ULP_HF18_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF18_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF18_BITMASK_O_IPV4_DST_ADDR |
 		BNXT_ULP_HF18_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	.class_tid = 18,
 	.wc_pri = 0
 	},
 	[150] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0749,
+	.class_hid = BNXT_ULP_CLASS_HID_00ce,
 	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_F1 |
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
 		BNXT_ULP_HDR_BIT_O_UDP |
-		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
+		BNXT_ULP_HF18_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF18_BITMASK_O_ETH_SMAC |
 		BNXT_ULP_HF18_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF18_BITMASK_O_IPV4_SRC_ADDR |
 		BNXT_ULP_HF18_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF18_BITMASK_O_UDP_SRC_PORT |
 		BNXT_ULP_HF18_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	.class_tid = 18,
 	.wc_pri = 1
 	},
 	[151] = {
-	.class_hid = BNXT_ULP_CLASS_HID_05f1,
+	.class_hid = BNXT_ULP_CLASS_HID_01b6,
 	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_F1 |
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
 		BNXT_ULP_HDR_BIT_O_UDP |
-		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF18_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF18_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF18_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF18_BITMASK_O_ETH_SMAC |
 		BNXT_ULP_HF18_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF18_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF18_BITMASK_O_IPV4_DST_ADDR |
 		BNXT_ULP_HF18_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	.class_tid = 18,
 	.wc_pri = 2
 	},
 	[152] = {
-	.class_hid = BNXT_ULP_CLASS_HID_04b7,
+	.class_hid = BNXT_ULP_CLASS_HID_0074,
 	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_F1 |
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
 		BNXT_ULP_HDR_BIT_O_UDP |
-		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF18_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF18_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF18_BITMASK_O_ETH_SMAC |
 		BNXT_ULP_HF18_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF18_BITMASK_O_UDP_SRC_PORT |
 		BNXT_ULP_HF18_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	.class_tid = 18,
 	.wc_pri = 3
 	},
 	[153] = {
-	.class_hid = BNXT_ULP_CLASS_HID_049b,
+	.class_hid = BNXT_ULP_CLASS_HID_00fe,
 	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_F1 |
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_TCP |
-		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF18_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF18_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF18_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF18_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF18_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	.class_tid = 18,
+	.wc_pri = 4
+	},
+	[154] = {
+	.class_hid = BNXT_ULP_CLASS_HID_03bc,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_F1 |
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF18_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF18_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF18_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF18_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	.class_tid = 18,
+	.wc_pri = 5
+	},
+	[155] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0206,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_F1 |
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF18_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF18_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF18_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF18_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	.class_tid = 18,
+	.wc_pri = 6
+	},
+	[156] = {
+	.class_hid = BNXT_ULP_CLASS_HID_02c4,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_F1 |
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF18_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF18_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF18_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	.class_tid = 18,
+	.wc_pri = 7
+	},
+	[157] = {
+	.class_hid = BNXT_ULP_CLASS_HID_055a,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF19_BITMASK_O_ETH_TYPE |
 		BNXT_ULP_HF19_BITMASK_O_IPV4_SRC_ADDR |
 		BNXT_ULP_HF19_BITMASK_O_IPV4_DST_ADDR |
 		BNXT_ULP_HF19_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF19_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF19_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF19_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF19_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF19_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF19_BITMASK_I_ETH_SMAC |
+		BNXT_ULP_HF19_BITMASK_I_ETH_TYPE |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	.class_tid = 19,
 	.wc_pri = 0
 	},
-	[154] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0759,
+	[158] = {
+	.class_hid = BNXT_ULP_CLASS_HID_045a,
 	.hdr_sig = { .bits =
-		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_TCP |
-		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF19_BITMASK_O_ETH_TYPE |
 		BNXT_ULP_HF19_BITMASK_O_IPV4_SRC_ADDR |
 		BNXT_ULP_HF19_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF19_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF19_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF19_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF19_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF19_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF19_BITMASK_I_ETH_SMAC |
+		BNXT_ULP_HF19_BITMASK_I_ETH_TYPE |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	.class_tid = 19,
 	.wc_pri = 1
 	},
-	[155] = {
-	.class_hid = BNXT_ULP_CLASS_HID_05e1,
+	[159] = {
+	.class_hid = BNXT_ULP_CLASS_HID_061a,
 	.hdr_sig = { .bits =
-		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_TCP |
-		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
 		BNXT_ULP_HF19_BITMASK_O_IPV4_SRC_ADDR |
 		BNXT_ULP_HF19_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF19_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF19_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF19_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF19_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF19_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF19_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF19_BITMASK_I_ETH_SMAC |
+		BNXT_ULP_HF19_BITMASK_I_ETH_TYPE |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	.class_tid = 19,
 	.wc_pri = 2
 	},
-	[156] = {
-	.class_hid = BNXT_ULP_CLASS_HID_04a7,
+	[160] = {
+	.class_hid = BNXT_ULP_CLASS_HID_051a,
 	.hdr_sig = { .bits =
-		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_TCP |
-		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
 		BNXT_ULP_HF19_BITMASK_O_IPV4_SRC_ADDR |
 		BNXT_ULP_HF19_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF19_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF19_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF19_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF19_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF19_BITMASK_I_ETH_SMAC |
+		BNXT_ULP_HF19_BITMASK_I_ETH_TYPE |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	.class_tid = 19,
 	.wc_pri = 3
 	},
-	[157] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0301,
+	[161] = {
+	.class_hid = BNXT_ULP_CLASS_HID_074a,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF19_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF19_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF19_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF19_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF19_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF19_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF19_BITMASK_I_ETH_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	.class_tid = 19,
+	.wc_pri = 4
+	},
+	[162] = {
+	.class_hid = BNXT_ULP_CLASS_HID_004e,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF19_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF19_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF19_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF19_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF19_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF19_BITMASK_I_ETH_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	.class_tid = 19,
+	.wc_pri = 5
+	},
+	[163] = {
+	.class_hid = BNXT_ULP_CLASS_HID_040a,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF19_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF19_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF19_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF19_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF19_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF19_BITMASK_I_ETH_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	.class_tid = 19,
+	.wc_pri = 6
+	},
+	[164] = {
+	.class_hid = BNXT_ULP_CLASS_HID_010e,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF19_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF19_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF19_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF19_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF19_BITMASK_I_ETH_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	.class_tid = 19,
+	.wc_pri = 7
+	},
+	[165] = {
+	.class_hid = BNXT_ULP_CLASS_HID_048b,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
 		BNXT_ULP_HF20_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF20_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF20_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF20_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF20_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF20_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF20_BITMASK_O_IPV4_PROTO_ID |
 		BNXT_ULP_HF20_BITMASK_O_UDP_SRC_PORT |
 		BNXT_ULP_HF20_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	.class_tid = 20,
 	.wc_pri = 0
 	},
-	[158] = {
-	.class_hid = BNXT_ULP_CLASS_HID_07f9,
+	[166] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0749,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
 		BNXT_ULP_HF20_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF20_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF20_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF20_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF20_BITMASK_O_IPV4_DST_ADDR |
 		BNXT_ULP_HF20_BITMASK_O_UDP_SRC_PORT |
 		BNXT_ULP_HF20_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	.class_tid = 20,
 	.wc_pri = 1
 	},
-	[159] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0397,
+	[167] = {
+	.class_hid = BNXT_ULP_CLASS_HID_05f1,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF20_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF20_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF20_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF20_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF20_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF20_BITMASK_O_IPV4_PROTO_ID |
 		BNXT_ULP_HF20_BITMASK_O_UDP_SRC_PORT |
 		BNXT_ULP_HF20_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	.class_tid = 20,
 	.wc_pri = 2
 	},
-	[160] = {
-	.class_hid = BNXT_ULP_CLASS_HID_068f,
+	[168] = {
+	.class_hid = BNXT_ULP_CLASS_HID_04b7,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF20_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF20_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF20_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF20_BITMASK_O_IPV4_DST_ADDR |
 		BNXT_ULP_HF20_BITMASK_O_UDP_SRC_PORT |
 		BNXT_ULP_HF20_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	.class_tid = 20,
 	.wc_pri = 3
 	},
-	[161] = {
-	.class_hid = BNXT_ULP_CLASS_HID_02f1,
+	[169] = {
+	.class_hid = BNXT_ULP_CLASS_HID_049b,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
 		BNXT_ULP_HF21_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF21_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF21_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF21_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF21_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF21_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF21_BITMASK_O_IPV4_PROTO_ID |
 		BNXT_ULP_HF21_BITMASK_O_TCP_SRC_PORT |
 		BNXT_ULP_HF21_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	.class_tid = 21,
 	.wc_pri = 0
 	},
-	[162] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0609,
+	[170] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0759,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
 		BNXT_ULP_HF21_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF21_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF21_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF21_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF21_BITMASK_O_IPV4_DST_ADDR |
 		BNXT_ULP_HF21_BITMASK_O_TCP_SRC_PORT |
 		BNXT_ULP_HF21_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	.class_tid = 21,
 	.wc_pri = 1
 	},
-	[163] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0267,
+	[171] = {
+	.class_hid = BNXT_ULP_CLASS_HID_05e1,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF21_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF21_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF21_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF21_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF21_BITMASK_O_IPV4_PROTO_ID |
 		BNXT_ULP_HF21_BITMASK_O_TCP_SRC_PORT |
 		BNXT_ULP_HF21_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	.class_tid = 21,
 	.wc_pri = 2
 	},
-	[164] = {
-	.class_hid = BNXT_ULP_CLASS_HID_077f,
+	[172] = {
+	.class_hid = BNXT_ULP_CLASS_HID_04a7,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF21_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF21_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF21_BITMASK_O_IPV4_DST_ADDR |
 		BNXT_ULP_HF21_BITMASK_O_TCP_SRC_PORT |
 		BNXT_ULP_HF21_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	.class_tid = 21,
 	.wc_pri = 3
 	},
-	[165] = {
-	.class_hid = BNXT_ULP_CLASS_HID_01e1,
+	[173] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0301,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF22_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF22_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_HF22_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF22_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF22_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF22_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF22_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF22_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	.class_tid = 22,
 	.wc_pri = 0
 	},
-	[166] = {
+	[174] = {
+	.class_hid = BNXT_ULP_CLASS_HID_07f9,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF22_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF22_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF22_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF22_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF22_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	.class_tid = 22,
+	.wc_pri = 1
+	},
+	[175] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0397,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF22_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF22_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF22_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF22_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF22_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	.class_tid = 22,
+	.wc_pri = 2
+	},
+	[176] = {
+	.class_hid = BNXT_ULP_CLASS_HID_068f,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF22_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF22_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF22_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF22_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	.class_tid = 22,
+	.wc_pri = 3
+	},
+	[177] = {
+	.class_hid = BNXT_ULP_CLASS_HID_02f1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF23_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF23_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF23_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF23_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF23_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF23_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	.class_tid = 23,
+	.wc_pri = 0
+	},
+	[178] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0609,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF23_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF23_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF23_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF23_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF23_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	.class_tid = 23,
+	.wc_pri = 1
+	},
+	[179] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0267,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF23_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF23_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF23_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF23_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF23_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	.class_tid = 23,
+	.wc_pri = 2
+	},
+	[180] = {
+	.class_hid = BNXT_ULP_CLASS_HID_077f,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF23_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF23_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF23_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF23_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	.class_tid = 23,
+	.wc_pri = 3
+	},
+	[181] = {
+	.class_hid = BNXT_ULP_CLASS_HID_01e1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF24_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF24_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF24_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	.class_tid = 24,
+	.wc_pri = 0
+	},
+	[182] = {
 	.class_hid = BNXT_ULP_CLASS_HID_0329,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF22_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF22_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF24_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF24_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 22,
+	.class_tid = 24,
 	.wc_pri = 1
 	},
-	[167] = {
+	[183] = {
 	.class_hid = BNXT_ULP_CLASS_HID_01c1,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3137,14 +3465,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF22_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF22_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF22_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF24_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF24_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF24_BITMASK_O_ETH_TYPE |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 22,
+	.class_tid = 24,
 	.wc_pri = 2
 	},
-	[168] = {
+	[184] = {
 	.class_hid = BNXT_ULP_CLASS_HID_0309,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3152,13 +3480,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF22_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF22_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF24_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF24_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 22,
+	.class_tid = 24,
 	.wc_pri = 3
 	},
-	[169] = {
+	[185] = {
 	.class_hid = BNXT_ULP_CLASS_HID_01d1,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3166,14 +3494,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF22_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF22_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF22_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF24_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF24_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF24_BITMASK_O_ETH_TYPE |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 22,
+	.class_tid = 24,
 	.wc_pri = 4
 	},
-	[170] = {
+	[186] = {
 	.class_hid = BNXT_ULP_CLASS_HID_0319,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3181,13 +3509,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF22_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF22_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF24_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF24_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 22,
+	.class_tid = 24,
 	.wc_pri = 5
 	},
-	[171] = {
+	[187] = {
 	.class_hid = BNXT_ULP_CLASS_HID_01e2,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3195,14 +3523,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_IPV4 |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF22_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF22_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF22_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF24_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF24_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF24_BITMASK_O_ETH_TYPE |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 22,
+	.class_tid = 24,
 	.wc_pri = 6
 	},
-	[172] = {
+	[188] = {
 	.class_hid = BNXT_ULP_CLASS_HID_032a,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3210,13 +3538,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_IPV4 |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF22_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF22_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF24_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF24_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 22,
+	.class_tid = 24,
 	.wc_pri = 7
 	},
-	[173] = {
+	[189] = {
 	.class_hid = BNXT_ULP_CLASS_HID_0650,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3224,15 +3552,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_IPV4 |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF22_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF22_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF22_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF22_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF24_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF24_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF24_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF24_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 22,
+	.class_tid = 24,
 	.wc_pri = 8
 	},
-	[174] = {
+	[190] = {
 	.class_hid = BNXT_ULP_CLASS_HID_0198,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3240,14 +3568,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_IPV4 |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF22_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF22_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF22_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF24_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF24_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF24_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 22,
+	.class_tid = 24,
 	.wc_pri = 9
 	},
-	[175] = {
+	[191] = {
 	.class_hid = BNXT_ULP_CLASS_HID_01c2,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3256,14 +3584,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF22_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF22_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF22_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF24_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF24_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF24_BITMASK_O_ETH_TYPE |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 22,
+	.class_tid = 24,
 	.wc_pri = 10
 	},
-	[176] = {
+	[192] = {
 	.class_hid = BNXT_ULP_CLASS_HID_030a,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3272,13 +3600,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF22_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF22_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF24_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF24_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 22,
+	.class_tid = 24,
 	.wc_pri = 11
 	},
-	[177] = {
+	[193] = {
 	.class_hid = BNXT_ULP_CLASS_HID_0670,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3287,15 +3615,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF22_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF22_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF22_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF22_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF24_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF24_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF24_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF24_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 22,
+	.class_tid = 24,
 	.wc_pri = 12
 	},
-	[178] = {
+	[194] = {
 	.class_hid = BNXT_ULP_CLASS_HID_01b8,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3304,14 +3632,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF22_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF22_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF22_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF24_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF24_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF24_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 22,
+	.class_tid = 24,
 	.wc_pri = 13
 	},
-	[179] = {
+	[195] = {
 	.class_hid = BNXT_ULP_CLASS_HID_01d2,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3320,14 +3648,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF22_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF22_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF22_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF24_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF24_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF24_BITMASK_O_ETH_TYPE |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 22,
+	.class_tid = 24,
 	.wc_pri = 14
 	},
-	[180] = {
+	[196] = {
 	.class_hid = BNXT_ULP_CLASS_HID_031a,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3336,13 +3664,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF22_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF22_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF24_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF24_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 22,
+	.class_tid = 24,
 	.wc_pri = 15
 	},
-	[181] = {
+	[197] = {
 	.class_hid = BNXT_ULP_CLASS_HID_0660,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3351,15 +3679,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF22_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF22_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF22_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF22_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF24_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF24_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF24_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF24_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 22,
+	.class_tid = 24,
 	.wc_pri = 16
 	},
-	[182] = {
+	[198] = {
 	.class_hid = BNXT_ULP_CLASS_HID_01a8,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3368,41 +3696,41 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF22_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF22_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF22_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF24_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF24_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF24_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 22,
+	.class_tid = 24,
 	.wc_pri = 17
 	},
-	[183] = {
+	[199] = {
 	.class_hid = BNXT_ULP_CLASS_HID_01dd,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF23_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF23_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF23_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF25_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF25_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF25_BITMASK_O_ETH_TYPE |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 23,
+	.class_tid = 25,
 	.wc_pri = 0
 	},
-	[184] = {
+	[200] = {
 	.class_hid = BNXT_ULP_CLASS_HID_0315,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF23_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF23_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF25_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF25_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 23,
+	.class_tid = 25,
 	.wc_pri = 1
 	},
-	[185] = {
+	[201] = {
 	.class_hid = BNXT_ULP_CLASS_HID_003d,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3410,14 +3738,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF23_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF23_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF23_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF25_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF25_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF25_BITMASK_O_ETH_TYPE |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 23,
+	.class_tid = 25,
 	.wc_pri = 2
 	},
-	[186] = {
+	[202] = {
 	.class_hid = BNXT_ULP_CLASS_HID_02f5,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3425,13 +3753,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF23_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF23_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF25_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF25_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 23,
+	.class_tid = 25,
 	.wc_pri = 3
 	},
-	[187] = {
+	[203] = {
 	.class_hid = BNXT_ULP_CLASS_HID_01cd,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3439,14 +3767,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF23_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF23_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF23_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF25_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF25_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF25_BITMASK_O_ETH_TYPE |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 23,
+	.class_tid = 25,
 	.wc_pri = 4
 	},
-	[188] = {
+	[204] = {
 	.class_hid = BNXT_ULP_CLASS_HID_0305,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3454,13 +3782,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF23_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF23_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF25_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF25_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 23,
+	.class_tid = 25,
 	.wc_pri = 5
 	},
-	[189] = {
+	[205] = {
 	.class_hid = BNXT_ULP_CLASS_HID_01de,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3468,14 +3796,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF23_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF23_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF23_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF25_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF25_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF25_BITMASK_O_ETH_TYPE |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 23,
+	.class_tid = 25,
 	.wc_pri = 6
 	},
-	[190] = {
+	[206] = {
 	.class_hid = BNXT_ULP_CLASS_HID_0316,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3483,13 +3811,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF23_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF23_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF25_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF25_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 23,
+	.class_tid = 25,
 	.wc_pri = 7
 	},
-	[191] = {
+	[207] = {
 	.class_hid = BNXT_ULP_CLASS_HID_066c,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3497,15 +3825,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF23_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF23_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF23_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF23_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF25_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF25_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF25_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF25_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 23,
+	.class_tid = 25,
 	.wc_pri = 8
 	},
-	[192] = {
+	[208] = {
 	.class_hid = BNXT_ULP_CLASS_HID_01a4,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3513,14 +3841,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF23_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF23_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF23_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF25_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF25_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF25_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 23,
+	.class_tid = 25,
 	.wc_pri = 9
 	},
-	[193] = {
+	[209] = {
 	.class_hid = BNXT_ULP_CLASS_HID_003e,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3529,14 +3857,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF23_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF23_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF23_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF25_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF25_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF25_BITMASK_O_ETH_TYPE |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 23,
+	.class_tid = 25,
 	.wc_pri = 10
 	},
-	[194] = {
+	[210] = {
 	.class_hid = BNXT_ULP_CLASS_HID_02f6,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3545,13 +3873,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF23_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF23_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF25_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF25_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 23,
+	.class_tid = 25,
 	.wc_pri = 11
 	},
-	[195] = {
+	[211] = {
 	.class_hid = BNXT_ULP_CLASS_HID_078c,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3560,15 +3888,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF23_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF23_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF23_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF23_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF25_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF25_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF25_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF25_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 23,
+	.class_tid = 25,
 	.wc_pri = 12
 	},
-	[196] = {
+	[212] = {
 	.class_hid = BNXT_ULP_CLASS_HID_0044,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3577,14 +3905,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF23_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF23_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF23_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF25_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF25_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF25_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 23,
+	.class_tid = 25,
 	.wc_pri = 13
 	},
-	[197] = {
+	[213] = {
 	.class_hid = BNXT_ULP_CLASS_HID_01ce,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3593,14 +3921,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF23_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF23_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF23_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF25_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF25_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF25_BITMASK_O_ETH_TYPE |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 23,
+	.class_tid = 25,
 	.wc_pri = 14
 	},
-	[198] = {
+	[214] = {
 	.class_hid = BNXT_ULP_CLASS_HID_0306,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3609,13 +3937,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF23_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF23_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF25_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF25_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 23,
+	.class_tid = 25,
 	.wc_pri = 15
 	},
-	[199] = {
+	[215] = {
 	.class_hid = BNXT_ULP_CLASS_HID_067c,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3624,15 +3952,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF23_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF23_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF23_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF23_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF25_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF25_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF25_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF25_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 23,
+	.class_tid = 25,
 	.wc_pri = 16
 	},
-	[200] = {
+	[216] = {
 	.class_hid = BNXT_ULP_CLASS_HID_01b4,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3641,11 +3969,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF23_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF23_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF23_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF25_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF25_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF25_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 23,
+	.class_tid = 25,
 	.wc_pri = 17
 	}
 };
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
index 6dade9a..10838f5 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
@@ -11,7 +11,7 @@
 #define BNXT_ULP_LOG2_MAX_NUM_DEV 2
 #define BNXT_ULP_CACHE_TBL_MAX_SZ 4
 #define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 2048
-#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 201
+#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 217
 #define BNXT_ULP_CLASS_HID_LOW_PRIME 7919
 #define BNXT_ULP_CLASS_HID_HIGH_PRIME 7907
 #define BNXT_ULP_CLASS_HID_SHFTR 32
@@ -52,7 +52,8 @@ enum bnxt_ulp_action_bit {
 	BNXT_ULP_ACTION_BIT_SET_TP_SRC       = 0x0000000000100000,
 	BNXT_ULP_ACTION_BIT_SET_TP_DST       = 0x0000000000200000,
 	BNXT_ULP_ACTION_BIT_VXLAN_ENCAP      = 0x0000000000400000,
-	BNXT_ULP_ACTION_BIT_LAST             = 0x0000000000800000
+	BNXT_ULP_ACTION_BIT_JUMP             = 0x0000000000800000,
+	BNXT_ULP_ACTION_BIT_LAST             = 0x0000000001000000
 };
 
 enum bnxt_ulp_hdr_bit {
@@ -72,7 +73,8 @@ enum bnxt_ulp_hdr_bit {
 	BNXT_ULP_HDR_BIT_I_IPV6              = 0x0000000000002000,
 	BNXT_ULP_HDR_BIT_I_TCP               = 0x0000000000004000,
 	BNXT_ULP_HDR_BIT_I_UDP               = 0x0000000000008000,
-	BNXT_ULP_HDR_BIT_LAST                = 0x0000000000010000
+	BNXT_ULP_HDR_BIT_F1                  = 0x0000000000010000,
+	BNXT_ULP_HDR_BIT_LAST                = 0x0000000000020000
 };
 
 enum bnxt_ulp_act_type {
@@ -341,6 +343,10 @@ enum bnxt_ulp_resource_sub_type {
 enum bnxt_ulp_sym {
 	BNXT_ULP_SYM_PKT_TYPE_IGNORE = 0,
 	BNXT_ULP_SYM_PKT_TYPE_L2 = 0,
+	BNXT_ULP_SYM_PKT_TYPE_0_IGNORE = 0,
+	BNXT_ULP_SYM_PKT_TYPE_0_L2 = 0,
+	BNXT_ULP_SYM_PKT_TYPE_1_IGNORE = 0,
+	BNXT_ULP_SYM_PKT_TYPE_1_L2 = 0,
 	BNXT_ULP_SYM_RECYCLE_CNT_IGNORE = 0,
 	BNXT_ULP_SYM_RECYCLE_CNT_ZERO = 0,
 	BNXT_ULP_SYM_RECYCLE_CNT_ONE = 1,
@@ -551,7 +557,8 @@ enum bnxt_ulp_sym {
 	BNXT_ULP_SYM_IP_PROTO_UDP = 17,
 	BNXT_ULP_SYM_VF_FUNC_PARIF = 15,
 	BNXT_ULP_SYM_NO = 0,
-	BNXT_ULP_SYM_YES = 1
+	BNXT_ULP_SYM_YES = 1,
+	BNXT_ULP_SYM_RECYCLE_DST = 0x800
 };
 
 enum bnxt_ulp_wh_plus {
@@ -600,6 +607,7 @@ enum bnxt_ulp_act_prop_sz {
 	BNXT_ULP_ACT_PROP_SZ_ENCAP_IP_SRC = 16,
 	BNXT_ULP_ACT_PROP_SZ_ENCAP_UDP = 4,
 	BNXT_ULP_ACT_PROP_SZ_ENCAP_TUN = 32,
+	BNXT_ULP_ACT_PROP_SZ_JUMP = 4,
 	BNXT_ULP_ACT_PROP_SZ_LAST = 4
 };
 
@@ -644,7 +652,8 @@ enum bnxt_ulp_act_prop_idx {
 	BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC = 205,
 	BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP = 221,
 	BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN = 225,
-	BNXT_ULP_ACT_PROP_IDX_LAST = 257
+	BNXT_ULP_ACT_PROP_IDX_JUMP = 257,
+	BNXT_ULP_ACT_PROP_IDX_LAST = 261
 };
 
 enum bnxt_ulp_class_hid {
@@ -796,6 +805,22 @@ enum bnxt_ulp_class_hid {
 	BNXT_ULP_CLASS_HID_05b9 = 0x05b9,
 	BNXT_ULP_CLASS_HID_0371 = 0x0371,
 	BNXT_ULP_CLASS_HID_00e1 = 0x00e1,
+	BNXT_ULP_CLASS_HID_0000 = 0x0000,
+	BNXT_ULP_CLASS_HID_00ce = 0x00ce,
+	BNXT_ULP_CLASS_HID_01b6 = 0x01b6,
+	BNXT_ULP_CLASS_HID_0074 = 0x0074,
+	BNXT_ULP_CLASS_HID_00fe = 0x00fe,
+	BNXT_ULP_CLASS_HID_03bc = 0x03bc,
+	BNXT_ULP_CLASS_HID_0206 = 0x0206,
+	BNXT_ULP_CLASS_HID_02c4 = 0x02c4,
+	BNXT_ULP_CLASS_HID_055a = 0x055a,
+	BNXT_ULP_CLASS_HID_045a = 0x045a,
+	BNXT_ULP_CLASS_HID_061a = 0x061a,
+	BNXT_ULP_CLASS_HID_051a = 0x051a,
+	BNXT_ULP_CLASS_HID_074a = 0x074a,
+	BNXT_ULP_CLASS_HID_004e = 0x004e,
+	BNXT_ULP_CLASS_HID_040a = 0x040a,
+	BNXT_ULP_CLASS_HID_010e = 0x010e,
 	BNXT_ULP_CLASS_HID_048b = 0x048b,
 	BNXT_ULP_CLASS_HID_0749 = 0x0749,
 	BNXT_ULP_CLASS_HID_05f1 = 0x05f1,
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h
index 137b7fd..516f471 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h
@@ -382,7 +382,11 @@ enum bnxt_ulp_hf18 {
 	BNXT_ULP_HF18_IDX_O_UDP_SRC_PORT         = 20,
 	BNXT_ULP_HF18_IDX_O_UDP_DST_PORT         = 21,
 	BNXT_ULP_HF18_IDX_O_UDP_LENGTH           = 22,
-	BNXT_ULP_HF18_IDX_O_UDP_CSUM             = 23
+	BNXT_ULP_HF18_IDX_O_UDP_CSUM             = 23,
+	BNXT_ULP_HF18_IDX_T_VXLAN_FLAGS          = 24,
+	BNXT_ULP_HF18_IDX_T_VXLAN_RSVD0          = 25,
+	BNXT_ULP_HF18_IDX_T_VXLAN_VNI            = 26,
+	BNXT_ULP_HF18_IDX_T_VXLAN_RSVD1          = 27
 };
 
 enum bnxt_ulp_hf19 {
@@ -406,15 +410,33 @@ enum bnxt_ulp_hf19 {
 	BNXT_ULP_HF19_IDX_O_IPV4_CSUM            = 17,
 	BNXT_ULP_HF19_IDX_O_IPV4_SRC_ADDR        = 18,
 	BNXT_ULP_HF19_IDX_O_IPV4_DST_ADDR        = 19,
-	BNXT_ULP_HF19_IDX_O_TCP_SRC_PORT         = 20,
-	BNXT_ULP_HF19_IDX_O_TCP_DST_PORT         = 21,
-	BNXT_ULP_HF19_IDX_O_TCP_SENT_SEQ         = 22,
-	BNXT_ULP_HF19_IDX_O_TCP_RECV_ACK         = 23,
-	BNXT_ULP_HF19_IDX_O_TCP_DATA_OFF         = 24,
-	BNXT_ULP_HF19_IDX_O_TCP_TCP_FLAGS        = 25,
-	BNXT_ULP_HF19_IDX_O_TCP_RX_WIN           = 26,
-	BNXT_ULP_HF19_IDX_O_TCP_CSUM             = 27,
-	BNXT_ULP_HF19_IDX_O_TCP_URP              = 28
+	BNXT_ULP_HF19_IDX_O_UDP_SRC_PORT         = 20,
+	BNXT_ULP_HF19_IDX_O_UDP_DST_PORT         = 21,
+	BNXT_ULP_HF19_IDX_O_UDP_LENGTH           = 22,
+	BNXT_ULP_HF19_IDX_O_UDP_CSUM             = 23,
+	BNXT_ULP_HF19_IDX_T_VXLAN_FLAGS          = 24,
+	BNXT_ULP_HF19_IDX_T_VXLAN_RSVD0          = 25,
+	BNXT_ULP_HF19_IDX_T_VXLAN_VNI            = 26,
+	BNXT_ULP_HF19_IDX_T_VXLAN_RSVD1          = 27,
+	BNXT_ULP_HF19_IDX_I_ETH_DMAC             = 28,
+	BNXT_ULP_HF19_IDX_I_ETH_SMAC             = 29,
+	BNXT_ULP_HF19_IDX_I_ETH_TYPE             = 30,
+	BNXT_ULP_HF19_IDX_IO_VLAN_CFI_PRI        = 31,
+	BNXT_ULP_HF19_IDX_IO_VLAN_VID            = 32,
+	BNXT_ULP_HF19_IDX_IO_VLAN_TYPE           = 33,
+	BNXT_ULP_HF19_IDX_II_VLAN_CFI_PRI        = 34,
+	BNXT_ULP_HF19_IDX_II_VLAN_VID            = 35,
+	BNXT_ULP_HF19_IDX_II_VLAN_TYPE           = 36,
+	BNXT_ULP_HF19_IDX_I_IPV4_VER             = 37,
+	BNXT_ULP_HF19_IDX_I_IPV4_TOS             = 38,
+	BNXT_ULP_HF19_IDX_I_IPV4_LEN             = 39,
+	BNXT_ULP_HF19_IDX_I_IPV4_FRAG_ID         = 40,
+	BNXT_ULP_HF19_IDX_I_IPV4_FRAG_OFF        = 41,
+	BNXT_ULP_HF19_IDX_I_IPV4_TTL             = 42,
+	BNXT_ULP_HF19_IDX_I_IPV4_PROTO_ID        = 43,
+	BNXT_ULP_HF19_IDX_I_IPV4_CSUM            = 44,
+	BNXT_ULP_HF19_IDX_I_IPV4_SRC_ADDR        = 45,
+	BNXT_ULP_HF19_IDX_I_IPV4_DST_ADDR        = 46
 };
 
 enum bnxt_ulp_hf20 {
@@ -428,18 +450,20 @@ enum bnxt_ulp_hf20 {
 	BNXT_ULP_HF20_IDX_OI_VLAN_CFI_PRI        = 7,
 	BNXT_ULP_HF20_IDX_OI_VLAN_VID            = 8,
 	BNXT_ULP_HF20_IDX_OI_VLAN_TYPE           = 9,
-	BNXT_ULP_HF20_IDX_O_IPV6_VER             = 10,
-	BNXT_ULP_HF20_IDX_O_IPV6_TC              = 11,
-	BNXT_ULP_HF20_IDX_O_IPV6_FLOW_LABEL      = 12,
-	BNXT_ULP_HF20_IDX_O_IPV6_PAYLOAD_LEN     = 13,
-	BNXT_ULP_HF20_IDX_O_IPV6_PROTO_ID        = 14,
-	BNXT_ULP_HF20_IDX_O_IPV6_TTL             = 15,
-	BNXT_ULP_HF20_IDX_O_IPV6_SRC_ADDR        = 16,
-	BNXT_ULP_HF20_IDX_O_IPV6_DST_ADDR        = 17,
-	BNXT_ULP_HF20_IDX_O_UDP_SRC_PORT         = 18,
-	BNXT_ULP_HF20_IDX_O_UDP_DST_PORT         = 19,
-	BNXT_ULP_HF20_IDX_O_UDP_LENGTH           = 20,
-	BNXT_ULP_HF20_IDX_O_UDP_CSUM             = 21
+	BNXT_ULP_HF20_IDX_O_IPV4_VER             = 10,
+	BNXT_ULP_HF20_IDX_O_IPV4_TOS             = 11,
+	BNXT_ULP_HF20_IDX_O_IPV4_LEN             = 12,
+	BNXT_ULP_HF20_IDX_O_IPV4_FRAG_ID         = 13,
+	BNXT_ULP_HF20_IDX_O_IPV4_FRAG_OFF        = 14,
+	BNXT_ULP_HF20_IDX_O_IPV4_TTL             = 15,
+	BNXT_ULP_HF20_IDX_O_IPV4_PROTO_ID        = 16,
+	BNXT_ULP_HF20_IDX_O_IPV4_CSUM            = 17,
+	BNXT_ULP_HF20_IDX_O_IPV4_SRC_ADDR        = 18,
+	BNXT_ULP_HF20_IDX_O_IPV4_DST_ADDR        = 19,
+	BNXT_ULP_HF20_IDX_O_UDP_SRC_PORT         = 20,
+	BNXT_ULP_HF20_IDX_O_UDP_DST_PORT         = 21,
+	BNXT_ULP_HF20_IDX_O_UDP_LENGTH           = 22,
+	BNXT_ULP_HF20_IDX_O_UDP_CSUM             = 23
 };
 
 enum bnxt_ulp_hf21 {
@@ -453,23 +477,25 @@ enum bnxt_ulp_hf21 {
 	BNXT_ULP_HF21_IDX_OI_VLAN_CFI_PRI        = 7,
 	BNXT_ULP_HF21_IDX_OI_VLAN_VID            = 8,
 	BNXT_ULP_HF21_IDX_OI_VLAN_TYPE           = 9,
-	BNXT_ULP_HF21_IDX_O_IPV6_VER             = 10,
-	BNXT_ULP_HF21_IDX_O_IPV6_TC              = 11,
-	BNXT_ULP_HF21_IDX_O_IPV6_FLOW_LABEL      = 12,
-	BNXT_ULP_HF21_IDX_O_IPV6_PAYLOAD_LEN     = 13,
-	BNXT_ULP_HF21_IDX_O_IPV6_PROTO_ID        = 14,
-	BNXT_ULP_HF21_IDX_O_IPV6_TTL             = 15,
-	BNXT_ULP_HF21_IDX_O_IPV6_SRC_ADDR        = 16,
-	BNXT_ULP_HF21_IDX_O_IPV6_DST_ADDR        = 17,
-	BNXT_ULP_HF21_IDX_O_TCP_SRC_PORT         = 18,
-	BNXT_ULP_HF21_IDX_O_TCP_DST_PORT         = 19,
-	BNXT_ULP_HF21_IDX_O_TCP_SENT_SEQ         = 20,
-	BNXT_ULP_HF21_IDX_O_TCP_RECV_ACK         = 21,
-	BNXT_ULP_HF21_IDX_O_TCP_DATA_OFF         = 22,
-	BNXT_ULP_HF21_IDX_O_TCP_TCP_FLAGS        = 23,
-	BNXT_ULP_HF21_IDX_O_TCP_RX_WIN           = 24,
-	BNXT_ULP_HF21_IDX_O_TCP_CSUM             = 25,
-	BNXT_ULP_HF21_IDX_O_TCP_URP              = 26
+	BNXT_ULP_HF21_IDX_O_IPV4_VER             = 10,
+	BNXT_ULP_HF21_IDX_O_IPV4_TOS             = 11,
+	BNXT_ULP_HF21_IDX_O_IPV4_LEN             = 12,
+	BNXT_ULP_HF21_IDX_O_IPV4_FRAG_ID         = 13,
+	BNXT_ULP_HF21_IDX_O_IPV4_FRAG_OFF        = 14,
+	BNXT_ULP_HF21_IDX_O_IPV4_TTL             = 15,
+	BNXT_ULP_HF21_IDX_O_IPV4_PROTO_ID        = 16,
+	BNXT_ULP_HF21_IDX_O_IPV4_CSUM            = 17,
+	BNXT_ULP_HF21_IDX_O_IPV4_SRC_ADDR        = 18,
+	BNXT_ULP_HF21_IDX_O_IPV4_DST_ADDR        = 19,
+	BNXT_ULP_HF21_IDX_O_TCP_SRC_PORT         = 20,
+	BNXT_ULP_HF21_IDX_O_TCP_DST_PORT         = 21,
+	BNXT_ULP_HF21_IDX_O_TCP_SENT_SEQ         = 22,
+	BNXT_ULP_HF21_IDX_O_TCP_RECV_ACK         = 23,
+	BNXT_ULP_HF21_IDX_O_TCP_DATA_OFF         = 24,
+	BNXT_ULP_HF21_IDX_O_TCP_TCP_FLAGS        = 25,
+	BNXT_ULP_HF21_IDX_O_TCP_RX_WIN           = 26,
+	BNXT_ULP_HF21_IDX_O_TCP_CSUM             = 27,
+	BNXT_ULP_HF21_IDX_O_TCP_URP              = 28
 };
 
 enum bnxt_ulp_hf22 {
@@ -483,16 +509,18 @@ enum bnxt_ulp_hf22 {
 	BNXT_ULP_HF22_IDX_OI_VLAN_CFI_PRI        = 7,
 	BNXT_ULP_HF22_IDX_OI_VLAN_VID            = 8,
 	BNXT_ULP_HF22_IDX_OI_VLAN_TYPE           = 9,
-	BNXT_ULP_HF22_IDX_O_IPV4_VER             = 10,
-	BNXT_ULP_HF22_IDX_O_IPV4_TOS             = 11,
-	BNXT_ULP_HF22_IDX_O_IPV4_LEN             = 12,
-	BNXT_ULP_HF22_IDX_O_IPV4_FRAG_ID         = 13,
-	BNXT_ULP_HF22_IDX_O_IPV4_FRAG_OFF        = 14,
-	BNXT_ULP_HF22_IDX_O_IPV4_TTL             = 15,
-	BNXT_ULP_HF22_IDX_O_IPV4_PROTO_ID        = 16,
-	BNXT_ULP_HF22_IDX_O_IPV4_CSUM            = 17,
-	BNXT_ULP_HF22_IDX_O_IPV4_SRC_ADDR        = 18,
-	BNXT_ULP_HF22_IDX_O_IPV4_DST_ADDR        = 19
+	BNXT_ULP_HF22_IDX_O_IPV6_VER             = 10,
+	BNXT_ULP_HF22_IDX_O_IPV6_TC              = 11,
+	BNXT_ULP_HF22_IDX_O_IPV6_FLOW_LABEL      = 12,
+	BNXT_ULP_HF22_IDX_O_IPV6_PAYLOAD_LEN     = 13,
+	BNXT_ULP_HF22_IDX_O_IPV6_PROTO_ID        = 14,
+	BNXT_ULP_HF22_IDX_O_IPV6_TTL             = 15,
+	BNXT_ULP_HF22_IDX_O_IPV6_SRC_ADDR        = 16,
+	BNXT_ULP_HF22_IDX_O_IPV6_DST_ADDR        = 17,
+	BNXT_ULP_HF22_IDX_O_UDP_SRC_PORT         = 18,
+	BNXT_ULP_HF22_IDX_O_UDP_DST_PORT         = 19,
+	BNXT_ULP_HF22_IDX_O_UDP_LENGTH           = 20,
+	BNXT_ULP_HF22_IDX_O_UDP_CSUM             = 21
 };
 
 enum bnxt_ulp_hf23 {
@@ -513,7 +541,60 @@ enum bnxt_ulp_hf23 {
 	BNXT_ULP_HF23_IDX_O_IPV6_PROTO_ID        = 14,
 	BNXT_ULP_HF23_IDX_O_IPV6_TTL             = 15,
 	BNXT_ULP_HF23_IDX_O_IPV6_SRC_ADDR        = 16,
-	BNXT_ULP_HF23_IDX_O_IPV6_DST_ADDR        = 17
+	BNXT_ULP_HF23_IDX_O_IPV6_DST_ADDR        = 17,
+	BNXT_ULP_HF23_IDX_O_TCP_SRC_PORT         = 18,
+	BNXT_ULP_HF23_IDX_O_TCP_DST_PORT         = 19,
+	BNXT_ULP_HF23_IDX_O_TCP_SENT_SEQ         = 20,
+	BNXT_ULP_HF23_IDX_O_TCP_RECV_ACK         = 21,
+	BNXT_ULP_HF23_IDX_O_TCP_DATA_OFF         = 22,
+	BNXT_ULP_HF23_IDX_O_TCP_TCP_FLAGS        = 23,
+	BNXT_ULP_HF23_IDX_O_TCP_RX_WIN           = 24,
+	BNXT_ULP_HF23_IDX_O_TCP_CSUM             = 25,
+	BNXT_ULP_HF23_IDX_O_TCP_URP              = 26
+};
+
+enum bnxt_ulp_hf24 {
+	BNXT_ULP_HF24_IDX_SVIF_INDEX             = 0,
+	BNXT_ULP_HF24_IDX_O_ETH_DMAC             = 1,
+	BNXT_ULP_HF24_IDX_O_ETH_SMAC             = 2,
+	BNXT_ULP_HF24_IDX_O_ETH_TYPE             = 3,
+	BNXT_ULP_HF24_IDX_OO_VLAN_CFI_PRI        = 4,
+	BNXT_ULP_HF24_IDX_OO_VLAN_VID            = 5,
+	BNXT_ULP_HF24_IDX_OO_VLAN_TYPE           = 6,
+	BNXT_ULP_HF24_IDX_OI_VLAN_CFI_PRI        = 7,
+	BNXT_ULP_HF24_IDX_OI_VLAN_VID            = 8,
+	BNXT_ULP_HF24_IDX_OI_VLAN_TYPE           = 9,
+	BNXT_ULP_HF24_IDX_O_IPV4_VER             = 10,
+	BNXT_ULP_HF24_IDX_O_IPV4_TOS             = 11,
+	BNXT_ULP_HF24_IDX_O_IPV4_LEN             = 12,
+	BNXT_ULP_HF24_IDX_O_IPV4_FRAG_ID         = 13,
+	BNXT_ULP_HF24_IDX_O_IPV4_FRAG_OFF        = 14,
+	BNXT_ULP_HF24_IDX_O_IPV4_TTL             = 15,
+	BNXT_ULP_HF24_IDX_O_IPV4_PROTO_ID        = 16,
+	BNXT_ULP_HF24_IDX_O_IPV4_CSUM            = 17,
+	BNXT_ULP_HF24_IDX_O_IPV4_SRC_ADDR        = 18,
+	BNXT_ULP_HF24_IDX_O_IPV4_DST_ADDR        = 19
+};
+
+enum bnxt_ulp_hf25 {
+	BNXT_ULP_HF25_IDX_SVIF_INDEX             = 0,
+	BNXT_ULP_HF25_IDX_O_ETH_DMAC             = 1,
+	BNXT_ULP_HF25_IDX_O_ETH_SMAC             = 2,
+	BNXT_ULP_HF25_IDX_O_ETH_TYPE             = 3,
+	BNXT_ULP_HF25_IDX_OO_VLAN_CFI_PRI        = 4,
+	BNXT_ULP_HF25_IDX_OO_VLAN_VID            = 5,
+	BNXT_ULP_HF25_IDX_OO_VLAN_TYPE           = 6,
+	BNXT_ULP_HF25_IDX_OI_VLAN_CFI_PRI        = 7,
+	BNXT_ULP_HF25_IDX_OI_VLAN_VID            = 8,
+	BNXT_ULP_HF25_IDX_OI_VLAN_TYPE           = 9,
+	BNXT_ULP_HF25_IDX_O_IPV6_VER             = 10,
+	BNXT_ULP_HF25_IDX_O_IPV6_TC              = 11,
+	BNXT_ULP_HF25_IDX_O_IPV6_FLOW_LABEL      = 12,
+	BNXT_ULP_HF25_IDX_O_IPV6_PAYLOAD_LEN     = 13,
+	BNXT_ULP_HF25_IDX_O_IPV6_PROTO_ID        = 14,
+	BNXT_ULP_HF25_IDX_O_IPV6_TTL             = 15,
+	BNXT_ULP_HF25_IDX_O_IPV6_SRC_ADDR        = 16,
+	BNXT_ULP_HF25_IDX_O_IPV6_DST_ADDR        = 17
 };
 
 enum bnxt_ulp_hf_bitmask1 {
@@ -892,7 +973,11 @@ enum bnxt_ulp_hf_bitmask18 {
 	BNXT_ULP_HF18_BITMASK_O_UDP_SRC_PORT     = 0x0000080000000000,
 	BNXT_ULP_HF18_BITMASK_O_UDP_DST_PORT     = 0x0000040000000000,
 	BNXT_ULP_HF18_BITMASK_O_UDP_LENGTH       = 0x0000020000000000,
-	BNXT_ULP_HF18_BITMASK_O_UDP_CSUM         = 0x0000010000000000
+	BNXT_ULP_HF18_BITMASK_O_UDP_CSUM         = 0x0000010000000000,
+	BNXT_ULP_HF18_BITMASK_T_VXLAN_FLAGS      = 0x0000008000000000,
+	BNXT_ULP_HF18_BITMASK_T_VXLAN_RSVD0      = 0x0000004000000000,
+	BNXT_ULP_HF18_BITMASK_T_VXLAN_VNI        = 0x0000002000000000,
+	BNXT_ULP_HF18_BITMASK_T_VXLAN_RSVD1      = 0x0000001000000000
 };
 
 enum bnxt_ulp_hf_bitmask19 {
@@ -916,15 +1001,33 @@ enum bnxt_ulp_hf_bitmask19 {
 	BNXT_ULP_HF19_BITMASK_O_IPV4_CSUM        = 0x0000400000000000,
 	BNXT_ULP_HF19_BITMASK_O_IPV4_SRC_ADDR    = 0x0000200000000000,
 	BNXT_ULP_HF19_BITMASK_O_IPV4_DST_ADDR    = 0x0000100000000000,
-	BNXT_ULP_HF19_BITMASK_O_TCP_SRC_PORT     = 0x0000080000000000,
-	BNXT_ULP_HF19_BITMASK_O_TCP_DST_PORT     = 0x0000040000000000,
-	BNXT_ULP_HF19_BITMASK_O_TCP_SENT_SEQ     = 0x0000020000000000,
-	BNXT_ULP_HF19_BITMASK_O_TCP_RECV_ACK     = 0x0000010000000000,
-	BNXT_ULP_HF19_BITMASK_O_TCP_DATA_OFF     = 0x0000008000000000,
-	BNXT_ULP_HF19_BITMASK_O_TCP_TCP_FLAGS    = 0x0000004000000000,
-	BNXT_ULP_HF19_BITMASK_O_TCP_RX_WIN       = 0x0000002000000000,
-	BNXT_ULP_HF19_BITMASK_O_TCP_CSUM         = 0x0000001000000000,
-	BNXT_ULP_HF19_BITMASK_O_TCP_URP          = 0x0000000800000000
+	BNXT_ULP_HF19_BITMASK_O_UDP_SRC_PORT     = 0x0000080000000000,
+	BNXT_ULP_HF19_BITMASK_O_UDP_DST_PORT     = 0x0000040000000000,
+	BNXT_ULP_HF19_BITMASK_O_UDP_LENGTH       = 0x0000020000000000,
+	BNXT_ULP_HF19_BITMASK_O_UDP_CSUM         = 0x0000010000000000,
+	BNXT_ULP_HF19_BITMASK_T_VXLAN_FLAGS      = 0x0000008000000000,
+	BNXT_ULP_HF19_BITMASK_T_VXLAN_RSVD0      = 0x0000004000000000,
+	BNXT_ULP_HF19_BITMASK_T_VXLAN_VNI        = 0x0000002000000000,
+	BNXT_ULP_HF19_BITMASK_T_VXLAN_RSVD1      = 0x0000001000000000,
+	BNXT_ULP_HF19_BITMASK_I_ETH_DMAC         = 0x0000000800000000,
+	BNXT_ULP_HF19_BITMASK_I_ETH_SMAC         = 0x0000000400000000,
+	BNXT_ULP_HF19_BITMASK_I_ETH_TYPE         = 0x0000000200000000,
+	BNXT_ULP_HF19_BITMASK_IO_VLAN_CFI_PRI    = 0x0000000100000000,
+	BNXT_ULP_HF19_BITMASK_IO_VLAN_VID        = 0x0000000080000000,
+	BNXT_ULP_HF19_BITMASK_IO_VLAN_TYPE       = 0x0000000040000000,
+	BNXT_ULP_HF19_BITMASK_II_VLAN_CFI_PRI    = 0x0000000020000000,
+	BNXT_ULP_HF19_BITMASK_II_VLAN_VID        = 0x0000000010000000,
+	BNXT_ULP_HF19_BITMASK_II_VLAN_TYPE       = 0x0000000008000000,
+	BNXT_ULP_HF19_BITMASK_I_IPV4_VER         = 0x0000000004000000,
+	BNXT_ULP_HF19_BITMASK_I_IPV4_TOS         = 0x0000000002000000,
+	BNXT_ULP_HF19_BITMASK_I_IPV4_LEN         = 0x0000000001000000,
+	BNXT_ULP_HF19_BITMASK_I_IPV4_FRAG_ID     = 0x0000000000800000,
+	BNXT_ULP_HF19_BITMASK_I_IPV4_FRAG_OFF    = 0x0000000000400000,
+	BNXT_ULP_HF19_BITMASK_I_IPV4_TTL         = 0x0000000000200000,
+	BNXT_ULP_HF19_BITMASK_I_IPV4_PROTO_ID    = 0x0000000000100000,
+	BNXT_ULP_HF19_BITMASK_I_IPV4_CSUM        = 0x0000000000080000,
+	BNXT_ULP_HF19_BITMASK_I_IPV4_SRC_ADDR    = 0x0000000000040000,
+	BNXT_ULP_HF19_BITMASK_I_IPV4_DST_ADDR    = 0x0000000000020000
 };
 
 enum bnxt_ulp_hf_bitmask20 {
@@ -938,18 +1041,20 @@ enum bnxt_ulp_hf_bitmask20 {
 	BNXT_ULP_HF20_BITMASK_OI_VLAN_CFI_PRI    = 0x0100000000000000,
 	BNXT_ULP_HF20_BITMASK_OI_VLAN_VID        = 0x0080000000000000,
 	BNXT_ULP_HF20_BITMASK_OI_VLAN_TYPE       = 0x0040000000000000,
-	BNXT_ULP_HF20_BITMASK_O_IPV6_VER         = 0x0020000000000000,
-	BNXT_ULP_HF20_BITMASK_O_IPV6_TC          = 0x0010000000000000,
-	BNXT_ULP_HF20_BITMASK_O_IPV6_FLOW_LABEL  = 0x0008000000000000,
-	BNXT_ULP_HF20_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0004000000000000,
-	BNXT_ULP_HF20_BITMASK_O_IPV6_PROTO_ID    = 0x0002000000000000,
-	BNXT_ULP_HF20_BITMASK_O_IPV6_TTL         = 0x0001000000000000,
-	BNXT_ULP_HF20_BITMASK_O_IPV6_SRC_ADDR    = 0x0000800000000000,
-	BNXT_ULP_HF20_BITMASK_O_IPV6_DST_ADDR    = 0x0000400000000000,
-	BNXT_ULP_HF20_BITMASK_O_UDP_SRC_PORT     = 0x0000200000000000,
-	BNXT_ULP_HF20_BITMASK_O_UDP_DST_PORT     = 0x0000100000000000,
-	BNXT_ULP_HF20_BITMASK_O_UDP_LENGTH       = 0x0000080000000000,
-	BNXT_ULP_HF20_BITMASK_O_UDP_CSUM         = 0x0000040000000000
+	BNXT_ULP_HF20_BITMASK_O_IPV4_VER         = 0x0020000000000000,
+	BNXT_ULP_HF20_BITMASK_O_IPV4_TOS         = 0x0010000000000000,
+	BNXT_ULP_HF20_BITMASK_O_IPV4_LEN         = 0x0008000000000000,
+	BNXT_ULP_HF20_BITMASK_O_IPV4_FRAG_ID     = 0x0004000000000000,
+	BNXT_ULP_HF20_BITMASK_O_IPV4_FRAG_OFF    = 0x0002000000000000,
+	BNXT_ULP_HF20_BITMASK_O_IPV4_TTL         = 0x0001000000000000,
+	BNXT_ULP_HF20_BITMASK_O_IPV4_PROTO_ID    = 0x0000800000000000,
+	BNXT_ULP_HF20_BITMASK_O_IPV4_CSUM        = 0x0000400000000000,
+	BNXT_ULP_HF20_BITMASK_O_IPV4_SRC_ADDR    = 0x0000200000000000,
+	BNXT_ULP_HF20_BITMASK_O_IPV4_DST_ADDR    = 0x0000100000000000,
+	BNXT_ULP_HF20_BITMASK_O_UDP_SRC_PORT     = 0x0000080000000000,
+	BNXT_ULP_HF20_BITMASK_O_UDP_DST_PORT     = 0x0000040000000000,
+	BNXT_ULP_HF20_BITMASK_O_UDP_LENGTH       = 0x0000020000000000,
+	BNXT_ULP_HF20_BITMASK_O_UDP_CSUM         = 0x0000010000000000
 };
 
 enum bnxt_ulp_hf_bitmask21 {
@@ -963,23 +1068,25 @@ enum bnxt_ulp_hf_bitmask21 {
 	BNXT_ULP_HF21_BITMASK_OI_VLAN_CFI_PRI    = 0x0100000000000000,
 	BNXT_ULP_HF21_BITMASK_OI_VLAN_VID        = 0x0080000000000000,
 	BNXT_ULP_HF21_BITMASK_OI_VLAN_TYPE       = 0x0040000000000000,
-	BNXT_ULP_HF21_BITMASK_O_IPV6_VER         = 0x0020000000000000,
-	BNXT_ULP_HF21_BITMASK_O_IPV6_TC          = 0x0010000000000000,
-	BNXT_ULP_HF21_BITMASK_O_IPV6_FLOW_LABEL  = 0x0008000000000000,
-	BNXT_ULP_HF21_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0004000000000000,
-	BNXT_ULP_HF21_BITMASK_O_IPV6_PROTO_ID    = 0x0002000000000000,
-	BNXT_ULP_HF21_BITMASK_O_IPV6_TTL         = 0x0001000000000000,
-	BNXT_ULP_HF21_BITMASK_O_IPV6_SRC_ADDR    = 0x0000800000000000,
-	BNXT_ULP_HF21_BITMASK_O_IPV6_DST_ADDR    = 0x0000400000000000,
-	BNXT_ULP_HF21_BITMASK_O_TCP_SRC_PORT     = 0x0000200000000000,
-	BNXT_ULP_HF21_BITMASK_O_TCP_DST_PORT     = 0x0000100000000000,
-	BNXT_ULP_HF21_BITMASK_O_TCP_SENT_SEQ     = 0x0000080000000000,
-	BNXT_ULP_HF21_BITMASK_O_TCP_RECV_ACK     = 0x0000040000000000,
-	BNXT_ULP_HF21_BITMASK_O_TCP_DATA_OFF     = 0x0000020000000000,
-	BNXT_ULP_HF21_BITMASK_O_TCP_TCP_FLAGS    = 0x0000010000000000,
-	BNXT_ULP_HF21_BITMASK_O_TCP_RX_WIN       = 0x0000008000000000,
-	BNXT_ULP_HF21_BITMASK_O_TCP_CSUM         = 0x0000004000000000,
-	BNXT_ULP_HF21_BITMASK_O_TCP_URP          = 0x0000002000000000
+	BNXT_ULP_HF21_BITMASK_O_IPV4_VER         = 0x0020000000000000,
+	BNXT_ULP_HF21_BITMASK_O_IPV4_TOS         = 0x0010000000000000,
+	BNXT_ULP_HF21_BITMASK_O_IPV4_LEN         = 0x0008000000000000,
+	BNXT_ULP_HF21_BITMASK_O_IPV4_FRAG_ID     = 0x0004000000000000,
+	BNXT_ULP_HF21_BITMASK_O_IPV4_FRAG_OFF    = 0x0002000000000000,
+	BNXT_ULP_HF21_BITMASK_O_IPV4_TTL         = 0x0001000000000000,
+	BNXT_ULP_HF21_BITMASK_O_IPV4_PROTO_ID    = 0x0000800000000000,
+	BNXT_ULP_HF21_BITMASK_O_IPV4_CSUM        = 0x0000400000000000,
+	BNXT_ULP_HF21_BITMASK_O_IPV4_SRC_ADDR    = 0x0000200000000000,
+	BNXT_ULP_HF21_BITMASK_O_IPV4_DST_ADDR    = 0x0000100000000000,
+	BNXT_ULP_HF21_BITMASK_O_TCP_SRC_PORT     = 0x0000080000000000,
+	BNXT_ULP_HF21_BITMASK_O_TCP_DST_PORT     = 0x0000040000000000,
+	BNXT_ULP_HF21_BITMASK_O_TCP_SENT_SEQ     = 0x0000020000000000,
+	BNXT_ULP_HF21_BITMASK_O_TCP_RECV_ACK     = 0x0000010000000000,
+	BNXT_ULP_HF21_BITMASK_O_TCP_DATA_OFF     = 0x0000008000000000,
+	BNXT_ULP_HF21_BITMASK_O_TCP_TCP_FLAGS    = 0x0000004000000000,
+	BNXT_ULP_HF21_BITMASK_O_TCP_RX_WIN       = 0x0000002000000000,
+	BNXT_ULP_HF21_BITMASK_O_TCP_CSUM         = 0x0000001000000000,
+	BNXT_ULP_HF21_BITMASK_O_TCP_URP          = 0x0000000800000000
 };
 
 enum bnxt_ulp_hf_bitmask22 {
@@ -993,16 +1100,18 @@ enum bnxt_ulp_hf_bitmask22 {
 	BNXT_ULP_HF22_BITMASK_OI_VLAN_CFI_PRI    = 0x0100000000000000,
 	BNXT_ULP_HF22_BITMASK_OI_VLAN_VID        = 0x0080000000000000,
 	BNXT_ULP_HF22_BITMASK_OI_VLAN_TYPE       = 0x0040000000000000,
-	BNXT_ULP_HF22_BITMASK_O_IPV4_VER         = 0x0020000000000000,
-	BNXT_ULP_HF22_BITMASK_O_IPV4_TOS         = 0x0010000000000000,
-	BNXT_ULP_HF22_BITMASK_O_IPV4_LEN         = 0x0008000000000000,
-	BNXT_ULP_HF22_BITMASK_O_IPV4_FRAG_ID     = 0x0004000000000000,
-	BNXT_ULP_HF22_BITMASK_O_IPV4_FRAG_OFF    = 0x0002000000000000,
-	BNXT_ULP_HF22_BITMASK_O_IPV4_TTL         = 0x0001000000000000,
-	BNXT_ULP_HF22_BITMASK_O_IPV4_PROTO_ID    = 0x0000800000000000,
-	BNXT_ULP_HF22_BITMASK_O_IPV4_CSUM        = 0x0000400000000000,
-	BNXT_ULP_HF22_BITMASK_O_IPV4_SRC_ADDR    = 0x0000200000000000,
-	BNXT_ULP_HF22_BITMASK_O_IPV4_DST_ADDR    = 0x0000100000000000
+	BNXT_ULP_HF22_BITMASK_O_IPV6_VER         = 0x0020000000000000,
+	BNXT_ULP_HF22_BITMASK_O_IPV6_TC          = 0x0010000000000000,
+	BNXT_ULP_HF22_BITMASK_O_IPV6_FLOW_LABEL  = 0x0008000000000000,
+	BNXT_ULP_HF22_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0004000000000000,
+	BNXT_ULP_HF22_BITMASK_O_IPV6_PROTO_ID    = 0x0002000000000000,
+	BNXT_ULP_HF22_BITMASK_O_IPV6_TTL         = 0x0001000000000000,
+	BNXT_ULP_HF22_BITMASK_O_IPV6_SRC_ADDR    = 0x0000800000000000,
+	BNXT_ULP_HF22_BITMASK_O_IPV6_DST_ADDR    = 0x0000400000000000,
+	BNXT_ULP_HF22_BITMASK_O_UDP_SRC_PORT     = 0x0000200000000000,
+	BNXT_ULP_HF22_BITMASK_O_UDP_DST_PORT     = 0x0000100000000000,
+	BNXT_ULP_HF22_BITMASK_O_UDP_LENGTH       = 0x0000080000000000,
+	BNXT_ULP_HF22_BITMASK_O_UDP_CSUM         = 0x0000040000000000
 };
 
 enum bnxt_ulp_hf_bitmask23 {
@@ -1023,6 +1132,60 @@ enum bnxt_ulp_hf_bitmask23 {
 	BNXT_ULP_HF23_BITMASK_O_IPV6_PROTO_ID    = 0x0002000000000000,
 	BNXT_ULP_HF23_BITMASK_O_IPV6_TTL         = 0x0001000000000000,
 	BNXT_ULP_HF23_BITMASK_O_IPV6_SRC_ADDR    = 0x0000800000000000,
-	BNXT_ULP_HF23_BITMASK_O_IPV6_DST_ADDR    = 0x0000400000000000
+	BNXT_ULP_HF23_BITMASK_O_IPV6_DST_ADDR    = 0x0000400000000000,
+	BNXT_ULP_HF23_BITMASK_O_TCP_SRC_PORT     = 0x0000200000000000,
+	BNXT_ULP_HF23_BITMASK_O_TCP_DST_PORT     = 0x0000100000000000,
+	BNXT_ULP_HF23_BITMASK_O_TCP_SENT_SEQ     = 0x0000080000000000,
+	BNXT_ULP_HF23_BITMASK_O_TCP_RECV_ACK     = 0x0000040000000000,
+	BNXT_ULP_HF23_BITMASK_O_TCP_DATA_OFF     = 0x0000020000000000,
+	BNXT_ULP_HF23_BITMASK_O_TCP_TCP_FLAGS    = 0x0000010000000000,
+	BNXT_ULP_HF23_BITMASK_O_TCP_RX_WIN       = 0x0000008000000000,
+	BNXT_ULP_HF23_BITMASK_O_TCP_CSUM         = 0x0000004000000000,
+	BNXT_ULP_HF23_BITMASK_O_TCP_URP          = 0x0000002000000000
 };
+
+enum bnxt_ulp_hf_bitmask24 {
+	BNXT_ULP_HF24_BITMASK_SVIF_INDEX         = 0x8000000000000000,
+	BNXT_ULP_HF24_BITMASK_O_ETH_DMAC         = 0x4000000000000000,
+	BNXT_ULP_HF24_BITMASK_O_ETH_SMAC         = 0x2000000000000000,
+	BNXT_ULP_HF24_BITMASK_O_ETH_TYPE         = 0x1000000000000000,
+	BNXT_ULP_HF24_BITMASK_OO_VLAN_CFI_PRI    = 0x0800000000000000,
+	BNXT_ULP_HF24_BITMASK_OO_VLAN_VID        = 0x0400000000000000,
+	BNXT_ULP_HF24_BITMASK_OO_VLAN_TYPE       = 0x0200000000000000,
+	BNXT_ULP_HF24_BITMASK_OI_VLAN_CFI_PRI    = 0x0100000000000000,
+	BNXT_ULP_HF24_BITMASK_OI_VLAN_VID        = 0x0080000000000000,
+	BNXT_ULP_HF24_BITMASK_OI_VLAN_TYPE       = 0x0040000000000000,
+	BNXT_ULP_HF24_BITMASK_O_IPV4_VER         = 0x0020000000000000,
+	BNXT_ULP_HF24_BITMASK_O_IPV4_TOS         = 0x0010000000000000,
+	BNXT_ULP_HF24_BITMASK_O_IPV4_LEN         = 0x0008000000000000,
+	BNXT_ULP_HF24_BITMASK_O_IPV4_FRAG_ID     = 0x0004000000000000,
+	BNXT_ULP_HF24_BITMASK_O_IPV4_FRAG_OFF    = 0x0002000000000000,
+	BNXT_ULP_HF24_BITMASK_O_IPV4_TTL         = 0x0001000000000000,
+	BNXT_ULP_HF24_BITMASK_O_IPV4_PROTO_ID    = 0x0000800000000000,
+	BNXT_ULP_HF24_BITMASK_O_IPV4_CSUM        = 0x0000400000000000,
+	BNXT_ULP_HF24_BITMASK_O_IPV4_SRC_ADDR    = 0x0000200000000000,
+	BNXT_ULP_HF24_BITMASK_O_IPV4_DST_ADDR    = 0x0000100000000000
+};
+
+enum bnxt_ulp_hf_bitmask25 {
+	BNXT_ULP_HF25_BITMASK_SVIF_INDEX         = 0x8000000000000000,
+	BNXT_ULP_HF25_BITMASK_O_ETH_DMAC         = 0x4000000000000000,
+	BNXT_ULP_HF25_BITMASK_O_ETH_SMAC         = 0x2000000000000000,
+	BNXT_ULP_HF25_BITMASK_O_ETH_TYPE         = 0x1000000000000000,
+	BNXT_ULP_HF25_BITMASK_OO_VLAN_CFI_PRI    = 0x0800000000000000,
+	BNXT_ULP_HF25_BITMASK_OO_VLAN_VID        = 0x0400000000000000,
+	BNXT_ULP_HF25_BITMASK_OO_VLAN_TYPE       = 0x0200000000000000,
+	BNXT_ULP_HF25_BITMASK_OI_VLAN_CFI_PRI    = 0x0100000000000000,
+	BNXT_ULP_HF25_BITMASK_OI_VLAN_VID        = 0x0080000000000000,
+	BNXT_ULP_HF25_BITMASK_OI_VLAN_TYPE       = 0x0040000000000000,
+	BNXT_ULP_HF25_BITMASK_O_IPV6_VER         = 0x0020000000000000,
+	BNXT_ULP_HF25_BITMASK_O_IPV6_TC          = 0x0010000000000000,
+	BNXT_ULP_HF25_BITMASK_O_IPV6_FLOW_LABEL  = 0x0008000000000000,
+	BNXT_ULP_HF25_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0004000000000000,
+	BNXT_ULP_HF25_BITMASK_O_IPV6_PROTO_ID    = 0x0002000000000000,
+	BNXT_ULP_HF25_BITMASK_O_IPV6_TTL         = 0x0001000000000000,
+	BNXT_ULP_HF25_BITMASK_O_IPV6_SRC_ADDR    = 0x0000800000000000,
+	BNXT_ULP_HF25_BITMASK_O_IPV6_DST_ADDR    = 0x0000400000000000
+};
+
 #endif
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_act.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_act.c
index 2237ffb..7a4d492 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_act.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_act.c
@@ -55,9 +55,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {
 	.result_bit_size = 64,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -72,9 +72,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {
 	.result_bit_size = 32,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_SRC_PTR_0,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_SRC_PTR_0
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -89,9 +89,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {
 	.result_bit_size = 32,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_DST_PTR_0,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_DST_PTR_0
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -105,9 +105,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {
 	.result_bit_size = 0,
 	.result_num_fields = 0,
 	.encap_num_fields = 12,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_GLOBAL,
-	.index_operand = BNXT_ULP_GLB_REGFILE_INDEX_ENCAP_MAC_PTR,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_GLB_REGFILE_INDEX_ENCAP_MAC_PTR
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -121,9 +121,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {
 	.result_bit_size = 128,
 	.result_num_fields = 26,
 	.encap_num_fields = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -137,9 +137,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {
 	.result_bit_size = 128,
 	.result_num_fields = 26,
 	.encap_num_fields = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -154,9 +154,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {
 	.result_bit_size = 64,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -170,9 +170,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {
 	.result_bit_size = 128,
 	.result_num_fields = 26,
 	.encap_num_fields = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -186,9 +186,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {
 	.result_bit_size = 128,
 	.result_num_fields = 26,
 	.encap_num_fields = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -203,9 +203,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {
 	.result_bit_size = 64,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -219,9 +219,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {
 	.result_bit_size = 128,
 	.result_num_fields = 26,
 	.encap_num_fields = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -235,9 +235,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {
 	.result_bit_size = 128,
 	.result_num_fields = 26,
 	.encap_num_fields = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -252,9 +252,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {
 	.result_bit_size = 64,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -269,9 +269,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {
 	.result_bit_size = 0,
 	.result_num_fields = 0,
 	.encap_num_fields = 3,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -286,9 +286,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {
 	.result_bit_size = 0,
 	.result_num_fields = 0,
 	.encap_num_fields = 3,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -301,9 +301,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {
 	.result_bit_size = 0,
 	.result_num_fields = 0,
 	.encap_num_fields = 12,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -317,9 +317,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {
 	.result_bit_size = 128,
 	.result_num_fields = 26,
 	.encap_num_fields = 12,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -333,9 +333,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {
 	.result_bit_size = 128,
 	.result_num_fields = 26,
 	.encap_num_fields = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -350,9 +350,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {
 	.result_bit_size = 64,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -367,9 +367,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {
 	.result_bit_size = 32,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_SRC_PTR_0,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_SRC_PTR_0
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -384,9 +384,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {
 	.result_bit_size = 32,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_DST_PTR_0,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_DST_PTR_0
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -400,9 +400,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {
 	.result_bit_size = 0,
 	.result_num_fields = 0,
 	.encap_num_fields = 12,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_GLOBAL,
-	.index_operand = BNXT_ULP_GLB_REGFILE_INDEX_ENCAP_MAC_PTR,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_GLB_REGFILE_INDEX_ENCAP_MAC_PTR
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -416,9 +416,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {
 	.result_bit_size = 128,
 	.result_num_fields = 26,
 	.encap_num_fields = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -432,9 +432,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {
 	.result_bit_size = 128,
 	.result_num_fields = 26,
 	.encap_num_fields = 11,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -449,9 +449,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {
 	.result_bit_size = 64,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -467,9 +467,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {
 	.result_bit_size = 0,
 	.result_num_fields = 0,
 	.encap_num_fields = 12,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -483,9 +483,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {
 	.result_bit_size = 128,
 	.result_num_fields = 26,
 	.encap_num_fields = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -501,9 +501,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {
 	.result_bit_size = 128,
 	.result_num_fields = 26,
 	.encap_num_fields = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -519,9 +519,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {
 	.result_bit_size = 128,
 	.result_num_fields = 26,
 	.encap_num_fields = 11,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR
 	}
 };
 
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_class.c
index 62b940d..346e155 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_class.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_class.c
@@ -96,33 +96,43 @@ struct bnxt_ulp_mapper_tbl_list_info ulp_stingray_class_tmpl_list[] = {
 	},
 	[18] = {
 	.device_name = BNXT_ULP_DEVICE_ID_STINGRAY,
-	.num_tbls = 6,
+	.num_tbls = 5,
 	.start_tbl_idx = 92
 	},
 	[19] = {
 	.device_name = BNXT_ULP_DEVICE_ID_STINGRAY,
-	.num_tbls = 6,
-	.start_tbl_idx = 98
+	.num_tbls = 5,
+	.start_tbl_idx = 97
 	},
 	[20] = {
 	.device_name = BNXT_ULP_DEVICE_ID_STINGRAY,
 	.num_tbls = 6,
-	.start_tbl_idx = 104
+	.start_tbl_idx = 102
 	},
 	[21] = {
 	.device_name = BNXT_ULP_DEVICE_ID_STINGRAY,
 	.num_tbls = 6,
-	.start_tbl_idx = 110
+	.start_tbl_idx = 108
 	},
 	[22] = {
 	.device_name = BNXT_ULP_DEVICE_ID_STINGRAY,
-	.num_tbls = 5,
-	.start_tbl_idx = 116
+	.num_tbls = 6,
+	.start_tbl_idx = 114
 	},
 	[23] = {
 	.device_name = BNXT_ULP_DEVICE_ID_STINGRAY,
+	.num_tbls = 6,
+	.start_tbl_idx = 120
+	},
+	[24] = {
+	.device_name = BNXT_ULP_DEVICE_ID_STINGRAY,
+	.num_tbls = 5,
+	.start_tbl_idx = 126
+	},
+	[25] = {
+	.device_name = BNXT_ULP_DEVICE_ID_STINGRAY,
 	.num_tbls = 5,
-	.start_tbl_idx = 121
+	.start_tbl_idx = 131
 	}
 };
 
@@ -133,6 +143,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL,
 	.direction = TF_DIR_RX,
+	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
 	.result_start_idx = 0,
 	.result_bit_size = 128,
 	.result_num_fields = 26,
@@ -162,8 +173,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 1,
 	.blob_key_bit_size = 171,
 	.key_bit_size = 171,
@@ -216,6 +227,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_VFR_CFA_ACTION,
 	.direction = TF_DIR_TX,
+	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
 	.result_start_idx = 43,
 	.result_bit_size = 128,
 	.result_num_fields = 26,
@@ -230,8 +242,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.cond_opcode = BNXT_ULP_COND_OPCODE_COMP_FIELD_IS_SET,
 	.cond_operand = BNXT_ULP_CF_IDX_VFR_MODE,
 	.direction = TF_DIR_TX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 14,
 	.blob_key_bit_size = 171,
 	.key_bit_size = 171,
@@ -270,8 +282,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.cond_opcode = BNXT_ULP_COND_OPCODE_COMP_FIELD_NOT_SET,
 	.cond_operand = BNXT_ULP_CF_IDX_VFR_MODE,
 	.direction = TF_DIR_TX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 28,
 	.blob_key_bit_size = 171,
 	.key_bit_size = 171,
@@ -324,6 +336,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL,
 	.direction = TF_DIR_TX,
+	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
 	.result_start_idx = 99,
 	.result_bit_size = 0,
 	.result_num_fields = 0,
@@ -338,6 +351,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_VFR_CFA_ACTION,
 	.direction = TF_DIR_TX,
+	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
 	.result_start_idx = 111,
 	.result_bit_size = 128,
 	.result_num_fields = 26,
@@ -367,8 +381,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
 	.direction = TF_DIR_TX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 42,
 	.blob_key_bit_size = 171,
 	.key_bit_size = 171,
@@ -388,6 +402,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL,
 	.direction = TF_DIR_RX,
+	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
 	.result_start_idx = 150,
 	.result_bit_size = 128,
 	.result_num_fields = 26,
@@ -400,8 +415,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 55,
 	.blob_key_bit_size = 171,
 	.key_bit_size = 171,
@@ -419,8 +434,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 68,
 	.blob_key_bit_size = 171,
 	.key_bit_size = 171,
@@ -455,8 +470,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
 	.direction = TF_DIR_TX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 82,
 	.blob_key_bit_size = 171,
 	.key_bit_size = 171,
@@ -509,6 +524,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL,
 	.direction = TF_DIR_RX,
+	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
 	.result_start_idx = 219,
 	.result_bit_size = 128,
 	.result_num_fields = 26,
@@ -521,8 +537,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 95,
 	.blob_key_bit_size = 171,
 	.key_bit_size = 171,
@@ -542,6 +558,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_VFR_CFA_ACTION,
 	.direction = TF_DIR_TX,
+	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
 	.result_start_idx = 258,
 	.result_bit_size = 128,
 	.result_num_fields = 26,
@@ -554,8 +571,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 108,
 	.blob_key_bit_size = 171,
 	.key_bit_size = 171,
@@ -590,8 +607,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_1,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_1,
 	.key_start_idx = 124,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
@@ -645,8 +662,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 189,
 	.blob_key_bit_size = 171,
 	.key_bit_size = 171,
@@ -681,8 +698,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_1,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_1,
 	.key_start_idx = 205,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
@@ -753,8 +770,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 271,
 	.blob_key_bit_size = 171,
 	.key_bit_size = 171,
@@ -789,8 +806,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 287,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
@@ -861,8 +878,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 353,
 	.blob_key_bit_size = 171,
 	.key_bit_size = 171,
@@ -897,8 +914,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 369,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
@@ -969,8 +986,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 435,
 	.blob_key_bit_size = 171,
 	.key_bit_size = 171,
@@ -1005,8 +1022,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 451,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
@@ -1077,8 +1094,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 517,
 	.blob_key_bit_size = 171,
 	.key_bit_size = 171,
@@ -1113,8 +1130,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 533,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
@@ -1168,8 +1185,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 598,
 	.blob_key_bit_size = 171,
 	.key_bit_size = 171,
@@ -1204,8 +1221,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 614,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
@@ -1259,8 +1276,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 679,
 	.blob_key_bit_size = 171,
 	.key_bit_size = 171,
@@ -1295,8 +1312,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 695,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
@@ -1350,8 +1367,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 760,
 	.blob_key_bit_size = 171,
 	.key_bit_size = 171,
@@ -1386,8 +1403,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 776,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
@@ -1441,8 +1458,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 841,
 	.blob_key_bit_size = 171,
 	.key_bit_size = 171,
@@ -1477,8 +1494,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 857,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
@@ -1532,8 +1549,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 922,
 	.blob_key_bit_size = 171,
 	.key_bit_size = 171,
@@ -1568,8 +1585,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 938,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
@@ -1623,8 +1640,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 1003,
 	.blob_key_bit_size = 171,
 	.key_bit_size = 171,
@@ -1659,8 +1676,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 1019,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
@@ -1711,29 +1728,29 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES
 	},
 	{
-	.resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE,
-	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+	.resource_type = TF_TBL_TYPE_ACT_STATS_64,
 	.resource_sub_type =
-		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM,
-	.direction = TF_DIR_TX,
-	.key_start_idx = 1084,
-	.blob_key_bit_size = 12,
-	.key_bit_size = 12,
-	.key_num_fields = 1,
+		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT_ACC,
+	.cond_opcode = BNXT_ULP_COND_OPCODE_ACTION_BIT_IS_SET,
+	.cond_operand = BNXT_ULP_ACTION_BIT_COUNT,
+	.direction = TF_DIR_RX,
+	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
 	.result_start_idx = 768,
-	.result_bit_size = 10,
+	.result_bit_size = 64,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
-	.ident_start_idx = 27,
-	.ident_nums = 1
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
+	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
+	.index_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
-	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
-	.direction = TF_DIR_TX,
+	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+	.direction = TF_DIR_RX,
+	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP,
 	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
-	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 1085,
+	.key_start_idx = 1084,
 	.blob_key_bit_size = 171,
 	.key_bit_size = 171,
 	.key_num_fields = 13,
@@ -1741,8 +1758,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.result_bit_size = 64,
 	.result_num_fields = 13,
 	.encap_num_fields = 0,
-	.ident_start_idx = 28,
-	.ident_nums = 0,
+	.ident_start_idx = 27,
+	.ident_nums = 1,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
 	},
@@ -1751,71 +1768,145 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
-	.direction = TF_DIR_TX,
-	.key_start_idx = 1098,
+	.direction = TF_DIR_RX,
+	.key_start_idx = 1097,
 	.blob_key_bit_size = 16,
 	.key_bit_size = 16,
 	.key_num_fields = 3,
 	.result_start_idx = 782,
-	.result_bit_size = 10,
-	.result_num_fields = 1,
+	.result_bit_size = 20,
+	.result_num_fields = 2,
 	.encap_num_fields = 0,
 	.ident_start_idx = 28,
-	.ident_nums = 1
+	.ident_nums = 2
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
-	.direction = TF_DIR_TX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
+	.direction = TF_DIR_RX,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 1101,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
+	.key_start_idx = 1100,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
 	.key_num_fields = 43,
-	.result_start_idx = 783,
+	.result_start_idx = 784,
 	.result_bit_size = 38,
 	.result_num_fields = 8,
 	.encap_num_fields = 0,
-	.ident_start_idx = 29,
+	.ident_start_idx = 30,
 	.ident_nums = 0,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
 	},
 	{
-	.resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE,
-	.resource_type = TF_MEM_EXTERNAL,
-	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT,
-	.direction = TF_DIR_TX,
-	.key_start_idx = 1144,
-	.blob_key_bit_size = 448,
-	.key_bit_size = 448,
-	.key_num_fields = 11,
-	.result_start_idx = 791,
-	.result_bit_size = 64,
-	.result_num_fields = 9,
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+	.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+	.direction = TF_DIR_RX,
+	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
+	.key_start_idx = 1143,
+	.blob_key_bit_size = 192,
+	.key_bit_size = 160,
+	.key_num_fields = 5,
+	.result_start_idx = 792,
+	.result_bit_size = 19,
+	.result_num_fields = 3,
 	.encap_num_fields = 0,
-	.ident_start_idx = 29,
+	.ident_start_idx = 30,
 	.ident_nums = 0,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES
 	},
 	{
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+	.direction = TF_DIR_RX,
+	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
+	.key_start_idx = 1148,
+	.blob_key_bit_size = 171,
+	.key_bit_size = 171,
+	.key_num_fields = 13,
+	.result_start_idx = 795,
+	.result_bit_size = 64,
+	.result_num_fields = 13,
+	.encap_num_fields = 0,
+	.ident_start_idx = 30,
+	.ident_nums = 1,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
+	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
+	},
+	{
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE,
+	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+	.resource_sub_type =
+		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
+	.direction = TF_DIR_RX,
+	.key_start_idx = 1161,
+	.blob_key_bit_size = 16,
+	.key_bit_size = 16,
+	.key_num_fields = 3,
+	.result_start_idx = 808,
+	.result_bit_size = 20,
+	.result_num_fields = 2,
+	.encap_num_fields = 0,
+	.ident_start_idx = 31,
+	.ident_nums = 2
+	},
+	{
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+	.direction = TF_DIR_RX,
+	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
+	.key_start_idx = 1164,
+	.blob_key_bit_size = 81,
+	.key_bit_size = 81,
+	.key_num_fields = 43,
+	.result_start_idx = 810,
+	.result_bit_size = 38,
+	.result_num_fields = 8,
+	.encap_num_fields = 0,
+	.ident_start_idx = 33,
+	.ident_nums = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
+	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
+	},
+	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE,
 	.resource_type = TF_MEM_INTERNAL,
 	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT,
-	.direction = TF_DIR_TX,
-	.key_start_idx = 1155,
-	.blob_key_bit_size = 200,
-	.key_bit_size = 200,
-	.key_num_fields = 11,
-	.result_start_idx = 800,
+	.direction = TF_DIR_RX,
+	.key_start_idx = 1207,
+	.blob_key_bit_size = 112,
+	.key_bit_size = 112,
+	.key_num_fields = 8,
+	.result_start_idx = 818,
 	.result_bit_size = 64,
 	.result_num_fields = 9,
 	.encap_num_fields = 0,
-	.ident_start_idx = 29,
+	.ident_start_idx = 33,
 	.ident_nums = 0,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
+	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES
+	},
+	{
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE,
+	.resource_type = TF_MEM_EXTERNAL,
+	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT,
+	.direction = TF_DIR_RX,
+	.key_start_idx = 1215,
+	.blob_key_bit_size = 448,
+	.key_bit_size = 448,
+	.key_num_fields = 8,
+	.result_start_idx = 827,
+	.result_bit_size = 64,
+	.result_num_fields = 9,
+	.encap_num_fields = 0,
+	.ident_start_idx = 33,
+	.ident_nums = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES
 	},
 	{
@@ -1824,32 +1915,32 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1166,
+	.key_start_idx = 1223,
 	.blob_key_bit_size = 12,
 	.key_bit_size = 12,
 	.key_num_fields = 1,
-	.result_start_idx = 809,
+	.result_start_idx = 836,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
-	.ident_start_idx = 29,
+	.ident_start_idx = 33,
 	.ident_nums = 1
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
 	.direction = TF_DIR_TX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 1167,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
+	.key_start_idx = 1224,
 	.blob_key_bit_size = 171,
 	.key_bit_size = 171,
 	.key_num_fields = 13,
-	.result_start_idx = 810,
+	.result_start_idx = 837,
 	.result_bit_size = 64,
 	.result_num_fields = 13,
 	.encap_num_fields = 0,
-	.ident_start_idx = 30,
+	.ident_start_idx = 34,
 	.ident_nums = 0,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
@@ -1860,32 +1951,32 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1180,
+	.key_start_idx = 1237,
 	.blob_key_bit_size = 16,
 	.key_bit_size = 16,
 	.key_num_fields = 3,
-	.result_start_idx = 823,
+	.result_start_idx = 850,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
-	.ident_start_idx = 30,
+	.ident_start_idx = 34,
 	.ident_nums = 1
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
 	.direction = TF_DIR_TX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 1183,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
+	.key_start_idx = 1240,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
 	.key_num_fields = 43,
-	.result_start_idx = 824,
+	.result_start_idx = 851,
 	.result_bit_size = 38,
 	.result_num_fields = 8,
 	.encap_num_fields = 0,
-	.ident_start_idx = 31,
+	.ident_start_idx = 35,
 	.ident_nums = 0,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
@@ -1895,15 +1986,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_type = TF_MEM_EXTERNAL,
 	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1226,
+	.key_start_idx = 1283,
 	.blob_key_bit_size = 448,
 	.key_bit_size = 448,
 	.key_num_fields = 11,
-	.result_start_idx = 832,
+	.result_start_idx = 859,
 	.result_bit_size = 64,
 	.result_num_fields = 9,
 	.encap_num_fields = 0,
-	.ident_start_idx = 31,
+	.ident_start_idx = 35,
 	.ident_nums = 0,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES
@@ -1913,15 +2004,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_type = TF_MEM_INTERNAL,
 	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1237,
+	.key_start_idx = 1294,
 	.blob_key_bit_size = 200,
 	.key_bit_size = 200,
 	.key_num_fields = 11,
-	.result_start_idx = 841,
+	.result_start_idx = 868,
 	.result_bit_size = 64,
 	.result_num_fields = 9,
 	.encap_num_fields = 0,
-	.ident_start_idx = 31,
+	.ident_start_idx = 35,
 	.ident_nums = 0,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES
@@ -1932,32 +2023,32 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1248,
+	.key_start_idx = 1305,
 	.blob_key_bit_size = 12,
 	.key_bit_size = 12,
 	.key_num_fields = 1,
-	.result_start_idx = 850,
+	.result_start_idx = 877,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
-	.ident_start_idx = 31,
+	.ident_start_idx = 35,
 	.ident_nums = 1
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
 	.direction = TF_DIR_TX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 1249,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
+	.key_start_idx = 1306,
 	.blob_key_bit_size = 171,
 	.key_bit_size = 171,
 	.key_num_fields = 13,
-	.result_start_idx = 851,
+	.result_start_idx = 878,
 	.result_bit_size = 64,
 	.result_num_fields = 13,
 	.encap_num_fields = 0,
-	.ident_start_idx = 32,
+	.ident_start_idx = 36,
 	.ident_nums = 0,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
@@ -1968,32 +2059,32 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1262,
+	.key_start_idx = 1319,
 	.blob_key_bit_size = 16,
 	.key_bit_size = 16,
 	.key_num_fields = 3,
-	.result_start_idx = 864,
+	.result_start_idx = 891,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
-	.ident_start_idx = 32,
+	.ident_start_idx = 36,
 	.ident_nums = 1
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
 	.direction = TF_DIR_TX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 1265,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
+	.key_start_idx = 1322,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
 	.key_num_fields = 43,
-	.result_start_idx = 865,
+	.result_start_idx = 892,
 	.result_bit_size = 38,
 	.result_num_fields = 8,
 	.encap_num_fields = 0,
-	.ident_start_idx = 33,
+	.ident_start_idx = 37,
 	.ident_nums = 0,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
@@ -2003,15 +2094,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_type = TF_MEM_EXTERNAL,
 	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1308,
+	.key_start_idx = 1365,
 	.blob_key_bit_size = 448,
 	.key_bit_size = 448,
 	.key_num_fields = 11,
-	.result_start_idx = 873,
+	.result_start_idx = 900,
 	.result_bit_size = 64,
 	.result_num_fields = 9,
 	.encap_num_fields = 0,
-	.ident_start_idx = 33,
+	.ident_start_idx = 37,
 	.ident_nums = 0,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES
@@ -2021,15 +2112,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_type = TF_MEM_INTERNAL,
 	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1319,
-	.blob_key_bit_size = 392,
-	.key_bit_size = 392,
+	.key_start_idx = 1376,
+	.blob_key_bit_size = 200,
+	.key_bit_size = 200,
 	.key_num_fields = 11,
-	.result_start_idx = 882,
+	.result_start_idx = 909,
 	.result_bit_size = 64,
 	.result_num_fields = 9,
 	.encap_num_fields = 0,
-	.ident_start_idx = 33,
+	.ident_start_idx = 37,
 	.ident_nums = 0,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES
@@ -2040,32 +2131,32 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1330,
+	.key_start_idx = 1387,
 	.blob_key_bit_size = 12,
 	.key_bit_size = 12,
 	.key_num_fields = 1,
-	.result_start_idx = 891,
+	.result_start_idx = 918,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
-	.ident_start_idx = 33,
+	.ident_start_idx = 37,
 	.ident_nums = 1
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
 	.direction = TF_DIR_TX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 1331,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
+	.key_start_idx = 1388,
 	.blob_key_bit_size = 171,
 	.key_bit_size = 171,
 	.key_num_fields = 13,
-	.result_start_idx = 892,
+	.result_start_idx = 919,
 	.result_bit_size = 64,
 	.result_num_fields = 13,
 	.encap_num_fields = 0,
-	.ident_start_idx = 34,
+	.ident_start_idx = 38,
 	.ident_nums = 0,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
@@ -2076,32 +2167,140 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1344,
+	.key_start_idx = 1401,
 	.blob_key_bit_size = 16,
 	.key_bit_size = 16,
 	.key_num_fields = 3,
-	.result_start_idx = 905,
+	.result_start_idx = 932,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
-	.ident_start_idx = 34,
+	.ident_start_idx = 38,
 	.ident_nums = 1
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
 	.direction = TF_DIR_TX,
+	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
+	.key_start_idx = 1404,
+	.blob_key_bit_size = 81,
+	.key_bit_size = 81,
+	.key_num_fields = 43,
+	.result_start_idx = 933,
+	.result_bit_size = 38,
+	.result_num_fields = 8,
+	.encap_num_fields = 0,
+	.ident_start_idx = 39,
+	.ident_nums = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
+	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
+	},
+	{
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE,
+	.resource_type = TF_MEM_EXTERNAL,
+	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT,
+	.direction = TF_DIR_TX,
+	.key_start_idx = 1447,
+	.blob_key_bit_size = 448,
+	.key_bit_size = 448,
+	.key_num_fields = 11,
+	.result_start_idx = 941,
+	.result_bit_size = 64,
+	.result_num_fields = 9,
+	.encap_num_fields = 0,
+	.ident_start_idx = 39,
+	.ident_nums = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION,
+	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES
+	},
+	{
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE,
+	.resource_type = TF_MEM_INTERNAL,
+	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT,
+	.direction = TF_DIR_TX,
+	.key_start_idx = 1458,
+	.blob_key_bit_size = 392,
+	.key_bit_size = 392,
+	.key_num_fields = 11,
+	.result_start_idx = 950,
+	.result_bit_size = 64,
+	.result_num_fields = 9,
+	.encap_num_fields = 0,
+	.ident_start_idx = 39,
+	.ident_nums = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION,
+	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES
+	},
+	{
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE,
+	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+	.resource_sub_type =
+		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM,
+	.direction = TF_DIR_TX,
+	.key_start_idx = 1469,
+	.blob_key_bit_size = 12,
+	.key_bit_size = 12,
+	.key_num_fields = 1,
+	.result_start_idx = 959,
+	.result_bit_size = 10,
+	.result_num_fields = 1,
+	.encap_num_fields = 0,
+	.ident_start_idx = 39,
+	.ident_nums = 1
+	},
+	{
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+	.direction = TF_DIR_TX,
+	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
 	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
+	.key_start_idx = 1470,
+	.blob_key_bit_size = 171,
+	.key_bit_size = 171,
+	.key_num_fields = 13,
+	.result_start_idx = 960,
+	.result_bit_size = 64,
+	.result_num_fields = 13,
+	.encap_num_fields = 0,
+	.ident_start_idx = 40,
+	.ident_nums = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
+	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
+	},
+	{
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE,
+	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+	.resource_sub_type =
+		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
+	.direction = TF_DIR_TX,
+	.key_start_idx = 1483,
+	.blob_key_bit_size = 16,
+	.key_bit_size = 16,
+	.key_num_fields = 3,
+	.result_start_idx = 973,
+	.result_bit_size = 10,
+	.result_num_fields = 1,
+	.encap_num_fields = 0,
+	.ident_start_idx = 40,
+	.ident_nums = 1
+	},
+	{
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+	.direction = TF_DIR_TX,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 1347,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
+	.key_start_idx = 1486,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
 	.key_num_fields = 43,
-	.result_start_idx = 906,
+	.result_start_idx = 974,
 	.result_bit_size = 38,
 	.result_num_fields = 8,
 	.encap_num_fields = 0,
-	.ident_start_idx = 35,
+	.ident_start_idx = 41,
 	.ident_nums = 0,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
@@ -2111,15 +2310,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_type = TF_MEM_EXTERNAL,
 	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1390,
+	.key_start_idx = 1529,
 	.blob_key_bit_size = 448,
 	.key_bit_size = 448,
 	.key_num_fields = 11,
-	.result_start_idx = 914,
+	.result_start_idx = 982,
 	.result_bit_size = 64,
 	.result_num_fields = 9,
 	.encap_num_fields = 0,
-	.ident_start_idx = 35,
+	.ident_start_idx = 41,
 	.ident_nums = 0,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES
@@ -2129,15 +2328,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_type = TF_MEM_INTERNAL,
 	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1401,
+	.key_start_idx = 1540,
 	.blob_key_bit_size = 392,
 	.key_bit_size = 392,
 	.key_num_fields = 11,
-	.result_start_idx = 923,
+	.result_start_idx = 991,
 	.result_bit_size = 64,
 	.result_num_fields = 9,
 	.encap_num_fields = 0,
-	.ident_start_idx = 35,
+	.ident_start_idx = 41,
 	.ident_nums = 0,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES
@@ -2146,17 +2345,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
 	.direction = TF_DIR_TX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_UPDATE,
-	.key_start_idx = 1412,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
+	.key_start_idx = 1551,
 	.blob_key_bit_size = 171,
 	.key_bit_size = 171,
 	.key_num_fields = 13,
-	.result_start_idx = 932,
+	.result_start_idx = 1000,
 	.result_bit_size = 64,
 	.result_num_fields = 13,
 	.encap_num_fields = 0,
-	.ident_start_idx = 35,
+	.ident_start_idx = 41,
 	.ident_nums = 1,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
@@ -2167,32 +2366,32 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1425,
+	.key_start_idx = 1564,
 	.blob_key_bit_size = 16,
 	.key_bit_size = 16,
 	.key_num_fields = 3,
-	.result_start_idx = 945,
+	.result_start_idx = 1013,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
-	.ident_start_idx = 36,
+	.ident_start_idx = 42,
 	.ident_nums = 1
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
 	.direction = TF_DIR_TX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 1428,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
+	.key_start_idx = 1567,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
 	.key_num_fields = 43,
-	.result_start_idx = 946,
+	.result_start_idx = 1014,
 	.result_bit_size = 38,
 	.result_num_fields = 8,
 	.encap_num_fields = 0,
-	.ident_start_idx = 37,
+	.ident_start_idx = 43,
 	.ident_nums = 0,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
@@ -2202,15 +2401,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_type = TF_MEM_EXTERNAL,
 	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1471,
+	.key_start_idx = 1610,
 	.blob_key_bit_size = 448,
 	.key_bit_size = 448,
 	.key_num_fields = 7,
-	.result_start_idx = 954,
+	.result_start_idx = 1022,
 	.result_bit_size = 64,
 	.result_num_fields = 9,
 	.encap_num_fields = 0,
-	.ident_start_idx = 37,
+	.ident_start_idx = 43,
 	.ident_nums = 0,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES
@@ -2220,15 +2419,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_type = TF_MEM_INTERNAL,
 	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1478,
+	.key_start_idx = 1617,
 	.blob_key_bit_size = 104,
 	.key_bit_size = 104,
 	.key_num_fields = 7,
-	.result_start_idx = 963,
+	.result_start_idx = 1031,
 	.result_bit_size = 64,
 	.result_num_fields = 9,
 	.encap_num_fields = 0,
-	.ident_start_idx = 37,
+	.ident_start_idx = 43,
 	.ident_nums = 0,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES
@@ -2237,17 +2436,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
 	.direction = TF_DIR_TX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_UPDATE,
-	.key_start_idx = 1485,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
+	.key_start_idx = 1624,
 	.blob_key_bit_size = 171,
 	.key_bit_size = 171,
 	.key_num_fields = 13,
-	.result_start_idx = 972,
+	.result_start_idx = 1040,
 	.result_bit_size = 64,
 	.result_num_fields = 13,
 	.encap_num_fields = 0,
-	.ident_start_idx = 37,
+	.ident_start_idx = 43,
 	.ident_nums = 1,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
@@ -2258,32 +2457,32 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1498,
+	.key_start_idx = 1637,
 	.blob_key_bit_size = 16,
 	.key_bit_size = 16,
 	.key_num_fields = 3,
-	.result_start_idx = 985,
+	.result_start_idx = 1053,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
-	.ident_start_idx = 38,
+	.ident_start_idx = 44,
 	.ident_nums = 1
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
 	.direction = TF_DIR_TX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 1501,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
+	.key_start_idx = 1640,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
 	.key_num_fields = 43,
-	.result_start_idx = 986,
+	.result_start_idx = 1054,
 	.result_bit_size = 38,
 	.result_num_fields = 8,
 	.encap_num_fields = 0,
-	.ident_start_idx = 39,
+	.ident_start_idx = 45,
 	.ident_nums = 0,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
@@ -2293,15 +2492,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_type = TF_MEM_EXTERNAL,
 	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1544,
+	.key_start_idx = 1683,
 	.blob_key_bit_size = 448,
 	.key_bit_size = 448,
 	.key_num_fields = 7,
-	.result_start_idx = 994,
+	.result_start_idx = 1062,
 	.result_bit_size = 64,
 	.result_num_fields = 9,
 	.encap_num_fields = 0,
-	.ident_start_idx = 39,
+	.ident_start_idx = 45,
 	.ident_nums = 0,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES
@@ -2311,15 +2510,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_type = TF_MEM_INTERNAL,
 	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1551,
+	.key_start_idx = 1690,
 	.blob_key_bit_size = 104,
 	.key_bit_size = 104,
 	.key_num_fields = 7,
-	.result_start_idx = 1003,
+	.result_start_idx = 1071,
 	.result_bit_size = 64,
 	.result_num_fields = 9,
 	.encap_num_fields = 0,
-	.ident_start_idx = 39,
+	.ident_start_idx = 45,
 	.ident_nums = 0,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES
@@ -9156,68 +9355,1047 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
 	.spec_operand = {
-		(BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
-		BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
+		(BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
+		BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 3,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 3,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 16,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 16,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 8,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_operand = {
+		BNXT_ULP_SYM_IP_PROTO_UDP,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 32,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+	.spec_operand = {
+		(BNXT_ULP_HF16_IDX_O_IPV4_DST_ADDR >> 8) & 0xff,
+		BNXT_ULP_HF16_IDX_O_IPV4_DST_ADDR & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 32,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 48,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 24,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 10,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+	.spec_operand = {
+		(BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
+		BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 8,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+	.spec_operand = {
+		(BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
+		BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 12,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 12,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 48,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+	.spec_operand = {
+		(BNXT_ULP_HF17_IDX_O_ETH_DMAC >> 8) & 0xff,
+		BNXT_ULP_HF17_IDX_O_ETH_DMAC & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 12,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+	.mask_operand = {
+		(BNXT_ULP_HF17_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF17_IDX_SVIF_INDEX & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+	.spec_operand = {
+		(BNXT_ULP_HF17_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF17_IDX_SVIF_INDEX & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 12,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+	.mask_operand = {
+		(BNXT_ULP_HF17_IDX_OO_VLAN_VID >> 8) & 0xff,
+		BNXT_ULP_HF17_IDX_OO_VLAN_VID & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+	.spec_operand = {
+		(BNXT_ULP_HF17_IDX_OO_VLAN_VID >> 8) & 0xff,
+		BNXT_ULP_HF17_IDX_OO_VLAN_VID & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 12,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 48,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD,
+	.spec_operand = {
+		(BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff,
+		BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 4,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 4,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 7,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE,
+	.spec_operand = {
+		(BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
+		BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 8,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+	.spec_operand = {
+		(BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff,
+		BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 4,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 4,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 3,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 4,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_operand = {
+		BNXT_ULP_SYM_TUN_HDR_VALID_YES,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 4,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_operand = {
+		BNXT_ULP_SYM_TL4_HDR_TYPE_UDP,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_operand = {
+		BNXT_ULP_SYM_TL4_HDR_VALID_YES,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 4,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_operand = {
+		BNXT_ULP_SYM_TL3_HDR_TYPE_IPV6,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_operand = {
+		BNXT_ULP_SYM_TL3_HDR_VALID_YES,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_operand = {
+		BNXT_ULP_SYM_TL2_HDR_VALID_YES,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 9,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 7,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE,
+	.spec_operand = {
+		(BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
+		BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 59,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 3,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 16,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 16,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 8,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_operand = {
+		BNXT_ULP_SYM_IP_PROTO_UDP,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 128,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+	.spec_operand = {
+		(BNXT_ULP_HF17_IDX_O_IPV6_DST_ADDR >> 8) & 0xff,
+		BNXT_ULP_HF17_IDX_O_IPV6_DST_ADDR & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 128,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 48,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 24,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 10,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+	.spec_operand = {
+		(BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
+		BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 8,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+	.spec_operand = {
+		(BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
+		BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 3,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 3,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 16,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 16,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 8,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_operand = {
+		BNXT_ULP_SYM_IP_PROTO_UDP,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 128,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+	.spec_operand = {
+		(BNXT_ULP_HF17_IDX_O_IPV6_DST_ADDR >> 8) & 0xff,
+		BNXT_ULP_HF17_IDX_O_IPV6_DST_ADDR & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 128,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 48,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 24,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 10,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+	.spec_operand = {
+		(BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
+		BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 8,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+	.spec_operand = {
+		(BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
+		BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 12,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 12,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 48,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+	.spec_operand = {
+		(BNXT_ULP_HF18_IDX_O_ETH_DMAC >> 8) & 0xff,
+		BNXT_ULP_HF18_IDX_O_ETH_DMAC & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 12,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+	.mask_operand = {
+		(BNXT_ULP_HF18_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF18_IDX_SVIF_INDEX & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+	.spec_operand = {
+		(BNXT_ULP_HF18_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF18_IDX_SVIF_INDEX & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 12,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 12,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 48,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 4,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 4,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 7,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE,
+	.spec_operand = {
+		(BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
+		BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 8,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 4,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 4,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 3,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 4,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_operand = {
+		BNXT_ULP_SYM_TUN_HDR_VALID_YES,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 4,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_operand = {
+		BNXT_ULP_SYM_TL4_HDR_TYPE_UDP,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_operand = {
+		BNXT_ULP_SYM_TL4_HDR_VALID_YES,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 4,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_operand = {
+		BNXT_ULP_SYM_TL3_HDR_VALID_YES,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_operand = {
+		BNXT_ULP_SYM_TL2_HDR_VALID_YES,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 9,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 7,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE,
+	.spec_operand = {
+		(BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
+		BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
-	.field_bit_size = 3,
+	.field_bit_size = 1,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
-	.field_bit_size = 3,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
-	.field_bit_size = 16,
+	.field_bit_size = 2,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
-	.field_bit_size = 16,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
-	.field_bit_size = 8,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.spec_operand = {
-		BNXT_ULP_SYM_IP_PROTO_UDP,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	.spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
-	.field_bit_size = 32,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+	.field_bit_size = 8,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
 	.spec_operand = {
-		(BNXT_ULP_HF16_IDX_O_IPV4_DST_ADDR >> 8) & 0xff,
-		BNXT_ULP_HF16_IDX_O_IPV4_DST_ADDR & 0xff,
+		(BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_0 >> 8) & 0xff,
+		BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_0 & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
-	.field_bit_size = 32,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
-	},
-	{
-	.field_bit_size = 48,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
-	},
-	{
-	.field_bit_size = 24,
+	.field_bit_size = 10,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 10,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
 	.spec_operand = {
 		(BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
@@ -9226,14 +10404,16 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = {
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
-	.field_bit_size = 8,
+	.field_bit_size = 4,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 128,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
-	.spec_operand = {
-		(BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
-		BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 12,
@@ -9252,8 +10432,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = {
 		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF17_IDX_O_ETH_DMAC >> 8) & 0xff,
-		BNXT_ULP_HF17_IDX_O_ETH_DMAC & 0xff,
+		(BNXT_ULP_HF19_IDX_O_ETH_DMAC >> 8) & 0xff,
+		BNXT_ULP_HF19_IDX_O_ETH_DMAC & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -9261,31 +10441,26 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = {
 	.field_bit_size = 12,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.mask_operand = {
-		(BNXT_ULP_HF17_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF17_IDX_SVIF_INDEX & 0xff,
+		(BNXT_ULP_HF19_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF19_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF17_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF17_IDX_SVIF_INDEX & 0xff,
+		(BNXT_ULP_HF19_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF19_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
+	.field_bit_size = 4,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
 	.field_bit_size = 12,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
-	.mask_operand = {
-		(BNXT_ULP_HF17_IDX_OO_VLAN_VID >> 8) & 0xff,
-		BNXT_ULP_HF17_IDX_OO_VLAN_VID & 0xff,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
-	.spec_operand = {
-		(BNXT_ULP_HF17_IDX_OO_VLAN_VID >> 8) & 0xff,
-		BNXT_ULP_HF17_IDX_OO_VLAN_VID & 0xff,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 12,
@@ -9307,12 +10482,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD,
-	.spec_operand = {
-		(BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff,
-		BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 4,
@@ -9327,11 +10497,6 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = {
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
-	.field_bit_size = 4,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
-	},
-	{
 	.field_bit_size = 1,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
@@ -9358,12 +10523,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = {
 	{
 	.field_bit_size = 8,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
-	.spec_operand = {
-		(BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff,
-		BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 1,
@@ -9529,11 +10689,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.spec_operand = {
-		BNXT_ULP_SYM_TL3_HDR_TYPE_IPV6,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 1,
@@ -9644,56 +10800,42 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = {
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
-	.field_bit_size = 59,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
-	},
-	{
 	.field_bit_size = 3,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
-	.field_bit_size = 16,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
-	},
-	{
-	.field_bit_size = 16,
+	.field_bit_size = 12,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
-	.field_bit_size = 8,
+	.field_bit_size = 48,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		BNXT_ULP_SYM_IP_PROTO_UDP,
+		(BNXT_ULP_HF19_IDX_I_ETH_DMAC >> 8) & 0xff,
+		BNXT_ULP_HF19_IDX_I_ETH_DMAC & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
-	.field_bit_size = 128,
+	.field_bit_size = 24,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF17_IDX_O_IPV6_DST_ADDR >> 8) & 0xff,
-		BNXT_ULP_HF17_IDX_O_IPV6_DST_ADDR & 0xff,
+		(BNXT_ULP_HF19_IDX_T_VXLAN_VNI >> 8) & 0xff,
+		BNXT_ULP_HF19_IDX_T_VXLAN_VNI & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
-	.field_bit_size = 128,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
-	},
-	{
-	.field_bit_size = 48,
+	.field_bit_size = 3,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
-	.field_bit_size = 24,
+	.field_bit_size = 4,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
@@ -9718,56 +10860,42 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = {
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
-	.field_bit_size = 3,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
-	},
-	{
-	.field_bit_size = 3,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
-	},
-	{
-	.field_bit_size = 16,
+	.field_bit_size = 339,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
-	.field_bit_size = 16,
+	.field_bit_size = 12,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
-	.field_bit_size = 8,
+	.field_bit_size = 48,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		BNXT_ULP_SYM_IP_PROTO_UDP,
+		(BNXT_ULP_HF19_IDX_I_ETH_DMAC >> 8) & 0xff,
+		BNXT_ULP_HF19_IDX_I_ETH_DMAC & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
-	.field_bit_size = 128,
+	.field_bit_size = 24,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF17_IDX_O_IPV6_DST_ADDR >> 8) & 0xff,
-		BNXT_ULP_HF17_IDX_O_IPV6_DST_ADDR & 0xff,
+		(BNXT_ULP_HF19_IDX_T_VXLAN_VNI >> 8) & 0xff,
+		BNXT_ULP_HF19_IDX_T_VXLAN_VNI & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
-	.field_bit_size = 128,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
-	},
-	{
-	.field_bit_size = 48,
+	.field_bit_size = 3,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
-	.field_bit_size = 24,
+	.field_bit_size = 4,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
@@ -9796,8 +10924,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF18_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF18_IDX_SVIF_INDEX & 0xff,
+		(BNXT_ULP_HF20_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF20_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -9820,14 +10948,14 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = {
 	.field_bit_size = 12,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.mask_operand = {
-		(BNXT_ULP_HF18_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF18_IDX_SVIF_INDEX & 0xff,
+		(BNXT_ULP_HF20_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF20_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF18_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF18_IDX_SVIF_INDEX & 0xff,
+		(BNXT_ULP_HF20_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF20_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -10190,8 +11318,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF18_IDX_O_UDP_DST_PORT >> 8) & 0xff,
-		BNXT_ULP_HF18_IDX_O_UDP_DST_PORT & 0xff,
+		(BNXT_ULP_HF20_IDX_O_UDP_DST_PORT >> 8) & 0xff,
+		BNXT_ULP_HF20_IDX_O_UDP_DST_PORT & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -10200,8 +11328,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF18_IDX_O_UDP_SRC_PORT >> 8) & 0xff,
-		BNXT_ULP_HF18_IDX_O_UDP_SRC_PORT & 0xff,
+		(BNXT_ULP_HF20_IDX_O_UDP_SRC_PORT >> 8) & 0xff,
+		BNXT_ULP_HF20_IDX_O_UDP_SRC_PORT & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -10219,8 +11347,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF18_IDX_O_IPV4_DST_ADDR >> 8) & 0xff,
-		BNXT_ULP_HF18_IDX_O_IPV4_DST_ADDR & 0xff,
+		(BNXT_ULP_HF20_IDX_O_IPV4_DST_ADDR >> 8) & 0xff,
+		BNXT_ULP_HF20_IDX_O_IPV4_DST_ADDR & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -10229,8 +11357,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF18_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff,
-		BNXT_ULP_HF18_IDX_O_IPV4_SRC_ADDR & 0xff,
+		(BNXT_ULP_HF20_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff,
+		BNXT_ULP_HF20_IDX_O_IPV4_SRC_ADDR & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -10279,8 +11407,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF18_IDX_O_UDP_DST_PORT >> 8) & 0xff,
-		BNXT_ULP_HF18_IDX_O_UDP_DST_PORT & 0xff,
+		(BNXT_ULP_HF20_IDX_O_UDP_DST_PORT >> 8) & 0xff,
+		BNXT_ULP_HF20_IDX_O_UDP_DST_PORT & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -10289,8 +11417,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF18_IDX_O_UDP_SRC_PORT >> 8) & 0xff,
-		BNXT_ULP_HF18_IDX_O_UDP_SRC_PORT & 0xff,
+		(BNXT_ULP_HF20_IDX_O_UDP_SRC_PORT >> 8) & 0xff,
+		BNXT_ULP_HF20_IDX_O_UDP_SRC_PORT & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -10308,8 +11436,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF18_IDX_O_IPV4_DST_ADDR >> 8) & 0xff,
-		BNXT_ULP_HF18_IDX_O_IPV4_DST_ADDR & 0xff,
+		(BNXT_ULP_HF20_IDX_O_IPV4_DST_ADDR >> 8) & 0xff,
+		BNXT_ULP_HF20_IDX_O_IPV4_DST_ADDR & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -10318,8 +11446,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF18_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff,
-		BNXT_ULP_HF18_IDX_O_IPV4_SRC_ADDR & 0xff,
+		(BNXT_ULP_HF20_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff,
+		BNXT_ULP_HF20_IDX_O_IPV4_SRC_ADDR & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -10358,8 +11486,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF19_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF19_IDX_SVIF_INDEX & 0xff,
+		(BNXT_ULP_HF21_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF21_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -10382,14 +11510,14 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = {
 	.field_bit_size = 12,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.mask_operand = {
-		(BNXT_ULP_HF19_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF19_IDX_SVIF_INDEX & 0xff,
+		(BNXT_ULP_HF21_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF21_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF19_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF19_IDX_SVIF_INDEX & 0xff,
+		(BNXT_ULP_HF21_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF21_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -10748,8 +11876,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF19_IDX_O_TCP_DST_PORT >> 8) & 0xff,
-		BNXT_ULP_HF19_IDX_O_TCP_DST_PORT & 0xff,
+		(BNXT_ULP_HF21_IDX_O_TCP_DST_PORT >> 8) & 0xff,
+		BNXT_ULP_HF21_IDX_O_TCP_DST_PORT & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -10758,8 +11886,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF19_IDX_O_TCP_SRC_PORT >> 8) & 0xff,
-		BNXT_ULP_HF19_IDX_O_TCP_SRC_PORT & 0xff,
+		(BNXT_ULP_HF21_IDX_O_TCP_SRC_PORT >> 8) & 0xff,
+		BNXT_ULP_HF21_IDX_O_TCP_SRC_PORT & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -10777,8 +11905,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF19_IDX_O_IPV4_DST_ADDR >> 8) & 0xff,
-		BNXT_ULP_HF19_IDX_O_IPV4_DST_ADDR & 0xff,
+		(BNXT_ULP_HF21_IDX_O_IPV4_DST_ADDR >> 8) & 0xff,
+		BNXT_ULP_HF21_IDX_O_IPV4_DST_ADDR & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -10787,8 +11915,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF19_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff,
-		BNXT_ULP_HF19_IDX_O_IPV4_SRC_ADDR & 0xff,
+		(BNXT_ULP_HF21_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff,
+		BNXT_ULP_HF21_IDX_O_IPV4_SRC_ADDR & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -10837,8 +11965,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF19_IDX_O_TCP_DST_PORT >> 8) & 0xff,
-		BNXT_ULP_HF19_IDX_O_TCP_DST_PORT & 0xff,
+		(BNXT_ULP_HF21_IDX_O_TCP_DST_PORT >> 8) & 0xff,
+		BNXT_ULP_HF21_IDX_O_TCP_DST_PORT & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -10847,8 +11975,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF19_IDX_O_TCP_SRC_PORT >> 8) & 0xff,
-		BNXT_ULP_HF19_IDX_O_TCP_SRC_PORT & 0xff,
+		(BNXT_ULP_HF21_IDX_O_TCP_SRC_PORT >> 8) & 0xff,
+		BNXT_ULP_HF21_IDX_O_TCP_SRC_PORT & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -10866,8 +11994,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF19_IDX_O_IPV4_DST_ADDR >> 8) & 0xff,
-		BNXT_ULP_HF19_IDX_O_IPV4_DST_ADDR & 0xff,
+		(BNXT_ULP_HF21_IDX_O_IPV4_DST_ADDR >> 8) & 0xff,
+		BNXT_ULP_HF21_IDX_O_IPV4_DST_ADDR & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -10876,8 +12004,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF19_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff,
-		BNXT_ULP_HF19_IDX_O_IPV4_SRC_ADDR & 0xff,
+		(BNXT_ULP_HF21_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff,
+		BNXT_ULP_HF21_IDX_O_IPV4_SRC_ADDR & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -10916,8 +12044,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF20_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF20_IDX_SVIF_INDEX & 0xff,
+		(BNXT_ULP_HF22_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF22_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -10940,14 +12068,14 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = {
 	.field_bit_size = 12,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.mask_operand = {
-		(BNXT_ULP_HF20_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF20_IDX_SVIF_INDEX & 0xff,
+		(BNXT_ULP_HF22_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF22_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF20_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF20_IDX_SVIF_INDEX & 0xff,
+		(BNXT_ULP_HF22_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF22_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -11314,8 +12442,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF20_IDX_O_UDP_DST_PORT >> 8) & 0xff,
-		BNXT_ULP_HF20_IDX_O_UDP_DST_PORT & 0xff,
+		(BNXT_ULP_HF22_IDX_O_UDP_DST_PORT >> 8) & 0xff,
+		BNXT_ULP_HF22_IDX_O_UDP_DST_PORT & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -11324,8 +12452,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF20_IDX_O_UDP_SRC_PORT >> 8) & 0xff,
-		BNXT_ULP_HF20_IDX_O_UDP_SRC_PORT & 0xff,
+		(BNXT_ULP_HF22_IDX_O_UDP_SRC_PORT >> 8) & 0xff,
+		BNXT_ULP_HF22_IDX_O_UDP_SRC_PORT & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -11343,8 +12471,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF20_IDX_O_IPV6_DST_ADDR >> 8) & 0xff,
-		BNXT_ULP_HF20_IDX_O_IPV6_DST_ADDR & 0xff,
+		(BNXT_ULP_HF22_IDX_O_IPV6_DST_ADDR >> 8) & 0xff,
+		BNXT_ULP_HF22_IDX_O_IPV6_DST_ADDR & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -11353,8 +12481,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF20_IDX_O_IPV6_SRC_ADDR >> 8) & 0xff,
-		BNXT_ULP_HF20_IDX_O_IPV6_SRC_ADDR & 0xff,
+		(BNXT_ULP_HF22_IDX_O_IPV6_SRC_ADDR >> 8) & 0xff,
+		BNXT_ULP_HF22_IDX_O_IPV6_SRC_ADDR & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -11403,8 +12531,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF20_IDX_O_UDP_DST_PORT >> 8) & 0xff,
-		BNXT_ULP_HF20_IDX_O_UDP_DST_PORT & 0xff,
+		(BNXT_ULP_HF22_IDX_O_UDP_DST_PORT >> 8) & 0xff,
+		BNXT_ULP_HF22_IDX_O_UDP_DST_PORT & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -11413,8 +12541,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF20_IDX_O_UDP_SRC_PORT >> 8) & 0xff,
-		BNXT_ULP_HF20_IDX_O_UDP_SRC_PORT & 0xff,
+		(BNXT_ULP_HF22_IDX_O_UDP_SRC_PORT >> 8) & 0xff,
+		BNXT_ULP_HF22_IDX_O_UDP_SRC_PORT & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -11432,8 +12560,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF20_IDX_O_IPV6_DST_ADDR >> 8) & 0xff,
-		BNXT_ULP_HF20_IDX_O_IPV6_DST_ADDR & 0xff,
+		(BNXT_ULP_HF22_IDX_O_IPV6_DST_ADDR >> 8) & 0xff,
+		BNXT_ULP_HF22_IDX_O_IPV6_DST_ADDR & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -11442,8 +12570,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF20_IDX_O_IPV6_SRC_ADDR >> 8) & 0xff,
-		BNXT_ULP_HF20_IDX_O_IPV6_SRC_ADDR & 0xff,
+		(BNXT_ULP_HF22_IDX_O_IPV6_SRC_ADDR >> 8) & 0xff,
+		BNXT_ULP_HF22_IDX_O_IPV6_SRC_ADDR & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -11481,9 +12609,9 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = {
 	.field_bit_size = 12,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
-	.spec_operand = {
-		(BNXT_ULP_HF21_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF21_IDX_SVIF_INDEX & 0xff,
+	.spec_operand = {
+		(BNXT_ULP_HF23_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF23_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -11506,14 +12634,14 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = {
 	.field_bit_size = 12,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.mask_operand = {
-		(BNXT_ULP_HF21_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF21_IDX_SVIF_INDEX & 0xff,
+		(BNXT_ULP_HF23_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF23_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF21_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF21_IDX_SVIF_INDEX & 0xff,
+		(BNXT_ULP_HF23_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF23_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -11876,8 +13004,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF21_IDX_O_TCP_DST_PORT >> 8) & 0xff,
-		BNXT_ULP_HF21_IDX_O_TCP_DST_PORT & 0xff,
+		(BNXT_ULP_HF23_IDX_O_TCP_DST_PORT >> 8) & 0xff,
+		BNXT_ULP_HF23_IDX_O_TCP_DST_PORT & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -11886,8 +13014,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF21_IDX_O_TCP_SRC_PORT >> 8) & 0xff,
-		BNXT_ULP_HF21_IDX_O_TCP_SRC_PORT & 0xff,
+		(BNXT_ULP_HF23_IDX_O_TCP_SRC_PORT >> 8) & 0xff,
+		BNXT_ULP_HF23_IDX_O_TCP_SRC_PORT & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -11905,8 +13033,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF21_IDX_O_IPV6_DST_ADDR >> 8) & 0xff,
-		BNXT_ULP_HF21_IDX_O_IPV6_DST_ADDR & 0xff,
+		(BNXT_ULP_HF23_IDX_O_IPV6_DST_ADDR >> 8) & 0xff,
+		BNXT_ULP_HF23_IDX_O_IPV6_DST_ADDR & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -11915,8 +13043,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF21_IDX_O_IPV6_SRC_ADDR >> 8) & 0xff,
-		BNXT_ULP_HF21_IDX_O_IPV6_SRC_ADDR & 0xff,
+		(BNXT_ULP_HF23_IDX_O_IPV6_SRC_ADDR >> 8) & 0xff,
+		BNXT_ULP_HF23_IDX_O_IPV6_SRC_ADDR & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -11965,8 +13093,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF21_IDX_O_TCP_DST_PORT >> 8) & 0xff,
-		BNXT_ULP_HF21_IDX_O_TCP_DST_PORT & 0xff,
+		(BNXT_ULP_HF23_IDX_O_TCP_DST_PORT >> 8) & 0xff,
+		BNXT_ULP_HF23_IDX_O_TCP_DST_PORT & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -11975,8 +13103,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF21_IDX_O_TCP_SRC_PORT >> 8) & 0xff,
-		BNXT_ULP_HF21_IDX_O_TCP_SRC_PORT & 0xff,
+		(BNXT_ULP_HF23_IDX_O_TCP_SRC_PORT >> 8) & 0xff,
+		BNXT_ULP_HF23_IDX_O_TCP_SRC_PORT & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -11994,8 +13122,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF21_IDX_O_IPV6_DST_ADDR >> 8) & 0xff,
-		BNXT_ULP_HF21_IDX_O_IPV6_DST_ADDR & 0xff,
+		(BNXT_ULP_HF23_IDX_O_IPV6_DST_ADDR >> 8) & 0xff,
+		BNXT_ULP_HF23_IDX_O_IPV6_DST_ADDR & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -12004,8 +13132,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF21_IDX_O_IPV6_SRC_ADDR >> 8) & 0xff,
-		BNXT_ULP_HF21_IDX_O_IPV6_SRC_ADDR & 0xff,
+		(BNXT_ULP_HF23_IDX_O_IPV6_SRC_ADDR >> 8) & 0xff,
+		BNXT_ULP_HF23_IDX_O_IPV6_SRC_ADDR & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -12043,14 +13171,14 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = {
 	.field_bit_size = 12,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.mask_operand = {
-		(BNXT_ULP_HF22_IDX_OO_VLAN_VID >> 8) & 0xff,
-		BNXT_ULP_HF22_IDX_OO_VLAN_VID & 0xff,
+		(BNXT_ULP_HF24_IDX_OO_VLAN_VID >> 8) & 0xff,
+		BNXT_ULP_HF24_IDX_OO_VLAN_VID & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF22_IDX_OO_VLAN_VID >> 8) & 0xff,
-		BNXT_ULP_HF22_IDX_OO_VLAN_VID & 0xff,
+		(BNXT_ULP_HF24_IDX_OO_VLAN_VID >> 8) & 0xff,
+		BNXT_ULP_HF24_IDX_OO_VLAN_VID & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -12063,14 +13191,14 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = {
 	.field_bit_size = 48,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.mask_operand = {
-		(BNXT_ULP_HF22_IDX_O_ETH_SMAC >> 8) & 0xff,
-		BNXT_ULP_HF22_IDX_O_ETH_SMAC & 0xff,
+		(BNXT_ULP_HF24_IDX_O_ETH_SMAC >> 8) & 0xff,
+		BNXT_ULP_HF24_IDX_O_ETH_SMAC & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF22_IDX_O_ETH_SMAC >> 8) & 0xff,
-		BNXT_ULP_HF22_IDX_O_ETH_SMAC & 0xff,
+		(BNXT_ULP_HF24_IDX_O_ETH_SMAC >> 8) & 0xff,
+		BNXT_ULP_HF24_IDX_O_ETH_SMAC & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -12078,14 +13206,14 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = {
 	.field_bit_size = 12,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.mask_operand = {
-		(BNXT_ULP_HF22_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF22_IDX_SVIF_INDEX & 0xff,
+		(BNXT_ULP_HF24_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF24_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF22_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF22_IDX_SVIF_INDEX & 0xff,
+		(BNXT_ULP_HF24_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF24_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -12465,8 +13593,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF22_IDX_O_ETH_DMAC >> 8) & 0xff,
-		BNXT_ULP_HF22_IDX_O_ETH_DMAC & 0xff,
+		(BNXT_ULP_HF24_IDX_O_ETH_DMAC >> 8) & 0xff,
+		BNXT_ULP_HF24_IDX_O_ETH_DMAC & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -12515,8 +13643,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF22_IDX_O_ETH_DMAC >> 8) & 0xff,
-		BNXT_ULP_HF22_IDX_O_ETH_DMAC & 0xff,
+		(BNXT_ULP_HF24_IDX_O_ETH_DMAC >> 8) & 0xff,
+		BNXT_ULP_HF24_IDX_O_ETH_DMAC & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -12544,14 +13672,14 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = {
 	.field_bit_size = 12,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.mask_operand = {
-		(BNXT_ULP_HF23_IDX_OO_VLAN_VID >> 8) & 0xff,
-		BNXT_ULP_HF23_IDX_OO_VLAN_VID & 0xff,
+		(BNXT_ULP_HF25_IDX_OO_VLAN_VID >> 8) & 0xff,
+		BNXT_ULP_HF25_IDX_OO_VLAN_VID & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF23_IDX_OO_VLAN_VID >> 8) & 0xff,
-		BNXT_ULP_HF23_IDX_OO_VLAN_VID & 0xff,
+		(BNXT_ULP_HF25_IDX_OO_VLAN_VID >> 8) & 0xff,
+		BNXT_ULP_HF25_IDX_OO_VLAN_VID & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -12564,14 +13692,14 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = {
 	.field_bit_size = 48,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.mask_operand = {
-		(BNXT_ULP_HF23_IDX_O_ETH_SMAC >> 8) & 0xff,
-		BNXT_ULP_HF23_IDX_O_ETH_SMAC & 0xff,
+		(BNXT_ULP_HF25_IDX_O_ETH_SMAC >> 8) & 0xff,
+		BNXT_ULP_HF25_IDX_O_ETH_SMAC & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF23_IDX_O_ETH_SMAC >> 8) & 0xff,
-		BNXT_ULP_HF23_IDX_O_ETH_SMAC & 0xff,
+		(BNXT_ULP_HF25_IDX_O_ETH_SMAC >> 8) & 0xff,
+		BNXT_ULP_HF25_IDX_O_ETH_SMAC & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -12579,14 +13707,14 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = {
 	.field_bit_size = 12,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.mask_operand = {
-		(BNXT_ULP_HF23_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF23_IDX_SVIF_INDEX & 0xff,
+		(BNXT_ULP_HF25_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF25_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF23_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF23_IDX_SVIF_INDEX & 0xff,
+		(BNXT_ULP_HF25_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF25_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -12970,8 +14098,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF23_IDX_O_ETH_DMAC >> 8) & 0xff,
-		BNXT_ULP_HF23_IDX_O_ETH_DMAC & 0xff,
+		(BNXT_ULP_HF25_IDX_O_ETH_DMAC >> 8) & 0xff,
+		BNXT_ULP_HF25_IDX_O_ETH_DMAC & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -13020,8 +14148,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF23_IDX_O_ETH_DMAC >> 8) & 0xff,
-		BNXT_ULP_HF23_IDX_O_ETH_DMAC & 0xff,
+		(BNXT_ULP_HF25_IDX_O_ETH_DMAC >> 8) & 0xff,
+		BNXT_ULP_HF25_IDX_O_ETH_DMAC & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -15685,7 +16813,239 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[]
 	{
 	.field_bit_size = 5,
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.result_operand = {0x19, 0x00, 0x00, 0x00, 0x00, 0x00,
+	.result_operand = {0x19, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 8,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+	.result_operand = {
+		(BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
+		BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 33,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+	.result_operand = {
+		(BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff,
+		BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 5,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 9,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.result_operand = {
+		(0x0185 >> 8) & 0xff,
+		0x0185 & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 11,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 33,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+	.result_operand = {
+		(BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff,
+		BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 5,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 9,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.result_operand = {
+		(0x0185 >> 8) & 0xff,
+		0x0185 & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 11,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 10,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+	.result_operand = {
+		(BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
+		BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 7,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE,
+	.result_operand = {
+		(BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff,
+		BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 4,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD,
+	.result_operand = {
+		(BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
+		BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 8,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 3,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 6,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 3,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 16,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 2,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 10,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+	.result_operand = {
+		(BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
+		BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 4,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 8,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 10,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.result_operand = {
+		(0x00f9 >> 8) & 0xff,
+		0x00f9 & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 5,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
@@ -15736,8 +17096,8 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[]
 	.field_bit_size = 9,
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.result_operand = {
-		(0x0185 >> 8) & 0xff,
-		0x0185 & 0xff,
+		(0x00c5 >> 8) & 0xff,
+		0x00c5 & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -15790,8 +17150,8 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[]
 	.field_bit_size = 9,
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.result_operand = {
-		(0x0185 >> 8) & 0xff,
-		0x0185 & 0xff,
+		(0x00c5 >> 8) & 0xff,
+		0x00c5 & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -16149,7 +17509,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[]
 	{
 	.field_bit_size = 5,
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00,
+	.result_operand = {0x19, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
@@ -16200,8 +17560,8 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[]
 	.field_bit_size = 9,
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.result_operand = {
-		(0x00c5 >> 8) & 0xff,
-		0x00c5 & 0xff,
+		(0x0185 >> 8) & 0xff,
+		0x0185 & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -16254,8 +17614,8 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[]
 	.field_bit_size = 9,
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.result_operand = {
-		(0x00c5 >> 8) & 0xff,
-		0x00c5 & 0xff,
+		(0x0185 >> 8) & 0xff,
+		0x0185 & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -16524,8 +17884,8 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[]
 	.field_bit_size = 7,
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE,
 	.result_operand = {
-		(BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff,
-		BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff,
+		(BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
+		BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -16605,15 +17965,15 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[]
 	.field_bit_size = 10,
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.result_operand = {
-		(0x00f9 >> 8) & 0xff,
-		0x00f9 & 0xff,
+		(0x0031 >> 8) & 0xff,
+		0x0031 & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 5,
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.result_operand = {0x19, 0x00, 0x00, 0x00, 0x00, 0x00,
+	.result_operand = {0x14, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
@@ -16664,8 +18024,8 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[]
 	.field_bit_size = 9,
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.result_operand = {
-		(0x0185 >> 8) & 0xff,
-		0x0185 & 0xff,
+		(0x00c5 >> 8) & 0xff,
+		0x00c5 & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -16718,8 +18078,8 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[]
 	.field_bit_size = 9,
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.result_operand = {
-		(0x0185 >> 8) & 0xff,
-		0x0185 & 0xff,
+		(0x00c5 >> 8) & 0xff,
+		0x00c5 & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -16845,7 +18205,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[]
 	{
 	.field_bit_size = 5,
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.result_operand = {0x14, 0x00, 0x00, 0x00, 0x00, 0x00,
+	.result_operand = {0x18, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
@@ -16896,8 +18256,8 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[]
 	.field_bit_size = 9,
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.result_operand = {
-		(0x00c5 >> 8) & 0xff,
-		0x00c5 & 0xff,
+		(0x0185 >> 8) & 0xff,
+		0x0185 & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -16950,8 +18310,8 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[]
 	.field_bit_size = 9,
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.result_operand = {
-		(0x00c5 >> 8) & 0xff,
-		0x00c5 & 0xff,
+		(0x0185 >> 8) & 0xff,
+		0x0185 & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -16976,6 +18336,10 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[]
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
+	.field_bit_size = 64,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
 	.field_bit_size = 10,
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
 	.result_operand = {
@@ -17054,30 +18418,46 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[]
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
+	.field_bit_size = 10,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+	.result_operand = {
+		(BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_0 >> 8) & 0xff,
+		BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_0 & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
 	.field_bit_size = 4,
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 8,
-	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+	.result_operand = {
+		(BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_0 >> 8) & 0xff,
+		BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_0 & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 1,
-	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 10,
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.result_operand = {
-		(0x0031 >> 8) & 0xff,
-		0x0031 & 0xff,
+		(0x001b >> 8) & 0xff,
+		0x001b & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 5,
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.result_operand = {0x18, 0x00, 0x00, 0x00, 0x00, 0x00,
+	.result_operand = {0x08, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
@@ -17100,6 +18480,146 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[]
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
+	.field_bit_size = 2,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 16,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+	.result_operand = {
+		(BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff,
+		BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 10,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+	.result_operand = {
+		(BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
+		BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 7,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE,
+	.result_operand = {
+		(BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
+		BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 4,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD,
+	.result_operand = {
+		(BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
+		BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 8,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 3,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 6,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 3,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 16,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 2,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 10,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+	.result_operand = {
+		(BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
+		BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 10,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+	.result_operand = {
+		(BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_0 >> 8) & 0xff,
+		BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_0 & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 4,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 8,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 10,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 5,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 8,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
 	.field_bit_size = 33,
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
 	.result_operand = {
@@ -17128,8 +18648,8 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[]
 	.field_bit_size = 9,
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.result_operand = {
-		(0x0185 >> 8) & 0xff,
-		0x0185 & 0xff,
+		(0x006d >> 8) & 0xff,
+		0x006d & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -17182,8 +18702,8 @@ struct bnxt_ulp_mapper_result_field_info ulp_stingray_class_result_field_list[]
 	.field_bit_size = 9,
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.result_operand = {
-		(0x0185 >> 8) & 0xff,
-		0x0185 & 0xff,
+		(0x006d >> 8) & 0xff,
+		0x006d & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -18933,6 +20453,48 @@ struct bnxt_ulp_mapper_ident_info ulp_stingray_class_ident_list[] = {
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+	.ident_type = TF_IDENT_TYPE_EM_PROF,
+	.regfile_idx = BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_0,
+	.ident_bit_size = 10,
+	.ident_bit_pos = 0
+	},
+	{
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+	.ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+	.regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0,
+	.ident_bit_size = 10,
+	.ident_bit_pos = 0
+	},
+	{
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+	.ident_type = TF_IDENT_TYPE_EM_PROF,
+	.regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0,
+	.ident_bit_size = 10,
+	.ident_bit_pos = 0
+	},
+	{
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+	.ident_type = TF_IDENT_TYPE_EM_PROF,
+	.regfile_idx = BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_0,
+	.ident_bit_size = 10,
+	.ident_bit_pos = 0
+	},
+	{
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+	.ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+	.regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0,
+	.ident_bit_size = 10,
+	.ident_bit_pos = 0
+	},
+	{
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+	.ident_type = TF_IDENT_TYPE_EM_PROF,
+	.regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0,
+	.ident_bit_size = 10,
+	.ident_bit_pos = 0
+	},
+	{
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
 	.ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
 	.regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0,
 	.ident_bit_size = 10,
@@ -19002,4 +20564,3 @@ struct bnxt_ulp_mapper_ident_info ulp_stingray_class_ident_list[] = {
 	.ident_bit_pos = 0
 	}
 };
-
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c
index 7f5a316..c5f340d 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c
@@ -90,6 +90,8 @@ uint32_t ulp_act_prop_map_table[] = {
 		BNXT_ULP_ACT_PROP_SZ_ENCAP_UDP,
 	[BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN] =
 		BNXT_ULP_ACT_PROP_SZ_ENCAP_TUN,
+	[BNXT_ULP_ACT_PROP_IDX_JUMP] =
+		BNXT_ULP_ACT_PROP_SZ_JUMP,
 	[BNXT_ULP_ACT_PROP_IDX_LAST] =
 		BNXT_ULP_ACT_PROP_SZ_LAST
 };
@@ -108,8 +110,8 @@ struct bnxt_ulp_rte_act_info ulp_act_info[] = {
 	.proto_act_func          = NULL
 	},
 	[RTE_FLOW_ACTION_TYPE_JUMP] = {
-	.act_type                = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
-	.proto_act_func          = NULL
+	.act_type                = BNXT_ULP_ACT_TYPE_SUPPORTED,
+	.proto_act_func          = ulp_rte_jump_act_handler
 	},
 	[RTE_FLOW_ACTION_TYPE_MARK] = {
 	.act_type                = BNXT_ULP_ACT_TYPE_SUPPORTED,
@@ -369,6 +371,7 @@ struct bnxt_ulp_device_params ulp_device_params[BNXT_ULP_DEVICE_ID_LAST] = {
 	.mark_db_lfid_entries    = 65536,
 	.mark_db_gfid_entries    = 65536,
 	.flow_count_db_entries   = 16384,
+	.fdb_parent_flow_entries = 2,
 	.num_resources_per_flow  = 8,
 	.num_phy_ports           = 2,
 	.ext_cntr_table_type     = 0,
@@ -414,7 +417,7 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = {
 	[5] = {
 	.resource_func           = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
 	.resource_type           = TF_IDENT_TYPE_PROF_FUNC,
-	.glb_regfile_index = BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID,
+	.glb_regfile_index       = BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID,
 	.direction               = TF_DIR_RX
 	},
 	[6] = {
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c
index 39e8ec4..33e7585 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c
@@ -55,9 +55,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
 	.result_bit_size = 64,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -72,9 +72,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
 	.result_bit_size = 32,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_SRC_PTR_0,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_SRC_PTR_0
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -89,9 +89,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
 	.result_bit_size = 32,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_DST_PTR_0,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_DST_PTR_0
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -104,9 +104,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
 	.result_bit_size = 0,
 	.result_num_fields = 0,
 	.encap_num_fields = 12,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_GLOBAL,
-	.index_operand = BNXT_ULP_GLB_REGFILE_INDEX_ENCAP_MAC_PTR,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_GLB_REGFILE_INDEX_ENCAP_MAC_PTR
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -120,9 +120,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
 	.result_bit_size = 128,
 	.result_num_fields = 26,
 	.encap_num_fields = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -136,9 +136,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
 	.result_bit_size = 128,
 	.result_num_fields = 26,
 	.encap_num_fields = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -153,9 +153,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
 	.result_bit_size = 64,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -169,9 +169,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
 	.result_bit_size = 128,
 	.result_num_fields = 26,
 	.encap_num_fields = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -185,9 +185,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
 	.result_bit_size = 128,
 	.result_num_fields = 26,
 	.encap_num_fields = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -202,9 +202,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
 	.result_bit_size = 64,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -218,9 +218,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
 	.result_bit_size = 128,
 	.result_num_fields = 26,
 	.encap_num_fields = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -234,9 +234,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
 	.result_bit_size = 128,
 	.result_num_fields = 26,
 	.encap_num_fields = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -251,9 +251,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
 	.result_bit_size = 64,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -268,9 +268,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
 	.result_bit_size = 0,
 	.result_num_fields = 0,
 	.encap_num_fields = 3,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -285,9 +285,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
 	.result_bit_size = 0,
 	.result_num_fields = 0,
 	.encap_num_fields = 3,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -300,9 +300,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
 	.result_bit_size = 0,
 	.result_num_fields = 0,
 	.encap_num_fields = 12,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -316,9 +316,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
 	.result_bit_size = 128,
 	.result_num_fields = 26,
 	.encap_num_fields = 12,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -332,9 +332,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
 	.result_bit_size = 128,
 	.result_num_fields = 26,
 	.encap_num_fields = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -349,9 +349,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
 	.result_bit_size = 64,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -366,9 +366,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
 	.result_bit_size = 32,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_SRC_PTR_0,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_SRC_PTR_0
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -383,9 +383,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
 	.result_bit_size = 32,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_DST_PTR_0,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_DST_PTR_0
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -399,9 +399,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
 	.result_bit_size = 0,
 	.result_num_fields = 0,
 	.encap_num_fields = 12,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_GLOBAL,
-	.index_operand = BNXT_ULP_GLB_REGFILE_INDEX_ENCAP_MAC_PTR,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_GLB_REGFILE_INDEX_ENCAP_MAC_PTR
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -415,9 +415,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
 	.result_bit_size = 128,
 	.result_num_fields = 26,
 	.encap_num_fields = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -431,9 +431,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
 	.result_bit_size = 128,
 	.result_num_fields = 26,
 	.encap_num_fields = 11,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -448,9 +448,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
 	.result_bit_size = 64,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -466,9 +466,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
 	.result_bit_size = 0,
 	.result_num_fields = 0,
 	.encap_num_fields = 12,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -482,9 +482,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
 	.result_bit_size = 128,
 	.result_num_fields = 26,
 	.encap_num_fields = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -500,9 +500,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
 	.result_bit_size = 128,
 	.result_num_fields = 26,
 	.encap_num_fields = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -518,9 +518,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
 	.result_bit_size = 128,
 	.result_num_fields = 26,
 	.encap_num_fields = 11,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR
 	}
 };
 
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c
index 470d91c..2270691 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c
@@ -96,33 +96,43 @@ struct bnxt_ulp_mapper_tbl_list_info ulp_wh_plus_class_tmpl_list[] = {
 	},
 	[18] = {
 	.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
-	.num_tbls = 6,
+	.num_tbls = 5,
 	.start_tbl_idx = 92
 	},
 	[19] = {
 	.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
-	.num_tbls = 6,
-	.start_tbl_idx = 98
+	.num_tbls = 5,
+	.start_tbl_idx = 97
 	},
 	[20] = {
 	.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
 	.num_tbls = 6,
-	.start_tbl_idx = 104
+	.start_tbl_idx = 102
 	},
 	[21] = {
 	.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
 	.num_tbls = 6,
-	.start_tbl_idx = 110
+	.start_tbl_idx = 108
 	},
 	[22] = {
 	.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
-	.num_tbls = 5,
-	.start_tbl_idx = 116
+	.num_tbls = 6,
+	.start_tbl_idx = 114
 	},
 	[23] = {
 	.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
+	.num_tbls = 6,
+	.start_tbl_idx = 120
+	},
+	[24] = {
+	.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
+	.num_tbls = 5,
+	.start_tbl_idx = 126
+	},
+	[25] = {
+	.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
 	.num_tbls = 5,
-	.start_tbl_idx = 121
+	.start_tbl_idx = 131
 	}
 };
 
@@ -133,6 +143,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL,
 	.direction = TF_DIR_RX,
+	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
 	.result_start_idx = 0,
 	.result_bit_size = 128,
 	.result_num_fields = 26,
@@ -162,8 +173,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 1,
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
@@ -216,6 +227,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_VFR_CFA_ACTION,
 	.direction = TF_DIR_TX,
+	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
 	.result_start_idx = 43,
 	.result_bit_size = 128,
 	.result_num_fields = 26,
@@ -230,8 +242,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
 	.cond_opcode = BNXT_ULP_COND_OPCODE_COMP_FIELD_IS_SET,
 	.cond_operand = BNXT_ULP_CF_IDX_VFR_MODE,
 	.direction = TF_DIR_TX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 14,
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
@@ -270,8 +282,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
 	.cond_opcode = BNXT_ULP_COND_OPCODE_COMP_FIELD_NOT_SET,
 	.cond_operand = BNXT_ULP_CF_IDX_VFR_MODE,
 	.direction = TF_DIR_TX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 28,
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
@@ -324,6 +336,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL,
 	.direction = TF_DIR_TX,
+	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
 	.result_start_idx = 99,
 	.result_bit_size = 0,
 	.result_num_fields = 0,
@@ -338,6 +351,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_VFR_CFA_ACTION,
 	.direction = TF_DIR_TX,
+	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
 	.result_start_idx = 111,
 	.result_bit_size = 128,
 	.result_num_fields = 26,
@@ -367,8 +381,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
 	.direction = TF_DIR_TX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 42,
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
@@ -388,6 +402,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL,
 	.direction = TF_DIR_RX,
+	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
 	.result_start_idx = 150,
 	.result_bit_size = 128,
 	.result_num_fields = 26,
@@ -400,8 +415,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 55,
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
@@ -419,8 +434,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 68,
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
@@ -455,8 +470,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
 	.direction = TF_DIR_TX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 82,
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
@@ -509,6 +524,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL,
 	.direction = TF_DIR_RX,
+	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
 	.result_start_idx = 219,
 	.result_bit_size = 128,
 	.result_num_fields = 26,
@@ -521,8 +537,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 95,
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
@@ -542,6 +558,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_VFR_CFA_ACTION,
 	.direction = TF_DIR_TX,
+	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
 	.result_start_idx = 258,
 	.result_bit_size = 128,
 	.result_num_fields = 26,
@@ -554,8 +571,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 108,
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
@@ -590,8 +607,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_1,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_1,
 	.key_start_idx = 124,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
@@ -645,8 +662,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 189,
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
@@ -681,8 +698,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_1,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_1,
 	.key_start_idx = 205,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
@@ -753,8 +770,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 271,
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
@@ -789,8 +806,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 287,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
@@ -861,8 +878,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 353,
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
@@ -897,8 +914,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 369,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
@@ -969,8 +986,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 435,
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
@@ -1005,8 +1022,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 451,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
@@ -1077,8 +1094,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 517,
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
@@ -1113,8 +1130,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 533,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
@@ -1168,8 +1185,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 598,
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
@@ -1204,8 +1221,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 614,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
@@ -1259,8 +1276,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 679,
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
@@ -1295,8 +1312,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 695,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
@@ -1350,8 +1367,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 760,
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
@@ -1386,8 +1403,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 776,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
@@ -1441,8 +1458,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 841,
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
@@ -1477,8 +1494,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 857,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
@@ -1532,8 +1549,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 922,
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
@@ -1568,8 +1585,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 938,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
@@ -1623,8 +1640,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 1003,
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
@@ -1659,8 +1676,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 1019,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
@@ -1711,29 +1728,29 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES
 	},
 	{
-	.resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE,
-	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+	.resource_type = TF_TBL_TYPE_ACT_STATS_64,
 	.resource_sub_type =
-		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM,
-	.direction = TF_DIR_TX,
-	.key_start_idx = 1084,
-	.blob_key_bit_size = 8,
-	.key_bit_size = 8,
-	.key_num_fields = 1,
+		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT_ACC,
+	.cond_opcode = BNXT_ULP_COND_OPCODE_ACTION_BIT_IS_SET,
+	.cond_operand = BNXT_ULP_ACTION_BIT_COUNT,
+	.direction = TF_DIR_RX,
+	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
 	.result_start_idx = 768,
-	.result_bit_size = 10,
+	.result_bit_size = 64,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
-	.ident_start_idx = 27,
-	.ident_nums = 1
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
+	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
+	.index_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
-	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
-	.direction = TF_DIR_TX,
+	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+	.direction = TF_DIR_RX,
+	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP,
 	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
-	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 1085,
+	.key_start_idx = 1084,
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
 	.key_num_fields = 13,
@@ -1741,8 +1758,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
 	.result_bit_size = 64,
 	.result_num_fields = 13,
 	.encap_num_fields = 0,
-	.ident_start_idx = 28,
-	.ident_nums = 0,
+	.ident_start_idx = 27,
+	.ident_nums = 1,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
 	},
@@ -1751,71 +1768,145 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
 	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
-	.direction = TF_DIR_TX,
-	.key_start_idx = 1098,
+	.direction = TF_DIR_RX,
+	.key_start_idx = 1097,
 	.blob_key_bit_size = 16,
 	.key_bit_size = 16,
 	.key_num_fields = 3,
 	.result_start_idx = 782,
-	.result_bit_size = 10,
-	.result_num_fields = 1,
+	.result_bit_size = 20,
+	.result_num_fields = 2,
 	.encap_num_fields = 0,
 	.ident_start_idx = 28,
-	.ident_nums = 1
+	.ident_nums = 2
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
-	.direction = TF_DIR_TX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
+	.direction = TF_DIR_RX,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 1101,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
+	.key_start_idx = 1100,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
 	.key_num_fields = 43,
-	.result_start_idx = 783,
+	.result_start_idx = 784,
 	.result_bit_size = 38,
 	.result_num_fields = 8,
 	.encap_num_fields = 0,
-	.ident_start_idx = 29,
+	.ident_start_idx = 30,
 	.ident_nums = 0,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
 	},
 	{
-	.resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE,
-	.resource_type = TF_MEM_EXTERNAL,
-	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT,
-	.direction = TF_DIR_TX,
-	.key_start_idx = 1144,
-	.blob_key_bit_size = 448,
-	.key_bit_size = 448,
-	.key_num_fields = 11,
-	.result_start_idx = 791,
-	.result_bit_size = 64,
-	.result_num_fields = 9,
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+	.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+	.direction = TF_DIR_RX,
+	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
+	.key_start_idx = 1143,
+	.blob_key_bit_size = 192,
+	.key_bit_size = 160,
+	.key_num_fields = 5,
+	.result_start_idx = 792,
+	.result_bit_size = 19,
+	.result_num_fields = 3,
 	.encap_num_fields = 0,
-	.ident_start_idx = 29,
+	.ident_start_idx = 30,
 	.ident_nums = 0,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES
 	},
 	{
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+	.direction = TF_DIR_RX,
+	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
+	.key_start_idx = 1148,
+	.blob_key_bit_size = 167,
+	.key_bit_size = 167,
+	.key_num_fields = 13,
+	.result_start_idx = 795,
+	.result_bit_size = 64,
+	.result_num_fields = 13,
+	.encap_num_fields = 0,
+	.ident_start_idx = 30,
+	.ident_nums = 1,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
+	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
+	},
+	{
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE,
+	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+	.resource_sub_type =
+		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
+	.direction = TF_DIR_RX,
+	.key_start_idx = 1161,
+	.blob_key_bit_size = 16,
+	.key_bit_size = 16,
+	.key_num_fields = 3,
+	.result_start_idx = 808,
+	.result_bit_size = 20,
+	.result_num_fields = 2,
+	.encap_num_fields = 0,
+	.ident_start_idx = 31,
+	.ident_nums = 2
+	},
+	{
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+	.direction = TF_DIR_RX,
+	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
+	.key_start_idx = 1164,
+	.blob_key_bit_size = 81,
+	.key_bit_size = 81,
+	.key_num_fields = 43,
+	.result_start_idx = 810,
+	.result_bit_size = 38,
+	.result_num_fields = 8,
+	.encap_num_fields = 0,
+	.ident_start_idx = 33,
+	.ident_nums = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
+	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
+	},
+	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE,
 	.resource_type = TF_MEM_INTERNAL,
 	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT,
-	.direction = TF_DIR_TX,
-	.key_start_idx = 1155,
-	.blob_key_bit_size = 200,
-	.key_bit_size = 200,
-	.key_num_fields = 11,
-	.result_start_idx = 800,
+	.direction = TF_DIR_RX,
+	.key_start_idx = 1207,
+	.blob_key_bit_size = 112,
+	.key_bit_size = 112,
+	.key_num_fields = 8,
+	.result_start_idx = 818,
 	.result_bit_size = 64,
 	.result_num_fields = 9,
 	.encap_num_fields = 0,
-	.ident_start_idx = 29,
+	.ident_start_idx = 33,
 	.ident_nums = 0,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
+	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES
+	},
+	{
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE,
+	.resource_type = TF_MEM_EXTERNAL,
+	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT,
+	.direction = TF_DIR_RX,
+	.key_start_idx = 1215,
+	.blob_key_bit_size = 448,
+	.key_bit_size = 448,
+	.key_num_fields = 8,
+	.result_start_idx = 827,
+	.result_bit_size = 64,
+	.result_num_fields = 9,
+	.encap_num_fields = 0,
+	.ident_start_idx = 33,
+	.ident_nums = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES
 	},
 	{
@@ -1824,32 +1915,32 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1166,
+	.key_start_idx = 1223,
 	.blob_key_bit_size = 8,
 	.key_bit_size = 8,
 	.key_num_fields = 1,
-	.result_start_idx = 809,
+	.result_start_idx = 836,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
-	.ident_start_idx = 29,
+	.ident_start_idx = 33,
 	.ident_nums = 1
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
 	.direction = TF_DIR_TX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 1167,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
+	.key_start_idx = 1224,
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
 	.key_num_fields = 13,
-	.result_start_idx = 810,
+	.result_start_idx = 837,
 	.result_bit_size = 64,
 	.result_num_fields = 13,
 	.encap_num_fields = 0,
-	.ident_start_idx = 30,
+	.ident_start_idx = 34,
 	.ident_nums = 0,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
@@ -1860,32 +1951,32 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1180,
+	.key_start_idx = 1237,
 	.blob_key_bit_size = 16,
 	.key_bit_size = 16,
 	.key_num_fields = 3,
-	.result_start_idx = 823,
+	.result_start_idx = 850,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
-	.ident_start_idx = 30,
+	.ident_start_idx = 34,
 	.ident_nums = 1
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
 	.direction = TF_DIR_TX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 1183,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
+	.key_start_idx = 1240,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
 	.key_num_fields = 43,
-	.result_start_idx = 824,
+	.result_start_idx = 851,
 	.result_bit_size = 38,
 	.result_num_fields = 8,
 	.encap_num_fields = 0,
-	.ident_start_idx = 31,
+	.ident_start_idx = 35,
 	.ident_nums = 0,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
@@ -1895,15 +1986,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
 	.resource_type = TF_MEM_EXTERNAL,
 	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1226,
+	.key_start_idx = 1283,
 	.blob_key_bit_size = 448,
 	.key_bit_size = 448,
 	.key_num_fields = 11,
-	.result_start_idx = 832,
+	.result_start_idx = 859,
 	.result_bit_size = 64,
 	.result_num_fields = 9,
 	.encap_num_fields = 0,
-	.ident_start_idx = 31,
+	.ident_start_idx = 35,
 	.ident_nums = 0,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES
@@ -1913,15 +2004,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
 	.resource_type = TF_MEM_INTERNAL,
 	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1237,
+	.key_start_idx = 1294,
 	.blob_key_bit_size = 200,
 	.key_bit_size = 200,
 	.key_num_fields = 11,
-	.result_start_idx = 841,
+	.result_start_idx = 868,
 	.result_bit_size = 64,
 	.result_num_fields = 9,
 	.encap_num_fields = 0,
-	.ident_start_idx = 31,
+	.ident_start_idx = 35,
 	.ident_nums = 0,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES
@@ -1932,32 +2023,32 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1248,
+	.key_start_idx = 1305,
 	.blob_key_bit_size = 8,
 	.key_bit_size = 8,
 	.key_num_fields = 1,
-	.result_start_idx = 850,
+	.result_start_idx = 877,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
-	.ident_start_idx = 31,
+	.ident_start_idx = 35,
 	.ident_nums = 1
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
 	.direction = TF_DIR_TX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 1249,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
+	.key_start_idx = 1306,
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
 	.key_num_fields = 13,
-	.result_start_idx = 851,
+	.result_start_idx = 878,
 	.result_bit_size = 64,
 	.result_num_fields = 13,
 	.encap_num_fields = 0,
-	.ident_start_idx = 32,
+	.ident_start_idx = 36,
 	.ident_nums = 0,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
@@ -1968,32 +2059,32 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1262,
+	.key_start_idx = 1319,
 	.blob_key_bit_size = 16,
 	.key_bit_size = 16,
 	.key_num_fields = 3,
-	.result_start_idx = 864,
+	.result_start_idx = 891,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
-	.ident_start_idx = 32,
+	.ident_start_idx = 36,
 	.ident_nums = 1
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
 	.direction = TF_DIR_TX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 1265,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
+	.key_start_idx = 1322,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
 	.key_num_fields = 43,
-	.result_start_idx = 865,
+	.result_start_idx = 892,
 	.result_bit_size = 38,
 	.result_num_fields = 8,
 	.encap_num_fields = 0,
-	.ident_start_idx = 33,
+	.ident_start_idx = 37,
 	.ident_nums = 0,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
@@ -2003,15 +2094,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
 	.resource_type = TF_MEM_EXTERNAL,
 	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1308,
+	.key_start_idx = 1365,
 	.blob_key_bit_size = 448,
 	.key_bit_size = 448,
 	.key_num_fields = 11,
-	.result_start_idx = 873,
+	.result_start_idx = 900,
 	.result_bit_size = 64,
 	.result_num_fields = 9,
 	.encap_num_fields = 0,
-	.ident_start_idx = 33,
+	.ident_start_idx = 37,
 	.ident_nums = 0,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES
@@ -2021,15 +2112,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
 	.resource_type = TF_MEM_INTERNAL,
 	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1319,
-	.blob_key_bit_size = 392,
-	.key_bit_size = 392,
+	.key_start_idx = 1376,
+	.blob_key_bit_size = 200,
+	.key_bit_size = 200,
 	.key_num_fields = 11,
-	.result_start_idx = 882,
+	.result_start_idx = 909,
 	.result_bit_size = 64,
 	.result_num_fields = 9,
 	.encap_num_fields = 0,
-	.ident_start_idx = 33,
+	.ident_start_idx = 37,
 	.ident_nums = 0,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES
@@ -2040,32 +2131,32 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1330,
+	.key_start_idx = 1387,
 	.blob_key_bit_size = 8,
 	.key_bit_size = 8,
 	.key_num_fields = 1,
-	.result_start_idx = 891,
+	.result_start_idx = 918,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
-	.ident_start_idx = 33,
+	.ident_start_idx = 37,
 	.ident_nums = 1
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
 	.direction = TF_DIR_TX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 1331,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
+	.key_start_idx = 1388,
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
 	.key_num_fields = 13,
-	.result_start_idx = 892,
+	.result_start_idx = 919,
 	.result_bit_size = 64,
 	.result_num_fields = 13,
 	.encap_num_fields = 0,
-	.ident_start_idx = 34,
+	.ident_start_idx = 38,
 	.ident_nums = 0,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
@@ -2076,32 +2167,140 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1344,
+	.key_start_idx = 1401,
 	.blob_key_bit_size = 16,
 	.key_bit_size = 16,
 	.key_num_fields = 3,
-	.result_start_idx = 905,
+	.result_start_idx = 932,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
-	.ident_start_idx = 34,
+	.ident_start_idx = 38,
 	.ident_nums = 1
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
 	.direction = TF_DIR_TX,
+	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
+	.key_start_idx = 1404,
+	.blob_key_bit_size = 81,
+	.key_bit_size = 81,
+	.key_num_fields = 43,
+	.result_start_idx = 933,
+	.result_bit_size = 38,
+	.result_num_fields = 8,
+	.encap_num_fields = 0,
+	.ident_start_idx = 39,
+	.ident_nums = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
+	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
+	},
+	{
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE,
+	.resource_type = TF_MEM_EXTERNAL,
+	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT,
+	.direction = TF_DIR_TX,
+	.key_start_idx = 1447,
+	.blob_key_bit_size = 448,
+	.key_bit_size = 448,
+	.key_num_fields = 11,
+	.result_start_idx = 941,
+	.result_bit_size = 64,
+	.result_num_fields = 9,
+	.encap_num_fields = 0,
+	.ident_start_idx = 39,
+	.ident_nums = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION,
+	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES
+	},
+	{
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE,
+	.resource_type = TF_MEM_INTERNAL,
+	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT,
+	.direction = TF_DIR_TX,
+	.key_start_idx = 1458,
+	.blob_key_bit_size = 392,
+	.key_bit_size = 392,
+	.key_num_fields = 11,
+	.result_start_idx = 950,
+	.result_bit_size = 64,
+	.result_num_fields = 9,
+	.encap_num_fields = 0,
+	.ident_start_idx = 39,
+	.ident_nums = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION,
+	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES
+	},
+	{
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE,
+	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+	.resource_sub_type =
+		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM,
+	.direction = TF_DIR_TX,
+	.key_start_idx = 1469,
+	.blob_key_bit_size = 8,
+	.key_bit_size = 8,
+	.key_num_fields = 1,
+	.result_start_idx = 959,
+	.result_bit_size = 10,
+	.result_num_fields = 1,
+	.encap_num_fields = 0,
+	.ident_start_idx = 39,
+	.ident_nums = 1
+	},
+	{
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+	.direction = TF_DIR_TX,
+	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
 	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
+	.key_start_idx = 1470,
+	.blob_key_bit_size = 167,
+	.key_bit_size = 167,
+	.key_num_fields = 13,
+	.result_start_idx = 960,
+	.result_bit_size = 64,
+	.result_num_fields = 13,
+	.encap_num_fields = 0,
+	.ident_start_idx = 40,
+	.ident_nums = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
+	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
+	},
+	{
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE,
+	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+	.resource_sub_type =
+		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
+	.direction = TF_DIR_TX,
+	.key_start_idx = 1483,
+	.blob_key_bit_size = 16,
+	.key_bit_size = 16,
+	.key_num_fields = 3,
+	.result_start_idx = 973,
+	.result_bit_size = 10,
+	.result_num_fields = 1,
+	.encap_num_fields = 0,
+	.ident_start_idx = 40,
+	.ident_nums = 1
+	},
+	{
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+	.direction = TF_DIR_TX,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 1347,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
+	.key_start_idx = 1486,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
 	.key_num_fields = 43,
-	.result_start_idx = 906,
+	.result_start_idx = 974,
 	.result_bit_size = 38,
 	.result_num_fields = 8,
 	.encap_num_fields = 0,
-	.ident_start_idx = 35,
+	.ident_start_idx = 41,
 	.ident_nums = 0,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
@@ -2111,15 +2310,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
 	.resource_type = TF_MEM_EXTERNAL,
 	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1390,
+	.key_start_idx = 1529,
 	.blob_key_bit_size = 448,
 	.key_bit_size = 448,
 	.key_num_fields = 11,
-	.result_start_idx = 914,
+	.result_start_idx = 982,
 	.result_bit_size = 64,
 	.result_num_fields = 9,
 	.encap_num_fields = 0,
-	.ident_start_idx = 35,
+	.ident_start_idx = 41,
 	.ident_nums = 0,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES
@@ -2129,15 +2328,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
 	.resource_type = TF_MEM_INTERNAL,
 	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1401,
+	.key_start_idx = 1540,
 	.blob_key_bit_size = 392,
 	.key_bit_size = 392,
 	.key_num_fields = 11,
-	.result_start_idx = 923,
+	.result_start_idx = 991,
 	.result_bit_size = 64,
 	.result_num_fields = 9,
 	.encap_num_fields = 0,
-	.ident_start_idx = 35,
+	.ident_start_idx = 41,
 	.ident_nums = 0,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES
@@ -2146,17 +2345,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
 	.direction = TF_DIR_TX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_UPDATE,
-	.key_start_idx = 1412,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
+	.key_start_idx = 1551,
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
 	.key_num_fields = 13,
-	.result_start_idx = 932,
+	.result_start_idx = 1000,
 	.result_bit_size = 64,
 	.result_num_fields = 13,
 	.encap_num_fields = 0,
-	.ident_start_idx = 35,
+	.ident_start_idx = 41,
 	.ident_nums = 1,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
@@ -2167,32 +2366,32 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1425,
+	.key_start_idx = 1564,
 	.blob_key_bit_size = 16,
 	.key_bit_size = 16,
 	.key_num_fields = 3,
-	.result_start_idx = 945,
+	.result_start_idx = 1013,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
-	.ident_start_idx = 36,
+	.ident_start_idx = 42,
 	.ident_nums = 1
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
 	.direction = TF_DIR_TX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 1428,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
+	.key_start_idx = 1567,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
 	.key_num_fields = 43,
-	.result_start_idx = 946,
+	.result_start_idx = 1014,
 	.result_bit_size = 38,
 	.result_num_fields = 8,
 	.encap_num_fields = 0,
-	.ident_start_idx = 37,
+	.ident_start_idx = 43,
 	.ident_nums = 0,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
@@ -2202,15 +2401,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
 	.resource_type = TF_MEM_EXTERNAL,
 	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1471,
+	.key_start_idx = 1610,
 	.blob_key_bit_size = 448,
 	.key_bit_size = 448,
 	.key_num_fields = 7,
-	.result_start_idx = 954,
+	.result_start_idx = 1022,
 	.result_bit_size = 64,
 	.result_num_fields = 9,
 	.encap_num_fields = 0,
-	.ident_start_idx = 37,
+	.ident_start_idx = 43,
 	.ident_nums = 0,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES
@@ -2220,15 +2419,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
 	.resource_type = TF_MEM_INTERNAL,
 	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1478,
+	.key_start_idx = 1617,
 	.blob_key_bit_size = 104,
 	.key_bit_size = 104,
 	.key_num_fields = 7,
-	.result_start_idx = 963,
+	.result_start_idx = 1031,
 	.result_bit_size = 64,
 	.result_num_fields = 9,
 	.encap_num_fields = 0,
-	.ident_start_idx = 37,
+	.ident_start_idx = 43,
 	.ident_nums = 0,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES
@@ -2237,17 +2436,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
 	.direction = TF_DIR_TX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_UPDATE,
-	.key_start_idx = 1485,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
+	.key_start_idx = 1624,
 	.blob_key_bit_size = 167,
 	.key_bit_size = 167,
 	.key_num_fields = 13,
-	.result_start_idx = 972,
+	.result_start_idx = 1040,
 	.result_bit_size = 64,
 	.result_num_fields = 13,
 	.encap_num_fields = 0,
-	.ident_start_idx = 37,
+	.ident_start_idx = 43,
 	.ident_nums = 1,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
@@ -2258,32 +2457,32 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1498,
+	.key_start_idx = 1637,
 	.blob_key_bit_size = 16,
 	.key_bit_size = 16,
 	.key_num_fields = 3,
-	.result_start_idx = 985,
+	.result_start_idx = 1053,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
-	.ident_start_idx = 38,
+	.ident_start_idx = 44,
 	.ident_nums = 1
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
 	.direction = TF_DIR_TX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 1501,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
+	.key_start_idx = 1640,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
 	.key_num_fields = 43,
-	.result_start_idx = 986,
+	.result_start_idx = 1054,
 	.result_bit_size = 38,
 	.result_num_fields = 8,
 	.encap_num_fields = 0,
-	.ident_start_idx = 39,
+	.ident_start_idx = 45,
 	.ident_nums = 0,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
@@ -2293,15 +2492,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
 	.resource_type = TF_MEM_EXTERNAL,
 	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1544,
+	.key_start_idx = 1683,
 	.blob_key_bit_size = 448,
 	.key_bit_size = 448,
 	.key_num_fields = 7,
-	.result_start_idx = 994,
+	.result_start_idx = 1062,
 	.result_bit_size = 64,
 	.result_num_fields = 9,
 	.encap_num_fields = 0,
-	.ident_start_idx = 39,
+	.ident_start_idx = 45,
 	.ident_nums = 0,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES
@@ -2311,15 +2510,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_class_tbl_list[] = {
 	.resource_type = TF_MEM_INTERNAL,
 	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1551,
+	.key_start_idx = 1690,
 	.blob_key_bit_size = 104,
 	.key_bit_size = 104,
 	.key_num_fields = 7,
-	.result_start_idx = 1003,
+	.result_start_idx = 1071,
 	.result_bit_size = 64,
 	.result_num_fields = 9,
 	.encap_num_fields = 0,
-	.ident_start_idx = 39,
+	.ident_start_idx = 45,
 	.ident_nums = 0,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES
@@ -9152,72 +9351,1051 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = {
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
-	.field_bit_size = 8,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+	.field_bit_size = 8,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+	.spec_operand = {
+		(BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
+		BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 3,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 3,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 16,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 16,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 8,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_operand = {
+		BNXT_ULP_SYM_IP_PROTO_UDP,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 32,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+	.spec_operand = {
+		(BNXT_ULP_HF16_IDX_O_IPV4_DST_ADDR >> 8) & 0xff,
+		BNXT_ULP_HF16_IDX_O_IPV4_DST_ADDR & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 32,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 48,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 24,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 10,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+	.spec_operand = {
+		(BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
+		BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 8,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+	.spec_operand = {
+		(BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
+		BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 12,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 12,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 48,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+	.spec_operand = {
+		(BNXT_ULP_HF17_IDX_O_ETH_DMAC >> 8) & 0xff,
+		BNXT_ULP_HF17_IDX_O_ETH_DMAC & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 8,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+	.mask_operand = {
+		(BNXT_ULP_HF17_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF17_IDX_SVIF_INDEX & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+	.spec_operand = {
+		(BNXT_ULP_HF17_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF17_IDX_SVIF_INDEX & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 4,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 12,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+	.mask_operand = {
+		(BNXT_ULP_HF17_IDX_OO_VLAN_VID >> 8) & 0xff,
+		BNXT_ULP_HF17_IDX_OO_VLAN_VID & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+	.spec_operand = {
+		(BNXT_ULP_HF17_IDX_OO_VLAN_VID >> 8) & 0xff,
+		BNXT_ULP_HF17_IDX_OO_VLAN_VID & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 12,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 48,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD,
+	.spec_operand = {
+		(BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff,
+		BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 4,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 7,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE,
+	.spec_operand = {
+		(BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
+		BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 8,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+	.spec_operand = {
+		(BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff,
+		BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 4,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 4,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 3,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 4,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_operand = {
+		BNXT_ULP_SYM_TUN_HDR_VALID_YES,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 4,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_operand = {
+		BNXT_ULP_SYM_TL4_HDR_TYPE_UDP,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_operand = {
+		BNXT_ULP_SYM_TL4_HDR_VALID_YES,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 4,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_operand = {
+		BNXT_ULP_SYM_TL3_HDR_TYPE_IPV6,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_operand = {
+		BNXT_ULP_SYM_TL3_HDR_VALID_YES,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_operand = {
+		BNXT_ULP_SYM_TL2_HDR_VALID_YES,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 9,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 7,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE,
+	.spec_operand = {
+		(BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
+		BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 59,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 3,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 16,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 16,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 8,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_operand = {
+		BNXT_ULP_SYM_IP_PROTO_UDP,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 128,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+	.spec_operand = {
+		(BNXT_ULP_HF17_IDX_O_IPV6_DST_ADDR >> 8) & 0xff,
+		BNXT_ULP_HF17_IDX_O_IPV6_DST_ADDR & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 128,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 48,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 24,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 10,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+	.spec_operand = {
+		(BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
+		BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 8,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+	.spec_operand = {
+		(BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
+		BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 3,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 3,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 16,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 16,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 8,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_operand = {
+		BNXT_ULP_SYM_IP_PROTO_UDP,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 128,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+	.spec_operand = {
+		(BNXT_ULP_HF17_IDX_O_IPV6_DST_ADDR >> 8) & 0xff,
+		BNXT_ULP_HF17_IDX_O_IPV6_DST_ADDR & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 128,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 48,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 24,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 10,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+	.spec_operand = {
+		(BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
+		BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 8,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+	.spec_operand = {
+		(BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
+		BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 12,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 12,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 48,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+	.spec_operand = {
+		(BNXT_ULP_HF18_IDX_O_ETH_DMAC >> 8) & 0xff,
+		BNXT_ULP_HF18_IDX_O_ETH_DMAC & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 8,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+	.mask_operand = {
+		(BNXT_ULP_HF18_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF18_IDX_SVIF_INDEX & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+	.spec_operand = {
+		(BNXT_ULP_HF18_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF18_IDX_SVIF_INDEX & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 4,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 12,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 12,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 48,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 4,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 7,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE,
+	.spec_operand = {
+		(BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
+		BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 8,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 4,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 4,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 3,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 4,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_operand = {
+		BNXT_ULP_SYM_TUN_HDR_VALID_YES,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 4,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_operand = {
+		BNXT_ULP_SYM_TL4_HDR_TYPE_UDP,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_operand = {
+		BNXT_ULP_SYM_TL4_HDR_VALID_YES,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 4,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_operand = {
+		BNXT_ULP_SYM_TL3_HDR_VALID_YES,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_operand = {
+		BNXT_ULP_SYM_TL2_HDR_VALID_YES,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 9,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 7,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE,
 	.spec_operand = {
-		(BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
-		BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
+		(BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
+		BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
-	.field_bit_size = 3,
+	.field_bit_size = 1,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
-	.field_bit_size = 3,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
-	.field_bit_size = 16,
+	.field_bit_size = 2,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
-	.field_bit_size = 16,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
-	.field_bit_size = 8,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.spec_operand = {
-		BNXT_ULP_SYM_IP_PROTO_UDP,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	.spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
-	.field_bit_size = 32,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+	.field_bit_size = 8,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
 	.spec_operand = {
-		(BNXT_ULP_HF16_IDX_O_IPV4_DST_ADDR >> 8) & 0xff,
-		BNXT_ULP_HF16_IDX_O_IPV4_DST_ADDR & 0xff,
+		(BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_0 >> 8) & 0xff,
+		BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_0 & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
-	.field_bit_size = 32,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
-	},
-	{
-	.field_bit_size = 48,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
-	},
-	{
-	.field_bit_size = 24,
+	.field_bit_size = 10,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 10,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
 	.spec_operand = {
 		(BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
@@ -9226,14 +10404,16 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = {
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
-	.field_bit_size = 8,
+	.field_bit_size = 4,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 128,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
-	.spec_operand = {
-		(BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
-		BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 12,
@@ -9252,8 +10432,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = {
 		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF17_IDX_O_ETH_DMAC >> 8) & 0xff,
-		BNXT_ULP_HF17_IDX_O_ETH_DMAC & 0xff,
+		(BNXT_ULP_HF19_IDX_O_ETH_DMAC >> 8) & 0xff,
+		BNXT_ULP_HF19_IDX_O_ETH_DMAC & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -9261,14 +10441,14 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = {
 	.field_bit_size = 8,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.mask_operand = {
-		(BNXT_ULP_HF17_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF17_IDX_SVIF_INDEX & 0xff,
+		(BNXT_ULP_HF19_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF19_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF17_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF17_IDX_SVIF_INDEX & 0xff,
+		(BNXT_ULP_HF19_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF19_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -9279,18 +10459,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = {
 	},
 	{
 	.field_bit_size = 12,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
-	.mask_operand = {
-		(BNXT_ULP_HF17_IDX_OO_VLAN_VID >> 8) & 0xff,
-		BNXT_ULP_HF17_IDX_OO_VLAN_VID & 0xff,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
-	.spec_operand = {
-		(BNXT_ULP_HF17_IDX_OO_VLAN_VID >> 8) & 0xff,
-		BNXT_ULP_HF17_IDX_OO_VLAN_VID & 0xff,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 12,
@@ -9312,12 +10482,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD,
-	.spec_operand = {
-		(BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff,
-		BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 4,
@@ -9358,12 +10523,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = {
 	{
 	.field_bit_size = 8,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
-	.spec_operand = {
-		(BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff,
-		BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 1,
@@ -9529,11 +10689,7 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.spec_operand = {
-		BNXT_ULP_SYM_TL3_HDR_TYPE_IPV6,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 1,
@@ -9644,56 +10800,42 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = {
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
-	.field_bit_size = 59,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
-	},
-	{
 	.field_bit_size = 3,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
-	.field_bit_size = 16,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
-	},
-	{
-	.field_bit_size = 16,
+	.field_bit_size = 12,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
-	.field_bit_size = 8,
+	.field_bit_size = 48,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		BNXT_ULP_SYM_IP_PROTO_UDP,
+		(BNXT_ULP_HF19_IDX_I_ETH_DMAC >> 8) & 0xff,
+		BNXT_ULP_HF19_IDX_I_ETH_DMAC & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
-	.field_bit_size = 128,
+	.field_bit_size = 24,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF17_IDX_O_IPV6_DST_ADDR >> 8) & 0xff,
-		BNXT_ULP_HF17_IDX_O_IPV6_DST_ADDR & 0xff,
+		(BNXT_ULP_HF19_IDX_T_VXLAN_VNI >> 8) & 0xff,
+		BNXT_ULP_HF19_IDX_T_VXLAN_VNI & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
-	.field_bit_size = 128,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
-	},
-	{
-	.field_bit_size = 48,
+	.field_bit_size = 3,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
-	.field_bit_size = 24,
+	.field_bit_size = 4,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
@@ -9718,56 +10860,42 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = {
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
-	.field_bit_size = 3,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
-	},
-	{
-	.field_bit_size = 3,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
-	},
-	{
-	.field_bit_size = 16,
+	.field_bit_size = 339,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
-	.field_bit_size = 16,
+	.field_bit_size = 12,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
-	.field_bit_size = 8,
+	.field_bit_size = 48,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		BNXT_ULP_SYM_IP_PROTO_UDP,
+		(BNXT_ULP_HF19_IDX_I_ETH_DMAC >> 8) & 0xff,
+		BNXT_ULP_HF19_IDX_I_ETH_DMAC & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
-	.field_bit_size = 128,
+	.field_bit_size = 24,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF17_IDX_O_IPV6_DST_ADDR >> 8) & 0xff,
-		BNXT_ULP_HF17_IDX_O_IPV6_DST_ADDR & 0xff,
+		(BNXT_ULP_HF19_IDX_T_VXLAN_VNI >> 8) & 0xff,
+		BNXT_ULP_HF19_IDX_T_VXLAN_VNI & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
-	.field_bit_size = 128,
-	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
-	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
-	},
-	{
-	.field_bit_size = 48,
+	.field_bit_size = 3,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
-	.field_bit_size = 24,
+	.field_bit_size = 4,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
@@ -9796,8 +10924,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF18_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF18_IDX_SVIF_INDEX & 0xff,
+		(BNXT_ULP_HF20_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF20_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -9820,14 +10948,14 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = {
 	.field_bit_size = 8,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.mask_operand = {
-		(BNXT_ULP_HF18_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF18_IDX_SVIF_INDEX & 0xff,
+		(BNXT_ULP_HF20_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF20_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF18_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF18_IDX_SVIF_INDEX & 0xff,
+		(BNXT_ULP_HF20_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF20_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -10190,8 +11318,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF18_IDX_O_UDP_DST_PORT >> 8) & 0xff,
-		BNXT_ULP_HF18_IDX_O_UDP_DST_PORT & 0xff,
+		(BNXT_ULP_HF20_IDX_O_UDP_DST_PORT >> 8) & 0xff,
+		BNXT_ULP_HF20_IDX_O_UDP_DST_PORT & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -10200,8 +11328,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF18_IDX_O_UDP_SRC_PORT >> 8) & 0xff,
-		BNXT_ULP_HF18_IDX_O_UDP_SRC_PORT & 0xff,
+		(BNXT_ULP_HF20_IDX_O_UDP_SRC_PORT >> 8) & 0xff,
+		BNXT_ULP_HF20_IDX_O_UDP_SRC_PORT & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -10219,8 +11347,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF18_IDX_O_IPV4_DST_ADDR >> 8) & 0xff,
-		BNXT_ULP_HF18_IDX_O_IPV4_DST_ADDR & 0xff,
+		(BNXT_ULP_HF20_IDX_O_IPV4_DST_ADDR >> 8) & 0xff,
+		BNXT_ULP_HF20_IDX_O_IPV4_DST_ADDR & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -10229,8 +11357,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF18_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff,
-		BNXT_ULP_HF18_IDX_O_IPV4_SRC_ADDR & 0xff,
+		(BNXT_ULP_HF20_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff,
+		BNXT_ULP_HF20_IDX_O_IPV4_SRC_ADDR & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -10279,8 +11407,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF18_IDX_O_UDP_DST_PORT >> 8) & 0xff,
-		BNXT_ULP_HF18_IDX_O_UDP_DST_PORT & 0xff,
+		(BNXT_ULP_HF20_IDX_O_UDP_DST_PORT >> 8) & 0xff,
+		BNXT_ULP_HF20_IDX_O_UDP_DST_PORT & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -10289,8 +11417,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF18_IDX_O_UDP_SRC_PORT >> 8) & 0xff,
-		BNXT_ULP_HF18_IDX_O_UDP_SRC_PORT & 0xff,
+		(BNXT_ULP_HF20_IDX_O_UDP_SRC_PORT >> 8) & 0xff,
+		BNXT_ULP_HF20_IDX_O_UDP_SRC_PORT & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -10308,8 +11436,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF18_IDX_O_IPV4_DST_ADDR >> 8) & 0xff,
-		BNXT_ULP_HF18_IDX_O_IPV4_DST_ADDR & 0xff,
+		(BNXT_ULP_HF20_IDX_O_IPV4_DST_ADDR >> 8) & 0xff,
+		BNXT_ULP_HF20_IDX_O_IPV4_DST_ADDR & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -10318,8 +11446,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF18_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff,
-		BNXT_ULP_HF18_IDX_O_IPV4_SRC_ADDR & 0xff,
+		(BNXT_ULP_HF20_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff,
+		BNXT_ULP_HF20_IDX_O_IPV4_SRC_ADDR & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -10358,8 +11486,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF19_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF19_IDX_SVIF_INDEX & 0xff,
+		(BNXT_ULP_HF21_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF21_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -10382,14 +11510,14 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = {
 	.field_bit_size = 8,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.mask_operand = {
-		(BNXT_ULP_HF19_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF19_IDX_SVIF_INDEX & 0xff,
+		(BNXT_ULP_HF21_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF21_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF19_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF19_IDX_SVIF_INDEX & 0xff,
+		(BNXT_ULP_HF21_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF21_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -10748,8 +11876,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF19_IDX_O_TCP_DST_PORT >> 8) & 0xff,
-		BNXT_ULP_HF19_IDX_O_TCP_DST_PORT & 0xff,
+		(BNXT_ULP_HF21_IDX_O_TCP_DST_PORT >> 8) & 0xff,
+		BNXT_ULP_HF21_IDX_O_TCP_DST_PORT & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -10758,8 +11886,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF19_IDX_O_TCP_SRC_PORT >> 8) & 0xff,
-		BNXT_ULP_HF19_IDX_O_TCP_SRC_PORT & 0xff,
+		(BNXT_ULP_HF21_IDX_O_TCP_SRC_PORT >> 8) & 0xff,
+		BNXT_ULP_HF21_IDX_O_TCP_SRC_PORT & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -10777,8 +11905,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF19_IDX_O_IPV4_DST_ADDR >> 8) & 0xff,
-		BNXT_ULP_HF19_IDX_O_IPV4_DST_ADDR & 0xff,
+		(BNXT_ULP_HF21_IDX_O_IPV4_DST_ADDR >> 8) & 0xff,
+		BNXT_ULP_HF21_IDX_O_IPV4_DST_ADDR & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -10787,8 +11915,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF19_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff,
-		BNXT_ULP_HF19_IDX_O_IPV4_SRC_ADDR & 0xff,
+		(BNXT_ULP_HF21_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff,
+		BNXT_ULP_HF21_IDX_O_IPV4_SRC_ADDR & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -10837,8 +11965,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF19_IDX_O_TCP_DST_PORT >> 8) & 0xff,
-		BNXT_ULP_HF19_IDX_O_TCP_DST_PORT & 0xff,
+		(BNXT_ULP_HF21_IDX_O_TCP_DST_PORT >> 8) & 0xff,
+		BNXT_ULP_HF21_IDX_O_TCP_DST_PORT & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -10847,8 +11975,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF19_IDX_O_TCP_SRC_PORT >> 8) & 0xff,
-		BNXT_ULP_HF19_IDX_O_TCP_SRC_PORT & 0xff,
+		(BNXT_ULP_HF21_IDX_O_TCP_SRC_PORT >> 8) & 0xff,
+		BNXT_ULP_HF21_IDX_O_TCP_SRC_PORT & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -10866,8 +11994,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF19_IDX_O_IPV4_DST_ADDR >> 8) & 0xff,
-		BNXT_ULP_HF19_IDX_O_IPV4_DST_ADDR & 0xff,
+		(BNXT_ULP_HF21_IDX_O_IPV4_DST_ADDR >> 8) & 0xff,
+		BNXT_ULP_HF21_IDX_O_IPV4_DST_ADDR & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -10876,8 +12004,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF19_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff,
-		BNXT_ULP_HF19_IDX_O_IPV4_SRC_ADDR & 0xff,
+		(BNXT_ULP_HF21_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff,
+		BNXT_ULP_HF21_IDX_O_IPV4_SRC_ADDR & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -10916,8 +12044,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF20_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF20_IDX_SVIF_INDEX & 0xff,
+		(BNXT_ULP_HF22_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF22_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -10940,14 +12068,14 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = {
 	.field_bit_size = 8,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.mask_operand = {
-		(BNXT_ULP_HF20_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF20_IDX_SVIF_INDEX & 0xff,
+		(BNXT_ULP_HF22_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF22_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF20_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF20_IDX_SVIF_INDEX & 0xff,
+		(BNXT_ULP_HF22_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF22_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -11314,8 +12442,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF20_IDX_O_UDP_DST_PORT >> 8) & 0xff,
-		BNXT_ULP_HF20_IDX_O_UDP_DST_PORT & 0xff,
+		(BNXT_ULP_HF22_IDX_O_UDP_DST_PORT >> 8) & 0xff,
+		BNXT_ULP_HF22_IDX_O_UDP_DST_PORT & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -11324,8 +12452,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF20_IDX_O_UDP_SRC_PORT >> 8) & 0xff,
-		BNXT_ULP_HF20_IDX_O_UDP_SRC_PORT & 0xff,
+		(BNXT_ULP_HF22_IDX_O_UDP_SRC_PORT >> 8) & 0xff,
+		BNXT_ULP_HF22_IDX_O_UDP_SRC_PORT & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -11343,8 +12471,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF20_IDX_O_IPV6_DST_ADDR >> 8) & 0xff,
-		BNXT_ULP_HF20_IDX_O_IPV6_DST_ADDR & 0xff,
+		(BNXT_ULP_HF22_IDX_O_IPV6_DST_ADDR >> 8) & 0xff,
+		BNXT_ULP_HF22_IDX_O_IPV6_DST_ADDR & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -11353,8 +12481,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF20_IDX_O_IPV6_SRC_ADDR >> 8) & 0xff,
-		BNXT_ULP_HF20_IDX_O_IPV6_SRC_ADDR & 0xff,
+		(BNXT_ULP_HF22_IDX_O_IPV6_SRC_ADDR >> 8) & 0xff,
+		BNXT_ULP_HF22_IDX_O_IPV6_SRC_ADDR & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -11403,8 +12531,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF20_IDX_O_UDP_DST_PORT >> 8) & 0xff,
-		BNXT_ULP_HF20_IDX_O_UDP_DST_PORT & 0xff,
+		(BNXT_ULP_HF22_IDX_O_UDP_DST_PORT >> 8) & 0xff,
+		BNXT_ULP_HF22_IDX_O_UDP_DST_PORT & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -11413,8 +12541,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF20_IDX_O_UDP_SRC_PORT >> 8) & 0xff,
-		BNXT_ULP_HF20_IDX_O_UDP_SRC_PORT & 0xff,
+		(BNXT_ULP_HF22_IDX_O_UDP_SRC_PORT >> 8) & 0xff,
+		BNXT_ULP_HF22_IDX_O_UDP_SRC_PORT & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -11432,8 +12560,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF20_IDX_O_IPV6_DST_ADDR >> 8) & 0xff,
-		BNXT_ULP_HF20_IDX_O_IPV6_DST_ADDR & 0xff,
+		(BNXT_ULP_HF22_IDX_O_IPV6_DST_ADDR >> 8) & 0xff,
+		BNXT_ULP_HF22_IDX_O_IPV6_DST_ADDR & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -11442,8 +12570,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF20_IDX_O_IPV6_SRC_ADDR >> 8) & 0xff,
-		BNXT_ULP_HF20_IDX_O_IPV6_SRC_ADDR & 0xff,
+		(BNXT_ULP_HF22_IDX_O_IPV6_SRC_ADDR >> 8) & 0xff,
+		BNXT_ULP_HF22_IDX_O_IPV6_SRC_ADDR & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -11481,9 +12609,9 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = {
 	.field_bit_size = 8,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
-	.spec_operand = {
-		(BNXT_ULP_HF21_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF21_IDX_SVIF_INDEX & 0xff,
+	.spec_operand = {
+		(BNXT_ULP_HF23_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF23_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -11506,14 +12634,14 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = {
 	.field_bit_size = 8,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.mask_operand = {
-		(BNXT_ULP_HF21_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF21_IDX_SVIF_INDEX & 0xff,
+		(BNXT_ULP_HF23_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF23_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF21_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF21_IDX_SVIF_INDEX & 0xff,
+		(BNXT_ULP_HF23_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF23_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -11876,8 +13004,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF21_IDX_O_TCP_DST_PORT >> 8) & 0xff,
-		BNXT_ULP_HF21_IDX_O_TCP_DST_PORT & 0xff,
+		(BNXT_ULP_HF23_IDX_O_TCP_DST_PORT >> 8) & 0xff,
+		BNXT_ULP_HF23_IDX_O_TCP_DST_PORT & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -11886,8 +13014,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF21_IDX_O_TCP_SRC_PORT >> 8) & 0xff,
-		BNXT_ULP_HF21_IDX_O_TCP_SRC_PORT & 0xff,
+		(BNXT_ULP_HF23_IDX_O_TCP_SRC_PORT >> 8) & 0xff,
+		BNXT_ULP_HF23_IDX_O_TCP_SRC_PORT & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -11905,8 +13033,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF21_IDX_O_IPV6_DST_ADDR >> 8) & 0xff,
-		BNXT_ULP_HF21_IDX_O_IPV6_DST_ADDR & 0xff,
+		(BNXT_ULP_HF23_IDX_O_IPV6_DST_ADDR >> 8) & 0xff,
+		BNXT_ULP_HF23_IDX_O_IPV6_DST_ADDR & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -11915,8 +13043,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF21_IDX_O_IPV6_SRC_ADDR >> 8) & 0xff,
-		BNXT_ULP_HF21_IDX_O_IPV6_SRC_ADDR & 0xff,
+		(BNXT_ULP_HF23_IDX_O_IPV6_SRC_ADDR >> 8) & 0xff,
+		BNXT_ULP_HF23_IDX_O_IPV6_SRC_ADDR & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -11965,8 +13093,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF21_IDX_O_TCP_DST_PORT >> 8) & 0xff,
-		BNXT_ULP_HF21_IDX_O_TCP_DST_PORT & 0xff,
+		(BNXT_ULP_HF23_IDX_O_TCP_DST_PORT >> 8) & 0xff,
+		BNXT_ULP_HF23_IDX_O_TCP_DST_PORT & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -11975,8 +13103,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF21_IDX_O_TCP_SRC_PORT >> 8) & 0xff,
-		BNXT_ULP_HF21_IDX_O_TCP_SRC_PORT & 0xff,
+		(BNXT_ULP_HF23_IDX_O_TCP_SRC_PORT >> 8) & 0xff,
+		BNXT_ULP_HF23_IDX_O_TCP_SRC_PORT & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -11994,8 +13122,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF21_IDX_O_IPV6_DST_ADDR >> 8) & 0xff,
-		BNXT_ULP_HF21_IDX_O_IPV6_DST_ADDR & 0xff,
+		(BNXT_ULP_HF23_IDX_O_IPV6_DST_ADDR >> 8) & 0xff,
+		BNXT_ULP_HF23_IDX_O_IPV6_DST_ADDR & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -12004,8 +13132,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF21_IDX_O_IPV6_SRC_ADDR >> 8) & 0xff,
-		BNXT_ULP_HF21_IDX_O_IPV6_SRC_ADDR & 0xff,
+		(BNXT_ULP_HF23_IDX_O_IPV6_SRC_ADDR >> 8) & 0xff,
+		BNXT_ULP_HF23_IDX_O_IPV6_SRC_ADDR & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -12043,14 +13171,14 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = {
 	.field_bit_size = 12,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.mask_operand = {
-		(BNXT_ULP_HF22_IDX_OO_VLAN_VID >> 8) & 0xff,
-		BNXT_ULP_HF22_IDX_OO_VLAN_VID & 0xff,
+		(BNXT_ULP_HF24_IDX_OO_VLAN_VID >> 8) & 0xff,
+		BNXT_ULP_HF24_IDX_OO_VLAN_VID & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF22_IDX_OO_VLAN_VID >> 8) & 0xff,
-		BNXT_ULP_HF22_IDX_OO_VLAN_VID & 0xff,
+		(BNXT_ULP_HF24_IDX_OO_VLAN_VID >> 8) & 0xff,
+		BNXT_ULP_HF24_IDX_OO_VLAN_VID & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -12063,14 +13191,14 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = {
 	.field_bit_size = 48,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.mask_operand = {
-		(BNXT_ULP_HF22_IDX_O_ETH_SMAC >> 8) & 0xff,
-		BNXT_ULP_HF22_IDX_O_ETH_SMAC & 0xff,
+		(BNXT_ULP_HF24_IDX_O_ETH_SMAC >> 8) & 0xff,
+		BNXT_ULP_HF24_IDX_O_ETH_SMAC & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF22_IDX_O_ETH_SMAC >> 8) & 0xff,
-		BNXT_ULP_HF22_IDX_O_ETH_SMAC & 0xff,
+		(BNXT_ULP_HF24_IDX_O_ETH_SMAC >> 8) & 0xff,
+		BNXT_ULP_HF24_IDX_O_ETH_SMAC & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -12078,14 +13206,14 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = {
 	.field_bit_size = 8,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.mask_operand = {
-		(BNXT_ULP_HF22_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF22_IDX_SVIF_INDEX & 0xff,
+		(BNXT_ULP_HF24_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF24_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF22_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF22_IDX_SVIF_INDEX & 0xff,
+		(BNXT_ULP_HF24_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF24_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -12465,8 +13593,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF22_IDX_O_ETH_DMAC >> 8) & 0xff,
-		BNXT_ULP_HF22_IDX_O_ETH_DMAC & 0xff,
+		(BNXT_ULP_HF24_IDX_O_ETH_DMAC >> 8) & 0xff,
+		BNXT_ULP_HF24_IDX_O_ETH_DMAC & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -12515,8 +13643,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF22_IDX_O_ETH_DMAC >> 8) & 0xff,
-		BNXT_ULP_HF22_IDX_O_ETH_DMAC & 0xff,
+		(BNXT_ULP_HF24_IDX_O_ETH_DMAC >> 8) & 0xff,
+		BNXT_ULP_HF24_IDX_O_ETH_DMAC & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -12544,14 +13672,14 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = {
 	.field_bit_size = 12,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.mask_operand = {
-		(BNXT_ULP_HF23_IDX_OO_VLAN_VID >> 8) & 0xff,
-		BNXT_ULP_HF23_IDX_OO_VLAN_VID & 0xff,
+		(BNXT_ULP_HF25_IDX_OO_VLAN_VID >> 8) & 0xff,
+		BNXT_ULP_HF25_IDX_OO_VLAN_VID & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF23_IDX_OO_VLAN_VID >> 8) & 0xff,
-		BNXT_ULP_HF23_IDX_OO_VLAN_VID & 0xff,
+		(BNXT_ULP_HF25_IDX_OO_VLAN_VID >> 8) & 0xff,
+		BNXT_ULP_HF25_IDX_OO_VLAN_VID & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -12564,14 +13692,14 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = {
 	.field_bit_size = 48,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.mask_operand = {
-		(BNXT_ULP_HF23_IDX_O_ETH_SMAC >> 8) & 0xff,
-		BNXT_ULP_HF23_IDX_O_ETH_SMAC & 0xff,
+		(BNXT_ULP_HF25_IDX_O_ETH_SMAC >> 8) & 0xff,
+		BNXT_ULP_HF25_IDX_O_ETH_SMAC & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF23_IDX_O_ETH_SMAC >> 8) & 0xff,
-		BNXT_ULP_HF23_IDX_O_ETH_SMAC & 0xff,
+		(BNXT_ULP_HF25_IDX_O_ETH_SMAC >> 8) & 0xff,
+		BNXT_ULP_HF25_IDX_O_ETH_SMAC & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -12579,14 +13707,14 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = {
 	.field_bit_size = 8,
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.mask_operand = {
-		(BNXT_ULP_HF23_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF23_IDX_SVIF_INDEX & 0xff,
+		(BNXT_ULP_HF25_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF25_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF23_IDX_SVIF_INDEX >> 8) & 0xff,
-		BNXT_ULP_HF23_IDX_SVIF_INDEX & 0xff,
+		(BNXT_ULP_HF25_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF25_IDX_SVIF_INDEX & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -12970,8 +14098,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF23_IDX_O_ETH_DMAC >> 8) & 0xff,
-		BNXT_ULP_HF23_IDX_O_ETH_DMAC & 0xff,
+		(BNXT_ULP_HF25_IDX_O_ETH_DMAC >> 8) & 0xff,
+		BNXT_ULP_HF25_IDX_O_ETH_DMAC & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -13020,8 +14148,8 @@ struct bnxt_ulp_mapper_key_field_info ulp_wh_plus_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
 	.spec_operand = {
-		(BNXT_ULP_HF23_IDX_O_ETH_DMAC >> 8) & 0xff,
-		BNXT_ULP_HF23_IDX_O_ETH_DMAC & 0xff,
+		(BNXT_ULP_HF25_IDX_O_ETH_DMAC >> 8) & 0xff,
+		BNXT_ULP_HF25_IDX_O_ETH_DMAC & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -15685,7 +16813,239 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] =
 	{
 	.field_bit_size = 5,
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.result_operand = {0x19, 0x00, 0x00, 0x00, 0x00, 0x00,
+	.result_operand = {0x19, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 8,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+	.result_operand = {
+		(BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
+		BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 33,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+	.result_operand = {
+		(BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff,
+		BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 5,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 9,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.result_operand = {
+		(0x0185 >> 8) & 0xff,
+		0x0185 & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 11,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 33,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+	.result_operand = {
+		(BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff,
+		BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 5,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.result_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 9,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.result_operand = {
+		(0x0185 >> 8) & 0xff,
+		0x0185 & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 11,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 10,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+	.result_operand = {
+		(BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
+		BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 7,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE,
+	.result_operand = {
+		(BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff,
+		BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 4,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD,
+	.result_operand = {
+		(BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
+		BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 8,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 3,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 6,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 3,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 16,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 2,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 10,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+	.result_operand = {
+		(BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
+		BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 4,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 8,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 10,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.result_operand = {
+		(0x00f9 >> 8) & 0xff,
+		0x00f9 & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 5,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
@@ -15736,8 +17096,8 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] =
 	.field_bit_size = 9,
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.result_operand = {
-		(0x0185 >> 8) & 0xff,
-		0x0185 & 0xff,
+		(0x00c5 >> 8) & 0xff,
+		0x00c5 & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -15790,8 +17150,8 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] =
 	.field_bit_size = 9,
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.result_operand = {
-		(0x0185 >> 8) & 0xff,
-		0x0185 & 0xff,
+		(0x00c5 >> 8) & 0xff,
+		0x00c5 & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -16149,7 +17509,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] =
 	{
 	.field_bit_size = 5,
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.result_operand = {0x15, 0x00, 0x00, 0x00, 0x00, 0x00,
+	.result_operand = {0x19, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
@@ -16200,8 +17560,8 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] =
 	.field_bit_size = 9,
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.result_operand = {
-		(0x00c5 >> 8) & 0xff,
-		0x00c5 & 0xff,
+		(0x0185 >> 8) & 0xff,
+		0x0185 & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -16254,8 +17614,8 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] =
 	.field_bit_size = 9,
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.result_operand = {
-		(0x00c5 >> 8) & 0xff,
-		0x00c5 & 0xff,
+		(0x0185 >> 8) & 0xff,
+		0x0185 & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -16524,8 +17884,8 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] =
 	.field_bit_size = 7,
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE,
 	.result_operand = {
-		(BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID >> 8) & 0xff,
-		BNXT_ULP_GLB_REGFILE_INDEX_L2_PROF_FUNC_ID & 0xff,
+		(BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
+		BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -16605,15 +17965,15 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] =
 	.field_bit_size = 10,
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.result_operand = {
-		(0x00f9 >> 8) & 0xff,
-		0x00f9 & 0xff,
+		(0x0031 >> 8) & 0xff,
+		0x0031 & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 5,
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.result_operand = {0x19, 0x00, 0x00, 0x00, 0x00, 0x00,
+	.result_operand = {0x14, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
@@ -16664,8 +18024,8 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] =
 	.field_bit_size = 9,
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.result_operand = {
-		(0x0185 >> 8) & 0xff,
-		0x0185 & 0xff,
+		(0x00c5 >> 8) & 0xff,
+		0x00c5 & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -16718,8 +18078,8 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] =
 	.field_bit_size = 9,
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.result_operand = {
-		(0x0185 >> 8) & 0xff,
-		0x0185 & 0xff,
+		(0x00c5 >> 8) & 0xff,
+		0x00c5 & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -16845,7 +18205,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] =
 	{
 	.field_bit_size = 5,
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.result_operand = {0x14, 0x00, 0x00, 0x00, 0x00, 0x00,
+	.result_operand = {0x18, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
@@ -16896,8 +18256,8 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] =
 	.field_bit_size = 9,
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.result_operand = {
-		(0x00c5 >> 8) & 0xff,
-		0x00c5 & 0xff,
+		(0x0185 >> 8) & 0xff,
+		0x0185 & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -16950,8 +18310,8 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] =
 	.field_bit_size = 9,
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.result_operand = {
-		(0x00c5 >> 8) & 0xff,
-		0x00c5 & 0xff,
+		(0x0185 >> 8) & 0xff,
+		0x0185 & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -16976,6 +18336,10 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] =
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
+	.field_bit_size = 64,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
 	.field_bit_size = 10,
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
 	.result_operand = {
@@ -17054,30 +18418,46 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] =
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
+	.field_bit_size = 10,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+	.result_operand = {
+		(BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_0 >> 8) & 0xff,
+		BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_0 & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
 	.field_bit_size = 4,
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
 	.field_bit_size = 8,
-	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+	.result_operand = {
+		(BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_0 >> 8) & 0xff,
+		BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_0 & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 1,
-	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 10,
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.result_operand = {
-		(0x0031 >> 8) & 0xff,
-		0x0031 & 0xff,
+		(0x001b >> 8) & 0xff,
+		0x001b & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
 	.field_bit_size = 5,
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
-	.result_operand = {0x18, 0x00, 0x00, 0x00, 0x00, 0x00,
+	.result_operand = {0x08, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
 	{
@@ -17100,6 +18480,146 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] =
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
 	},
 	{
+	.field_bit_size = 2,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.result_operand = {0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 16,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+	.result_operand = {
+		(BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff,
+		BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 10,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+	.result_operand = {
+		(BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
+		BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 7,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE,
+	.result_operand = {
+		(BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
+		BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 4,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD,
+	.result_operand = {
+		(BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
+		BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 8,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 3,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 6,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 3,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 16,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 2,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 10,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+	.result_operand = {
+		(BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
+		BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 10,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+	.result_operand = {
+		(BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_0 >> 8) & 0xff,
+		BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_0 & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 4,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 8,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 10,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 5,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 8,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
 	.field_bit_size = 33,
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
 	.result_operand = {
@@ -17128,8 +18648,8 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] =
 	.field_bit_size = 9,
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.result_operand = {
-		(0x0185 >> 8) & 0xff,
-		0x0185 & 0xff,
+		(0x006d >> 8) & 0xff,
+		0x006d & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -17182,8 +18702,8 @@ struct bnxt_ulp_mapper_result_field_info ulp_wh_plus_class_result_field_list[] =
 	.field_bit_size = 9,
 	.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
 	.result_operand = {
-		(0x0185 >> 8) & 0xff,
-		0x0185 & 0xff,
+		(0x006d >> 8) & 0xff,
+		0x006d & 0xff,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
 	},
@@ -18933,6 +20453,48 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+	.ident_type = TF_IDENT_TYPE_EM_PROF,
+	.regfile_idx = BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_0,
+	.ident_bit_size = 10,
+	.ident_bit_pos = 0
+	},
+	{
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+	.ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+	.regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0,
+	.ident_bit_size = 10,
+	.ident_bit_pos = 0
+	},
+	{
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+	.ident_type = TF_IDENT_TYPE_EM_PROF,
+	.regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0,
+	.ident_bit_size = 10,
+	.ident_bit_pos = 0
+	},
+	{
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+	.ident_type = TF_IDENT_TYPE_EM_PROF,
+	.regfile_idx = BNXT_ULP_REGFILE_INDEX_WC_PROFILE_ID_0,
+	.ident_bit_size = 10,
+	.ident_bit_pos = 0
+	},
+	{
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+	.ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
+	.regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0,
+	.ident_bit_size = 10,
+	.ident_bit_pos = 0
+	},
+	{
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+	.ident_type = TF_IDENT_TYPE_EM_PROF,
+	.regfile_idx = BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0,
+	.ident_bit_size = 10,
+	.ident_bit_pos = 0
+	},
+	{
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
 	.ident_type = TF_IDENT_TYPE_L2_CTXT_HIGH,
 	.regfile_idx = BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0,
 	.ident_bit_size = 10,
@@ -19002,4 +20564,3 @@ struct bnxt_ulp_mapper_ident_info ulp_wh_plus_class_ident_list[] = {
 	.ident_bit_pos = 0
 	}
 };
-
-- 
2.7.4


^ permalink raw reply	[flat|nested] 32+ messages in thread

* [dpdk-dev] [PATCH 14/14] net/bnxt: add VXLAN decap offload support
  2020-10-17  6:27 [dpdk-dev] [PATCH 00/14] bnxt patches Venkat Duvvuru
                   ` (12 preceding siblings ...)
  2020-10-17  6:28 ` [dpdk-dev] [PATCH 13/14] net/bnxt: add support for VXLAN decap templates Venkat Duvvuru
@ 2020-10-17  6:28 ` Venkat Duvvuru
  2020-10-20 21:55 ` [dpdk-dev] [PATCH v2 00/11] bnxt fixes and enhancements to TRUFLOW support Ajit Khaparde
  14 siblings, 0 replies; 32+ messages in thread
From: Venkat Duvvuru @ 2020-10-17  6:28 UTC (permalink / raw)
  To: dev; +Cc: Venkat Duvvuru

vxlan decap offload can happen in stages. The offload request may
not come as a single flow request rather may come as two flow offload
requests F1 & F2. This patch is adding support for this two stage
offload design. The match criteria for F1 is O_DMAC, O_SMAC,
O_DST_IP, O_UDP_DPORT and actions are COUNT, MARK, JUMP. The match
criteria for F2 is O_SRC_IP, O_DST_IP, VNI and inner header fields.
F1 and F2 flow offload requests can come in any order. If F2 flow
offload request comes first then F2 can’t be offloaded as there is
no O_DMAC information in F2. In this case, F2 will be deferred until
F1 flow offload request arrives. When F1 flow offload request is
received it will have O_DMAC information. Using F1’s O_DMAC, driver
creates an L2 context entry in the hardware as part of offloading F1.
F2 will now use F1’s O_DMAC to get the L2 context id associated with
this O_DMAC and other flow fields that are cached already at the time
of deferring F2 for offloading. F2s that arrive after F1 is offloaded
will be directly programmed and not cached.

Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
Reviewed-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
---
 drivers/net/bnxt/meson.build                   |   1 +
 drivers/net/bnxt/tf_ulp/bnxt_tf_common.h       |   4 +-
 drivers/net/bnxt/tf_ulp/bnxt_ulp.c             |  10 +
 drivers/net/bnxt/tf_ulp/bnxt_ulp.h             |  12 +
 drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c        |  84 +++----
 drivers/net/bnxt/tf_ulp/ulp_flow_db.c          | 149 +++++++++---
 drivers/net/bnxt/tf_ulp/ulp_flow_db.h          |   2 +
 drivers/net/bnxt/tf_ulp/ulp_mapper.c           |   1 +
 drivers/net/bnxt/tf_ulp/ulp_mapper.h           |   2 +
 drivers/net/bnxt/tf_ulp/ulp_rte_parser.c       |  75 +++++-
 drivers/net/bnxt/tf_ulp/ulp_rte_parser.h       |   4 +-
 drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h |   4 +-
 drivers/net/bnxt/tf_ulp/ulp_template_struct.h  |   7 +
 drivers/net/bnxt/tf_ulp/ulp_tun.c              | 310 +++++++++++++++++++++++++
 drivers/net/bnxt/tf_ulp/ulp_tun.h              |  92 ++++++++
 15 files changed, 675 insertions(+), 82 deletions(-)
 create mode 100644 drivers/net/bnxt/tf_ulp/ulp_tun.c
 create mode 100644 drivers/net/bnxt/tf_ulp/ulp_tun.h

diff --git a/drivers/net/bnxt/meson.build b/drivers/net/bnxt/meson.build
index 3952108..bc74f88 100644
--- a/drivers/net/bnxt/meson.build
+++ b/drivers/net/bnxt/meson.build
@@ -64,6 +64,7 @@ sources = files('bnxt_cpr.c',
 	'tf_ulp/ulp_port_db.c',
 	'tf_ulp/ulp_def_rules.c',
 	'tf_ulp/ulp_fc_mgr.c',
+	'tf_ulp/ulp_tun.c',
 	'tf_ulp/ulp_template_db_wh_plus_act.c',
 	'tf_ulp/ulp_template_db_wh_plus_class.c',
 	'tf_ulp/ulp_template_db_stingray_act.c',
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h b/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h
index f0633f0..b2629e4 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h
+++ b/drivers/net/bnxt/tf_ulp/bnxt_tf_common.h
@@ -33,7 +33,9 @@
 enum bnxt_tf_rc {
 	BNXT_TF_RC_PARSE_ERR	= -2,
 	BNXT_TF_RC_ERROR	= -1,
-	BNXT_TF_RC_SUCCESS	= 0
+	BNXT_TF_RC_SUCCESS	= 0,
+	BNXT_TF_RC_NORMAL	= 1,
+	BNXT_TF_RC_FID		= 2,
 };
 
 /* eth IPv4 Type */
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
index d753b5a..26fd300 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
@@ -1321,6 +1321,16 @@ bnxt_ulp_cntxt_ptr2_flow_db_get(struct bnxt_ulp_context	*ulp_ctx)
 	return ulp_ctx->cfg_data->flow_db;
 }
 
+/* Function to get the tunnel cache table info from the ulp context. */
+struct bnxt_tun_cache_entry *
+bnxt_ulp_cntxt_ptr2_tun_tbl_get(struct bnxt_ulp_context *ulp_ctx)
+{
+	if (!ulp_ctx || !ulp_ctx->cfg_data)
+		return NULL;
+
+	return ulp_ctx->cfg_data->tun_tbl;
+}
+
 /* Function to get the ulp context from eth device. */
 struct bnxt_ulp_context	*
 bnxt_ulp_eth_dev_ptr2_cntxt_get(struct rte_eth_dev	*dev)
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
index c2c5bcb..db1ee50 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
@@ -13,6 +13,8 @@
 #include "rte_ethdev.h"
 
 #include "ulp_template_db_enum.h"
+#include "ulp_tun.h"
+#include "bnxt_tf_common.h"
 
 /* NAT defines to reuse existing inner L2 SMAC and DMAC */
 #define BNXT_ULP_NAT_INNER_L2_HEADER_SMAC	0x2000
@@ -55,6 +57,9 @@ struct bnxt_ulp_data {
 	struct bnxt_ulp_df_rule_info	df_rule_info[RTE_MAX_ETHPORTS];
 	struct bnxt_ulp_vfr_rule_info	vfr_rule_info[RTE_MAX_ETHPORTS];
 	enum bnxt_ulp_flow_mem_type	mem_type;
+#define	BNXT_ULP_TUN_ENTRY_INVALID	-1
+#define	BNXT_ULP_MAX_TUN_CACHE_ENTRIES	16
+	struct bnxt_tun_cache_entry	tun_tbl[BNXT_ULP_MAX_TUN_CACHE_ENTRIES];
 };
 
 struct bnxt_ulp_context {
@@ -151,6 +156,10 @@ bnxt_ulp_cntxt_ptr2_flow_db_set(struct bnxt_ulp_context	*ulp_ctx,
 struct bnxt_ulp_flow_db	*
 bnxt_ulp_cntxt_ptr2_flow_db_get(struct bnxt_ulp_context	*ulp_ctx);
 
+/* Function to get the tunnel cache table info from the ulp context. */
+struct bnxt_tun_cache_entry *
+bnxt_ulp_cntxt_ptr2_tun_tbl_get(struct bnxt_ulp_context	*ulp_ctx);
+
 /* Function to get the ulp context from eth device. */
 struct bnxt_ulp_context	*
 bnxt_ulp_eth_dev_ptr2_cntxt_get(struct rte_eth_dev *dev);
@@ -214,4 +223,7 @@ bnxt_ulp_cntxt_acquire_fdb_lock(struct bnxt_ulp_context	*ulp_ctx);
 void
 bnxt_ulp_cntxt_release_fdb_lock(struct bnxt_ulp_context	*ulp_ctx);
 
+int32_t
+ulp_post_process_tun_flow(struct ulp_rte_parser_params *params);
+
 #endif /* _BNXT_ULP_H_ */
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
index 47fbaba..75a7dbe 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
@@ -77,24 +77,22 @@ bnxt_ulp_set_dir_attributes(struct ulp_rte_parser_params *params,
 void
 bnxt_ulp_init_mapper_params(struct bnxt_ulp_mapper_create_parms *mapper_cparms,
 			    struct ulp_rte_parser_params *params,
-			    uint32_t priority, uint32_t class_id,
-			    uint32_t act_tmpl, uint16_t func_id,
-			    uint32_t fid,
 			    enum bnxt_ulp_fdb_type flow_type)
 {
-	mapper_cparms->app_priority = priority;
-	mapper_cparms->dir_attr = params->dir_attr;
-
-	mapper_cparms->class_tid = class_id;
-	mapper_cparms->act_tid = act_tmpl;
-	mapper_cparms->func_id = func_id;
-	mapper_cparms->hdr_bitmap = &params->hdr_bitmap;
-	mapper_cparms->hdr_field = params->hdr_field;
-	mapper_cparms->comp_fld = params->comp_fld;
-	mapper_cparms->act = &params->act_bitmap;
-	mapper_cparms->act_prop = &params->act_prop;
-	mapper_cparms->flow_type = flow_type;
-	mapper_cparms->flow_id = fid;
+	mapper_cparms->flow_type	= flow_type;
+	mapper_cparms->app_priority	= params->priority;
+	mapper_cparms->dir_attr		= params->dir_attr;
+	mapper_cparms->class_tid	= params->class_id;
+	mapper_cparms->act_tid		= params->act_tmpl;
+	mapper_cparms->func_id		= params->func_id;
+	mapper_cparms->hdr_bitmap	= &params->hdr_bitmap;
+	mapper_cparms->hdr_field	= params->hdr_field;
+	mapper_cparms->comp_fld		= params->comp_fld;
+	mapper_cparms->act		= &params->act_bitmap;
+	mapper_cparms->act_prop		= &params->act_prop;
+	mapper_cparms->flow_id		= params->fid;
+	mapper_cparms->parent_flow	= params->parent_flow;
+	mapper_cparms->parent_fid	= params->parent_fid;
 }
 
 /* Function to create the rte flow. */
@@ -109,7 +107,6 @@ bnxt_ulp_flow_create(struct rte_eth_dev *dev,
 	struct ulp_rte_parser_params params;
 	struct bnxt_ulp_context *ulp_ctx;
 	int rc, ret = BNXT_TF_RC_ERROR;
-	uint32_t class_id, act_tmpl;
 	struct rte_flow *flow_id;
 	uint16_t func_id;
 	uint32_t fid;
@@ -118,13 +115,13 @@ bnxt_ulp_flow_create(struct rte_eth_dev *dev,
 					pattern, actions,
 					error) == BNXT_TF_RC_ERROR) {
 		BNXT_TF_DBG(ERR, "Invalid arguments being passed\n");
-		goto parse_err1;
+		goto flow_error;
 	}
 
 	ulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(dev);
 	if (!ulp_ctx) {
 		BNXT_TF_DBG(ERR, "ULP context is not initialized\n");
-		goto parse_err1;
+		goto flow_error;
 	}
 
 	/* Initialize the parser params */
@@ -145,13 +142,13 @@ bnxt_ulp_flow_create(struct rte_eth_dev *dev,
 					 dev->data->port_id,
 					 &func_id)) {
 		BNXT_TF_DBG(ERR, "conversion of port to func id failed\n");
-		goto parse_err1;
+		goto flow_error;
 	}
 
 	/* Protect flow creation */
 	if (bnxt_ulp_cntxt_acquire_fdb_lock(ulp_ctx)) {
 		BNXT_TF_DBG(ERR, "Flow db lock acquire failed\n");
-		goto parse_err1;
+		goto flow_error;
 	}
 
 	/* Allocate a Flow ID for attaching all resources for the flow to.
@@ -162,50 +159,55 @@ bnxt_ulp_flow_create(struct rte_eth_dev *dev,
 				   func_id, &fid);
 	if (rc) {
 		BNXT_TF_DBG(ERR, "Unable to allocate flow table entry\n");
-		goto parse_err2;
+		goto release_lock;
 	}
 
 	/* Parse the rte flow pattern */
 	ret = bnxt_ulp_rte_parser_hdr_parse(pattern, &params);
 	if (ret != BNXT_TF_RC_SUCCESS)
-		goto parse_err3;
+		goto free_fid;
 
 	/* Parse the rte flow action */
 	ret = bnxt_ulp_rte_parser_act_parse(actions, &params);
 	if (ret != BNXT_TF_RC_SUCCESS)
-		goto parse_err3;
+		goto free_fid;
 
+	params.fid = fid;
+	params.func_id = func_id;
+	params.priority = attr->priority;
 	/* Perform the rte flow post process */
 	ret = bnxt_ulp_rte_parser_post_process(&params);
-	if (ret != BNXT_TF_RC_SUCCESS)
-		goto parse_err3;
+	if (ret == BNXT_TF_RC_ERROR)
+		goto free_fid;
+	else if (ret == BNXT_TF_RC_FID)
+		goto return_fid;
 
-	ret = ulp_matcher_pattern_match(&params, &class_id);
+	ret = ulp_matcher_pattern_match(&params, &params.class_id);
 	if (ret != BNXT_TF_RC_SUCCESS)
-		goto parse_err3;
+		goto free_fid;
 
-	ret = ulp_matcher_action_match(&params, &act_tmpl);
+	ret = ulp_matcher_action_match(&params, &params.act_tmpl);
 	if (ret != BNXT_TF_RC_SUCCESS)
-		goto parse_err3;
+		goto free_fid;
 
-	bnxt_ulp_init_mapper_params(&mapper_cparms, &params, attr->priority,
-				    class_id, act_tmpl, func_id, fid,
+	bnxt_ulp_init_mapper_params(&mapper_cparms, &params,
 				    BNXT_ULP_FDB_TYPE_REGULAR);
 	/* Call the ulp mapper to create the flow in the hardware. */
 	ret = ulp_mapper_flow_create(ulp_ctx, &mapper_cparms);
 	if (ret)
-		goto parse_err3;
+		goto free_fid;
 
+return_fid:
 	bnxt_ulp_cntxt_release_fdb_lock(ulp_ctx);
 
 	flow_id = (struct rte_flow *)((uintptr_t)fid);
 	return flow_id;
 
-parse_err3:
+free_fid:
 	ulp_flow_db_fid_free(ulp_ctx, BNXT_ULP_FDB_TYPE_REGULAR, fid);
-parse_err2:
+release_lock:
 	bnxt_ulp_cntxt_release_fdb_lock(ulp_ctx);
-parse_err1:
+flow_error:
 	rte_flow_error_set(error, ret, RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
 			   "Failed to create flow.");
 	return NULL;
@@ -219,10 +221,10 @@ bnxt_ulp_flow_validate(struct rte_eth_dev *dev,
 		       const struct rte_flow_action actions[],
 		       struct rte_flow_error *error)
 {
-	struct ulp_rte_parser_params		params;
+	struct ulp_rte_parser_params params;
+	struct bnxt_ulp_context *ulp_ctx;
 	uint32_t class_id, act_tmpl;
 	int ret = BNXT_TF_RC_ERROR;
-	struct bnxt_ulp_context *ulp_ctx;
 
 	if (bnxt_ulp_flow_validate_args(attr,
 					pattern, actions,
@@ -256,8 +258,10 @@ bnxt_ulp_flow_validate(struct rte_eth_dev *dev,
 
 	/* Perform the rte flow post process */
 	ret = bnxt_ulp_rte_parser_post_process(&params);
-	if (ret != BNXT_TF_RC_SUCCESS)
+	if (ret == BNXT_TF_RC_ERROR)
 		goto parse_error;
+	else if (ret == BNXT_TF_RC_FID)
+		return 0;
 
 	ret = ulp_matcher_pattern_match(&params, &class_id);
 
@@ -283,10 +287,10 @@ bnxt_ulp_flow_destroy(struct rte_eth_dev *dev,
 		      struct rte_flow *flow,
 		      struct rte_flow_error *error)
 {
-	int ret = 0;
 	struct bnxt_ulp_context *ulp_ctx;
 	uint32_t flow_id;
 	uint16_t func_id;
+	int ret;
 
 	ulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(dev);
 	if (!ulp_ctx) {
diff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c
index 8780c01..5e7c8ab 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c
@@ -11,6 +11,7 @@
 #include "ulp_mapper.h"
 #include "ulp_flow_db.h"
 #include "ulp_fc_mgr.h"
+#include "ulp_tun.h"
 
 #define ULP_FLOW_DB_RES_DIR_BIT		31
 #define ULP_FLOW_DB_RES_DIR_MASK	0x80000000
@@ -375,6 +376,101 @@ ulp_flow_db_parent_tbl_deinit(struct bnxt_ulp_flow_db *flow_db)
 	}
 }
 
+/* internal validation function for parent flow tbl */
+static struct bnxt_ulp_flow_db *
+ulp_flow_db_parent_arg_validation(struct bnxt_ulp_context *ulp_ctxt,
+				  uint32_t fid)
+{
+	struct bnxt_ulp_flow_db *flow_db;
+
+	flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);
+	if (!flow_db) {
+		BNXT_TF_DBG(ERR, "Invalid Arguments\n");
+		return NULL;
+	}
+
+	/* check for max flows */
+	if (fid >= flow_db->flow_tbl.num_flows || !fid) {
+		BNXT_TF_DBG(ERR, "Invalid flow index\n");
+		return NULL;
+	}
+
+	/* No support for parent child db then just exit */
+	if (!flow_db->parent_child_db.entries_count) {
+		BNXT_TF_DBG(ERR, "parent child db not supported\n");
+		return NULL;
+	}
+
+	return flow_db;
+}
+
+/*
+ * Set the tunnel index in the parent flow
+ *
+ * ulp_ctxt [in] Ptr to ulp_context
+ * parent_idx [in] The parent index of the parent flow entry
+ *
+ * returns index on success and negative on failure.
+ */
+static int32_t
+ulp_flow_db_parent_tun_idx_set(struct bnxt_ulp_context *ulp_ctxt,
+			       uint32_t parent_idx, uint8_t tun_idx)
+{
+	struct bnxt_ulp_flow_db *flow_db;
+	struct ulp_fdb_parent_child_db *p_pdb;
+
+	flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);
+	if (!flow_db) {
+		BNXT_TF_DBG(ERR, "Invalid Arguments\n");
+		return -EINVAL;
+	}
+
+	/* check for parent idx validity */
+	p_pdb = &flow_db->parent_child_db;
+	if (parent_idx >= p_pdb->entries_count ||
+	    !p_pdb->parent_flow_tbl[parent_idx].parent_fid) {
+		BNXT_TF_DBG(ERR, "Invalid parent flow index %x\n", parent_idx);
+		return -EINVAL;
+	}
+
+	p_pdb->parent_flow_tbl[parent_idx].tun_idx = tun_idx;
+	return 0;
+}
+
+/*
+ * Get the tunnel index from the parent flow
+ *
+ * ulp_ctxt [in] Ptr to ulp_context
+ * parent_fid [in] The flow id of the parent flow entry
+ *
+ * returns 0 if counter accum is set else -1.
+ */
+static int32_t
+ulp_flow_db_parent_tun_idx_get(struct bnxt_ulp_context *ulp_ctxt,
+			       uint32_t parent_fid, uint8_t *tun_idx)
+{
+	struct bnxt_ulp_flow_db *flow_db;
+	struct ulp_fdb_parent_child_db *p_pdb;
+	uint32_t idx;
+
+	/* validate the arguments */
+	flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, parent_fid);
+	if (!flow_db) {
+		BNXT_TF_DBG(ERR, "parent child db validation failed\n");
+		return -EINVAL;
+	}
+
+	p_pdb = &flow_db->parent_child_db;
+	for (idx = 0; idx < p_pdb->entries_count; idx++) {
+		if (p_pdb->parent_flow_tbl[idx].parent_fid == parent_fid) {
+			*tun_idx = p_pdb->parent_flow_tbl[idx].tun_idx;
+			return 0;
+		}
+	}
+
+	return -EINVAL;
+}
+
 /*
  * Initialize the flow database. Memory is allocated in this
  * call and assigned to the flow database.
@@ -663,6 +759,9 @@ ulp_flow_db_resource_del(struct bnxt_ulp_context *ulp_ctxt,
 	struct bnxt_ulp_flow_tbl *flow_tbl;
 	struct ulp_fdb_resource_info *nxt_resource, *fid_resource;
 	uint32_t nxt_idx = 0;
+	struct bnxt_tun_cache_entry *tun_tbl;
+	uint8_t tun_idx = 0;
+	int rc;
 
 	flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);
 	if (!flow_db) {
@@ -739,6 +838,18 @@ ulp_flow_db_resource_del(struct bnxt_ulp_context *ulp_ctxt,
 				      params->resource_hndl);
 	}
 
+	if (params->resource_func == BNXT_ULP_RESOURCE_FUNC_PARENT_FLOW) {
+		tun_tbl = bnxt_ulp_cntxt_ptr2_tun_tbl_get(ulp_ctxt);
+		if (!tun_tbl)
+			return -EINVAL;
+
+		rc = ulp_flow_db_parent_tun_idx_get(ulp_ctxt, fid, &tun_idx);
+		if (rc)
+			return rc;
+
+		ulp_clear_tun_entry(tun_tbl, tun_idx);
+	}
+
 	/* all good, return success */
 	return 0;
 }
@@ -1159,34 +1270,6 @@ ulp_default_flow_db_cfa_action_get(struct bnxt_ulp_context *ulp_ctx,
 	return 0;
 }
 
-/* internal validation function for parent flow tbl */
-static struct bnxt_ulp_flow_db *
-ulp_flow_db_parent_arg_validation(struct bnxt_ulp_context *ulp_ctxt,
-				  uint32_t fid)
-{
-	struct bnxt_ulp_flow_db *flow_db;
-
-	flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);
-	if (!flow_db) {
-		BNXT_TF_DBG(ERR, "Invalid Arguments\n");
-		return NULL;
-	}
-
-	/* check for max flows */
-	if (fid >= flow_db->flow_tbl.num_flows || !fid) {
-		BNXT_TF_DBG(ERR, "Invalid flow index\n");
-		return NULL;
-	}
-
-	/* No support for parent child db then just exit */
-	if (!flow_db->parent_child_db.entries_count) {
-		BNXT_TF_DBG(ERR, "parent child db not supported\n");
-		return NULL;
-	}
-
-	return flow_db;
-}
-
 /*
  * Allocate the entry in the parent-child database
  *
@@ -1559,7 +1642,7 @@ ulp_flow_db_parent_flow_create(struct bnxt_ulp_mapper_parms *parms)
 	struct ulp_flow_db_res_params fid_parms;
 	uint32_t sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT_ACC;
 	struct ulp_flow_db_res_params res_params;
-	int32_t fid_idx;
+	int32_t fid_idx, rc;
 
 	/* create the child flow entry in parent flow table */
 	fid_idx = ulp_flow_db_parent_flow_alloc(parms->ulp_ctx, parms->fid);
@@ -1596,6 +1679,14 @@ ulp_flow_db_parent_flow_create(struct bnxt_ulp_mapper_parms *parms)
 			return -1;
 		}
 	}
+
+	rc  = ulp_flow_db_parent_tun_idx_set(parms->ulp_ctx, fid_idx,
+					     parms->tun_idx);
+	if (rc) {
+		BNXT_TF_DBG(ERR, "Error setting tun_idx in the parent flow\n");
+		return rc;
+	}
+
 	return 0;
 }
 
diff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.h b/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
index 10e69ba..f7dfd67 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
@@ -60,6 +60,8 @@ struct ulp_fdb_parent_info {
 	uint64_t	pkt_count;
 	uint64_t	byte_count;
 	uint64_t	*child_fid_bitset;
+	uint32_t	f2_cnt;
+	uint8_t		tun_idx;
 };
 
 /* Structure to maintain parent-child flow relationships */
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
index d5c129b..2964323 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
@@ -2815,6 +2815,7 @@ ulp_mapper_flow_create(struct bnxt_ulp_context *ulp_ctx,
 	parms.parent_flow = cparms->parent_flow;
 	parms.parent_fid = cparms->parent_fid;
 	parms.fid = cparms->flow_id;
+	parms.tun_idx = cparms->tun_idx;
 
 	/* Get the device id from the ulp context */
 	if (bnxt_ulp_cntxt_dev_id_get(ulp_ctx, &parms.dev_id)) {
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.h b/drivers/net/bnxt/tf_ulp/ulp_mapper.h
index 0595d15..9bd94f5 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.h
@@ -78,6 +78,7 @@ struct bnxt_ulp_mapper_parms {
 	struct bnxt_ulp_device_params           *device_params;
 	uint32_t				parent_fid;
 	uint32_t				parent_flow;
+	uint8_t					tun_idx;
 };
 
 struct bnxt_ulp_mapper_create_parms {
@@ -98,6 +99,7 @@ struct bnxt_ulp_mapper_create_parms {
 	uint32_t			parent_fid;
 	/* if set then create a parent flow */
 	uint32_t			parent_flow;
+	uint8_t				tun_idx;
 };
 
 /* Function to initialize any dynamic mapper data. */
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
index 42021ae..df38b83 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
@@ -6,11 +6,16 @@
 #include "bnxt.h"
 #include "ulp_template_db_enum.h"
 #include "ulp_template_struct.h"
+#include "bnxt_ulp.h"
 #include "bnxt_tf_common.h"
 #include "ulp_rte_parser.h"
+#include "ulp_matcher.h"
 #include "ulp_utils.h"
 #include "tfp.h"
 #include "ulp_port_db.h"
+#include "ulp_flow_db.h"
+#include "ulp_mapper.h"
+#include "ulp_tun.h"
 
 /* Local defines for the parsing functions */
 #define ULP_VLAN_PRIORITY_SHIFT		13 /* First 3 bits */
@@ -243,14 +248,11 @@ bnxt_ulp_comp_fld_intf_update(struct ulp_rte_parser_params *params)
 	}
 }
 
-/*
- * Function to handle the post processing of the parsing details
- */
-int32_t
-bnxt_ulp_rte_parser_post_process(struct ulp_rte_parser_params *params)
+static int32_t
+ulp_post_process_normal_flow(struct ulp_rte_parser_params *params)
 {
-	enum bnxt_ulp_direction_type dir;
 	enum bnxt_ulp_intf_type match_port_type, act_port_type;
+	enum bnxt_ulp_direction_type dir;
 	uint32_t act_port_set;
 
 	/* Get the computed details */
@@ -306,6 +308,16 @@ bnxt_ulp_rte_parser_post_process(struct ulp_rte_parser_params *params)
 }
 
 /*
+ * Function to handle the post processing of the parsing details
+ */
+int32_t
+bnxt_ulp_rte_parser_post_process(struct ulp_rte_parser_params *params)
+{
+	ulp_post_process_normal_flow(params);
+	return ulp_post_process_tun_flow(params);
+}
+
+/*
  * Function to compute the flow direction based on the match port details
  */
 static void
@@ -679,7 +691,16 @@ ulp_rte_eth_hdr_handler(const struct rte_flow_item *item,
 	params->field_idx += BNXT_ULP_PROTO_HDR_VLAN_NUM;
 
 	/* Update the protocol hdr bitmap */
-	if (ULP_BITMAP_ISSET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_O_ETH)) {
+	if (ULP_BITMAP_ISSET(params->hdr_bitmap.bits,
+			     BNXT_ULP_HDR_BIT_O_ETH) ||
+	    ULP_BITMAP_ISSET(params->hdr_bitmap.bits,
+			     BNXT_ULP_HDR_BIT_O_IPV4) ||
+	    ULP_BITMAP_ISSET(params->hdr_bitmap.bits,
+			     BNXT_ULP_HDR_BIT_O_IPV6) ||
+	    ULP_BITMAP_ISSET(params->hdr_bitmap.bits,
+			     BNXT_ULP_HDR_BIT_O_UDP) ||
+	    ULP_BITMAP_ISSET(params->hdr_bitmap.bits,
+			     BNXT_ULP_HDR_BIT_O_TCP)) {
 		ULP_BITMAP_SET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_I_ETH);
 		inner_flag = 1;
 	} else {
@@ -875,6 +896,22 @@ ulp_rte_ipv4_hdr_handler(const struct rte_flow_item *item,
 		return BNXT_TF_RC_ERROR;
 	}
 
+	if (!ULP_BITMAP_ISSET(params->hdr_bitmap.bits,
+			      BNXT_ULP_HDR_BIT_O_ETH) &&
+	    !ULP_BITMAP_ISSET(params->hdr_bitmap.bits,
+			      BNXT_ULP_HDR_BIT_I_ETH)) {
+		/* Since F2 flow does not include eth item, when parser detects
+		 * IPv4/IPv6 item list and it belongs to the outer header; i.e.,
+		 * o_ipv4/o_ipv6, check if O_ETH and I_ETH is set. If not set,
+		 * then add offset sizeof(o_eth/oo_vlan/oi_vlan) to the index.
+		 * This will allow the parser post processor to update the
+		 * t_dmac in hdr_field[o_eth.dmac]
+		 */
+		idx += (BNXT_ULP_PROTO_HDR_ETH_NUM +
+			BNXT_ULP_PROTO_HDR_VLAN_NUM);
+		params->field_idx = idx;
+	}
+
 	/*
 	 * Copy the rte_flow_item for ipv4 into hdr_field using ipv4
 	 * header fields
@@ -1004,6 +1041,22 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item,
 		return BNXT_TF_RC_ERROR;
 	}
 
+	if (!ULP_BITMAP_ISSET(params->hdr_bitmap.bits,
+			      BNXT_ULP_HDR_BIT_O_ETH) &&
+	    !ULP_BITMAP_ISSET(params->hdr_bitmap.bits,
+			      BNXT_ULP_HDR_BIT_I_ETH)) {
+		/* Since F2 flow does not include eth item, when parser detects
+		 * IPv4/IPv6 item list and it belongs to the outer header; i.e.,
+		 * o_ipv4/o_ipv6, check if O_ETH and I_ETH is set. If not set,
+		 * then add offset sizeof(o_eth/oo_vlan/oi_vlan) to the index.
+		 * This will allow the parser post processor to update the
+		 * t_dmac in hdr_field[o_eth.dmac]
+		 */
+		idx += (BNXT_ULP_PROTO_HDR_ETH_NUM +
+			BNXT_ULP_PROTO_HDR_VLAN_NUM);
+		params->field_idx = idx;
+	}
+
 	/*
 	 * Copy the rte_flow_item for ipv6 into hdr_field using ipv6
 	 * header fields
@@ -1109,9 +1162,11 @@ static void
 ulp_rte_l4_proto_type_update(struct ulp_rte_parser_params *param,
 			     uint16_t dst_port)
 {
-	if (dst_port == tfp_cpu_to_be_16(ULP_UDP_PORT_VXLAN))
+	if (dst_port == tfp_cpu_to_be_16(ULP_UDP_PORT_VXLAN)) {
 		ULP_BITMAP_SET(param->hdr_fp_bit.bits,
 			       BNXT_ULP_HDR_BIT_T_VXLAN);
+		ULP_COMP_FLD_IDX_WR(param, BNXT_ULP_CF_IDX_L3_TUN, 1);
+	}
 }
 
 /* Function to handle the parsing of RTE Flow item UDP Header. */
@@ -1143,6 +1198,7 @@ ulp_rte_udp_hdr_handler(const struct rte_flow_item *item,
 		field = ulp_rte_parser_fld_copy(&params->hdr_field[idx],
 						&udp_spec->hdr.src_port,
 						size);
+
 		size = sizeof(udp_spec->hdr.dst_port);
 		field = ulp_rte_parser_fld_copy(field,
 						&udp_spec->hdr.dst_port,
@@ -1689,6 +1745,9 @@ ulp_rte_vxlan_decap_act_handler(const struct rte_flow_action *action_item
 	/* update the hdr_bitmap with vxlan */
 	ULP_BITMAP_SET(params->act_bitmap.bits,
 		       BNXT_ULP_ACTION_BIT_VXLAN_DECAP);
+	/* Update computational field with tunnel decap info */
+	ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_L3_TUN_DECAP, 1);
+	ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_L3_TUN, 1);
 	return BNXT_TF_RC_SUCCESS;
 }
 
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
index a71aabe..7996317 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
@@ -12,6 +12,7 @@
 #include "ulp_template_db_enum.h"
 #include "ulp_template_struct.h"
 #include "ulp_mapper.h"
+#include "bnxt_tf_common.h"
 
 /* defines to be used in the tunnel header parsing */
 #define BNXT_ULP_ENCAP_IPV4_VER_HLEN_TOS	2
@@ -38,9 +39,6 @@
 void
 bnxt_ulp_init_mapper_params(struct bnxt_ulp_mapper_create_parms *mapper_cparms,
 			    struct ulp_rte_parser_params *params,
-			    uint32_t priority, uint32_t class_id,
-			    uint32_t act_tmpl, uint16_t func_id,
-			    uint32_t flow_id,
 			    enum bnxt_ulp_fdb_type flow_type);
 
 /* Function to handle the parsing of the RTE port id. */
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
index 10838f5..6802deb 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
@@ -135,7 +135,9 @@ enum bnxt_ulp_cf_idx {
 	BNXT_ULP_CF_IDX_L4_HDR_CNT = 41,
 	BNXT_ULP_CF_IDX_VFR_MODE = 42,
 	BNXT_ULP_CF_IDX_LOOPBACK_PARIF = 43,
-	BNXT_ULP_CF_IDX_LAST = 44
+	BNXT_ULP_CF_IDX_L3_TUN = 44,
+	BNXT_ULP_CF_IDX_L3_TUN_DECAP = 45,
+	BNXT_ULP_CF_IDX_LAST = 46
 };
 
 enum bnxt_ulp_cond_opcode {
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
index 69bb61e..9d690a9 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_struct.h
@@ -72,6 +72,13 @@ struct ulp_rte_parser_params {
 	struct ulp_rte_act_bitmap	act_bitmap;
 	struct ulp_rte_act_prop		act_prop;
 	uint32_t			dir_attr;
+	uint32_t			priority;
+	uint32_t			fid;
+	uint32_t			parent_flow;
+	uint32_t			parent_fid;
+	uint16_t			func_id;
+	uint32_t			class_id;
+	uint32_t			act_tmpl;
 	struct bnxt_ulp_context		*ulp_ctx;
 };
 
diff --git a/drivers/net/bnxt/tf_ulp/ulp_tun.c b/drivers/net/bnxt/tf_ulp/ulp_tun.c
new file mode 100644
index 0000000..e8d2861
--- /dev/null
+++ b/drivers/net/bnxt/tf_ulp/ulp_tun.c
@@ -0,0 +1,310 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2014-2020 Broadcom
+ * All rights reserved.
+ */
+
+#include <rte_malloc.h>
+
+#include "ulp_tun.h"
+#include "ulp_rte_parser.h"
+#include "ulp_template_db_enum.h"
+#include "ulp_template_struct.h"
+#include "ulp_matcher.h"
+#include "ulp_mapper.h"
+#include "ulp_flow_db.h"
+
+/* This function programs the outer tunnel flow in the hardware. */
+static int32_t
+ulp_install_outer_tun_flow(struct ulp_rte_parser_params *params,
+			   struct bnxt_tun_cache_entry *tun_entry,
+			   uint16_t tun_idx)
+{
+	struct bnxt_ulp_mapper_create_parms mparms = { 0 };
+	int ret;
+
+	/* Reset the JUMP action bit in the action bitmap as we don't
+	 * offload this action.
+	 */
+	ULP_BITMAP_RESET(params->act_bitmap.bits, BNXT_ULP_ACTION_BIT_JUMP);
+
+	ULP_BITMAP_SET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_F1);
+
+	ret = ulp_matcher_pattern_match(params, &params->class_id);
+	if (ret != BNXT_TF_RC_SUCCESS)
+		goto err;
+
+	ret = ulp_matcher_action_match(params, &params->act_tmpl);
+	if (ret != BNXT_TF_RC_SUCCESS)
+		goto err;
+
+	params->parent_flow = true;
+	bnxt_ulp_init_mapper_params(&mparms, params,
+				    BNXT_ULP_FDB_TYPE_REGULAR);
+	mparms.tun_idx = tun_idx;
+
+	/* Call the ulp mapper to create the flow in the hardware. */
+	ret = ulp_mapper_flow_create(params->ulp_ctx, &mparms);
+	if (ret)
+		goto err;
+
+	/* Store the tunnel dmac in the tunnel cache table and use it while
+	 * programming tunnel flow F2.
+	 */
+	memcpy(tun_entry->t_dmac,
+	       &params->hdr_field[ULP_TUN_O_DMAC_HDR_FIELD_INDEX].spec,
+	       RTE_ETHER_ADDR_LEN);
+
+	tun_entry->valid = true;
+	tun_entry->state = BNXT_ULP_FLOW_STATE_TUN_O_OFFLD;
+	tun_entry->outer_tun_flow_id = params->fid;
+
+	/* F1 and it's related F2s are correlated based on
+	 * Tunnel Destination IP Address.
+	 */
+	if (tun_entry->t_dst_ip_valid)
+		goto done;
+	if (ULP_BITMAP_ISSET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_O_IPV4))
+		memcpy(&tun_entry->t_dst_ip,
+		       &params->hdr_field[ULP_TUN_O_IPV4_DIP_INDEX].spec,
+		       sizeof(rte_be32_t));
+	else
+		memcpy(tun_entry->t_dst_ip6,
+		       &params->hdr_field[ULP_TUN_O_IPV6_DIP_INDEX].spec,
+		       sizeof(tun_entry->t_dst_ip6));
+	tun_entry->t_dst_ip_valid = true;
+
+done:
+	return BNXT_TF_RC_FID;
+
+err:
+	memset(tun_entry, 0, sizeof(struct bnxt_tun_cache_entry));
+	return BNXT_TF_RC_ERROR;
+}
+
+/* This function programs the inner tunnel flow in the hardware. */
+static void
+ulp_install_inner_tun_flow(struct bnxt_tun_cache_entry *tun_entry)
+{
+	struct bnxt_ulp_mapper_create_parms mparms = { 0 };
+	struct ulp_rte_parser_params *params;
+	int ret;
+
+	/* F2 doesn't have tunnel dmac, use the tunnel dmac that was
+	 * stored during F1 programming.
+	 */
+	params = &tun_entry->first_inner_tun_params;
+	memcpy(&params->hdr_field[ULP_TUN_O_DMAC_HDR_FIELD_INDEX],
+	       tun_entry->t_dmac, RTE_ETHER_ADDR_LEN);
+	params->parent_fid = tun_entry->outer_tun_flow_id;
+	params->fid = tun_entry->first_inner_tun_flow_id;
+
+	bnxt_ulp_init_mapper_params(&mparms, params,
+				    BNXT_ULP_FDB_TYPE_REGULAR);
+
+	ret = ulp_mapper_flow_create(params->ulp_ctx, &mparms);
+	if (ret)
+		PMD_DRV_LOG(ERR, "Failed to create F2 flow.");
+}
+
+/* This function either install outer tunnel flow & inner tunnel flow
+ * or just the outer tunnel flow based on the flow state.
+ */
+static int32_t
+ulp_post_process_outer_tun_flow(struct ulp_rte_parser_params *params,
+			     struct bnxt_tun_cache_entry *tun_entry,
+			     uint16_t tun_idx)
+{
+	enum bnxt_ulp_tun_flow_state flow_state;
+	int ret;
+
+	flow_state = tun_entry->state;
+	ret = ulp_install_outer_tun_flow(params, tun_entry, tun_idx);
+	if (ret)
+		return ret;
+
+	/* If flow_state == BNXT_ULP_FLOW_STATE_NORMAL before installing
+	 * F1, that means F2 is not deferred. Hence, no need to install F2.
+	 */
+	if (flow_state != BNXT_ULP_FLOW_STATE_NORMAL)
+		ulp_install_inner_tun_flow(tun_entry);
+
+	return 0;
+}
+
+/* This function will be called if inner tunnel flow request comes before
+ * outer tunnel flow request.
+ */
+static int32_t
+ulp_post_process_first_inner_tun_flow(struct ulp_rte_parser_params *params,
+				      struct bnxt_tun_cache_entry *tun_entry)
+{
+	int ret;
+
+	ret = ulp_matcher_pattern_match(params, &params->class_id);
+	if (ret != BNXT_TF_RC_SUCCESS)
+		return BNXT_TF_RC_ERROR;
+
+	ret = ulp_matcher_action_match(params, &params->act_tmpl);
+	if (ret != BNXT_TF_RC_SUCCESS)
+		return BNXT_TF_RC_ERROR;
+
+	/* If Tunnel F2 flow comes first then we can't install it in the
+	 * hardware, because, F2 flow will not have L2 context information.
+	 * So, just cache the F2 information and program it in the context
+	 * of F1 flow installation.
+	 */
+	memcpy(&tun_entry->first_inner_tun_params, params,
+	       sizeof(struct ulp_rte_parser_params));
+
+	tun_entry->first_inner_tun_flow_id = params->fid;
+	tun_entry->state = BNXT_ULP_FLOW_STATE_TUN_I_CACHED;
+
+	/* F1 and it's related F2s are correlated based on
+	 * Tunnel Destination IP Address. It could be already set, if
+	 * the inner flow got offloaded first.
+	 */
+	if (tun_entry->t_dst_ip_valid)
+		goto done;
+	if (ULP_BITMAP_ISSET(params->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_O_IPV4))
+		memcpy(&tun_entry->t_dst_ip,
+		       &params->hdr_field[ULP_TUN_O_IPV4_DIP_INDEX].spec,
+		       sizeof(rte_be32_t));
+	else
+		memcpy(tun_entry->t_dst_ip6,
+		       &params->hdr_field[ULP_TUN_O_IPV6_DIP_INDEX].spec,
+		       sizeof(tun_entry->t_dst_ip6));
+	tun_entry->t_dst_ip_valid = true;
+
+done:
+	return BNXT_TF_RC_FID;
+}
+
+/* This function will be called if inner tunnel flow request comes after
+ * the outer tunnel flow request.
+ */
+static int32_t
+ulp_post_process_inner_tun_flow(struct ulp_rte_parser_params *params,
+				struct bnxt_tun_cache_entry *tun_entry)
+{
+	memcpy(&params->hdr_field[ULP_TUN_O_DMAC_HDR_FIELD_INDEX],
+	       tun_entry->t_dmac, RTE_ETHER_ADDR_LEN);
+
+	params->parent_fid = tun_entry->outer_tun_flow_id;
+
+	return BNXT_TF_RC_NORMAL;
+}
+
+static int32_t
+ulp_get_tun_entry(struct ulp_rte_parser_params *params,
+		  struct bnxt_tun_cache_entry **tun_entry,
+		  uint16_t *tun_idx)
+{
+	int i, first_free_entry = BNXT_ULP_TUN_ENTRY_INVALID;
+	struct bnxt_tun_cache_entry *tun_tbl;
+	bool tun_entry_found = false, free_entry_found = false;
+
+	tun_tbl = bnxt_ulp_cntxt_ptr2_tun_tbl_get(params->ulp_ctx);
+	if (!tun_tbl)
+		return BNXT_TF_RC_ERROR;
+
+	for (i = 0; i < BNXT_ULP_MAX_TUN_CACHE_ENTRIES; i++) {
+		if (!memcmp(&tun_tbl[i].t_dst_ip,
+			    &params->hdr_field[ULP_TUN_O_IPV4_DIP_INDEX].spec,
+			    sizeof(rte_be32_t)) ||
+		    !memcmp(&tun_tbl[i].t_dst_ip6,
+			    &params->hdr_field[ULP_TUN_O_IPV6_DIP_INDEX].spec,
+			    16)) {
+			tun_entry_found = true;
+			break;
+		}
+
+		if (!tun_tbl[i].t_dst_ip_valid && !free_entry_found) {
+			first_free_entry = i;
+			free_entry_found = true;
+		}
+	}
+
+	if (tun_entry_found) {
+		*tun_entry = &tun_tbl[i];
+		*tun_idx = i;
+	} else {
+		if (first_free_entry == BNXT_ULP_TUN_ENTRY_INVALID)
+			return BNXT_TF_RC_ERROR;
+		*tun_entry = &tun_tbl[first_free_entry];
+		*tun_idx = first_free_entry;
+	}
+
+	return 0;
+}
+
+int32_t
+ulp_post_process_tun_flow(struct ulp_rte_parser_params *params)
+{
+	bool outer_tun_sig, inner_tun_sig, first_inner_tun_flow;
+	bool outer_tun_reject, inner_tun_reject, outer_tun_flow, inner_tun_flow;
+	enum bnxt_ulp_tun_flow_state flow_state;
+	struct bnxt_tun_cache_entry *tun_entry;
+	uint32_t l3_tun, l3_tun_decap;
+	uint16_t tun_idx;
+	int rc;
+
+	/* Computational fields that indicate it's a TUNNEL DECAP flow */
+	l3_tun = ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_L3_TUN);
+	l3_tun_decap = ULP_COMP_FLD_IDX_RD(params,
+					   BNXT_ULP_CF_IDX_L3_TUN_DECAP);
+	if (!l3_tun)
+		return BNXT_TF_RC_NORMAL;
+
+	rc = ulp_get_tun_entry(params, &tun_entry, &tun_idx);
+	if (rc == BNXT_TF_RC_ERROR)
+		return rc;
+
+	flow_state = tun_entry->state;
+	/* Outer tunnel flow validation */
+	outer_tun_sig = BNXT_OUTER_TUN_SIGNATURE(l3_tun, params);
+	outer_tun_flow = BNXT_OUTER_TUN_FLOW(outer_tun_sig);
+	outer_tun_reject = BNXT_REJECT_OUTER_TUN_FLOW(flow_state,
+						      outer_tun_sig);
+
+	/* Inner tunnel flow validation */
+	inner_tun_sig = BNXT_INNER_TUN_SIGNATURE(l3_tun, l3_tun_decap, params);
+	first_inner_tun_flow = BNXT_FIRST_INNER_TUN_FLOW(flow_state,
+							 inner_tun_sig);
+	inner_tun_flow = BNXT_INNER_TUN_FLOW(flow_state, inner_tun_sig);
+	inner_tun_reject = BNXT_REJECT_INNER_TUN_FLOW(flow_state,
+						      inner_tun_sig);
+
+	if (outer_tun_reject) {
+		tun_entry->outer_tun_rej_cnt++;
+		BNXT_TF_DBG(ERR,
+			    "Tunnel F1 flow rejected, COUNT: %d\n",
+			    tun_entry->outer_tun_rej_cnt);
+	/* Inner tunnel flow is rejected if it comes between first inner
+	 * tunnel flow and outer flow requests.
+	 */
+	} else if (inner_tun_reject) {
+		tun_entry->inner_tun_rej_cnt++;
+		BNXT_TF_DBG(ERR,
+			    "Tunnel F2 flow rejected, COUNT: %d\n",
+			    tun_entry->inner_tun_rej_cnt);
+	}
+
+	if (outer_tun_reject || inner_tun_reject)
+		return BNXT_TF_RC_ERROR;
+	else if (first_inner_tun_flow)
+		return ulp_post_process_first_inner_tun_flow(params, tun_entry);
+	else if (outer_tun_flow)
+		return ulp_post_process_outer_tun_flow(params, tun_entry,
+						       tun_idx);
+	else if (inner_tun_flow)
+		return ulp_post_process_inner_tun_flow(params, tun_entry);
+	else
+		return BNXT_TF_RC_NORMAL;
+}
+
+void
+ulp_clear_tun_entry(struct bnxt_tun_cache_entry *tun_tbl, uint8_t tun_idx)
+{
+	memset(&tun_tbl[tun_idx], 0,
+		sizeof(struct bnxt_tun_cache_entry));
+}
diff --git a/drivers/net/bnxt/tf_ulp/ulp_tun.h b/drivers/net/bnxt/tf_ulp/ulp_tun.h
new file mode 100644
index 0000000..ad70ae6
--- /dev/null
+++ b/drivers/net/bnxt/tf_ulp/ulp_tun.h
@@ -0,0 +1,92 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2014-2020 Broadcom
+ * All rights reserved.
+ */
+
+#ifndef _BNXT_TUN_H_
+#define _BNXT_TUN_H_
+
+#include <inttypes.h>
+#include <stdbool.h>
+#include <sys/queue.h>
+
+#include "rte_ethdev.h"
+
+#include "ulp_template_db_enum.h"
+#include "ulp_template_struct.h"
+
+#define	BNXT_OUTER_TUN_SIGNATURE(l3_tun, params)		\
+	((l3_tun) &&					\
+	 ULP_BITMAP_ISSET((params)->act_bitmap.bits,	\
+			  BNXT_ULP_ACTION_BIT_JUMP))
+#define	BNXT_INNER_TUN_SIGNATURE(l3_tun, l3_tun_decap, params)		\
+	((l3_tun) && (l3_tun_decap) &&					\
+	 !ULP_BITMAP_ISSET((params)->hdr_bitmap.bits,			\
+			   BNXT_ULP_HDR_BIT_O_ETH))
+
+#define	BNXT_FIRST_INNER_TUN_FLOW(state, inner_tun_sig)	\
+	((state) == BNXT_ULP_FLOW_STATE_NORMAL && (inner_tun_sig))
+#define	BNXT_INNER_TUN_FLOW(state, inner_tun_sig)		\
+	((state) == BNXT_ULP_FLOW_STATE_TUN_O_OFFLD && (inner_tun_sig))
+#define	BNXT_OUTER_TUN_FLOW(outer_tun_sig)		((outer_tun_sig))
+
+/* It is invalid to get another outer flow offload request
+ * for the same tunnel, while the outer flow is already offloaded.
+ */
+#define	BNXT_REJECT_OUTER_TUN_FLOW(state, outer_tun_sig)	\
+	((state) == BNXT_ULP_FLOW_STATE_TUN_O_OFFLD && (outer_tun_sig))
+/* It is invalid to get another inner flow offload request
+ * for the same tunnel, while the outer flow is not yet offloaded.
+ */
+#define	BNXT_REJECT_INNER_TUN_FLOW(state, inner_tun_sig)	\
+	((state) == BNXT_ULP_FLOW_STATE_TUN_I_CACHED && (inner_tun_sig))
+
+#define	ULP_TUN_O_DMAC_HDR_FIELD_INDEX	1
+#define	ULP_TUN_O_IPV4_DIP_INDEX	19
+#define	ULP_TUN_O_IPV6_DIP_INDEX	17
+
+/* When a flow offload request comes the following state transitions
+ * happen based on the order in which the outer & inner flow offload
+ * requests arrive.
+ *
+ * If inner tunnel flow offload request arrives first then the flow
+ * state will change from BNXT_ULP_FLOW_STATE_NORMAL to
+ * BNXT_ULP_FLOW_STATE_TUN_I_CACHED and the following outer tunnel
+ * flow offload request will change the state of the flow to
+ * BNXT_ULP_FLOW_STATE_TUN_O_OFFLD from BNXT_ULP_FLOW_STATE_TUN_I_CACHED.
+ *
+ * If outer tunnel flow offload request arrives first then the flow state
+ * will change from BNXT_ULP_FLOW_STATE_NORMAL to
+ * BNXT_ULP_FLOW_STATE_TUN_O_OFFLD.
+ *
+ * Once the flow state is in BNXT_ULP_FLOW_STATE_TUN_O_OFFLD, any inner
+ * tunnel flow offload requests after that point will be treated as a
+ * normal flow and the tunnel flow state remains in
+ * BNXT_ULP_FLOW_STATE_TUN_O_OFFLD
+ */
+enum bnxt_ulp_tun_flow_state {
+	BNXT_ULP_FLOW_STATE_NORMAL = 0,
+	BNXT_ULP_FLOW_STATE_TUN_O_OFFLD,
+	BNXT_ULP_FLOW_STATE_TUN_I_CACHED
+};
+
+struct bnxt_tun_cache_entry {
+	enum bnxt_ulp_tun_flow_state	state;
+	bool				valid;
+	bool				t_dst_ip_valid;
+	uint8_t				t_dmac[RTE_ETHER_ADDR_LEN];
+	union {
+		rte_be32_t		t_dst_ip;
+		uint8_t			t_dst_ip6[16];
+	};
+	uint32_t			outer_tun_flow_id;
+	uint32_t			first_inner_tun_flow_id;
+	uint16_t			outer_tun_rej_cnt;
+	uint16_t			inner_tun_rej_cnt;
+	struct ulp_rte_parser_params	first_inner_tun_params;
+};
+
+void
+ulp_clear_tun_entry(struct bnxt_tun_cache_entry *tun_tbl, uint8_t tun_idx);
+
+#endif
-- 
2.7.4


^ permalink raw reply	[flat|nested] 32+ messages in thread

* [dpdk-dev] [PATCH v2 00/11] bnxt fixes and enhancements to TRUFLOW support
  2020-10-17  6:27 [dpdk-dev] [PATCH 00/14] bnxt patches Venkat Duvvuru
                   ` (13 preceding siblings ...)
  2020-10-17  6:28 ` [dpdk-dev] [PATCH 14/14] net/bnxt: add VXLAN decap offload support Venkat Duvvuru
@ 2020-10-20 21:55 ` Ajit Khaparde
  2020-10-20 21:55   ` [dpdk-dev] [PATCH v2 01/11] net/bnxt: add stingray support to core layer Ajit Khaparde
                     ` (11 more replies)
  14 siblings, 12 replies; 32+ messages in thread
From: Ajit Khaparde @ 2020-10-20 21:55 UTC (permalink / raw)
  To: dev

This patchset has support for VXLAN decap full offload,
SR device support in tf_core and a few bug fixes.

v1->v2:
 - Squashed some patches.
 - Updated commit logs.
 - Fixed a compilation issue reported during clang builds.

Farah Smith (1):
  net/bnxt: add table scope to PF Mapping

Jay Ding (1):
  net/bnxt: changes to support two table scopes

Kishore Padmanabha (2):
  net/bnxt: add support for flow counter accumulation
  net/bnxt: add mapper support for wildcard TCAM

Peter Spreadborough (2):
  net/bnxt: add stingray support to core layer
  net/bnxt: update ULP resource counts

Somnath Kotur (2):
  net/bnxt: fix infinite loop in flow query count
  net/bnxt: change HWRM command to create reps

Venkat Duvvuru (3):
  net/bnxt: refactor flow id allocation
  net/bnxt: add support for VXLAN decap templates
  net/bnxt: add VXLAN decap offload support

 doc/guides/nics/bnxt.rst                      |   18 +
 doc/guides/rel_notes/release_20_11.rst        |    2 +
 drivers/net/bnxt/bnxt.h                       |    6 +-
 drivers/net/bnxt/bnxt_ethdev.c                |    2 +
 drivers/net/bnxt/bnxt_hwrm.c                  |   60 +-
 drivers/net/bnxt/bnxt_hwrm.h                  |    2 -
 drivers/net/bnxt/bnxt_reps.c                  |   18 +-
 drivers/net/bnxt/hcapi/hcapi_cfa.h            |   39 +-
 drivers/net/bnxt/meson.build                  |    1 +
 drivers/net/bnxt/tf_core/cfa_resource_types.h |   95 +-
 drivers/net/bnxt/tf_core/tf_core.c            |   57 +-
 drivers/net/bnxt/tf_core/tf_core.h            |   57 +-
 drivers/net/bnxt/tf_core/tf_device.c          |    9 +-
 drivers/net/bnxt/tf_core/tf_device.h          |   47 +-
 drivers/net/bnxt/tf_core/tf_device_p4.c       |   69 +-
 drivers/net/bnxt/tf_core/tf_device_p4.h       |    6 +
 drivers/net/bnxt/tf_core/tf_device_p45.h      |  105 +
 drivers/net/bnxt/tf_core/tf_em.h              |   25 +-
 drivers/net/bnxt/tf_core/tf_em_common.c       |  176 +-
 drivers/net/bnxt/tf_core/tf_em_common.h       |   27 +-
 drivers/net/bnxt/tf_core/tf_em_host.c         |   31 +-
 drivers/net/bnxt/tf_core/tf_global_cfg.c      |    4 +-
 drivers/net/bnxt/tf_core/tf_global_cfg.h      |   42 +-
 drivers/net/bnxt/tf_core/tf_msg.c             |   13 +-
 drivers/net/bnxt/tf_core/tf_msg.h             |    4 +-
 drivers/net/bnxt/tf_core/tf_session.h         |   16 +-
 drivers/net/bnxt/tf_core/tf_tbl.h             |    3 +
 drivers/net/bnxt/tf_core/tfp.c                |   19 +
 drivers/net/bnxt/tf_core/tfp.h                |   16 +
 drivers/net/bnxt/tf_ulp/bnxt_tf_common.h      |    4 +-
 drivers/net/bnxt/tf_ulp/bnxt_ulp.c            |   50 +-
 drivers/net/bnxt/tf_ulp/bnxt_ulp.h            |   12 +
 drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c       |  129 +-
 drivers/net/bnxt/tf_ulp/ulp_def_rules.c       |   48 +-
 drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c          |  133 +-
 drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h          |   19 +
 drivers/net/bnxt/tf_ulp/ulp_flow_db.c         |  475 +++-
 drivers/net/bnxt/tf_ulp/ulp_flow_db.h         |   46 +
 drivers/net/bnxt/tf_ulp/ulp_mapper.c          |   83 +-
 drivers/net/bnxt/tf_ulp/ulp_mapper.h          |    6 +-
 drivers/net/bnxt/tf_ulp/ulp_rte_parser.c      |   85 +-
 drivers/net/bnxt/tf_ulp/ulp_rte_parser.h      |   12 +
 .../net/bnxt/tf_ulp/ulp_template_db_class.c   |  962 ++++---
 .../net/bnxt/tf_ulp/ulp_template_db_enum.h    |   42 +-
 .../net/bnxt/tf_ulp/ulp_template_db_field.h   |  363 ++-
 .../tf_ulp/ulp_template_db_stingray_act.c     |  116 +-
 .../tf_ulp/ulp_template_db_stingray_class.c   | 2493 ++++++++++++++---
 drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c |    9 +-
 .../bnxt/tf_ulp/ulp_template_db_wh_plus_act.c |  116 +-
 .../tf_ulp/ulp_template_db_wh_plus_class.c    | 2489 +++++++++++++---
 drivers/net/bnxt/tf_ulp/ulp_template_struct.h |    7 +
 drivers/net/bnxt/tf_ulp/ulp_tun.c             |  310 ++
 drivers/net/bnxt/tf_ulp/ulp_tun.h             |   92 +
 drivers/net/bnxt/tf_ulp/ulp_utils.c           |  125 +
 drivers/net/bnxt/tf_ulp/ulp_utils.h           |   48 +-
 55 files changed, 7206 insertions(+), 2037 deletions(-)
 create mode 100644 drivers/net/bnxt/tf_core/tf_device_p45.h
 create mode 100644 drivers/net/bnxt/tf_ulp/ulp_tun.c
 create mode 100644 drivers/net/bnxt/tf_ulp/ulp_tun.h

-- 
2.21.1 (Apple Git-122.3)


^ permalink raw reply	[flat|nested] 32+ messages in thread

* [dpdk-dev] [PATCH v2 01/11] net/bnxt: add stingray support to core layer
  2020-10-20 21:55 ` [dpdk-dev] [PATCH v2 00/11] bnxt fixes and enhancements to TRUFLOW support Ajit Khaparde
@ 2020-10-20 21:55   ` Ajit Khaparde
  2020-10-20 21:55   ` [dpdk-dev] [PATCH v2 02/11] net/bnxt: changes to support two table scopes Ajit Khaparde
                     ` (10 subsequent siblings)
  11 siblings, 0 replies; 32+ messages in thread
From: Ajit Khaparde @ 2020-10-20 21:55 UTC (permalink / raw)
  To: dev; +Cc: Peter Spreadborough, Jay Ding, Farah Smith

From: Peter Spreadborough <peter.spreadborough@broadcom.com>

- Moved P4 specific code under the P4 directory
- Added P45 skeleton code for SR to build on
- Add SR support in truflow core layer

Signed-off-by: Peter Spreadborough <peter.spreadborough@broadcom.com>
Signed-off-by: Jay Ding <jay.ding@broadcom.com>
Reviewed-by: Farah Smith <farah.smith@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
 drivers/net/bnxt/hcapi/hcapi_cfa.h            |  39 +++++--
 drivers/net/bnxt/tf_core/cfa_resource_types.h |  95 ++++++----------
 drivers/net/bnxt/tf_core/tf_core.c            |   3 +-
 drivers/net/bnxt/tf_core/tf_core.h            |   2 +-
 drivers/net/bnxt/tf_core/tf_device.c          |   9 +-
 drivers/net/bnxt/tf_core/tf_device_p4.c       |  25 ++++-
 drivers/net/bnxt/tf_core/tf_device_p4.h       |   6 +
 drivers/net/bnxt/tf_core/tf_device_p45.h      | 105 ++++++++++++++++++
 drivers/net/bnxt/tf_core/tf_em.h              |   6 -
 9 files changed, 207 insertions(+), 83 deletions(-)
 create mode 100644 drivers/net/bnxt/tf_core/tf_device_p45.h

diff --git a/drivers/net/bnxt/hcapi/hcapi_cfa.h b/drivers/net/bnxt/hcapi/hcapi_cfa.h
index c7d87dec7..aa218d714 100644
--- a/drivers/net/bnxt/hcapi/hcapi_cfa.h
+++ b/drivers/net/bnxt/hcapi/hcapi_cfa.h
@@ -14,7 +14,15 @@
 
 #include "hcapi_cfa_defs.h"
 
+#if CHIP_CFG == SR_A
+#define SUPPORT_CFA_HW_P45  1
+#undef SUPPORT_CFA_HW_P4
+#define SUPPORT_CFA_HW_P4   0
+#elif CHIP_CFG == CMB_A
 #define SUPPORT_CFA_HW_P4  1
+#else
+#error "Chip not supported"
+#endif
 
 #if SUPPORT_CFA_HW_P4 && SUPPORT_CFA_HW_P58 && SUPPORT_CFA_HW_P59
 #define SUPPORT_CFA_HW_ALL  1
@@ -81,17 +89,20 @@ struct hcapi_cfa_key_result {
 /* common CFA register access macros */
 #define CFA_REG(x)		OFFSETOF(cfa_reg_t, cfa_##x)
 
-#ifndef REG_WR
-#define REG_WR(_p, x, y)  (*((uint32_t volatile *)(x)) = (y))
+#ifndef TF_REG_WR
+#define TF_REG_WR(_p, x, y)  (*((uint32_t volatile *)(x)) = (y))
 #endif
-#ifndef REG_RD
-#define REG_RD(_p, x)  (*((uint32_t volatile *)(x)))
+#ifndef TF_REG_RD
+#define TF_REG_RD(_p, x)  (*((uint32_t volatile *)(x)))
+#endif
+#ifndef TF_CFA_REG_RD
+#define TF_CFA_REG_RD(_p, x)	\
+	TF_REG_RD(0, (uint32_t)(_p)->base_addr + CFA_REG(x))
+#endif
+#ifndef TF_CFA_REG_WR
+#define TF_CFA_REG_WR(_p, x, y)	\
+	TF_REG_WR(0, (uint32_t)(_p)->base_addr + CFA_REG(x), y)
 #endif
-#define CFA_REG_RD(_p, x)	\
-	REG_RD(0, (uint32_t)(_p)->base_addr + CFA_REG(x))
-#define CFA_REG_WR(_p, x, y)	\
-	REG_WR(0, (uint32_t)(_p)->base_addr + CFA_REG(x), y)
-
 
 /* Constants used by Resource Manager Registration*/
 #define RM_CLIENT_NAME_MAX_LEN          32
@@ -248,7 +259,15 @@ int hcapi_cfa_p4_mirror_hwop(struct hcapi_cfa_hwop *op,
 int hcapi_cfa_p4_global_cfg_hwop(struct hcapi_cfa_hwop *op,
 				 uint32_t type,
 				 struct hcapi_cfa_data *config);
-#endif /* SUPPORT_CFA_HW_P4 */
+/* SUPPORT_CFA_HW_P4 */
+#elif SUPPORT_CFA_HW_P45
+int hcapi_cfa_p45_mirror_hwop(struct hcapi_cfa_hwop *op,
+			      struct hcapi_cfa_data *mirror);
+int hcapi_cfa_p45_global_cfg_hwop(struct hcapi_cfa_hwop *op,
+				  uint32_t type,
+				  struct hcapi_cfa_data *config);
+/* SUPPORT_CFA_HW_P45 */
+#endif
 /**
  *  HCAPI CFA device HW operation function callback definition
  *  This is standardized function callback hook to install different
diff --git a/drivers/net/bnxt/tf_core/cfa_resource_types.h b/drivers/net/bnxt/tf_core/cfa_resource_types.h
index 19838c393..a62063b0e 100644
--- a/drivers/net/bnxt/tf_core/cfa_resource_types.h
+++ b/drivers/net/bnxt/tf_core/cfa_resource_types.h
@@ -1,6 +1,13 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2020 Broadcom
- * All rights reserved.
+/*
+ * Copyright(c) 2001-2020, Broadcom. All rights reserved. The
+ * term Broadcom refers to Broadcom Inc. and/or its subsidiaries.
+ * Proprietary and Confidential Information.
+ *
+ * This source file is the property of Broadcom Corporation, and
+ * may not be copied or distributed in any isomorphic form without
+ * the prior written consent of Broadcom Corporation.
+ *
+ * DO NOT MODIFY!!! This file is automatically generated.
  */
 
 #ifndef _CFA_RESOURCE_TYPES_H_
@@ -64,79 +71,47 @@
 #define CFA_RESOURCE_TYPE_P59_LAST              CFA_RESOURCE_TYPE_P59_VEB_TCAM
 
 
-/* Multicast Group */
-#define CFA_RESOURCE_TYPE_P58_MCG                 0x0UL
-/* Encap 8 byte record */
-#define CFA_RESOURCE_TYPE_P58_ENCAP_8B            0x1UL
-/* Encap 16 byte record */
-#define CFA_RESOURCE_TYPE_P58_ENCAP_16B           0x2UL
-/* Encap 64 byte record */
-#define CFA_RESOURCE_TYPE_P58_ENCAP_64B           0x3UL
-/* Source Property MAC */
-#define CFA_RESOURCE_TYPE_P58_SP_MAC              0x4UL
-/* Source Property MAC and IPv4 */
-#define CFA_RESOURCE_TYPE_P58_SP_MAC_IPV4         0x5UL
-/* Source Property MAC and IPv6 */
-#define CFA_RESOURCE_TYPE_P58_SP_MAC_IPV6         0x6UL
-/* Network Address Translation Port */
-#define CFA_RESOURCE_TYPE_P58_NAT_PORT            0x7UL
-/* Network Address Translation IPv4 address */
-#define CFA_RESOURCE_TYPE_P58_NAT_IPV4            0x8UL
 /* Meter */
-#define CFA_RESOURCE_TYPE_P58_METER               0x9UL
-/* Flow State */
-#define CFA_RESOURCE_TYPE_P58_FLOW_STATE          0xaUL
-/* Full Action Records */
-#define CFA_RESOURCE_TYPE_P58_FULL_ACTION         0xbUL
-/* Action Record Format 0 */
-#define CFA_RESOURCE_TYPE_P58_FORMAT_0_ACTION     0xcUL
-/* Action Record Ext Format 0 */
-#define CFA_RESOURCE_TYPE_P58_EXT_FORMAT_0_ACTION 0xdUL
-/* Action Record Format 1 */
-#define CFA_RESOURCE_TYPE_P58_FORMAT_1_ACTION     0xeUL
-/* Action Record Format 2 */
-#define CFA_RESOURCE_TYPE_P58_FORMAT_2_ACTION     0xfUL
-/* Action Record Format 3 */
-#define CFA_RESOURCE_TYPE_P58_FORMAT_3_ACTION     0x10UL
-/* Action Record Format 4 */
-#define CFA_RESOURCE_TYPE_P58_FORMAT_4_ACTION     0x11UL
-/* Action Record Format 5 */
-#define CFA_RESOURCE_TYPE_P58_FORMAT_5_ACTION     0x12UL
-/* Action Record Format 6 */
-#define CFA_RESOURCE_TYPE_P58_FORMAT_6_ACTION     0x13UL
+#define CFA_RESOURCE_TYPE_P58_METER              0x0UL
+/* SRAM_Bank_0 */
+#define CFA_RESOURCE_TYPE_P58_SRAM_BANK_0        0x1UL
+/* SRAM_Bank_1 */
+#define CFA_RESOURCE_TYPE_P58_SRAM_BANK_1        0x2UL
+/* SRAM_Bank_2 */
+#define CFA_RESOURCE_TYPE_P58_SRAM_BANK_2        0x3UL
+/* SRAM_Bank_3 */
+#define CFA_RESOURCE_TYPE_P58_SRAM_BANK_3        0x4UL
 /* L2 Context TCAM High priority entries */
-#define CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_HIGH   0x14UL
+#define CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_HIGH  0x5UL
 /* L2 Context TCAM Low priority entries */
-#define CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_LOW    0x15UL
+#define CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_LOW   0x6UL
 /* L2 Context REMAP high priority entries */
-#define CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_HIGH  0x16UL
+#define CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_HIGH 0x7UL
 /* L2 Context REMAP Low priority entries */
-#define CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_LOW   0x17UL
+#define CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_LOW  0x8UL
 /* Profile Func */
-#define CFA_RESOURCE_TYPE_P58_PROF_FUNC           0x18UL
+#define CFA_RESOURCE_TYPE_P58_PROF_FUNC          0x9UL
 /* Profile TCAM */
-#define CFA_RESOURCE_TYPE_P58_PROF_TCAM           0x19UL
+#define CFA_RESOURCE_TYPE_P58_PROF_TCAM          0xaUL
 /* Exact Match Profile Id */
-#define CFA_RESOURCE_TYPE_P58_EM_PROF_ID          0x1aUL
+#define CFA_RESOURCE_TYPE_P58_EM_PROF_ID         0xbUL
 /* Wildcard Profile Id */
-#define CFA_RESOURCE_TYPE_P58_WC_TCAM_PROF_ID     0x1bUL
+#define CFA_RESOURCE_TYPE_P58_WC_TCAM_PROF_ID    0xcUL
 /* Exact Match Record */
-#define CFA_RESOURCE_TYPE_P58_EM_REC              0x1cUL
+#define CFA_RESOURCE_TYPE_P58_EM_REC             0xdUL
 /* Wildcard TCAM */
-#define CFA_RESOURCE_TYPE_P58_WC_TCAM             0x1dUL
+#define CFA_RESOURCE_TYPE_P58_WC_TCAM            0xeUL
 /* Meter profile */
-#define CFA_RESOURCE_TYPE_P58_METER_PROF          0x1eUL
+#define CFA_RESOURCE_TYPE_P58_METER_PROF         0xfUL
 /* Meter */
-#define CFA_RESOURCE_TYPE_P58_MIRROR              0x1fUL
-/* Source Property TCAM */
-#define CFA_RESOURCE_TYPE_P58_SP_TCAM             0x20UL
+#define CFA_RESOURCE_TYPE_P58_MIRROR             0x10UL
 /* Exact Match Flexible Key Builder */
-#define CFA_RESOURCE_TYPE_P58_EM_FKB              0x21UL
+#define CFA_RESOURCE_TYPE_P58_EM_FKB             0x11UL
 /* Wildcard Flexible Key Builder */
-#define CFA_RESOURCE_TYPE_P58_WC_FKB              0x22UL
+#define CFA_RESOURCE_TYPE_P58_WC_FKB             0x12UL
 /* VEB TCAM */
-#define CFA_RESOURCE_TYPE_P58_VEB_TCAM            0x23UL
-#define CFA_RESOURCE_TYPE_P58_LAST               CFA_RESOURCE_TYPE_P58_VEB_TCAM
+#define CFA_RESOURCE_TYPE_P58_VEB_TCAM           0x13UL
+#define CFA_RESOURCE_TYPE_P58_LAST              CFA_RESOURCE_TYPE_P58_VEB_TCAM
 
 
 /* Multicast Group */
diff --git a/drivers/net/bnxt/tf_core/tf_core.c b/drivers/net/bnxt/tf_core/tf_core.c
index 0dbde1de2..788335b81 100644
--- a/drivers/net/bnxt/tf_core/tf_core.c
+++ b/drivers/net/bnxt/tf_core/tf_core.c
@@ -34,7 +34,8 @@ tf_open_session(struct tf *tfp,
 	 * side. It is assumed that the Firmware will be supported if
 	 * firmware open session succeeds.
 	 */
-	if (parms->device_type != TF_DEVICE_TYPE_WH) {
+	if (parms->device_type != TF_DEVICE_TYPE_WH &&
+	    parms->device_type != TF_DEVICE_TYPE_SR) {
 		TFP_DRV_LOG(ERR,
 			    "Unsupported device type %d\n",
 			    parms->device_type);
diff --git a/drivers/net/bnxt/tf_core/tf_core.h b/drivers/net/bnxt/tf_core/tf_core.h
index db1093515..65be8f54a 100644
--- a/drivers/net/bnxt/tf_core/tf_core.h
+++ b/drivers/net/bnxt/tf_core/tf_core.h
@@ -10,7 +10,7 @@
 #include <stdlib.h>
 #include <stdbool.h>
 #include <stdio.h>
-#include "hcapi/hcapi_cfa.h"
+#include "hcapi/hcapi_cfa_defs.h"
 #include "tf_project.h"
 
 /**
diff --git a/drivers/net/bnxt/tf_core/tf_device.c b/drivers/net/bnxt/tf_core/tf_device.c
index 112944095..838982801 100644
--- a/drivers/net/bnxt/tf_core/tf_device.c
+++ b/drivers/net/bnxt/tf_core/tf_device.c
@@ -47,7 +47,6 @@ tf_dev_bind_p4(struct tf *tfp,
 	struct tf_if_tbl_cfg_parms if_tbl_cfg;
 	struct tf_global_cfg_cfg_parms global_cfg;
 
-	dev_handle->type = TF_DEVICE_TYPE_WH;
 	/* Initial function initialization */
 	dev_handle->ops = &tf_dev_ops_p4_init;
 
@@ -90,7 +89,10 @@ tf_dev_bind_p4(struct tf *tfp,
 	 * EEM
 	 */
 	em_cfg.num_elements = TF_EM_TBL_TYPE_MAX;
-	em_cfg.cfg = tf_em_ext_p4;
+	if (dev_handle->type == TF_DEVICE_TYPE_WH)
+		em_cfg.cfg = tf_em_ext_p4;
+	else
+		em_cfg.cfg = tf_em_ext_p45;
 	em_cfg.resources = resources;
 	em_cfg.mem_type = TF_EEM_MEM_TYPE_HOST;
 	rc = tf_em_ext_common_bind(tfp, &em_cfg);
@@ -241,6 +243,8 @@ tf_dev_bind(struct tf *tfp __rte_unused,
 {
 	switch (type) {
 	case TF_DEVICE_TYPE_WH:
+	case TF_DEVICE_TYPE_SR:
+		dev_handle->type = type;
 		return tf_dev_bind_p4(tfp,
 				      shadow_copy,
 				      resources,
@@ -258,6 +262,7 @@ tf_dev_unbind(struct tf *tfp,
 {
 	switch (dev_handle->type) {
 	case TF_DEVICE_TYPE_WH:
+	case TF_DEVICE_TYPE_SR:
 		return tf_dev_unbind_p4(tfp);
 	default:
 		TFP_DRV_LOG(ERR,
diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.c b/drivers/net/bnxt/tf_core/tf_device_p4.c
index fe8dec3af..0344565d7 100644
--- a/drivers/net/bnxt/tf_core/tf_device_p4.c
+++ b/drivers/net/bnxt/tf_core/tf_device_p4.c
@@ -28,13 +28,32 @@
  *   - (-EINVAL) on failure.
  */
 static int
-tf_dev_p4_get_max_types(struct tf *tfp __rte_unused,
+tf_dev_p4_get_max_types(struct tf *tfp,
 			uint16_t *max_types)
 {
-	if (max_types == NULL)
+	struct tf_session *tfs;
+	struct tf_dev_info *dev;
+	int rc;
+
+	if (max_types == NULL || tfp == NULL)
 		return -EINVAL;
 
-	*max_types = CFA_RESOURCE_TYPE_P4_LAST + 1;
+	/* Retrieve the session information */
+	rc = tf_session_get_session(tfp, &tfs);
+	if (rc)
+		return rc;
+
+	/* Retrieve the device information */
+	rc = tf_session_get_device(tfs, &dev);
+	if (rc)
+		return rc;
+
+	if (dev->type == TF_DEVICE_TYPE_WH)
+		*max_types = CFA_RESOURCE_TYPE_P4_LAST + 1;
+	else if (dev->type == TF_DEVICE_TYPE_SR)
+		*max_types = CFA_RESOURCE_TYPE_P45_LAST + 1;
+	else
+		return -ENODEV;
 
 	return 0;
 }
diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.h b/drivers/net/bnxt/tf_core/tf_device_p4.h
index 7e58469a0..aba28fe5f 100644
--- a/drivers/net/bnxt/tf_core/tf_device_p4.h
+++ b/drivers/net/bnxt/tf_core/tf_device_p4.h
@@ -83,6 +83,12 @@ struct tf_rm_element_cfg tf_em_ext_p4[TF_EM_TBL_TYPE_MAX] = {
 	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_TBL_SCOPE },
 };
 
+struct tf_rm_element_cfg tf_em_ext_p45[TF_EM_TBL_TYPE_MAX] = {
+	/* CFA_RESOURCE_TYPE_P4_EM_REC */
+	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
+	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_TBL_SCOPE },
+};
+
 struct tf_rm_element_cfg tf_em_int_p4[TF_EM_TBL_TYPE_MAX] = {
 	{ TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_EM_REC },
 	/* CFA_RESOURCE_TYPE_P4_TBL_SCOPE */
diff --git a/drivers/net/bnxt/tf_core/tf_device_p45.h b/drivers/net/bnxt/tf_core/tf_device_p45.h
new file mode 100644
index 000000000..016d6e254
--- /dev/null
+++ b/drivers/net/bnxt/tf_core/tf_device_p45.h
@@ -0,0 +1,105 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2019-2020 Broadcom
+ * All rights reserved.
+ */
+
+#ifndef _TF_DEVICE_P45_H_
+#define _TF_DEVICE_P45_H_
+
+#include <cfa_resource_types.h>
+
+#include "tf_core.h"
+#include "tf_rm.h"
+#include "tf_if_tbl.h"
+#include "tf_global_cfg.h"
+
+struct tf_rm_element_cfg tf_ident_p4[TF_IDENT_TYPE_MAX] = {
+	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_L2_CTXT_REMAP_HIGH },
+	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_L2_CTXT_REMAP_LOW },
+	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_PROF_FUNC },
+	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_WC_TCAM_PROF_ID },
+	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_EM_PROF_ID },
+	/* CFA_RESOURCE_TYPE_P45_L2_FUNC */
+	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }
+};
+
+struct tf_rm_element_cfg tf_tcam_p4[TF_TCAM_TBL_TYPE_MAX] = {
+	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_L2_CTXT_TCAM_HIGH },
+	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_L2_CTXT_TCAM_LOW },
+	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_PROF_TCAM },
+	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_WC_TCAM },
+	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_SP_TCAM },
+	/* CFA_RESOURCE_TYPE_P45_CT_RULE_TCAM */
+	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
+	/* CFA_RESOURCE_TYPE_P45_VEB_TCAM */
+	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }
+};
+
+struct tf_rm_element_cfg tf_tbl_p4[TF_TBL_TYPE_MAX] = {
+	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_FULL_ACTION },
+	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_MCG },
+	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_ENCAP_8B },
+	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_ENCAP_16B },
+	/* CFA_RESOURCE_TYPE_P45_ENCAP_32B */
+	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
+	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_ENCAP_64B },
+	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_SP_MAC },
+	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_SP_MAC_IPV4 },
+	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_SP_MAC_IPV6 },
+	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_COUNTER_64B },
+	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_NAT_PORT },
+	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_NAT_PORT },
+	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_NAT_IPV4 },
+	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_METER_PROF },
+	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_METER },
+	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_MIRROR },
+	/* CFA_RESOURCE_TYPE_P45_UPAR */
+	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
+	/* CFA_RESOURCE_TYPE_P45_EPOC */
+	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
+	/* CFA_RESOURCE_TYPE_P45_METADATA */
+	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
+	/* CFA_RESOURCE_TYPE_P45_CT_STATE */
+	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
+	/* CFA_RESOURCE_TYPE_P45_RANGE_PROF */
+	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
+	/* CFA_RESOURCE_TYPE_P45_RANGE_ENTRY */
+	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
+	/* CFA_RESOURCE_TYPE_P45_LAG */
+	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
+	/* CFA_RESOURCE_TYPE_P45_VNIC_SVIF */
+	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
+	/* CFA_RESOURCE_TYPE_P45_EM_FBK */
+	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
+	/* CFA_RESOURCE_TYPE_P45_WC_FKB */
+	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
+	/* CFA_RESOURCE_TYPE_P45_EXT */
+	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }
+};
+
+struct tf_rm_element_cfg tf_em_ext_p4[TF_EM_TBL_TYPE_MAX] = {
+	/* CFA_RESOURCE_TYPE_P45_EM_REC */
+	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
+	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_TBL_SCOPE },
+};
+
+struct tf_rm_element_cfg tf_em_int_p4[TF_EM_TBL_TYPE_MAX] = {
+	{ TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P45_EM_REC },
+	/* CFA_RESOURCE_TYPE_P45_TBL_SCOPE */
+	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
+};
+
+struct tf_if_tbl_cfg tf_if_tbl_p4[TF_IF_TBL_TYPE_MAX] = {
+	{ TF_IF_TBL_CFG, CFA_P4_TBL_PROF_SPIF_DFLT_L2CTXT },
+	{ TF_IF_TBL_CFG, CFA_P4_TBL_PROF_PARIF_DFLT_ACT_REC_PTR },
+	{ TF_IF_TBL_CFG, CFA_P4_TBL_PROF_PARIF_ERR_ACT_REC_PTR },
+	{ TF_IF_TBL_CFG, CFA_P4_TBL_LKUP_PARIF_DFLT_ACT_REC_PTR },
+	{ TF_IF_TBL_CFG_NULL, CFA_IF_TBL_TYPE_INVALID },
+	{ TF_IF_TBL_CFG_NULL, CFA_IF_TBL_TYPE_INVALID }
+};
+
+struct tf_global_cfg_cfg tf_global_cfg_p4[TF_GLOBAL_CFG_TYPE_MAX] = {
+	{ TF_GLOBAL_CFG_CFG_HCAPI, TF_TUNNEL_ENCAP },
+	{ TF_GLOBAL_CFG_CFG_HCAPI, TF_ACTION_BLOCK },
+};
+#endif /* _TF_DEVICE_P45_H_ */
diff --git a/drivers/net/bnxt/tf_core/tf_em.h b/drivers/net/bnxt/tf_core/tf_em.h
index 2a67e4760..51b08138e 100644
--- a/drivers/net/bnxt/tf_core/tf_em.h
+++ b/drivers/net/bnxt/tf_core/tf_em.h
@@ -9,12 +9,6 @@
 #include "tf_core.h"
 #include "tf_session.h"
 
-
-#define SUPPORT_CFA_HW_P4 1
-#define SUPPORT_CFA_HW_P58 0
-#define SUPPORT_CFA_HW_P59 0
-#define SUPPORT_CFA_HW_ALL 0
-
 #include "hcapi/hcapi_cfa_defs.h"
 
 #define TF_EM_MIN_ENTRIES     (1 << 15) /* 32K */
-- 
2.21.1 (Apple Git-122.3)


^ permalink raw reply	[flat|nested] 32+ messages in thread

* [dpdk-dev] [PATCH v2 02/11] net/bnxt: changes to support two table scopes
  2020-10-20 21:55 ` [dpdk-dev] [PATCH v2 00/11] bnxt fixes and enhancements to TRUFLOW support Ajit Khaparde
  2020-10-20 21:55   ` [dpdk-dev] [PATCH v2 01/11] net/bnxt: add stingray support to core layer Ajit Khaparde
@ 2020-10-20 21:55   ` Ajit Khaparde
  2020-10-20 21:55   ` [dpdk-dev] [PATCH v2 03/11] net/bnxt: add table scope to PF Mapping Ajit Khaparde
                     ` (9 subsequent siblings)
  11 siblings, 0 replies; 32+ messages in thread
From: Ajit Khaparde @ 2020-10-20 21:55 UTC (permalink / raw)
  To: dev; +Cc: Jay Ding, Farah Smith, Randy Schacher

From: Jay Ding <jay.ding@broadcom.com>

New API to map a PARIF to an EEM table scope (set of Rx and Tx EEM
base addresses). It uses HWRM_TF_GLOBAL_CFG_SET HWRM to configure.
PARIF is handler to a partition of the physical port.
Adjustments to tf_global_cfg_set() to reduce overhead and nominal
name clarification.

Signed-off-by: Jay Ding <jay.ding@broadcom.com>
Signed-off-by: Farah Smith <farah.smith@broadcom.com>
Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
 drivers/net/bnxt/tf_core/tf_core.c       |  54 +++++--
 drivers/net/bnxt/tf_core/tf_core.h       |  55 ++++++-
 drivers/net/bnxt/tf_core/tf_device.h     |  43 +++++-
 drivers/net/bnxt/tf_core/tf_device_p4.c  |  44 ++++++
 drivers/net/bnxt/tf_core/tf_em.h         |  19 ++-
 drivers/net/bnxt/tf_core/tf_em_common.c  | 174 ++++++++++++-----------
 drivers/net/bnxt/tf_core/tf_em_common.h  |  27 +---
 drivers/net/bnxt/tf_core/tf_em_host.c    |  23 ++-
 drivers/net/bnxt/tf_core/tf_global_cfg.c |   4 +-
 drivers/net/bnxt/tf_core/tf_global_cfg.h |  42 ++----
 drivers/net/bnxt/tf_core/tf_msg.c        |  13 +-
 drivers/net/bnxt/tf_core/tf_msg.h        |   4 +-
 12 files changed, 326 insertions(+), 176 deletions(-)

diff --git a/drivers/net/bnxt/tf_core/tf_core.c b/drivers/net/bnxt/tf_core/tf_core.c
index 788335b81..0f49a0025 100644
--- a/drivers/net/bnxt/tf_core/tf_core.c
+++ b/drivers/net/bnxt/tf_core/tf_core.c
@@ -303,7 +303,6 @@ int tf_get_global_cfg(struct tf *tfp,
 	int rc = 0;
 	struct tf_session *tfs;
 	struct tf_dev_info *dev;
-	struct tf_dev_global_cfg_parms gparms = { 0 };
 
 	TF_CHECK_PARMS2(tfp, parms);
 
@@ -342,12 +341,7 @@ int tf_get_global_cfg(struct tf *tfp,
 		return -EOPNOTSUPP;
 	}
 
-	gparms.dir = parms->dir;
-	gparms.type = parms->type;
-	gparms.offset = parms->offset;
-	gparms.config = parms->config;
-	gparms.config_sz_in_bytes = parms->config_sz_in_bytes;
-	rc = dev->ops->tf_dev_get_global_cfg(tfp, &gparms);
+	rc = dev->ops->tf_dev_get_global_cfg(tfp, parms);
 	if (rc) {
 		TFP_DRV_LOG(ERR,
 			    "%s: Global Cfg get failed, rc:%s\n",
@@ -371,7 +365,6 @@ int tf_set_global_cfg(struct tf *tfp,
 	int rc = 0;
 	struct tf_session *tfs;
 	struct tf_dev_info *dev;
-	struct tf_dev_global_cfg_parms gparms = { 0 };
 
 	TF_CHECK_PARMS2(tfp, parms);
 
@@ -410,12 +403,7 @@ int tf_set_global_cfg(struct tf *tfp,
 		return -EOPNOTSUPP;
 	}
 
-	gparms.dir = parms->dir;
-	gparms.type = parms->type;
-	gparms.offset = parms->offset;
-	gparms.config = parms->config;
-	gparms.config_sz_in_bytes = parms->config_sz_in_bytes;
-	rc = dev->ops->tf_dev_set_global_cfg(tfp, &gparms);
+	rc = dev->ops->tf_dev_set_global_cfg(tfp, parms);
 	if (rc) {
 		TFP_DRV_LOG(ERR,
 			    "%s: Global Cfg set failed, rc:%s\n",
@@ -1352,6 +1340,44 @@ tf_alloc_tbl_scope(struct tf *tfp,
 
 	return rc;
 }
+int
+tf_map_tbl_scope(struct tf *tfp,
+		   struct tf_map_tbl_scope_parms *parms)
+{
+	struct tf_session *tfs;
+	struct tf_dev_info *dev;
+	int rc;
+
+	TF_CHECK_PARMS2(tfp, parms);
+
+	/* Retrieve the session information */
+	rc = tf_session_get_session(tfp, &tfs);
+	if (rc) {
+		TFP_DRV_LOG(ERR,
+			    "Failed to lookup session, rc:%s\n",
+			    strerror(-rc));
+		return rc;
+	}
+
+	/* Retrieve the device information */
+	rc = tf_session_get_device(tfs, &dev);
+	if (rc) {
+		TFP_DRV_LOG(ERR,
+			    "Failed to lookup device, rc:%s\n",
+			    strerror(-rc));
+		return rc;
+	}
+
+	if (dev->ops->tf_dev_map_tbl_scope != NULL) {
+		rc = dev->ops->tf_dev_map_tbl_scope(tfp, parms);
+	} else {
+		TFP_DRV_LOG(ERR,
+			    "Map table scope not supported by device\n");
+		return -EINVAL;
+	}
+
+	return rc;
+}
 
 int
 tf_free_tbl_scope(struct tf *tfp,
diff --git a/drivers/net/bnxt/tf_core/tf_core.h b/drivers/net/bnxt/tf_core/tf_core.h
index 65be8f54a..fa8ab52af 100644
--- a/drivers/net/bnxt/tf_core/tf_core.h
+++ b/drivers/net/bnxt/tf_core/tf_core.h
@@ -898,7 +898,9 @@ struct tf_alloc_tbl_scope_parms {
 	 */
 	uint32_t tbl_scope_id;
 };
-
+/**
+ * tf_free_tbl_scope_parms definition
+ */
 struct tf_free_tbl_scope_parms {
 	/**
 	 * [in] table scope identifier
@@ -906,6 +908,21 @@ struct tf_free_tbl_scope_parms {
 	uint32_t tbl_scope_id;
 };
 
+/**
+ * tf_map_tbl_scope_parms definition
+ */
+struct tf_map_tbl_scope_parms {
+	/**
+	 * [in] table scope identifier
+	 */
+	uint32_t tbl_scope_id;
+	/**
+	 * [in] Which parifs are associated with this table scope.  Bit 0
+	 *      indicates parif 0.
+	 */
+	uint16_t parif_bitmask;
+};
+
 /**
  * allocate a table scope
  *
@@ -915,13 +932,13 @@ struct tf_free_tbl_scope_parms {
  * device constraints based upon calculations using either the number of flows
  * requested or the size of memory indicated.  Other parameters passed in
  * determine the configuration (maximum key size, maximum external action record
- * size.
+ * size).
  *
- * This API will allocate the table region in
- * DRAM, program the PTU page table entries, and program the number of static
- * buckets (if SR2) in the RX and TX CFAs.  Buckets are assumed to start at
- * 0 in the EM memory for the scope.  Upon successful completion of this API,
- * hash tables are fully initialized and ready for entries to be inserted.
+ * This API will allocate the table region in DRAM, program the PTU page table
+ * entries, and program the number of static buckets (if SR2) in the RX and TX
+ * CFAs.  Buckets are assumed to start at 0 in the EM memory for the scope.
+ * Upon successful completion of this API, hash tables are fully initialized and
+ * ready for entries to be inserted.
  *
  * A single API is used to allocate a common table scope identifier in both
  * receive and transmit CFA. The scope identifier is common due to nature of
@@ -944,7 +961,25 @@ struct tf_free_tbl_scope_parms {
 int tf_alloc_tbl_scope(struct tf *tfp,
 		       struct tf_alloc_tbl_scope_parms *parms);
 
+/**
+ * map a table scope (legacy device only Wh+/SR)
+ *
+ * Map a table scope to one or more partition interfaces (parifs).
+ * The parif can be remapped in the L2 context lookup for legacy devices.  This
+ * API allows a number of parifs to be mapped to the same table scope.  On
+ * legacy devices a table scope identifies one of 16 sets of EEM table base
+ * addresses and is associated with a PF communication channel.  The associated
+ * PF must be configured for the table scope to operate.
+ *
+ * An L2 context TCAM lookup returns a remapped parif value used to
+ * index into the set of 16 parif_to_pf registers which are used to map to one
+ * of the 16 table scopes.  This API allows the user to map the parifs in the
+ * mask to the previously allocated table scope (EEM table).
 
+ * Returns success or failure code.
+ */
+int tf_map_tbl_scope(struct tf *tfp,
+		      struct tf_map_tbl_scope_parms *parms);
 /**
  * free a table scope
  *
@@ -1908,6 +1943,12 @@ struct tf_global_cfg_parms {
 	 * get - Read the full configuration
 	 */
 	uint8_t *config;
+	/**
+	 * [in] Configuration mask
+	 * set - Read, Modify with mask and Write
+	 * get - unused
+	 */
+	uint8_t *config_mask;
 	/**
 	 * [in] struct containing size
 	 */
diff --git a/drivers/net/bnxt/tf_core/tf_device.h b/drivers/net/bnxt/tf_core/tf_device.h
index fce7f25a8..cf7c36e0e 100644
--- a/drivers/net/bnxt/tf_core/tf_device.h
+++ b/drivers/net/bnxt/tf_core/tf_device.h
@@ -573,6 +573,45 @@ struct tf_dev_ops {
 	 */
 	int (*tf_dev_alloc_tbl_scope)(struct tf *tfp,
 				      struct tf_alloc_tbl_scope_parms *parms);
+	/**
+	 * Map EEM parif
+	 *
+	 * [in] tfp
+	 *   Pointer to TF handle
+	 *
+	 * [in] parms
+	 *   Pointer to table scope map parameters
+	 *
+	 * [in/out] pointer to the parif_2_pf data to be updated
+	 *
+	 * [in/out] pointer to the parif_2_pf mask to be updated
+	 *
+	 * [in] sz_in_bytes - number of bytes to be written
+	 *
+	 *    returns:
+	 *    0       - Success
+	 *    -EINVAL - Error
+	 */
+	int (*tf_dev_map_parif)(struct tf *tfp,
+				struct tf_map_tbl_scope_parms *parms,
+				uint8_t *data,
+				uint8_t *mask,
+				uint16_t sz_in_bytes);
+	/**
+	 * Map EEM table scope
+	 *
+	 * [in] tfp
+	 *   Pointer to TF handle
+	 *
+	 * [in] parms
+	 *   Pointer to table scope map parameters
+	 *
+	 *    returns:
+	 *    0       - Success
+	 *    -EINVAL - Error
+	 */
+	int (*tf_dev_map_tbl_scope)(struct tf *tfp,
+				    struct tf_map_tbl_scope_parms *parms);
 
 	/**
 	 * Free EEM table scope
@@ -642,7 +681,7 @@ struct tf_dev_ops {
 	 *    -EINVAL - Error
 	 */
 	int (*tf_dev_set_global_cfg)(struct tf *tfp,
-				     struct tf_dev_global_cfg_parms *parms);
+				     struct tf_global_cfg_parms *parms);
 
 	/**
 	 * Get global cfg
@@ -658,7 +697,7 @@ struct tf_dev_ops {
 	 *    -EINVAL - Error
 	 */
 	int (*tf_dev_get_global_cfg)(struct tf *tfp,
-				     struct tf_dev_global_cfg_parms *parms);
+				     struct tf_global_cfg_parms *parms);
 };
 
 /**
diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.c b/drivers/net/bnxt/tf_core/tf_device_p4.c
index 0344565d7..07c8d02fa 100644
--- a/drivers/net/bnxt/tf_core/tf_device_p4.c
+++ b/drivers/net/bnxt/tf_core/tf_device_p4.c
@@ -12,6 +12,10 @@
 #include "tf_tcam.h"
 #include "tf_em.h"
 #include "tf_if_tbl.h"
+#include "tfp.h"
+
+#define TF_DEV_P4_PARIF_MAX 16
+#define TF_DEV_P4_PF_MASK 0xfUL
 
 /**
  * Device specific function that retrieves the MAX number of HCAPI
@@ -97,6 +101,42 @@ tf_dev_p4_get_tcam_slice_info(struct tf *tfp __rte_unused,
 	return 0;
 }
 
+static int
+tf_dev_p4_map_parif(struct tf *tfp __rte_unused,
+		    struct tf_map_tbl_scope_parms *parms,
+		    uint8_t *data,
+		    uint8_t *mask,
+		    uint16_t sz_in_bytes)
+{
+	uint32_t parif_pf[2] = { 0 };
+	uint32_t parif_pf_mask[2] = { 0 };
+	uint32_t parif;
+	uint32_t shift;
+	uint32_t scope_id = (uint32_t)(parms->tbl_scope_id);
+
+	if (sz_in_bytes != sizeof(uint64_t))
+		return -ENOTSUP;
+
+	for (parif = 0; parif < TF_DEV_P4_PARIF_MAX; parif++) {
+		if (parms->parif_bitmask & (1UL << parif)) {
+			if (parif < 8) {
+				shift = 4 * parif;
+				parif_pf_mask[0] |= TF_DEV_P4_PF_MASK << shift;
+				parif_pf[0] |= scope_id << shift;
+			} else {
+				shift = 4 * (parif - 8);
+				parif_pf_mask[1] |= TF_DEV_P4_PF_MASK << shift;
+				parif_pf[1] |= scope_id << shift;
+			}
+		}
+	}
+	tfp_memcpy(data, parif_pf, sz_in_bytes);
+	tfp_memcpy(mask, parif_pf_mask, sz_in_bytes);
+
+	return 0;
+}
+
+
 /**
  * Truflow P4 device specific functions
  */
@@ -125,6 +165,8 @@ const struct tf_dev_ops tf_dev_ops_p4_init = {
 	.tf_dev_insert_ext_em_entry = NULL,
 	.tf_dev_delete_ext_em_entry = NULL,
 	.tf_dev_alloc_tbl_scope = NULL,
+	.tf_dev_map_tbl_scope = NULL,
+	.tf_dev_map_parif = NULL,
 	.tf_dev_free_tbl_scope = NULL,
 	.tf_dev_set_if_tbl = NULL,
 	.tf_dev_get_if_tbl = NULL,
@@ -160,6 +202,8 @@ const struct tf_dev_ops tf_dev_ops_p4 = {
 	.tf_dev_insert_ext_em_entry = tf_em_insert_ext_entry,
 	.tf_dev_delete_ext_em_entry = tf_em_delete_ext_entry,
 	.tf_dev_alloc_tbl_scope = tf_em_ext_common_alloc,
+	.tf_dev_map_tbl_scope = tf_em_ext_map_tbl_scope,
+	.tf_dev_map_parif = tf_dev_p4_map_parif,
 	.tf_dev_free_tbl_scope = tf_em_ext_common_free,
 	.tf_dev_set_if_tbl = tf_if_tbl_set,
 	.tf_dev_get_if_tbl = tf_if_tbl_get,
diff --git a/drivers/net/bnxt/tf_core/tf_em.h b/drivers/net/bnxt/tf_core/tf_em.h
index 51b08138e..8820b28ef 100644
--- a/drivers/net/bnxt/tf_core/tf_em.h
+++ b/drivers/net/bnxt/tf_core/tf_em.h
@@ -358,7 +358,7 @@ int tf_em_ext_free(struct tf *tfp,
 		   struct tf_free_tbl_scope_parms *parms);
 
 /**
- * Common free for external EEM using host or system memory
+ * Common free table scope for external EEM using host or system memory
  *
  * [in] tfp
  *   Pointer to TruFlow handle
@@ -374,7 +374,7 @@ int tf_em_ext_common_free(struct tf *tfp,
 			  struct tf_free_tbl_scope_parms *parms);
 
 /**
- * Common alloc for external EEM using host or system memory
+ * Common alloc table scope for external EEM using host or system memory
  *
  * [in] tfp
  *   Pointer to TruFlow handle
@@ -388,6 +388,21 @@ int tf_em_ext_common_free(struct tf *tfp,
  */
 int tf_em_ext_common_alloc(struct tf *tfp,
 			   struct tf_alloc_tbl_scope_parms *parms);
+/**
+ * Map a set of parifs to a set of EEM base addresses (table scope)
+ *
+ * [in] tfp
+ *   Pointer to TruFlow handle
+ *
+ * [in] parms
+ *   Pointer to input parameters
+ *
+ * Returns:
+ *   0       - Success
+ *   -EINVAL - Parameter error
+ */
+int tf_em_ext_map_tbl_scope(struct tf *tfp,
+			    struct tf_map_tbl_scope_parms *parms);
 
 /**
  * Allocate External Tbl entry from the scope pool.
diff --git a/drivers/net/bnxt/tf_core/tf_em_common.c b/drivers/net/bnxt/tf_core/tf_em_common.c
index 0d8b90871..a6ddb4eaf 100644
--- a/drivers/net/bnxt/tf_core/tf_em_common.c
+++ b/drivers/net/bnxt/tf_core/tf_em_common.c
@@ -44,28 +44,6 @@ static enum tf_mem_type mem_type;
 /** Table scope array */
 struct tf_tbl_scope_cb tbl_scopes[TF_NUM_TBL_SCOPE];
 
-/** Table scope reversal table
- *
- * Table scope are allocated from 15 to 0 within HCAPI RM.  Because of the
- * association between PFs and legacy table scopes, reverse table scope ids.
- * 15 indicates 0, 14 indicates 1, etc... The application will only see the 0
- * based number.  The firmware will only use the 0 based number.  Only HCAPI RM
- * and Truflow RM believe the number is 15.  When HCAPI RM support allocation
- * from low to high is supported, this adjust function can be removed.
- */
-const uint32_t tbl_scope_reverse[TF_NUM_TBL_SCOPE] = {
-	15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0 };
-
-static uint32_t
-tf_tbl_scope_adjust(uint32_t tbl_scope_id)
-{
-	if (tbl_scope_id < TF_NUM_TBL_SCOPE)
-		return tbl_scope_reverse[tbl_scope_id];
-	else
-		return TF_TBL_SCOPE_INVALID;
-};
-
-
 /* API defined in tf_em.h */
 struct tf_tbl_scope_cb *
 tbl_scope_cb_find(uint32_t tbl_scope_id)
@@ -73,17 +51,11 @@ tbl_scope_cb_find(uint32_t tbl_scope_id)
 	int i;
 	struct tf_rm_is_allocated_parms parms = { 0 };
 	int allocated;
-	uint32_t rm_tbl_scope_id;
-
-	rm_tbl_scope_id = tf_tbl_scope_adjust(tbl_scope_id);
-
-	if (rm_tbl_scope_id == TF_TBL_SCOPE_INVALID)
-		return NULL;
 
 	/* Check that id is valid */
 	parms.rm_db = eem_db[TF_DIR_RX];
 	parms.db_index = TF_EM_TBL_TYPE_TBL_SCOPE;
-	parms.index = rm_tbl_scope_id;
+	parms.index = tbl_scope_id;
 	parms.allocated = &allocated;
 
 	i = tf_rm_is_allocated(&parms);
@@ -99,61 +71,6 @@ tbl_scope_cb_find(uint32_t tbl_scope_id)
 	return NULL;
 }
 
-int tf_tbl_scope_alloc(uint32_t *tbl_scope_id)
-{
-	int rc;
-	struct tf_rm_allocate_parms parms = { 0 };
-	uint32_t rm_tbl_scope_id;
-	uint32_t usr_tbl_scope_id = TF_TBL_SCOPE_INVALID;
-
-	/* Get Table Scope control block from the session pool */
-	parms.rm_db = eem_db[TF_DIR_RX];
-	parms.db_index = TF_EM_TBL_TYPE_TBL_SCOPE;
-	parms.index = &rm_tbl_scope_id;
-
-	rc = tf_rm_allocate(&parms);
-	if (rc) {
-		TFP_DRV_LOG(ERR,
-			    "Failed to allocate table scope rc:%s\n",
-			    strerror(-rc));
-		return rc;
-	}
-
-	usr_tbl_scope_id = tf_tbl_scope_adjust(rm_tbl_scope_id);
-
-	if (usr_tbl_scope_id == TF_TBL_SCOPE_INVALID) {
-		TFP_DRV_LOG(ERR,
-			    "Invalid table scope allocated id:%d\n",
-			    (int)rm_tbl_scope_id);
-		return -EINVAL;
-	}
-	*tbl_scope_id = usr_tbl_scope_id;
-	return 0;
-};
-
-int tf_tbl_scope_free(uint32_t tbl_scope_id)
-{
-	struct tf_rm_free_parms parms = { 0 };
-	uint32_t rm_tbl_scope_id;
-	uint32_t rc;
-
-	rm_tbl_scope_id = tf_tbl_scope_adjust(tbl_scope_id);
-
-	if (rm_tbl_scope_id == TF_TBL_SCOPE_INVALID) {
-		TFP_DRV_LOG(ERR,
-			    "Invalid table scope allocated id:%d\n",
-			    (int)tbl_scope_id);
-		return -EINVAL;
-	}
-
-	parms.rm_db = eem_db[TF_DIR_RX];
-	parms.db_index = TF_EM_TBL_TYPE_TBL_SCOPE;
-	parms.index = rm_tbl_scope_id;
-
-	rc = tf_rm_free(&parms);
-	return rc;
-};
-
 int
 tf_create_tbl_pool_external(enum tf_dir dir,
 			    struct tf_tbl_scope_cb *tbl_scope_cb,
@@ -1129,3 +1046,92 @@ tf_em_ext_common_free(struct tf *tfp,
 {
 	return tf_em_ext_free(tfp, parms);
 }
+
+int tf_em_ext_map_tbl_scope(struct tf *tfp,
+			    struct tf_map_tbl_scope_parms *parms)
+{
+	int rc = 0;
+	struct tf_session *tfs;
+	struct tf_tbl_scope_cb *tbl_scope_cb;
+	struct tf_global_cfg_parms gcfg_parms = { 0 };
+	struct tfp_calloc_parms aparms;
+	uint32_t *data, *mask;
+	uint32_t sz_in_bytes = 8;
+	struct tf_dev_info *dev;
+
+	tbl_scope_cb = tbl_scope_cb_find(parms->tbl_scope_id);
+
+	if (tbl_scope_cb == NULL) {
+		TFP_DRV_LOG(ERR, "Invalid tbl_scope_cb tbl_scope_id(%d)\n",
+			    parms->tbl_scope_id);
+		return -EINVAL;
+	}
+
+	/* Retrieve the session information */
+	rc = tf_session_get_session_internal(tfp, &tfs);
+	if (rc)
+		return rc;
+
+	/* Retrieve the device information */
+	rc = tf_session_get_device(tfs, &dev);
+	if (rc)
+		return rc;
+
+	if (dev->ops->tf_dev_map_tbl_scope == NULL) {
+		rc = -EOPNOTSUPP;
+		TFP_DRV_LOG(ERR,
+			    "Map table scope operation not supported, rc:%s\n",
+			    strerror(-rc));
+		return rc;
+	}
+
+	aparms.nitems = 2;
+	aparms.size = sizeof(uint32_t);
+	aparms.alignment = 0;
+
+	if (tfp_calloc(&aparms) != 0) {
+		TFP_DRV_LOG(ERR, "Map tbl scope alloc data error %s\n",
+			    strerror(ENOMEM));
+		return -ENOMEM;
+	}
+	data = aparms.mem_va;
+
+	if (tfp_calloc(&aparms) != 0) {
+		TFP_DRV_LOG(ERR, "Map tbl scope alloc mask error %s\n",
+			    strerror(ENOMEM));
+		rc = -ENOMEM;
+		goto clean;
+	}
+	mask = aparms.mem_va;
+
+	rc = dev->ops->tf_dev_map_parif(tfp, parms, (uint8_t *)data,
+					(uint8_t *)mask, sz_in_bytes);
+
+	if (rc) {
+		TFP_DRV_LOG(ERR,
+			    "Map table scope config failure, rc:%s\n",
+			    strerror(-rc));
+		goto cleaner;
+	}
+
+	gcfg_parms.type =
+		(enum tf_global_config_type) TF_GLOBAL_CFG_INTERNAL_PARIF_2_PF;
+	gcfg_parms.offset = 0;
+	gcfg_parms.config = (uint8_t *)data;
+	gcfg_parms.config_mask = (uint8_t *)mask;
+	gcfg_parms.config_sz_in_bytes = sizeof(uint64_t);
+
+
+	rc = tf_msg_set_global_cfg(tfp, &gcfg_parms);
+	if (rc) {
+		TFP_DRV_LOG(ERR,
+			    "Map tbl scope, set failed, rc:%s\n",
+			    strerror(-rc));
+	}
+cleaner:
+	tfp_free(mask);
+clean:
+	tfp_free(data);
+
+	return rc;
+}
diff --git a/drivers/net/bnxt/tf_core/tf_em_common.h b/drivers/net/bnxt/tf_core/tf_em_common.h
index f71a48767..fa313c458 100644
--- a/drivers/net/bnxt/tf_core/tf_em_common.h
+++ b/drivers/net/bnxt/tf_core/tf_em_common.h
@@ -9,6 +9,7 @@
 #include "tf_core.h"
 #include "tf_session.h"
 
+
 /**
  * Function to search for table scope control block structure
  * with specified table scope ID.
@@ -22,32 +23,6 @@
  */
 struct tf_tbl_scope_cb *tbl_scope_cb_find(uint32_t tbl_scope_id);
 
-/**
- * Table Scope Allocate
- *
- * Allocate a table scope
- *
- * [in/out] pointer to tbl_scope_id
- *
- * Returns:
- *  0 - success
- *  -EINVAL - error
- */
-int tf_tbl_scope_alloc(uint32_t *tbl_scope_id);
-
-/**
- * Table Scope Free
- *
- * Free a table scope
- *
- * [in] tbl_scope_id to free
- *
- * Returns:
- *  0 - success
- *  -EINVAL - error
- */
-int tf_tbl_scope_free(uint32_t tbl_scope_id);
-
 /**
  * Create and initialize a stack to use for action entries
  *
diff --git a/drivers/net/bnxt/tf_core/tf_em_host.c b/drivers/net/bnxt/tf_core/tf_em_host.c
index cfcb12f3b..b5db94f3e 100644
--- a/drivers/net/bnxt/tf_core/tf_em_host.c
+++ b/drivers/net/bnxt/tf_core/tf_em_host.c
@@ -374,8 +374,14 @@ tf_em_ext_alloc(struct tf *tfp, struct tf_alloc_tbl_scope_parms *parms)
 	struct tf_tbl_scope_cb *tbl_scope_cb;
 	struct hcapi_cfa_em_table *em_tables;
 	struct tf_free_tbl_scope_parms free_parms;
-
-	rc = tf_tbl_scope_alloc(&parms->tbl_scope_id);
+	struct tf_rm_allocate_parms aparms = { 0 };
+	struct tf_rm_free_parms fparms = { 0 };
+
+	/* Get Table Scope control block from the session pool */
+	aparms.rm_db = eem_db[TF_DIR_RX];
+	aparms.db_index = TF_EM_TBL_TYPE_TBL_SCOPE;
+	aparms.index = (uint32_t *)&parms->tbl_scope_id;
+	rc = tf_rm_allocate(&aparms);
 	if (rc) {
 		TFP_DRV_LOG(ERR,
 			    "Failed to allocate table scope\n");
@@ -472,7 +478,11 @@ tf_em_ext_alloc(struct tf *tfp, struct tf_alloc_tbl_scope_parms *parms)
 	return -EINVAL;
 
 cleanup:
-	tf_tbl_scope_free(parms->tbl_scope_id);
+	/* Free Table control block */
+	fparms.rm_db = eem_db[TF_DIR_RX];
+	fparms.db_index = TF_EM_TBL_TYPE_TBL_SCOPE;
+	fparms.index = parms->tbl_scope_id;
+	tf_rm_free(&fparms);
 	return -EINVAL;
 }
 
@@ -483,6 +493,7 @@ tf_em_ext_free(struct tf *tfp,
 	int rc = 0;
 	enum tf_dir  dir;
 	struct tf_tbl_scope_cb *tbl_scope_cb;
+	struct tf_rm_free_parms aparms = { 0 };
 
 	tbl_scope_cb = tbl_scope_cb_find(parms->tbl_scope_id);
 
@@ -491,7 +502,11 @@ tf_em_ext_free(struct tf *tfp,
 		return -EINVAL;
 	}
 
-	rc = tf_tbl_scope_free(parms->tbl_scope_id);
+	/* Free Table control block */
+	aparms.rm_db = eem_db[TF_DIR_RX];
+	aparms.db_index = TF_EM_TBL_TYPE_TBL_SCOPE;
+	aparms.index = parms->tbl_scope_id;
+	rc = tf_rm_free(&aparms);
 	if (rc) {
 		TFP_DRV_LOG(ERR,
 			    "Failed to free table scope\n");
diff --git a/drivers/net/bnxt/tf_core/tf_global_cfg.c b/drivers/net/bnxt/tf_core/tf_global_cfg.c
index 4ed4039db..ebd1a86ad 100644
--- a/drivers/net/bnxt/tf_core/tf_global_cfg.c
+++ b/drivers/net/bnxt/tf_core/tf_global_cfg.c
@@ -113,7 +113,7 @@ tf_global_cfg_unbind(struct tf *tfp __rte_unused)
 
 int
 tf_global_cfg_set(struct tf *tfp,
-		  struct tf_dev_global_cfg_parms *parms)
+		  struct tf_global_cfg_parms *parms)
 {
 	int rc;
 	struct tf_global_cfg_get_hcapi_parms hparms;
@@ -156,7 +156,7 @@ tf_global_cfg_set(struct tf *tfp,
 
 int
 tf_global_cfg_get(struct tf *tfp,
-		  struct tf_dev_global_cfg_parms *parms)
+		  struct tf_global_cfg_parms *parms)
 
 {
 	int rc;
diff --git a/drivers/net/bnxt/tf_core/tf_global_cfg.h b/drivers/net/bnxt/tf_core/tf_global_cfg.h
index 5c73bb115..685f38dc7 100644
--- a/drivers/net/bnxt/tf_core/tf_global_cfg.h
+++ b/drivers/net/bnxt/tf_core/tf_global_cfg.h
@@ -13,7 +13,15 @@
  * The global cfg module provides processing of global cfg types.
  */
 
-struct tf;
+/* struct tf; */
+
+/* Internal type not available to user
+ * but available internally within Truflow
+ */
+enum tf_global_config_internal_type {
+	TF_GLOBAL_CFG_INTERNAL_PARIF_2_PF = TF_GLOBAL_CFG_TYPE_MAX,
+	TF_GLOBAL_CFG_INTERNAL_TYPE_MAX
+};
 
 /**
  * Global cfg configuration enumeration.
@@ -61,34 +69,6 @@ struct tf_global_cfg_cfg_parms {
 	struct tf_global_cfg_cfg *cfg;
 };
 
-/**
- * global cfg parameters
- */
-struct tf_dev_global_cfg_parms {
-	/**
-	 * [in] Receive or transmit direction
-	 */
-	enum tf_dir dir;
-	/**
-	 * [in] Global config type
-	 */
-	enum tf_global_config_type type;
-	/**
-	 * [in] Offset @ the type
-	 */
-	uint32_t offset;
-	/**
-	 * [in/out] Value of the configuration
-	 * set - Read, Modify and Write
-	 * get - Read the full configuration
-	 */
-	uint8_t *config;
-	/**
-	 * [in] struct containing size
-	 */
-	uint16_t config_sz_in_bytes;
-};
-
 /**
  * @page global cfg
  *
@@ -149,7 +129,7 @@ tf_global_cfg_unbind(struct tf *tfp);
  *   - (-EINVAL) on failure.
  */
 int tf_global_cfg_set(struct tf *tfp,
-		      struct tf_dev_global_cfg_parms *parms);
+		      struct tf_global_cfg_parms *parms);
 
 /**
  * Get global configuration
@@ -165,6 +145,6 @@ int tf_global_cfg_set(struct tf *tfp,
  *   - (-EINVAL) on failure.
  */
 int tf_global_cfg_get(struct tf *tfp,
-		      struct tf_dev_global_cfg_parms *parms);
+		      struct tf_global_cfg_parms *parms);
 
 #endif /* TF_GLOBAL_CFG_H */
diff --git a/drivers/net/bnxt/tf_core/tf_msg.c b/drivers/net/bnxt/tf_core/tf_msg.c
index 7c2ad172f..5615eedbb 100644
--- a/drivers/net/bnxt/tf_core/tf_msg.c
+++ b/drivers/net/bnxt/tf_core/tf_msg.c
@@ -1075,7 +1075,7 @@ tf_msg_get_tbl_entry(struct tf *tfp,
 
 int
 tf_msg_get_global_cfg(struct tf *tfp,
-		      struct tf_dev_global_cfg_parms *params)
+		      struct tf_global_cfg_parms *params)
 {
 	int rc = 0;
 	struct tfp_send_msg_parms parms = { 0 };
@@ -1133,7 +1133,7 @@ tf_msg_get_global_cfg(struct tf *tfp,
 
 int
 tf_msg_set_global_cfg(struct tf *tfp,
-		      struct tf_dev_global_cfg_parms *params)
+		      struct tf_global_cfg_parms *params)
 {
 	int rc = 0;
 	struct tfp_send_msg_parms parms = { 0 };
@@ -1173,6 +1173,15 @@ tf_msg_set_global_cfg(struct tf *tfp,
 
 	tfp_memcpy(req.data, params->config,
 		   params->config_sz_in_bytes);
+
+	/* Only set mask if pointer is provided
+	 */
+	if (params->config_mask) {
+		tfp_memcpy(req.data + params->config_sz_in_bytes,
+			   params->config_mask,
+			   params->config_sz_in_bytes);
+	}
+
 	req.size = tfp_cpu_to_le_32(params->config_sz_in_bytes);
 
 	parms.tf_type = HWRM_TF_GLOBAL_CFG_SET;
diff --git a/drivers/net/bnxt/tf_core/tf_msg.h b/drivers/net/bnxt/tf_core/tf_msg.h
index 195710eb8..72bf85048 100644
--- a/drivers/net/bnxt/tf_core/tf_msg.h
+++ b/drivers/net/bnxt/tf_core/tf_msg.h
@@ -462,7 +462,7 @@ int tf_msg_get_tbl_entry(struct tf *tfp,
  *   0 on Success else internal Truflow error
  */
 int tf_msg_get_global_cfg(struct tf *tfp,
-			  struct tf_dev_global_cfg_parms *params);
+			  struct tf_global_cfg_parms *params);
 
 /**
  * Sends global cfg update request to Firmware
@@ -477,7 +477,7 @@ int tf_msg_get_global_cfg(struct tf *tfp,
  *   0 on Success else internal Truflow error
  */
 int tf_msg_set_global_cfg(struct tf *tfp,
-			  struct tf_dev_global_cfg_parms *params);
+			  struct tf_global_cfg_parms *params);
 
 /**
  * Sends bulk get message of a Table Type element to the firmware.
-- 
2.21.1 (Apple Git-122.3)


^ permalink raw reply	[flat|nested] 32+ messages in thread

* [dpdk-dev] [PATCH v2 03/11] net/bnxt: add table scope to PF Mapping
  2020-10-20 21:55 ` [dpdk-dev] [PATCH v2 00/11] bnxt fixes and enhancements to TRUFLOW support Ajit Khaparde
  2020-10-20 21:55   ` [dpdk-dev] [PATCH v2 01/11] net/bnxt: add stingray support to core layer Ajit Khaparde
  2020-10-20 21:55   ` [dpdk-dev] [PATCH v2 02/11] net/bnxt: changes to support two table scopes Ajit Khaparde
@ 2020-10-20 21:55   ` Ajit Khaparde
  2020-10-20 21:55   ` [dpdk-dev] [PATCH v2 04/11] net/bnxt: update ULP resource counts Ajit Khaparde
                     ` (8 subsequent siblings)
  11 siblings, 0 replies; 32+ messages in thread
From: Ajit Khaparde @ 2020-10-20 21:55 UTC (permalink / raw)
  To: dev; +Cc: Farah Smith, Randy Schacher

From: Farah Smith <farah.smith@broadcom.com>

Add table scope to PF Mapping for SR and Wh+ devices.
Legacy devices require PF set of base addresses for EEM operation.
A table scope id is a logical construct and is mapped to the PF
associated with the communications channel used.
In the case of a VF, the parent PF is used.

Signed-off-by: Farah Smith <farah.smith@broadcom.com>
Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
 drivers/net/bnxt/tf_core/tf_device.h    | 10 +++++++---
 drivers/net/bnxt/tf_core/tf_device_p4.c | 10 +++++-----
 drivers/net/bnxt/tf_core/tf_em_common.c |  6 ++++--
 drivers/net/bnxt/tf_core/tf_em_host.c   |  8 ++++++++
 drivers/net/bnxt/tf_core/tf_tbl.h       |  3 +++
 drivers/net/bnxt/tf_core/tfp.c          | 19 +++++++++++++++++++
 drivers/net/bnxt/tf_core/tfp.h          | 16 ++++++++++++++++
 7 files changed, 62 insertions(+), 10 deletions(-)

diff --git a/drivers/net/bnxt/tf_core/tf_device.h b/drivers/net/bnxt/tf_core/tf_device.h
index cf7c36e0e..b5fc695ec 100644
--- a/drivers/net/bnxt/tf_core/tf_device.h
+++ b/drivers/net/bnxt/tf_core/tf_device.h
@@ -579,8 +579,11 @@ struct tf_dev_ops {
 	 * [in] tfp
 	 *   Pointer to TF handle
 	 *
-	 * [in] parms
-	 *   Pointer to table scope map parameters
+	 * [in] pf
+	 * PF associated with the table scope
+	 *
+	 * [in] parif_bitmask
+	 * Bitmask of PARIFs to enable
 	 *
 	 * [in/out] pointer to the parif_2_pf data to be updated
 	 *
@@ -593,7 +596,8 @@ struct tf_dev_ops {
 	 *    -EINVAL - Error
 	 */
 	int (*tf_dev_map_parif)(struct tf *tfp,
-				struct tf_map_tbl_scope_parms *parms,
+				uint16_t parif_bitmask,
+				uint16_t pf,
 				uint8_t *data,
 				uint8_t *mask,
 				uint16_t sz_in_bytes);
diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.c b/drivers/net/bnxt/tf_core/tf_device_p4.c
index 07c8d02fa..b35e65a8d 100644
--- a/drivers/net/bnxt/tf_core/tf_device_p4.c
+++ b/drivers/net/bnxt/tf_core/tf_device_p4.c
@@ -103,7 +103,8 @@ tf_dev_p4_get_tcam_slice_info(struct tf *tfp __rte_unused,
 
 static int
 tf_dev_p4_map_parif(struct tf *tfp __rte_unused,
-		    struct tf_map_tbl_scope_parms *parms,
+		    uint16_t parif_bitmask,
+		    uint16_t pf,
 		    uint8_t *data,
 		    uint8_t *mask,
 		    uint16_t sz_in_bytes)
@@ -112,21 +113,20 @@ tf_dev_p4_map_parif(struct tf *tfp __rte_unused,
 	uint32_t parif_pf_mask[2] = { 0 };
 	uint32_t parif;
 	uint32_t shift;
-	uint32_t scope_id = (uint32_t)(parms->tbl_scope_id);
 
 	if (sz_in_bytes != sizeof(uint64_t))
 		return -ENOTSUP;
 
 	for (parif = 0; parif < TF_DEV_P4_PARIF_MAX; parif++) {
-		if (parms->parif_bitmask & (1UL << parif)) {
+		if (parif_bitmask & (1UL << parif)) {
 			if (parif < 8) {
 				shift = 4 * parif;
 				parif_pf_mask[0] |= TF_DEV_P4_PF_MASK << shift;
-				parif_pf[0] |= scope_id << shift;
+				parif_pf[0] |= pf << shift;
 			} else {
 				shift = 4 * (parif - 8);
 				parif_pf_mask[1] |= TF_DEV_P4_PF_MASK << shift;
-				parif_pf[1] |= scope_id << shift;
+				parif_pf[1] |= pf << shift;
 			}
 		}
 	}
diff --git a/drivers/net/bnxt/tf_core/tf_em_common.c b/drivers/net/bnxt/tf_core/tf_em_common.c
index a6ddb4eaf..cbce9389d 100644
--- a/drivers/net/bnxt/tf_core/tf_em_common.c
+++ b/drivers/net/bnxt/tf_core/tf_em_common.c
@@ -1104,8 +1104,10 @@ int tf_em_ext_map_tbl_scope(struct tf *tfp,
 	}
 	mask = aparms.mem_va;
 
-	rc = dev->ops->tf_dev_map_parif(tfp, parms, (uint8_t *)data,
-					(uint8_t *)mask, sz_in_bytes);
+	rc = dev->ops->tf_dev_map_parif(tfp, parms->parif_bitmask,
+					tbl_scope_cb->pf,
+					(uint8_t *)data, (uint8_t *)mask,
+					sz_in_bytes);
 
 	if (rc) {
 		TFP_DRV_LOG(ERR,
diff --git a/drivers/net/bnxt/tf_core/tf_em_host.c b/drivers/net/bnxt/tf_core/tf_em_host.c
index b5db94f3e..a106bdffd 100644
--- a/drivers/net/bnxt/tf_core/tf_em_host.c
+++ b/drivers/net/bnxt/tf_core/tf_em_host.c
@@ -392,6 +392,14 @@ tf_em_ext_alloc(struct tf *tfp, struct tf_alloc_tbl_scope_parms *parms)
 	tbl_scope_cb->index = parms->tbl_scope_id;
 	tbl_scope_cb->tbl_scope_id = parms->tbl_scope_id;
 
+	rc = tfp_get_pf(tfp, &tbl_scope_cb->pf);
+	if (rc) {
+		TFP_DRV_LOG(ERR,
+			    "EEM: PF query error rc:%s\n",
+			    strerror(-rc));
+		goto cleanup;
+	}
+
 	for (dir = 0; dir < TF_DIR_MAX; dir++) {
 		rc = tf_msg_em_qcaps(tfp,
 				     dir,
diff --git a/drivers/net/bnxt/tf_core/tf_tbl.h b/drivers/net/bnxt/tf_core/tf_tbl.h
index 2a5d24c94..230338c81 100644
--- a/drivers/net/bnxt/tf_core/tf_tbl.h
+++ b/drivers/net/bnxt/tf_core/tf_tbl.h
@@ -38,6 +38,9 @@ struct tf_em_caps {
  */
 struct tf_tbl_scope_cb {
 	uint32_t tbl_scope_id;
+       /** The pf or parent pf of the vf used for table scope creation
+	*/
+	uint16_t pf;
 	int index;
 	struct hcapi_cfa_em_ctx_mem_info em_ctx_info[TF_DIR_MAX];
 	struct tf_em_caps em_caps[TF_DIR_MAX];
diff --git a/drivers/net/bnxt/tf_core/tfp.c b/drivers/net/bnxt/tf_core/tfp.c
index 426a182a9..0f6d63cc0 100644
--- a/drivers/net/bnxt/tf_core/tfp.c
+++ b/drivers/net/bnxt/tf_core/tfp.c
@@ -178,3 +178,22 @@ tfp_get_fid(struct tf *tfp, uint16_t *fw_fid)
 
 	return 0;
 }
+
+int
+tfp_get_pf(struct tf *tfp, uint16_t *pf)
+{
+	struct bnxt *bp = NULL;
+
+	if (tfp == NULL || pf == NULL)
+		return -EINVAL;
+
+	bp = container_of(tfp, struct bnxt, tfp);
+	if (BNXT_VF(bp) && bp->parent) {
+		*pf = bp->parent->fid - 1;
+		return 0;
+	} else if (BNXT_PF(bp)) {
+		*pf = bp->fw_fid - 1;
+		return 0;
+	}
+	return -EINVAL;
+}
diff --git a/drivers/net/bnxt/tf_core/tfp.h b/drivers/net/bnxt/tf_core/tfp.h
index 421a7d9f7..551b9c569 100644
--- a/drivers/net/bnxt/tf_core/tfp.h
+++ b/drivers/net/bnxt/tf_core/tfp.h
@@ -268,4 +268,20 @@ int tfp_get_fid(struct tf *tfp, uint16_t *fw_fid);
  */
 int tfp_get_fid(struct tf *tfp, uint16_t *fw_fid);
 
+/**
+ * Get the PF associated with the fw communications channel.
+ *
+ * [in] session
+ *   Pointer to session handle
+ *
+ * [out] pf
+ *   Pointer to the pf id
+ *
+ * Returns:
+ *   0       - Success
+ *   -EINVAL - Failure
+ *
+ */
+int tfp_get_pf(struct tf *tfp, uint16_t *pf);
+
 #endif /* _TFP_H_ */
-- 
2.21.1 (Apple Git-122.3)


^ permalink raw reply	[flat|nested] 32+ messages in thread

* [dpdk-dev] [PATCH v2 04/11] net/bnxt: update ULP resource counts
  2020-10-20 21:55 ` [dpdk-dev] [PATCH v2 00/11] bnxt fixes and enhancements to TRUFLOW support Ajit Khaparde
                     ` (2 preceding siblings ...)
  2020-10-20 21:55   ` [dpdk-dev] [PATCH v2 03/11] net/bnxt: add table scope to PF Mapping Ajit Khaparde
@ 2020-10-20 21:55   ` Ajit Khaparde
  2020-10-20 21:55   ` [dpdk-dev] [PATCH v2 05/11] net/bnxt: fix infinite loop in flow query count Ajit Khaparde
                     ` (7 subsequent siblings)
  11 siblings, 0 replies; 32+ messages in thread
From: Ajit Khaparde @ 2020-10-20 21:55 UTC (permalink / raw)
  To: dev; +Cc: Peter Spreadborough, Farah Smith, Randy Schacher

From: Peter Spreadborough <peter.spreadborough@broadcom.com>

- Update the SR ULP requested resource counts to reflect
those available after AFM resources are accounted for.
- Add build option to select either 2 or 4 slot EM entries.
The default is 4 slot entries.

Signed-off-by: Peter Spreadborough <peter.spreadborough@broadcom.com>
Signed-off-by: Farah Smith <farah.smith@broadcom.com>
Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
 drivers/net/bnxt/tf_core/tf_session.h | 16 +++++------
 drivers/net/bnxt/tf_ulp/bnxt_ulp.c    | 40 +++++++++++++--------------
 2 files changed, 28 insertions(+), 28 deletions(-)

diff --git a/drivers/net/bnxt/tf_core/tf_session.h b/drivers/net/bnxt/tf_core/tf_session.h
index aa7a27877..6a5c89403 100644
--- a/drivers/net/bnxt/tf_core/tf_session.h
+++ b/drivers/net/bnxt/tf_core/tf_session.h
@@ -33,16 +33,16 @@
 #define TF_SESSION_ID_INVALID     0xFFFFFFFF /** Invalid Session ID define */
 
 /**
- * Number of EM entries. Static for now will be removed
- * when parameter added at a later date. At this stage we
- * are using fixed size entries so that each stack entry
- * represents 4 RT (f/n)blocks. So we take the total block
- * allocation for truflow and divide that by 4.
+ * At this stage we are using fixed size entries so that each
+ * stack entry represents either 2 or 4 RT (f/n)blocks. So we
+ * take the total block allocation for truflow and divide that
+ * by either 2 or 4.
  */
-#define TF_SESSION_TOTAL_FN_BLOCKS (1024 * 8) /* 8K blocks */
+#ifdef TF_EM_ENTRY_IPV4_ONLY
+#define TF_SESSION_EM_ENTRY_SIZE 2 /* 2 blocks per entry */
+#else
 #define TF_SESSION_EM_ENTRY_SIZE 4 /* 4 blocks per entry */
-#define TF_SESSION_EM_POOL_SIZE \
-	(TF_SESSION_TOTAL_FN_BLOCKS / TF_SESSION_EM_ENTRY_SIZE)
+#endif
 
 /**
  * Session
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
index b22929a63..d753b5af9 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
@@ -153,11 +153,11 @@ bnxt_ulp_tf_session_resources_get(struct bnxt *bp,
 	case BNXT_ULP_DEVICE_ID_STINGRAY:
 		/** RX **/
 		/* Identifiers */
-		res->ident_cnt[TF_DIR_RX].cnt[TF_IDENT_TYPE_L2_CTXT_HIGH] = 100;
+		res->ident_cnt[TF_DIR_RX].cnt[TF_IDENT_TYPE_L2_CTXT_HIGH] = 315;
 		res->ident_cnt[TF_DIR_RX].cnt[TF_IDENT_TYPE_L2_CTXT_LOW] = 6;
-		res->ident_cnt[TF_DIR_RX].cnt[TF_IDENT_TYPE_WC_PROF] = 10;
-		res->ident_cnt[TF_DIR_RX].cnt[TF_IDENT_TYPE_PROF_FUNC] = 10;
-		res->ident_cnt[TF_DIR_RX].cnt[TF_IDENT_TYPE_EM_PROF] = 10;
+		res->ident_cnt[TF_DIR_RX].cnt[TF_IDENT_TYPE_WC_PROF] = 192;
+		res->ident_cnt[TF_DIR_RX].cnt[TF_IDENT_TYPE_PROF_FUNC] = 64;
+		res->ident_cnt[TF_DIR_RX].cnt[TF_IDENT_TYPE_EM_PROF] = 192;
 
 		/* Table Types */
 		res->tbl_cnt[TF_DIR_RX].cnt[TF_TBL_TYPE_FULL_ACT_RECORD] = 8192;
@@ -170,28 +170,28 @@ bnxt_ulp_tf_session_resources_get(struct bnxt *bp,
 
 		/* TCAMs */
 		res->tcam_cnt[TF_DIR_RX].cnt[TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH] =
-			100;
+			315;
 		res->tcam_cnt[TF_DIR_RX].cnt[TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW] =
 			6;
-		res->tcam_cnt[TF_DIR_RX].cnt[TF_TCAM_TBL_TYPE_PROF_TCAM] = 100;
-		res->tcam_cnt[TF_DIR_RX].cnt[TF_TCAM_TBL_TYPE_WC_TCAM] = 0;
+		res->tcam_cnt[TF_DIR_RX].cnt[TF_TCAM_TBL_TYPE_PROF_TCAM] = 960;
+		res->tcam_cnt[TF_DIR_RX].cnt[TF_TCAM_TBL_TYPE_WC_TCAM] = 112;
 
 		/* EM */
-		res->em_cnt[TF_DIR_RX].cnt[TF_EM_TBL_TYPE_EM_RECORD] = 13168;
+		res->em_cnt[TF_DIR_RX].cnt[TF_EM_TBL_TYPE_EM_RECORD] = 13200;
 
 		/* EEM */
 		res->em_cnt[TF_DIR_RX].cnt[TF_EM_TBL_TYPE_TBL_SCOPE] = 1;
 
 		/* SP */
-		res->tbl_cnt[TF_DIR_RX].cnt[TF_TBL_TYPE_ACT_SP_SMAC] = 255;
+		res->tbl_cnt[TF_DIR_RX].cnt[TF_TBL_TYPE_ACT_SP_SMAC] = 256;
 
 		/** TX **/
 		/* Identifiers */
-		res->ident_cnt[TF_DIR_TX].cnt[TF_IDENT_TYPE_L2_CTXT_HIGH] = 100;
-		res->ident_cnt[TF_DIR_TX].cnt[TF_IDENT_TYPE_L2_CTXT_LOW] = 100;
-		res->ident_cnt[TF_DIR_TX].cnt[TF_IDENT_TYPE_WC_PROF] = 10;
-		res->ident_cnt[TF_DIR_TX].cnt[TF_IDENT_TYPE_PROF_FUNC] = 10;
-		res->ident_cnt[TF_DIR_TX].cnt[TF_IDENT_TYPE_EM_PROF] = 10;
+		res->ident_cnt[TF_DIR_TX].cnt[TF_IDENT_TYPE_L2_CTXT_HIGH] = 292;
+		res->ident_cnt[TF_DIR_TX].cnt[TF_IDENT_TYPE_L2_CTXT_LOW] = 127;
+		res->ident_cnt[TF_DIR_TX].cnt[TF_IDENT_TYPE_WC_PROF] = 192;
+		res->ident_cnt[TF_DIR_TX].cnt[TF_IDENT_TYPE_PROF_FUNC] = 64;
+		res->ident_cnt[TF_DIR_TX].cnt[TF_IDENT_TYPE_EM_PROF] = 192;
 
 		/* Table Types */
 		res->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_FULL_ACT_RECORD] = 8192;
@@ -199,17 +199,17 @@ bnxt_ulp_tf_session_resources_get(struct bnxt *bp,
 		res->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_ACT_MODIFY_IPV4] = 1023;
 
 		/* ENCAP */
-		res->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_ACT_ENCAP_64B] = 511;
+		res->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_ACT_ENCAP_64B] = 367;
 		res->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_ACT_ENCAP_16B] = 223;
 		res->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_ACT_ENCAP_8B] = 255;
 
 		/* TCAMs */
 		res->tcam_cnt[TF_DIR_TX].cnt[TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH] =
-			100;
+			292;
 		res->tcam_cnt[TF_DIR_TX].cnt[TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW] =
-			100;
-		res->tcam_cnt[TF_DIR_TX].cnt[TF_TCAM_TBL_TYPE_PROF_TCAM] = 100;
-		res->tcam_cnt[TF_DIR_TX].cnt[TF_TCAM_TBL_TYPE_WC_TCAM] = 0;
+			127;
+		res->tcam_cnt[TF_DIR_TX].cnt[TF_TCAM_TBL_TYPE_PROF_TCAM] = 960;
+		res->tcam_cnt[TF_DIR_TX].cnt[TF_TCAM_TBL_TYPE_WC_TCAM] = 928;
 
 		/* EM */
 		res->em_cnt[TF_DIR_TX].cnt[TF_EM_TBL_TYPE_EM_RECORD] = 15232;
@@ -219,7 +219,7 @@ bnxt_ulp_tf_session_resources_get(struct bnxt *bp,
 
 		/* SP */
 		res->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = 488;
-		res->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = 511;
+		res->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = 512;
 		break;
 	default:
 		return -EINVAL;
-- 
2.21.1 (Apple Git-122.3)


^ permalink raw reply	[flat|nested] 32+ messages in thread

* [dpdk-dev] [PATCH v2 05/11] net/bnxt: fix infinite loop in flow query count
  2020-10-20 21:55 ` [dpdk-dev] [PATCH v2 00/11] bnxt fixes and enhancements to TRUFLOW support Ajit Khaparde
                     ` (3 preceding siblings ...)
  2020-10-20 21:55   ` [dpdk-dev] [PATCH v2 04/11] net/bnxt: update ULP resource counts Ajit Khaparde
@ 2020-10-20 21:55   ` Ajit Khaparde
  2020-10-20 21:55   ` [dpdk-dev] [PATCH v2 06/11] net/bnxt: add support for flow counter accumulation Ajit Khaparde
                     ` (6 subsequent siblings)
  11 siblings, 0 replies; 32+ messages in thread
From: Ajit Khaparde @ 2020-10-20 21:55 UTC (permalink / raw)
  To: dev; +Cc: Somnath Kotur, Venkat Duvvuru

From: Somnath Kotur <somnath.kotur@broadcom.com>

`nxt_resource_idx` could be zero in some cases which is invalid and
should be part of the while loop condition. Also synchronize access to
the flow db using the fdb_lock

Fixes: 306c2d28e247 ("net/bnxt: support count action in flow query")

Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
Reviewed-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
 drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c | 51 +++++++++++++++-------------
 1 file changed, 27 insertions(+), 24 deletions(-)

diff --git a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c
index 051ebac04..41736a80d 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c
@@ -559,6 +559,9 @@ int ulp_fc_mgr_query_count_get(struct bnxt_ulp_context *ctxt,
 	if (!ulp_fc_info)
 		return -ENODEV;
 
+	if (bnxt_ulp_cntxt_acquire_fdb_lock(ctxt))
+		return -EIO;
+
 	do {
 		rc = ulp_flow_db_resource_get(ctxt,
 					      BNXT_ULP_FDB_TYPE_REGULAR,
@@ -575,35 +578,35 @@ int ulp_fc_mgr_query_count_get(struct bnxt_ulp_context *ctxt,
 			break;
 		}
 
-	} while (!rc);
+	} while (!rc && nxt_resource_index);
+
+	bnxt_ulp_cntxt_release_fdb_lock(ctxt);
 
-	if (rc)
+	if (rc || !found_cntr_resource)
 		return rc;
 
-	if (found_cntr_resource) {
-		dir = params.direction;
-		hw_cntr_id = params.resource_hndl;
-		sw_cntr_idx = hw_cntr_id -
-				ulp_fc_info->shadow_hw_tbl[dir].start_idx;
-		sw_acc_tbl_entry = &ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx];
-		if (params.resource_sub_type ==
+	dir = params.direction;
+	hw_cntr_id = params.resource_hndl;
+	sw_cntr_idx = hw_cntr_id -
+		ulp_fc_info->shadow_hw_tbl[dir].start_idx;
+	sw_acc_tbl_entry = &ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx];
+	if (params.resource_sub_type ==
 			BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT) {
-			pthread_mutex_lock(&ulp_fc_info->fc_lock);
-			if (sw_acc_tbl_entry->pkt_count) {
-				count->hits_set = 1;
-				count->bytes_set = 1;
-				count->hits = sw_acc_tbl_entry->pkt_count;
-				count->bytes = sw_acc_tbl_entry->byte_count;
-			}
-			if (count->reset) {
-				sw_acc_tbl_entry->pkt_count = 0;
-				sw_acc_tbl_entry->byte_count = 0;
-			}
-			pthread_mutex_unlock(&ulp_fc_info->fc_lock);
-		} else {
-			/* TBD: Handle External counters */
-			rc = -EINVAL;
+		pthread_mutex_lock(&ulp_fc_info->fc_lock);
+		if (sw_acc_tbl_entry->pkt_count) {
+			count->hits_set = 1;
+			count->bytes_set = 1;
+			count->hits = sw_acc_tbl_entry->pkt_count;
+			count->bytes = sw_acc_tbl_entry->byte_count;
 		}
+		if (count->reset) {
+			sw_acc_tbl_entry->pkt_count = 0;
+			sw_acc_tbl_entry->byte_count = 0;
+		}
+		pthread_mutex_unlock(&ulp_fc_info->fc_lock);
+	} else {
+		/* TBD: Handle External counters */
+		rc = -EINVAL;
 	}
 
 	return rc;
-- 
2.21.1 (Apple Git-122.3)


^ permalink raw reply	[flat|nested] 32+ messages in thread

* [dpdk-dev] [PATCH v2 06/11] net/bnxt: add support for flow counter accumulation
  2020-10-20 21:55 ` [dpdk-dev] [PATCH v2 00/11] bnxt fixes and enhancements to TRUFLOW support Ajit Khaparde
                     ` (4 preceding siblings ...)
  2020-10-20 21:55   ` [dpdk-dev] [PATCH v2 05/11] net/bnxt: fix infinite loop in flow query count Ajit Khaparde
@ 2020-10-20 21:55   ` Ajit Khaparde
  2020-10-20 21:55   ` [dpdk-dev] [PATCH v2 07/11] net/bnxt: change HWRM command to create reps Ajit Khaparde
                     ` (5 subsequent siblings)
  11 siblings, 0 replies; 32+ messages in thread
From: Ajit Khaparde @ 2020-10-20 21:55 UTC (permalink / raw)
  To: dev; +Cc: Kishore Padmanabha, Shahaji Bhosle

From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>

Add support for flow counter accumulation.
In case of hierarchical flows, involving parent and child flows,
the child flow counters are aggregated to get the parent flow counter
information.

Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Shahaji Bhosle <sbhosle@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
 drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c          |  92 ++++-
 drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h          |  19 +
 drivers/net/bnxt/tf_ulp/ulp_flow_db.c         | 382 ++++++++++++++----
 drivers/net/bnxt/tf_ulp/ulp_flow_db.h         |  44 ++
 .../net/bnxt/tf_ulp/ulp_template_db_enum.h    |   3 +-
 5 files changed, 447 insertions(+), 93 deletions(-)

diff --git a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c
index 41736a80d..734b41998 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c
@@ -21,13 +21,13 @@ static int
 ulp_fc_mgr_shadow_mem_alloc(struct hw_fc_mem_info *parms, int size)
 {
 	/* Allocate memory*/
-	if (parms == NULL)
+	if (!parms)
 		return -EINVAL;
 
 	parms->mem_va = rte_zmalloc("ulp_fc_info",
 				    RTE_CACHE_LINE_ROUNDUP(size),
 				    4096);
-	if (parms->mem_va == NULL) {
+	if (!parms->mem_va) {
 		BNXT_TF_DBG(ERR, "Allocate failed mem_va\n");
 		return -ENOMEM;
 	}
@@ -149,7 +149,6 @@ ulp_fc_mgr_deinit(struct bnxt_ulp_context *ctxt)
 	for (i = 0; i < TF_DIR_MAX; i++)
 		ulp_fc_mgr_shadow_mem_free(&ulp_fc_info->shadow_hw_tbl[i]);
 
-
 	rte_free(ulp_fc_info);
 
 	/* Safe to ignore on deinit */
@@ -254,7 +253,7 @@ ulp_bulk_get_flow_stats(struct tf *tfp,
 	stats = (uint64_t *)fc_info->shadow_hw_tbl[dir].mem_va;
 	parms.physical_mem_addr = (uintptr_t)fc_info->shadow_hw_tbl[dir].mem_pa;
 
-	if (stats == NULL) {
+	if (!stats) {
 		PMD_DRV_LOG(ERR,
 			    "BULK: Memory not initialized id:0x%x dir:%d\n",
 			    parms.starting_idx, dir);
@@ -274,7 +273,8 @@ ulp_bulk_get_flow_stats(struct tf *tfp,
 		sw_acc_tbl_entry = &fc_info->sw_acc_tbl[dir][i];
 		if (!sw_acc_tbl_entry->valid)
 			continue;
-		sw_acc_tbl_entry->pkt_count += FLOW_CNTR_PKTS(stats[i], dparms);
+		sw_acc_tbl_entry->pkt_count += FLOW_CNTR_PKTS(stats[i],
+							      dparms);
 		sw_acc_tbl_entry->byte_count += FLOW_CNTR_BYTES(stats[i],
 								dparms);
 	}
@@ -282,7 +282,8 @@ ulp_bulk_get_flow_stats(struct tf *tfp,
 	return rc;
 }
 
-static int ulp_get_single_flow_stat(struct tf *tfp,
+static int ulp_get_single_flow_stat(struct bnxt_ulp_context *ctxt,
+				    struct tf *tfp,
 				    struct bnxt_ulp_fc_info *fc_info,
 				    enum tf_dir dir,
 				    uint32_t hw_cntr_id,
@@ -291,7 +292,7 @@ static int ulp_get_single_flow_stat(struct tf *tfp,
 	int rc = 0;
 	struct tf_get_tbl_entry_parms parms = { 0 };
 	enum tf_tbl_type stype = TF_TBL_TYPE_ACT_STATS_64;  /* TBD:Template? */
-	struct sw_acc_counter *sw_acc_tbl_entry = NULL;
+	struct sw_acc_counter *sw_acc_tbl_entry = NULL, *t_sw;
 	uint64_t stats = 0;
 	uint32_t sw_cntr_indx = 0;
 
@@ -318,6 +319,18 @@ static int ulp_get_single_flow_stat(struct tf *tfp,
 	sw_acc_tbl_entry->pkt_count = FLOW_CNTR_PKTS(stats, dparms);
 	sw_acc_tbl_entry->byte_count = FLOW_CNTR_BYTES(stats, dparms);
 
+	/* Update the parent counters if it is child flow */
+	if (sw_acc_tbl_entry->parent_flow_id) {
+		/* Update the parent counters */
+		t_sw = sw_acc_tbl_entry;
+		if (ulp_flow_db_parent_flow_count_update(ctxt,
+							 t_sw->parent_flow_id,
+							 t_sw->pkt_count,
+							 t_sw->byte_count)) {
+			PMD_DRV_LOG(ERR, "Error updating parent counters\n");
+		}
+	}
+
 	return rc;
 }
 
@@ -384,13 +397,17 @@ ulp_fc_mgr_alarm_cb(void *arg)
 			break;
 	}
 	*/
+
+	/* reset the parent accumulation counters before accumulation if any */
+	ulp_flow_db_parent_flow_count_reset(ctxt);
+
 	num_entries = dparms->flow_count_db_entries / 2;
 	for (i = 0; i < TF_DIR_MAX; i++) {
 		for (j = 0; j < num_entries; j++) {
 			if (!ulp_fc_info->sw_acc_tbl[i][j].valid)
 				continue;
 			hw_cntr_id = ulp_fc_info->sw_acc_tbl[i][j].hw_cntr_id;
-			rc = ulp_get_single_flow_stat(tfp, ulp_fc_info, i,
+			rc = ulp_get_single_flow_stat(ctxt, tfp, ulp_fc_info, i,
 						      hw_cntr_id, dparms);
 			if (rc)
 				break;
@@ -573,11 +590,12 @@ int ulp_fc_mgr_query_count_get(struct bnxt_ulp_context *ctxt,
 		     (params.resource_sub_type ==
 		      BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT ||
 		      params.resource_sub_type ==
-		      BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_EXT_COUNT)) {
+		      BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_EXT_COUNT ||
+		      params.resource_sub_type ==
+		      BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT_ACC)) {
 			found_cntr_resource = true;
 			break;
 		}
-
 	} while (!rc && nxt_resource_index);
 
 	bnxt_ulp_cntxt_release_fdb_lock(ctxt);
@@ -587,12 +605,12 @@ int ulp_fc_mgr_query_count_get(struct bnxt_ulp_context *ctxt,
 
 	dir = params.direction;
 	hw_cntr_id = params.resource_hndl;
-	sw_cntr_idx = hw_cntr_id -
-		ulp_fc_info->shadow_hw_tbl[dir].start_idx;
-	sw_acc_tbl_entry = &ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx];
 	if (params.resource_sub_type ==
 			BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT) {
 		pthread_mutex_lock(&ulp_fc_info->fc_lock);
+		sw_cntr_idx = hw_cntr_id -
+			ulp_fc_info->shadow_hw_tbl[dir].start_idx;
+		sw_acc_tbl_entry = &ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx];
 		if (sw_acc_tbl_entry->pkt_count) {
 			count->hits_set = 1;
 			count->bytes_set = 1;
@@ -604,6 +622,15 @@ int ulp_fc_mgr_query_count_get(struct bnxt_ulp_context *ctxt,
 			sw_acc_tbl_entry->byte_count = 0;
 		}
 		pthread_mutex_unlock(&ulp_fc_info->fc_lock);
+	} else if (params.resource_sub_type ==
+			BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT_ACC) {
+		/* Get the stats from the parent child table */
+		ulp_flow_db_parent_flow_count_get(ctxt,
+						  flow_id,
+						  &count->hits,
+						  &count->bytes);
+		count->hits_set = 1;
+		count->bytes_set = 1;
 	} else {
 		/* TBD: Handle External counters */
 		rc = -EINVAL;
@@ -611,3 +638,42 @@ int ulp_fc_mgr_query_count_get(struct bnxt_ulp_context *ctxt,
 
 	return rc;
 }
+
+/*
+ * Set the parent flow if it is SW accumulation counter entry.
+ *
+ * ctxt [in] The ulp context for the flow counter manager
+ *
+ * dir [in] The direction of the flow
+ *
+ * hw_cntr_id [in] The HW flow counter ID
+ *
+ * fid [in] parent flow id
+ *
+ */
+int32_t ulp_fc_mgr_cntr_parent_flow_set(struct bnxt_ulp_context *ctxt,
+					enum tf_dir dir,
+					uint32_t hw_cntr_id,
+					uint32_t fid)
+{
+	struct bnxt_ulp_fc_info *ulp_fc_info;
+	uint32_t sw_cntr_idx;
+	int32_t rc = 0;
+
+	ulp_fc_info = bnxt_ulp_cntxt_ptr2_fc_info_get(ctxt);
+	if (!ulp_fc_info)
+		return -EIO;
+
+	pthread_mutex_lock(&ulp_fc_info->fc_lock);
+	sw_cntr_idx = hw_cntr_id - ulp_fc_info->shadow_hw_tbl[dir].start_idx;
+	if (ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].valid) {
+		ulp_fc_info->sw_acc_tbl[dir][sw_cntr_idx].parent_flow_id = fid;
+	} else {
+		BNXT_TF_DBG(ERR, "Failed to set parent flow id %x:%x\n",
+			    hw_cntr_id, fid);
+		rc = -ENOENT;
+	}
+	pthread_mutex_unlock(&ulp_fc_info->fc_lock);
+
+	return rc;
+}
diff --git a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h
index 0cb880d4b..de4d3dfe9 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h
@@ -26,6 +26,7 @@ struct sw_acc_counter {
 	uint64_t byte_count;
 	bool	valid;
 	uint32_t hw_cntr_id;
+	uint32_t parent_flow_id;
 };
 
 struct hw_fc_mem_info {
@@ -163,4 +164,22 @@ bool ulp_fc_mgr_thread_isstarted(struct bnxt_ulp_context *ctxt);
 int ulp_fc_mgr_query_count_get(struct bnxt_ulp_context *ulp_ctx,
 			       uint32_t flow_id,
 			       struct rte_flow_query_count *count);
+
+/*
+ * Set the parent flow if in the SW accumulator table entry
+ *
+ * ctxt [in] The ulp context for the flow counter manager
+ *
+ * dir [in] The direction of the flow
+ *
+ * hw_cntr_id [in] The HW flow counter ID
+ *
+ * fid [in] parent flow id
+ *
+ */
+int32_t ulp_fc_mgr_cntr_parent_flow_set(struct bnxt_ulp_context *ctxt,
+					enum tf_dir dir,
+					uint32_t hw_cntr_id,
+					uint32_t fid);
+
 #endif /* _ULP_FC_MGR_H_ */
diff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c
index 3be748908..8780c01cc 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.c
@@ -1058,12 +1058,12 @@ ulp_flow_db_validate_flow_func(struct bnxt_ulp_context *ulp_ctx,
  * the first match.
  */
 static int32_t
-ulp_flow_db_resource_hndl_get(struct bnxt_ulp_context *ulp_ctx,
-			      enum bnxt_ulp_fdb_type flow_type,
-			      uint32_t flow_id,
-			      uint32_t resource_func,
-			      uint32_t res_subtype,
-			      uint64_t *res_hndl)
+ulp_flow_db_resource_params_get(struct bnxt_ulp_context *ulp_ctx,
+				enum bnxt_ulp_fdb_type flow_type,
+				uint32_t flow_id,
+				uint32_t resource_func,
+				uint32_t res_subtype,
+				struct ulp_flow_db_res_params *params)
 {
 	struct bnxt_ulp_flow_db *flow_db;
 	struct bnxt_ulp_flow_tbl *flow_tbl;
@@ -1076,6 +1076,11 @@ ulp_flow_db_resource_hndl_get(struct bnxt_ulp_context *ulp_ctx,
 		return -EINVAL;
 	}
 
+	if (!params) {
+		BNXT_TF_DBG(ERR, "invalid argument\n");
+		return -EINVAL;
+	}
+
 	if (flow_type > BNXT_ULP_FDB_TYPE_DEFAULT) {
 		BNXT_TF_DBG(ERR, "Invalid flow type\n");
 		return -EINVAL;
@@ -1096,12 +1101,14 @@ ulp_flow_db_resource_hndl_get(struct bnxt_ulp_context *ulp_ctx,
 	}
 	/* Iterate the resource to get the resource handle */
 	res_id =  flow_id;
+	memset(params, 0, sizeof(struct ulp_flow_db_res_params));
 	while (res_id) {
 		fid_res = &flow_tbl->flow_resources[res_id];
 		if (ulp_flow_db_resource_func_get(fid_res) == resource_func) {
 			if (resource_func & ULP_FLOW_DB_RES_FUNC_NEED_LOWER) {
 				if (res_subtype == fid_res->resource_sub_type) {
-					*res_hndl = fid_res->resource_hndl;
+					ulp_flow_db_res_info_to_params(fid_res,
+								       params);
 					return 0;
 				}
 
@@ -1109,7 +1116,8 @@ ulp_flow_db_resource_hndl_get(struct bnxt_ulp_context *ulp_ctx,
 				   BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE ||
 				   resource_func ==
 				   BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE) {
-				*res_hndl = fid_res->resource_em_handle;
+				ulp_flow_db_res_info_to_params(fid_res,
+							       params);
 				return 0;
 			}
 		}
@@ -1134,23 +1142,51 @@ ulp_default_flow_db_cfa_action_get(struct bnxt_ulp_context *ulp_ctx,
 				   uint16_t *cfa_action)
 {
 	uint8_t sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_VFR_CFA_ACTION;
-	uint64_t hndl;
+	struct ulp_flow_db_res_params params;
 	int32_t rc;
 
-	rc = ulp_flow_db_resource_hndl_get(ulp_ctx,
-					   BNXT_ULP_FDB_TYPE_DEFAULT,
-					   flow_id,
-					   BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
-					   sub_type, &hndl);
+	rc = ulp_flow_db_resource_params_get(ulp_ctx,
+					     BNXT_ULP_FDB_TYPE_DEFAULT,
+					     flow_id,
+					     BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+					     sub_type, &params);
 	if (rc) {
 		BNXT_TF_DBG(ERR, "CFA Action ptr not found for flow id %u\n",
 			    flow_id);
 		return -ENOENT;
 	}
-	*cfa_action = hndl;
+	*cfa_action = params.resource_hndl;
 	return 0;
 }
 
+/* internal validation function for parent flow tbl */
+static struct bnxt_ulp_flow_db *
+ulp_flow_db_parent_arg_validation(struct bnxt_ulp_context *ulp_ctxt,
+				  uint32_t fid)
+{
+	struct bnxt_ulp_flow_db *flow_db;
+
+	flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);
+	if (!flow_db) {
+		BNXT_TF_DBG(ERR, "Invalid Arguments\n");
+		return NULL;
+	}
+
+	/* check for max flows */
+	if (fid >= flow_db->flow_tbl.num_flows || !fid) {
+		BNXT_TF_DBG(ERR, "Invalid flow index\n");
+		return NULL;
+	}
+
+	/* No support for parent child db then just exit */
+	if (!flow_db->parent_child_db.entries_count) {
+		BNXT_TF_DBG(ERR, "parent child db not supported\n");
+		return NULL;
+	}
+
+	return flow_db;
+}
+
 /*
  * Allocate the entry in the parent-child database
  *
@@ -1167,26 +1203,15 @@ ulp_flow_db_parent_flow_alloc(struct bnxt_ulp_context *ulp_ctxt,
 	struct ulp_fdb_parent_child_db *p_pdb;
 	uint32_t idx, free_idx = 0;
 
-	flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);
+	/* validate the arguments */
+	flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, fid);
 	if (!flow_db) {
-		BNXT_TF_DBG(ERR, "Invalid Arguments\n");
-		return -EINVAL;
-	}
-
-	/* check for max flows */
-	if (fid >= flow_db->flow_tbl.num_flows || !fid) {
-		BNXT_TF_DBG(ERR, "Invalid flow index\n");
-		return -EINVAL;
-	}
-
-	/* No support for parent child db then just exit */
-	if (!flow_db->parent_child_db.entries_count) {
-		BNXT_TF_DBG(ERR, "parent child db not supported\n");
+		BNXT_TF_DBG(ERR, "parent child db validation failed\n");
 		return -EINVAL;
 	}
 
 	p_pdb = &flow_db->parent_child_db;
-	for (idx = 0; idx <= p_pdb->entries_count; idx++) {
+	for (idx = 0; idx < p_pdb->entries_count; idx++) {
 		if (p_pdb->parent_flow_tbl[idx].parent_fid == fid) {
 			BNXT_TF_DBG(ERR, "fid is already allocated\n");
 			return -EINVAL;
@@ -1222,26 +1247,15 @@ ulp_flow_db_parent_flow_free(struct bnxt_ulp_context *ulp_ctxt,
 	struct ulp_fdb_parent_child_db *p_pdb;
 	uint32_t idx;
 
-	flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);
+	/* validate the arguments */
+	flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, fid);
 	if (!flow_db) {
-		BNXT_TF_DBG(ERR, "Invalid Arguments\n");
-		return -EINVAL;
-	}
-
-	/* check for max flows */
-	if (fid >= flow_db->flow_tbl.num_flows || !fid) {
-		BNXT_TF_DBG(ERR, "Invalid flow index\n");
-		return -EINVAL;
-	}
-
-	/* No support for parent child db then just exit */
-	if (!flow_db->parent_child_db.entries_count) {
-		BNXT_TF_DBG(ERR, "parent child db not supported\n");
+		BNXT_TF_DBG(ERR, "parent child db validation failed\n");
 		return -EINVAL;
 	}
 
 	p_pdb = &flow_db->parent_child_db;
-	for (idx = 0; idx <= p_pdb->entries_count; idx++) {
+	for (idx = 0; idx < p_pdb->entries_count; idx++) {
 		if (p_pdb->parent_flow_tbl[idx].parent_fid == fid) {
 			/* free the contents */
 			p_pdb->parent_flow_tbl[idx].parent_fid = 0;
@@ -1275,15 +1289,10 @@ ulp_flow_db_parent_child_flow_set(struct bnxt_ulp_context *ulp_ctxt,
 	uint32_t idx, a_idx;
 	uint64_t *t;
 
-	flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);
+	/* validate the arguments */
+	flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, parent_fid);
 	if (!flow_db) {
-		BNXT_TF_DBG(ERR, "Invalid Arguments\n");
-		return -EINVAL;
-	}
-
-	/* check for fid validity */
-	if (parent_fid >= flow_db->flow_tbl.num_flows || !parent_fid) {
-		BNXT_TF_DBG(ERR, "Invalid parent flow index %x\n", parent_fid);
+		BNXT_TF_DBG(ERR, "parent child db validation failed\n");
 		return -EINVAL;
 	}
 
@@ -1293,15 +1302,9 @@ ulp_flow_db_parent_child_flow_set(struct bnxt_ulp_context *ulp_ctxt,
 		return -EINVAL;
 	}
 
-	/* No support for parent child db then just exit */
-	if (!flow_db->parent_child_db.entries_count) {
-		BNXT_TF_DBG(ERR, "parent child db not supported\n");
-		return -EINVAL;
-	}
-
 	p_pdb = &flow_db->parent_child_db;
 	a_idx = child_fid / ULP_INDEX_BITMAP_SIZE;
-	for (idx = 0; idx <= p_pdb->entries_count; idx++) {
+	for (idx = 0; idx < p_pdb->entries_count; idx++) {
 		if (p_pdb->parent_flow_tbl[idx].parent_fid == parent_fid) {
 			t = p_pdb->parent_flow_tbl[idx].child_fid_bitset;
 			if (set_flag)
@@ -1334,26 +1337,15 @@ ulp_flow_db_parent_flow_idx_get(struct bnxt_ulp_context *ulp_ctxt,
 	struct ulp_fdb_parent_child_db *p_pdb;
 	uint32_t idx;
 
-	flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);
+	/* validate the arguments */
+	flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, parent_fid);
 	if (!flow_db) {
-		BNXT_TF_DBG(ERR, "Invalid Arguments\n");
-		return -EINVAL;
-	}
-
-	/* check for fid validity */
-	if (parent_fid >= flow_db->flow_tbl.num_flows || !parent_fid) {
-		BNXT_TF_DBG(ERR, "Invalid parent flow index %x\n", parent_fid);
-		return -EINVAL;
-	}
-
-	/* No support for parent child db then just exit */
-	if (!flow_db->parent_child_db.entries_count) {
-		BNXT_TF_DBG(ERR, "parent child db not supported\n");
+		BNXT_TF_DBG(ERR, "parent child db validation failed\n");
 		return -EINVAL;
 	}
 
 	p_pdb = &flow_db->parent_child_db;
-	for (idx = 0; idx <= p_pdb->entries_count; idx++) {
+	for (idx = 0; idx < p_pdb->entries_count; idx++) {
 		if (p_pdb->parent_flow_tbl[idx].parent_fid == parent_fid) {
 			*parent_idx = idx;
 			return 0;
@@ -1425,6 +1417,73 @@ ulp_flow_db_parent_child_flow_next_entry_get(struct bnxt_ulp_flow_db *flow_db,
 	return 0;
 }
 
+/*
+ * Set the counter accumulation in the parent flow
+ *
+ * ulp_ctxt [in] Ptr to ulp_context
+ * parent_idx [in] The parent index of the parent flow entry
+ *
+ * returns index on success and negative on failure.
+ */
+static int32_t
+ulp_flow_db_parent_flow_count_accum_set(struct bnxt_ulp_context *ulp_ctxt,
+					uint32_t parent_idx)
+{
+	struct bnxt_ulp_flow_db *flow_db;
+	struct ulp_fdb_parent_child_db *p_pdb;
+
+	flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);
+	if (!flow_db) {
+		BNXT_TF_DBG(ERR, "Invalid Arguments\n");
+		return -EINVAL;
+	}
+
+	/* check for parent idx validity */
+	p_pdb = &flow_db->parent_child_db;
+	if (parent_idx >= p_pdb->entries_count ||
+	    !p_pdb->parent_flow_tbl[parent_idx].parent_fid) {
+		BNXT_TF_DBG(ERR, "Invalid parent flow index %x\n", parent_idx);
+		return -EINVAL;
+	}
+
+	p_pdb->parent_flow_tbl[parent_idx].counter_acc = 1;
+	return 0;
+}
+
+/*
+ * Get the counter accumulation in the parent flow
+ *
+ * ulp_ctxt [in] Ptr to ulp_context
+ * parent_fid [in] The flow id of the parent flow entry
+ *
+ * returns 0 if counter accum is set else -1.
+ */
+static int32_t
+ulp_flow_db_parent_flow_count_accum_get(struct bnxt_ulp_context *ulp_ctxt,
+					uint32_t parent_fid)
+{
+	struct bnxt_ulp_flow_db *flow_db;
+	struct ulp_fdb_parent_child_db *p_pdb;
+	uint32_t idx;
+
+	/* validate the arguments */
+	flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, parent_fid);
+	if (!flow_db) {
+		BNXT_TF_DBG(ERR, "parent child db validation failed\n");
+		return -EINVAL;
+	}
+
+	p_pdb = &flow_db->parent_child_db;
+	for (idx = 0; idx < p_pdb->entries_count; idx++) {
+		if (p_pdb->parent_flow_tbl[idx].parent_fid == parent_fid) {
+			if (p_pdb->parent_flow_tbl[idx].counter_acc)
+				return 0;
+			break;
+		}
+	}
+	return -1;
+}
+
 /*
  * Orphan the child flow entry
  * This is called only for child flows that have
@@ -1498,6 +1557,8 @@ int32_t
 ulp_flow_db_parent_flow_create(struct bnxt_ulp_mapper_parms *parms)
 {
 	struct ulp_flow_db_res_params fid_parms;
+	uint32_t sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT_ACC;
+	struct ulp_flow_db_res_params res_params;
 	int32_t fid_idx;
 
 	/* create the child flow entry in parent flow table */
@@ -1519,6 +1580,22 @@ ulp_flow_db_parent_flow_create(struct bnxt_ulp_mapper_parms *parms)
 			    parms->fid);
 		return -1;
 	}
+
+	/* check of the flow has internal counter accumulation enabled */
+	if (!ulp_flow_db_resource_params_get(parms->ulp_ctx,
+					     BNXT_ULP_FDB_TYPE_REGULAR,
+					     parms->fid,
+					     BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+					     sub_type,
+					     &res_params)) {
+		/* Enable the counter accumulation in parent entry */
+		if (ulp_flow_db_parent_flow_count_accum_set(parms->ulp_ctx,
+							    fid_idx)) {
+			BNXT_TF_DBG(ERR, "Error in setting counter acc %x\n",
+				    parms->fid);
+			return -1;
+		}
+	}
 	return 0;
 }
 
@@ -1533,6 +1610,10 @@ int32_t
 ulp_flow_db_child_flow_create(struct bnxt_ulp_mapper_parms *parms)
 {
 	struct ulp_flow_db_res_params fid_parms;
+	uint32_t sub_type = BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT;
+	enum bnxt_ulp_resource_func res_fun;
+	struct ulp_flow_db_res_params res_p;
+	uint32_t parent_fid = parms->parent_fid;
 	int32_t rc;
 
 	/* create the parent flow entry in parent flow table */
@@ -1541,7 +1622,7 @@ ulp_flow_db_child_flow_create(struct bnxt_ulp_mapper_parms *parms)
 					       parms->fid, 1);
 	if (rc) {
 		BNXT_TF_DBG(ERR, "Error in setting child fid %x\n", parms->fid);
-		return -1;
+		return rc;
 	}
 
 	/* Add the parent details in the resource list of the flow */
@@ -1549,11 +1630,154 @@ ulp_flow_db_child_flow_create(struct bnxt_ulp_mapper_parms *parms)
 	fid_parms.resource_func	= BNXT_ULP_RESOURCE_FUNC_CHILD_FLOW;
 	fid_parms.resource_hndl	= parms->parent_fid;
 	fid_parms.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO;
-	if (ulp_flow_db_resource_add(parms->ulp_ctx, BNXT_ULP_FDB_TYPE_REGULAR,
-				     parms->fid, &fid_parms)) {
+	rc  = ulp_flow_db_resource_add(parms->ulp_ctx,
+				       BNXT_ULP_FDB_TYPE_REGULAR,
+				       parms->fid, &fid_parms);
+	if (rc) {
 		BNXT_TF_DBG(ERR, "Error in adding flow res for fid %x\n",
 			    parms->fid);
-		return -1;
+		return rc;
+	}
+
+	/* check if accumulation count is set for parent flow */
+	rc = ulp_flow_db_parent_flow_count_accum_get(parms->ulp_ctx,
+						     parms->parent_fid);
+	if (!rc) {
+		/* check if internal count action included for this flow.*/
+		res_fun = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE;
+		rc = ulp_flow_db_resource_params_get(parms->ulp_ctx,
+						     BNXT_ULP_FDB_TYPE_REGULAR,
+						     parms->fid,
+						     res_fun,
+						     sub_type,
+						     &res_p);
+		if (!rc) {
+			/* update the counter manager to include parent fid */
+			if (ulp_fc_mgr_cntr_parent_flow_set(parms->ulp_ctx,
+							    res_p.direction,
+							    res_p.resource_hndl,
+							    parent_fid)) {
+				BNXT_TF_DBG(ERR, "Error in setting child %x\n",
+					    parms->fid);
+				return -1;
+			}
+		}
 	}
+	/* return success */
 	return 0;
 }
+
+/*
+ * Update the parent counters
+ *
+ * ulp_ctxt [in] Ptr to ulp_context
+ * parent_fid [in] The flow id of the parent flow entry
+ * packet_count [in] - packet count
+ * byte_count [in] - byte count
+ *
+ * returns 0 on success
+ */
+int32_t
+ulp_flow_db_parent_flow_count_update(struct bnxt_ulp_context *ulp_ctxt,
+				     uint32_t parent_fid,
+				     uint64_t packet_count,
+				     uint64_t byte_count)
+{
+	struct bnxt_ulp_flow_db *flow_db;
+	struct ulp_fdb_parent_child_db *p_pdb;
+	uint32_t idx;
+
+	/* validate the arguments */
+	flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, parent_fid);
+	if (!flow_db) {
+		BNXT_TF_DBG(ERR, "parent child db validation failed\n");
+		return -EINVAL;
+	}
+
+	p_pdb = &flow_db->parent_child_db;
+	for (idx = 0; idx < p_pdb->entries_count; idx++) {
+		if (p_pdb->parent_flow_tbl[idx].parent_fid == parent_fid) {
+			if (p_pdb->parent_flow_tbl[idx].counter_acc) {
+				p_pdb->parent_flow_tbl[idx].pkt_count +=
+					packet_count;
+				p_pdb->parent_flow_tbl[idx].byte_count +=
+					byte_count;
+			}
+			return 0;
+		}
+	}
+	return -ENOENT;
+}
+
+/*
+ * Get the parent accumulation counters
+ *
+ * ulp_ctxt [in] Ptr to ulp_context
+ * parent_fid [in] The flow id of the parent flow entry
+ * packet_count [out] - packet count
+ * byte_count [out] - byte count
+ *
+ * returns 0 on success
+ */
+int32_t
+ulp_flow_db_parent_flow_count_get(struct bnxt_ulp_context *ulp_ctxt,
+				  uint32_t parent_fid,
+				  uint64_t *packet_count,
+				  uint64_t *byte_count)
+{
+	struct bnxt_ulp_flow_db *flow_db;
+	struct ulp_fdb_parent_child_db *p_pdb;
+	uint32_t idx;
+
+	/* validate the arguments */
+	flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, parent_fid);
+	if (!flow_db) {
+		BNXT_TF_DBG(ERR, "parent child db validation failed\n");
+		return -EINVAL;
+	}
+
+	p_pdb = &flow_db->parent_child_db;
+	for (idx = 0; idx < p_pdb->entries_count; idx++) {
+		if (p_pdb->parent_flow_tbl[idx].parent_fid == parent_fid) {
+			if (p_pdb->parent_flow_tbl[idx].counter_acc) {
+				*packet_count =
+					p_pdb->parent_flow_tbl[idx].pkt_count;
+				*byte_count =
+					p_pdb->parent_flow_tbl[idx].byte_count;
+			}
+			return 0;
+		}
+	}
+	return -ENOENT;
+}
+
+/*
+ * reset the parent accumulation counters
+ *
+ * ulp_ctxt [in] Ptr to ulp_context
+ *
+ * returns none
+ */
+void
+ulp_flow_db_parent_flow_count_reset(struct bnxt_ulp_context *ulp_ctxt)
+{
+	struct bnxt_ulp_flow_db *flow_db;
+	struct ulp_fdb_parent_child_db *p_pdb;
+	uint32_t idx;
+
+	/* validate the arguments */
+	flow_db = ulp_flow_db_parent_arg_validation(ulp_ctxt, 1);
+	if (!flow_db) {
+		BNXT_TF_DBG(ERR, "parent child db validation failed\n");
+		return;
+	}
+
+	p_pdb = &flow_db->parent_child_db;
+	for (idx = 0; idx < p_pdb->entries_count; idx++) {
+		if (p_pdb->parent_flow_tbl[idx].parent_fid &&
+		    p_pdb->parent_flow_tbl[idx].counter_acc) {
+			p_pdb->parent_flow_tbl[idx].pkt_count = 0;
+			p_pdb->parent_flow_tbl[idx].byte_count = 0;
+		}
+	}
+}
diff --git a/drivers/net/bnxt/tf_ulp/ulp_flow_db.h b/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
index 95fd1992d..10e69bae4 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_flow_db.h
@@ -56,6 +56,9 @@ struct bnxt_ulp_flow_tbl {
 /* Structure to maintain parent-child flow relationships */
 struct ulp_fdb_parent_info {
 	uint32_t	parent_fid;
+	uint32_t	counter_acc;
+	uint64_t	pkt_count;
+	uint64_t	byte_count;
 	uint64_t	*child_fid_bitset;
 };
 
@@ -356,4 +359,45 @@ ulp_flow_db_parent_flow_create(struct bnxt_ulp_mapper_parms *parms);
 int32_t
 ulp_flow_db_child_flow_create(struct bnxt_ulp_mapper_parms *parms);
 
+/*
+ * Update the parent counters
+ *
+ * ulp_ctxt [in] Ptr to ulp_context
+ * parent_fid [in] The flow id of the parent flow entry
+ * packet_count [in] - packet count
+ * byte_count [in] - byte count
+ *
+ * returns 0 on success
+ */
+int32_t
+ulp_flow_db_parent_flow_count_update(struct bnxt_ulp_context *ulp_ctxt,
+				     uint32_t parent_fid,
+				     uint64_t packet_count,
+				     uint64_t byte_count);
+/*
+ * Get the parent accumulation counters
+ *
+ * ulp_ctxt [in] Ptr to ulp_context
+ * parent_fid [in] The flow id of the parent flow entry
+ * packet_count [out] - packet count
+ * byte_count [out] - byte count
+ *
+ * returns 0 on success
+ */
+int32_t
+ulp_flow_db_parent_flow_count_get(struct bnxt_ulp_context *ulp_ctxt,
+				  uint32_t parent_fid,
+				  uint64_t *packet_count,
+				  uint64_t *byte_count);
+
+/*
+ * reset the parent accumulation counters
+ *
+ * ulp_ctxt [in] Ptr to ulp_context
+ *
+ * returns none
+ */
+void
+ulp_flow_db_parent_flow_count_reset(struct bnxt_ulp_context *ulp_ctxt);
+
 #endif /* _ULP_FLOW_DB_H_ */
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
index 168e308c2..6dade9afd 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
@@ -332,7 +332,8 @@ enum bnxt_ulp_resource_sub_type {
 	BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL = 0,
 	BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_VFR_CFA_ACTION = 1,
 	BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT = 2,
-	BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_EXT_COUNT = 3,
+	BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT_ACC = 3,
+	BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_EXT_COUNT = 4,
 	BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM = 0,
 	BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM = 1
 };
-- 
2.21.1 (Apple Git-122.3)


^ permalink raw reply	[flat|nested] 32+ messages in thread

* [dpdk-dev] [PATCH v2 07/11] net/bnxt: change HWRM command to create reps
  2020-10-20 21:55 ` [dpdk-dev] [PATCH v2 00/11] bnxt fixes and enhancements to TRUFLOW support Ajit Khaparde
                     ` (5 preceding siblings ...)
  2020-10-20 21:55   ` [dpdk-dev] [PATCH v2 06/11] net/bnxt: add support for flow counter accumulation Ajit Khaparde
@ 2020-10-20 21:55   ` Ajit Khaparde
  2020-10-20 21:55   ` [dpdk-dev] [PATCH v2 08/11] net/bnxt: add mapper support for wildcard TCAM Ajit Khaparde
                     ` (4 subsequent siblings)
  11 siblings, 0 replies; 32+ messages in thread
From: Ajit Khaparde @ 2020-10-20 21:55 UTC (permalink / raw)
  To: dev; +Cc: Somnath Kotur, Shahaji Bhosle

From: Somnath Kotur <somnath.kotur@broadcom.com>

Use cfa pair alloc for configuring reps.
Instead of cfa_vfr_alloc for Wh+ and cfa_pair_alloc for Stingray,
converge to cfa_pair_alloc/free for both devices. Set the command
request structure bits accordingly.
As part of this, remove the old cfa_vfr_alloc cmd definitions as FW
has deprecated support for those commands.

Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
Reviewed-by: Shahaji Bhosle <sbhosle@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
 doc/guides/rel_notes/release_20_11.rst |  1 +
 drivers/net/bnxt/bnxt.h                |  6 ++-
 drivers/net/bnxt/bnxt_ethdev.c         |  2 +
 drivers/net/bnxt/bnxt_hwrm.c           | 60 +++-----------------------
 drivers/net/bnxt/bnxt_hwrm.h           |  2 -
 drivers/net/bnxt/bnxt_reps.c           | 18 ++++----
 6 files changed, 22 insertions(+), 67 deletions(-)

diff --git a/doc/guides/rel_notes/release_20_11.rst b/doc/guides/rel_notes/release_20_11.rst
index caff9fe9d..c8b284e3b 100644
--- a/doc/guides/rel_notes/release_20_11.rst
+++ b/doc/guides/rel_notes/release_20_11.rst
@@ -147,6 +147,7 @@ New Features
   * Added support for RSS hash level selection.
   * Updated HWRM structures to 1.10.1.70 version.
   * Added TRUFLOW support for Stingray devices.
+  * Added support for representors on MAIA cores of SR.
 
 * **Updated Cisco enic driver.**
 
diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h
index a951bca7a..57178192d 100644
--- a/drivers/net/bnxt/bnxt.h
+++ b/drivers/net/bnxt/bnxt.h
@@ -836,12 +836,14 @@ struct bnxt_representor {
 #define BNXT_REP_Q_F2R_VALID		BIT(2)
 #define BNXT_REP_FC_R2F_VALID		BIT(3)
 #define BNXT_REP_FC_F2R_VALID		BIT(4)
+#define BNXT_REP_BASED_PF_VALID		BIT(5)
 	uint32_t		flags;
 	uint16_t		fw_fid;
 #define	BNXT_DFLT_VNIC_ID_INVALID	0xFFFF
 	uint16_t		dflt_vnic_id;
 	uint16_t		svif;
 	uint16_t		vfr_tx_cfa_action;
+	uint8_t			parent_pf_idx; /* Logical PF index */
 	uint32_t		dpdk_port_id;
 	uint32_t		rep_based_pf;
 	uint8_t			rep_q_r2f;
@@ -863,7 +865,9 @@ struct bnxt_representor {
 	uint64_t                rx_drop_bytes[BNXT_MAX_VF_REP_RINGS];
 };
 
-#define BNXT_REP_PF(vfr_bp)	((vfr_bp)->flags & BNXT_REP_IS_PF)
+#define BNXT_REP_PF(vfr_bp)		((vfr_bp)->flags & BNXT_REP_IS_PF)
+#define BNXT_REP_BASED_PF(vfr_bp)	\
+		((vfr_bp)->flags & BNXT_REP_BASED_PF_VALID)
 
 struct bnxt_vf_rep_tx_queue {
 	struct bnxt_tx_queue *txq;
diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
index 32318cfd0..2a00a5ea9 100644
--- a/drivers/net/bnxt/bnxt_ethdev.c
+++ b/drivers/net/bnxt/bnxt_ethdev.c
@@ -5767,6 +5767,8 @@ bnxt_parse_devarg_rep_based_pf(__rte_unused const char *key,
 	}
 
 	vfr_bp->rep_based_pf = rep_based_pf;
+	vfr_bp->flags |= BNXT_REP_BASED_PF_VALID;
+
 	PMD_DRV_LOG(INFO, "rep-based-pf = %d\n", vfr_bp->rep_based_pf);
 
 	return 0;
diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c
index 361f99536..84702125c 100644
--- a/drivers/net/bnxt/bnxt_hwrm.c
+++ b/drivers/net/bnxt/bnxt_hwrm.c
@@ -5671,55 +5671,6 @@ int bnxt_hwrm_cfa_counter_qstats(struct bnxt *bp,
 	return 0;
 }
 
-int bnxt_hwrm_cfa_vfr_alloc(struct bnxt *bp, uint16_t vf_idx)
-{
-	struct hwrm_cfa_vfr_alloc_output *resp = bp->hwrm_cmd_resp_addr;
-	struct hwrm_cfa_vfr_alloc_input req = {0};
-	int rc;
-
-	if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
-		PMD_DRV_LOG(DEBUG,
-			    "Not a PF or trusted VF. Command not supported\n");
-		return 0;
-	}
-
-	HWRM_PREP(&req, HWRM_CFA_VFR_ALLOC, BNXT_USE_CHIMP_MB);
-	req.vf_id = rte_cpu_to_le_16(vf_idx);
-	snprintf(req.vfr_name, sizeof(req.vfr_name), "%svfr%d",
-		 bp->eth_dev->data->name, vf_idx);
-
-	rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
-	HWRM_CHECK_RESULT();
-
-	HWRM_UNLOCK();
-	PMD_DRV_LOG(DEBUG, "VFR %d allocated\n", vf_idx);
-	return rc;
-}
-
-int bnxt_hwrm_cfa_vfr_free(struct bnxt *bp, uint16_t vf_idx)
-{
-	struct hwrm_cfa_vfr_free_output *resp = bp->hwrm_cmd_resp_addr;
-	struct hwrm_cfa_vfr_free_input req = {0};
-	int rc;
-
-	if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
-		PMD_DRV_LOG(DEBUG,
-			    "Not a PF or trusted VF. Command not supported\n");
-		return 0;
-	}
-
-	HWRM_PREP(&req, HWRM_CFA_VFR_FREE, BNXT_USE_CHIMP_MB);
-	req.vf_id = rte_cpu_to_le_16(vf_idx);
-	snprintf(req.vfr_name, sizeof(req.vfr_name), "%svfr%d",
-		 bp->eth_dev->data->name, vf_idx);
-
-	rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
-	HWRM_CHECK_RESULT();
-	HWRM_UNLOCK();
-	PMD_DRV_LOG(DEBUG, "VFR %d freed\n", vf_idx);
-	return rc;
-}
-
 int bnxt_hwrm_first_vf_id_query(struct bnxt *bp, uint16_t fid,
 				uint16_t *first_vf_id)
 {
@@ -5760,8 +5711,9 @@ int bnxt_hwrm_cfa_pair_alloc(struct bnxt *bp, struct bnxt_representor *rep_bp)
 	snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d",
 		 bp->eth_dev->data->name, rep_bp->vf_id);
 
-	req.pf_b_id = rte_cpu_to_le_32(rep_bp->rep_based_pf);
-	req.vf_b_id = rte_cpu_to_le_16(rep_bp->vf_id);
+	req.pf_b_id = rep_bp->parent_pf_idx;
+	req.vf_b_id = BNXT_REP_PF(rep_bp) ? rte_cpu_to_le_16(((uint16_t)-1)) :
+						rte_cpu_to_le_16(rep_bp->vf_id);
 	req.vf_a_id = rte_cpu_to_le_16(bp->fw_fid);
 	req.host_b_id = 1; /* TBD - Confirm if this is OK */
 
@@ -5803,10 +5755,10 @@ int bnxt_hwrm_cfa_pair_free(struct bnxt *bp, struct bnxt_representor *rep_bp)
 	HWRM_PREP(&req, HWRM_CFA_PAIR_FREE, BNXT_USE_CHIMP_MB);
 	snprintf(req.pair_name, sizeof(req.pair_name), "%svfr%d",
 		 bp->eth_dev->data->name, rep_bp->vf_id);
-	req.pf_b_id = rte_cpu_to_le_32(rep_bp->rep_based_pf);
-	req.vf_id = rte_cpu_to_le_16(rep_bp->vf_id);
+	req.pf_b_id = rep_bp->parent_pf_idx;
 	req.pair_mode = HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW;
-
+	req.vf_id = BNXT_REP_PF(rep_bp) ? rte_cpu_to_le_16(((uint16_t)-1)) :
+						rte_cpu_to_le_16(rep_bp->vf_id);
 	rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
 	HWRM_CHECK_RESULT();
 	HWRM_UNLOCK();
diff --git a/drivers/net/bnxt/bnxt_hwrm.h b/drivers/net/bnxt/bnxt_hwrm.h
index a7fa7f66b..23ca6ab51 100644
--- a/drivers/net/bnxt/bnxt_hwrm.h
+++ b/drivers/net/bnxt/bnxt_hwrm.h
@@ -297,8 +297,6 @@ int bnxt_hwrm_port_phy_qcaps(struct bnxt *bp);
 int bnxt_hwrm_oem_cmd(struct bnxt *bp, uint32_t entry_num);
 int bnxt_clear_one_vnic_filter(struct bnxt *bp,
 			       struct bnxt_filter_info *filter);
-int bnxt_hwrm_cfa_vfr_alloc(struct bnxt *bp, uint16_t vf_idx);
-int bnxt_hwrm_cfa_vfr_free(struct bnxt *bp, uint16_t vf_idx);
 void bnxt_hwrm_free_vf_info(struct bnxt *bp);
 int bnxt_hwrm_first_vf_id_query(struct bnxt *bp, uint16_t fid,
 				uint16_t *first_vf_id);
diff --git a/drivers/net/bnxt/bnxt_reps.c b/drivers/net/bnxt/bnxt_reps.c
index b4566c926..e5ba0909b 100644
--- a/drivers/net/bnxt/bnxt_reps.c
+++ b/drivers/net/bnxt/bnxt_reps.c
@@ -216,8 +216,9 @@ int bnxt_representor_init(struct rte_eth_dev *eth_dev, void *params)
 		    "Switch domain id %d: Representor Device %d init done\n",
 		    vf_rep_bp->switch_domain_id, vf_rep_bp->vf_id);
 
-	if (vf_rep_bp->rep_based_pf) {
+	if (BNXT_REP_BASED_PF(vf_rep_bp)) {
 		vf_rep_bp->fw_fid = vf_rep_bp->rep_based_pf + 1;
+		vf_rep_bp->parent_pf_idx = vf_rep_bp->rep_based_pf;
 		if (!(BNXT_REP_PF(vf_rep_bp))) {
 			/* VF representor for the remote PF,get first_vf_id */
 			rc = bnxt_hwrm_first_vf_id_query(parent_bp,
@@ -237,6 +238,10 @@ int bnxt_representor_init(struct rte_eth_dev *eth_dev, void *params)
 		}
 	}  else {
 		vf_rep_bp->fw_fid = rep_params->vf_id + parent_bp->first_vf_id;
+		if (BNXT_VF_IS_TRUSTED(parent_bp))
+			vf_rep_bp->parent_pf_idx = parent_bp->parent->fid - 1;
+		else
+			vf_rep_bp->parent_pf_idx = parent_bp->fw_fid - 1;
 	}
 
 	PMD_DRV_LOG(INFO, "vf_rep->fw_fid = %d\n", vf_rep_bp->fw_fid);
@@ -329,11 +334,7 @@ static int bnxt_tf_vfr_alloc(struct rte_eth_dev *vfr_ethdev)
 	/* update the port id so you can backtrack to ethdev */
 	vfr->dpdk_port_id = vfr_ethdev->data->port_id;
 
-	if (BNXT_STINGRAY(parent_bp)) {
-		rc = bnxt_hwrm_cfa_pair_alloc(parent_bp, vfr);
-	} else {
-		rc = bnxt_hwrm_cfa_vfr_alloc(parent_bp, vfr->vf_id);
-	}
+	rc = bnxt_hwrm_cfa_pair_alloc(parent_bp, vfr);
 	if (rc) {
 		BNXT_TF_DBG(ERR, "Failed in hwrm vfr alloc vfr:%u rc=%d\n",
 			    vfr->vf_id, rc);
@@ -468,10 +469,7 @@ static int bnxt_vfr_free(struct bnxt_representor *vfr)
 		    vfr->vf_id);
 	vfr->vfr_tx_cfa_action = 0;
 
-	if (BNXT_STINGRAY(parent_bp))
-		rc = bnxt_hwrm_cfa_pair_free(parent_bp, vfr);
-	else
-		rc = bnxt_hwrm_cfa_vfr_free(parent_bp, vfr->vf_id);
+	rc = bnxt_hwrm_cfa_pair_free(parent_bp, vfr);
 
 	return rc;
 }
-- 
2.21.1 (Apple Git-122.3)


^ permalink raw reply	[flat|nested] 32+ messages in thread

* [dpdk-dev] [PATCH v2 08/11] net/bnxt: add mapper support for wildcard TCAM
  2020-10-20 21:55 ` [dpdk-dev] [PATCH v2 00/11] bnxt fixes and enhancements to TRUFLOW support Ajit Khaparde
                     ` (6 preceding siblings ...)
  2020-10-20 21:55   ` [dpdk-dev] [PATCH v2 07/11] net/bnxt: change HWRM command to create reps Ajit Khaparde
@ 2020-10-20 21:55   ` Ajit Khaparde
  2020-10-20 21:55   ` [dpdk-dev] [PATCH v2 09/11] net/bnxt: refactor flow id allocation Ajit Khaparde
                     ` (3 subsequent siblings)
  11 siblings, 0 replies; 32+ messages in thread
From: Ajit Khaparde @ 2020-10-20 21:55 UTC (permalink / raw)
  To: dev; +Cc: Kishore Padmanabha, Mike Baucom

From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>

Added support for the key and mask fields encoding for the
wildcard tcam entry.

Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Mike Baucom <michael.baucom@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
 drivers/net/bnxt/tf_ulp/ulp_mapper.c |  47 ++++++++--
 drivers/net/bnxt/tf_ulp/ulp_utils.c  | 125 +++++++++++++++++++++++++++
 drivers/net/bnxt/tf_ulp/ulp_utils.h  |  48 +++++++++-
 3 files changed, 212 insertions(+), 8 deletions(-)

diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
index b74cb92f5..27b478099 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
@@ -1497,6 +1497,29 @@ ulp_mapper_tcam_tbl_entry_write(struct bnxt_ulp_mapper_parms *parms,
 	return rc;
 }
 
+#define BNXT_ULP_WC_TCAM_SLICE_SIZE 80
+/* internal function to post process the key/mask blobs for wildcard tcam tbl */
+static void ulp_mapper_wc_tcam_tbl_post_process(struct ulp_blob *blob,
+						uint32_t len)
+{
+	uint8_t mode[2] = {0x0, 0x0};
+	uint32_t mode_len = len / BNXT_ULP_WC_TCAM_SLICE_SIZE;
+	uint32_t size, idx;
+
+	/* Add the mode bits to the key and mask*/
+	if (mode_len == 2)
+		mode[1] = 2;
+	else if (mode_len > 2)
+		mode[1] = 3;
+
+	size = BNXT_ULP_WC_TCAM_SLICE_SIZE + ULP_BYTE_2_BITS(sizeof(mode));
+	for (idx = 0; idx < mode_len; idx++)
+		ulp_blob_insert(blob, (size * idx), mode,
+				ULP_BYTE_2_BITS(sizeof(mode)));
+	ulp_blob_perform_64B_word_swap(blob);
+	ulp_blob_perform_64B_byte_swap(blob);
+}
+
 static int32_t
 ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms,
 			    struct bnxt_ulp_mapper_tbl_info *tbl)
@@ -1533,9 +1556,9 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms,
 		return -EINVAL;
 	}
 
-	if (!ulp_blob_init(&key, tbl->key_bit_size,
+	if (!ulp_blob_init(&key, tbl->blob_key_bit_size,
 			   parms->device_params->byte_order) ||
-	    !ulp_blob_init(&mask, tbl->key_bit_size,
+	    !ulp_blob_init(&mask, tbl->blob_key_bit_size,
 			   parms->device_params->byte_order) ||
 	    !ulp_blob_init(&data, tbl->result_bit_size,
 			   parms->device_params->byte_order) ||
@@ -1545,6 +1568,11 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms,
 		return -EINVAL;
 	}
 
+	if (tbl->resource_type == TF_TCAM_TBL_TYPE_WC_TCAM) {
+		key.byte_order = BNXT_ULP_BYTE_ORDER_BE;
+		mask.byte_order = BNXT_ULP_BYTE_ORDER_BE;
+	}
+
 	/* create the key/mask */
 	/*
 	 * NOTE: The WC table will require some kind of flag to handle the
@@ -1570,6 +1598,11 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms,
 		}
 	}
 
+	if (tbl->resource_type == TF_TCAM_TBL_TYPE_WC_TCAM) {
+		ulp_mapper_wc_tcam_tbl_post_process(&key, tbl->key_bit_size);
+		ulp_mapper_wc_tcam_tbl_post_process(&mask, tbl->key_bit_size);
+	}
+
 	if (tbl->srch_b4_alloc == BNXT_ULP_SEARCH_BEFORE_ALLOC_NO) {
 		/*
 		 * No search for re-use is requested, so simply allocate the
@@ -1578,18 +1611,18 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms,
 		aparms.dir		= tbl->direction;
 		aparms.tcam_tbl_type	= tbl->resource_type;
 		aparms.search_enable	= tbl->srch_b4_alloc;
-		aparms.key_sz_in_bits	= tbl->key_bit_size;
 		aparms.key		= ulp_blob_data_get(&key, &tmplen);
-		if (tbl->key_bit_size != tmplen) {
+		aparms.key_sz_in_bits	= tmplen;
+		if (tbl->blob_key_bit_size != tmplen) {
 			BNXT_TF_DBG(ERR, "Key len (%d) != Expected (%d)\n",
-				    tmplen, tbl->key_bit_size);
+				    tmplen, tbl->blob_key_bit_size);
 			return -EINVAL;
 		}
 
 		aparms.mask		= ulp_blob_data_get(&mask, &tmplen);
-		if (tbl->key_bit_size != tmplen) {
+		if (tbl->blob_key_bit_size != tmplen) {
 			BNXT_TF_DBG(ERR, "Mask len (%d) != Expected (%d)\n",
-				    tmplen, tbl->key_bit_size);
+				    tmplen, tbl->blob_key_bit_size);
 			return -EINVAL;
 		}
 
diff --git a/drivers/net/bnxt/tf_ulp/ulp_utils.c b/drivers/net/bnxt/tf_ulp/ulp_utils.c
index 24474e2e2..a13a3bbf6 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_utils.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_utils.c
@@ -273,6 +273,69 @@ ulp_blob_push(struct ulp_blob *blob,
 	return datalen;
 }
 
+/*
+ * Insert data into the binary blob at the given offset.
+ *
+ * blob [in] The blob that data is added to.  The blob must
+ * be initialized prior to pushing data.
+ *
+ * offset [in] The offset where the data needs to be inserted.
+ *
+ * data [in/out] A pointer to bytes to be added to the blob.
+ *
+ * datalen [in] The number of bits to be added to the blob.
+ *
+ * The offset of the data is updated after each push of data.
+ * NULL returned on error.
+ */
+uint32_t
+ulp_blob_insert(struct ulp_blob *blob, uint32_t offset,
+		uint8_t *data, uint32_t datalen)
+{
+	uint32_t rc;
+	uint8_t local_data[BNXT_ULP_FLMP_BLOB_SIZE];
+	uint16_t mov_len;
+
+	/* validate the arguments */
+	if (!blob || datalen > (uint32_t)(blob->bitlen - blob->write_idx) ||
+	    offset > blob->write_idx) {
+		BNXT_TF_DBG(ERR, "invalid argument\n");
+		return 0; /* failure */
+	}
+
+	mov_len = blob->write_idx - offset;
+	/* If offset and data len are not 8 bit aligned then return error */
+	if (ULP_BITS_IS_BYTE_NOT_ALIGNED(offset) ||
+	    ULP_BITS_IS_BYTE_NOT_ALIGNED(datalen)) {
+		BNXT_TF_DBG(ERR, "invalid argument, not aligned\n");
+		return 0; /* failure */
+	}
+
+	/* copy the data so we can move the data */
+	memcpy(local_data, &blob->data[ULP_BITS_2_BYTE_NR(offset)],
+	       ULP_BITS_2_BYTE(mov_len));
+	blob->write_idx = offset;
+	if (blob->byte_order == BNXT_ULP_BYTE_ORDER_BE)
+		rc = ulp_bs_push_msb(blob->data,
+				     blob->write_idx,
+				     datalen,
+				     data);
+	else
+		rc = ulp_bs_push_lsb(blob->data,
+				     blob->write_idx,
+				     datalen,
+				     data);
+	if (!rc) {
+		BNXT_TF_DBG(ERR, "Failed ro write blob\n");
+		return 0;
+	}
+	/* copy the previously stored data */
+	memcpy(&blob->data[ULP_BITS_2_BYTE_NR(offset + datalen)], local_data,
+	       ULP_BITS_2_BYTE(mov_len));
+	blob->write_idx += (mov_len + datalen);
+	return datalen;
+}
+
 /*
  * Add data to the binary blob at the current offset.
  *
@@ -603,6 +666,68 @@ ulp_blob_perform_byte_reverse(struct ulp_blob *blob)
 	}
 }
 
+/*
+ * Perform the blob buffer 64 bit word swap.
+ * This api makes the first 4 bytes the last in
+ * a given 64 bit value and vice-versa.
+ *
+ * blob [in] The blob's data to be used for swap.
+ *
+ * returns void.
+ */
+void
+ulp_blob_perform_64B_word_swap(struct ulp_blob *blob)
+{
+	uint32_t i, j, num;
+	uint8_t xchar;
+	uint32_t word_size = ULP_64B_IN_BYTES / 2;
+
+	/* validate the arguments */
+	if (!blob) {
+		BNXT_TF_DBG(ERR, "invalid argument\n");
+		return; /* failure */
+	}
+	num = ULP_BITS_2_BYTE(blob->write_idx);
+	for (i = 0; i < num; i = i + ULP_64B_IN_BYTES) {
+		for (j = 0; j < word_size; j++) {
+			xchar = blob->data[i + j];
+			blob->data[i + j] = blob->data[i + j + word_size];
+			blob->data[i + j + word_size] = xchar;
+		}
+	}
+}
+
+/*
+ * Perform the blob buffer 64 bit byte swap.
+ * This api makes the first byte the last in
+ * a given 64 bit value and vice-versa.
+ *
+ * blob [in] The blob's data to be used for swap.
+ *
+ * returns void.
+ */
+void
+ulp_blob_perform_64B_byte_swap(struct ulp_blob *blob)
+{
+	uint32_t i, j, num;
+	uint8_t xchar;
+	uint32_t offset = ULP_64B_IN_BYTES - 1;
+
+	/* validate the arguments */
+	if (!blob) {
+		BNXT_TF_DBG(ERR, "invalid argument\n");
+		return; /* failure */
+	}
+	num = ULP_BITS_2_BYTE(blob->write_idx);
+	for (i = 0; i < num; i = i + ULP_64B_IN_BYTES) {
+		for (j = 0; j < (ULP_64B_IN_BYTES / 2); j++) {
+			xchar = blob->data[i + j];
+			blob->data[i + j] = blob->data[i + offset - j];
+			blob->data[i + offset - j] = xchar;
+		}
+	}
+}
+
 /*
  * Read data from the operand
  *
diff --git a/drivers/net/bnxt/tf_ulp/ulp_utils.h b/drivers/net/bnxt/tf_ulp/ulp_utils.h
index 898e85123..749ac06d8 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_utils.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_utils.h
@@ -12,7 +12,7 @@
 #define ULP_BUFFER_ALIGN_8_BYTE		8
 #define ULP_BUFFER_ALIGN_16_BYTE	16
 #define ULP_BUFFER_ALIGN_64_BYTE	64
-
+#define ULP_64B_IN_BYTES		8
 /*
  * Macros for bitmap sets and gets
  * These macros can be used if the val are power of 2.
@@ -57,6 +57,9 @@
 /* Macro to round off to next multiple of 8*/
 #define ULP_BYTE_ROUND_OFF_8(x)	(((x) + 7) & ~7)
 
+/* Macro to check bits are byte aligned */
+#define ULP_BITS_IS_BYTE_NOT_ALIGNED(x)	((x) % 8)
+
 /* Macros to read the computed fields */
 #define ULP_COMP_FLD_IDX_RD(params, idx) \
 	rte_be_to_cpu_32((params)->comp_fld[(idx)])
@@ -167,6 +170,25 @@ ulp_blob_push(struct ulp_blob *blob,
 	      uint8_t *data,
 	      uint32_t datalen);
 
+/*
+ * Insert data into the binary blob at the given offset.
+ *
+ * blob [in] The blob that data is added to.  The blob must
+ * be initialized prior to pushing data.
+ *
+ * offset [in] The offset where the data needs to be inserted.
+ *
+ * data [in/out] A pointer to bytes to be added to the blob.
+ *
+ * datalen [in] The number of bits to be added to the blob.
+ *
+ * The offset of the data is updated after each push of data.
+ * NULL returned on error.
+ */
+uint32_t
+ulp_blob_insert(struct ulp_blob *blob, uint32_t offset,
+		uint8_t *data, uint32_t datalen);
+
 /*
  * Add data to the binary blob at the current offset.
  *
@@ -299,6 +321,30 @@ ulp_blob_perform_encap_swap(struct ulp_blob *blob);
 void
 ulp_blob_perform_byte_reverse(struct ulp_blob *blob);
 
+/*
+ * Perform the blob buffer 64 bit word swap.
+ * This api makes the first 4 bytes the last in
+ * a given 64 bit value and vice-versa.
+ *
+ * blob [in] The blob's data to be used for swap.
+ *
+ * returns void.
+ */
+void
+ulp_blob_perform_64B_word_swap(struct ulp_blob *blob);
+
+/*
+ * Perform the blob buffer 64 bit byte swap.
+ * This api makes the first byte the last in
+ * a given 64 bit value and vice-versa.
+ *
+ * blob [in] The blob's data to be used for swap.
+ *
+ * returns void.
+ */
+void
+ulp_blob_perform_64B_byte_swap(struct ulp_blob *blob);
+
 /*
  * Read data from the operand
  *
-- 
2.21.1 (Apple Git-122.3)


^ permalink raw reply	[flat|nested] 32+ messages in thread

* [dpdk-dev] [PATCH v2 09/11] net/bnxt: refactor flow id allocation
  2020-10-20 21:55 ` [dpdk-dev] [PATCH v2 00/11] bnxt fixes and enhancements to TRUFLOW support Ajit Khaparde
                     ` (7 preceding siblings ...)
  2020-10-20 21:55   ` [dpdk-dev] [PATCH v2 08/11] net/bnxt: add mapper support for wildcard TCAM Ajit Khaparde
@ 2020-10-20 21:55   ` Ajit Khaparde
  2020-10-20 21:55   ` [dpdk-dev] [PATCH v2 10/11] net/bnxt: add support for VXLAN decap templates Ajit Khaparde
                     ` (2 subsequent siblings)
  11 siblings, 0 replies; 32+ messages in thread
From: Ajit Khaparde @ 2020-10-20 21:55 UTC (permalink / raw)
  To: dev; +Cc: Venkat Duvvuru, Somnath Kotur

From: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>

Currently, the flow id is allocated inside ulp_mapper_flow_create.
However with vxlan decap feature if F2 flow comes before F1 flow
then F2 is cached and not really installed in the hardware which
means the code will return without calling ulp_mapper_flow_create.
But, ULP has to still return valid flow id to the stack.
Hence, move the flow id allocation outside ulp_mapper_flow_create.

Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
Reviewed-by: Somnath Kotur <somnath.kotur@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
 drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c  | 109 ++++++++++++++++-------
 drivers/net/bnxt/tf_ulp/ulp_def_rules.c  |  48 ++++++++--
 drivers/net/bnxt/tf_ulp/ulp_mapper.c     |  35 +-------
 drivers/net/bnxt/tf_ulp/ulp_mapper.h     |   4 +-
 drivers/net/bnxt/tf_ulp/ulp_rte_parser.h |   9 ++
 5 files changed, 132 insertions(+), 73 deletions(-)

diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
index c7b29824e..47fbaba03 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
@@ -74,6 +74,29 @@ bnxt_ulp_set_dir_attributes(struct ulp_rte_parser_params *params,
 		params->dir_attr |= BNXT_ULP_FLOW_ATTR_TRANSFER;
 }
 
+void
+bnxt_ulp_init_mapper_params(struct bnxt_ulp_mapper_create_parms *mapper_cparms,
+			    struct ulp_rte_parser_params *params,
+			    uint32_t priority, uint32_t class_id,
+			    uint32_t act_tmpl, uint16_t func_id,
+			    uint32_t fid,
+			    enum bnxt_ulp_fdb_type flow_type)
+{
+	mapper_cparms->app_priority = priority;
+	mapper_cparms->dir_attr = params->dir_attr;
+
+	mapper_cparms->class_tid = class_id;
+	mapper_cparms->act_tid = act_tmpl;
+	mapper_cparms->func_id = func_id;
+	mapper_cparms->hdr_bitmap = &params->hdr_bitmap;
+	mapper_cparms->hdr_field = params->hdr_field;
+	mapper_cparms->comp_fld = params->comp_fld;
+	mapper_cparms->act = &params->act_bitmap;
+	mapper_cparms->act_prop = &params->act_prop;
+	mapper_cparms->flow_type = flow_type;
+	mapper_cparms->flow_id = fid;
+}
+
 /* Function to create the rte flow. */
 static struct rte_flow *
 bnxt_ulp_flow_create(struct rte_eth_dev *dev,
@@ -85,22 +108,23 @@ bnxt_ulp_flow_create(struct rte_eth_dev *dev,
 	struct bnxt_ulp_mapper_create_parms mapper_cparms = { 0 };
 	struct ulp_rte_parser_params params;
 	struct bnxt_ulp_context *ulp_ctx;
+	int rc, ret = BNXT_TF_RC_ERROR;
 	uint32_t class_id, act_tmpl;
 	struct rte_flow *flow_id;
+	uint16_t func_id;
 	uint32_t fid;
-	int ret = BNXT_TF_RC_ERROR;
 
 	if (bnxt_ulp_flow_validate_args(attr,
 					pattern, actions,
 					error) == BNXT_TF_RC_ERROR) {
 		BNXT_TF_DBG(ERR, "Invalid arguments being passed\n");
-		goto parse_error;
+		goto parse_err1;
 	}
 
 	ulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(dev);
 	if (!ulp_ctx) {
 		BNXT_TF_DBG(ERR, "ULP context is not initialized\n");
-		goto parse_error;
+		goto parse_err1;
 	}
 
 	/* Initialize the parser params */
@@ -116,56 +140,72 @@ bnxt_ulp_flow_create(struct rte_eth_dev *dev,
 	ULP_COMP_FLD_IDX_WR(&params, BNXT_ULP_CF_IDX_SVIF_FLAG,
 			    BNXT_ULP_INVALID_SVIF_VAL);
 
+	/* Get the function id */
+	if (ulp_port_db_port_func_id_get(ulp_ctx,
+					 dev->data->port_id,
+					 &func_id)) {
+		BNXT_TF_DBG(ERR, "conversion of port to func id failed\n");
+		goto parse_err1;
+	}
+
+	/* Protect flow creation */
+	if (bnxt_ulp_cntxt_acquire_fdb_lock(ulp_ctx)) {
+		BNXT_TF_DBG(ERR, "Flow db lock acquire failed\n");
+		goto parse_err1;
+	}
+
+	/* Allocate a Flow ID for attaching all resources for the flow to.
+	 * Once allocated, all errors have to walk the list of resources and
+	 * free each of them.
+	 */
+	rc = ulp_flow_db_fid_alloc(ulp_ctx, BNXT_ULP_FDB_TYPE_REGULAR,
+				   func_id, &fid);
+	if (rc) {
+		BNXT_TF_DBG(ERR, "Unable to allocate flow table entry\n");
+		goto parse_err2;
+	}
+
 	/* Parse the rte flow pattern */
 	ret = bnxt_ulp_rte_parser_hdr_parse(pattern, &params);
 	if (ret != BNXT_TF_RC_SUCCESS)
-		goto parse_error;
+		goto parse_err3;
 
 	/* Parse the rte flow action */
 	ret = bnxt_ulp_rte_parser_act_parse(actions, &params);
 	if (ret != BNXT_TF_RC_SUCCESS)
-		goto parse_error;
+		goto parse_err3;
 
 	/* Perform the rte flow post process */
 	ret = bnxt_ulp_rte_parser_post_process(&params);
 	if (ret != BNXT_TF_RC_SUCCESS)
-		goto parse_error;
+		goto parse_err3;
 
 	ret = ulp_matcher_pattern_match(&params, &class_id);
 	if (ret != BNXT_TF_RC_SUCCESS)
-		goto parse_error;
+		goto parse_err3;
 
 	ret = ulp_matcher_action_match(&params, &act_tmpl);
 	if (ret != BNXT_TF_RC_SUCCESS)
-		goto parse_error;
+		goto parse_err3;
 
-	mapper_cparms.app_priority = attr->priority;
-	mapper_cparms.hdr_bitmap = &params.hdr_bitmap;
-	mapper_cparms.hdr_field = params.hdr_field;
-	mapper_cparms.comp_fld = params.comp_fld;
-	mapper_cparms.act = &params.act_bitmap;
-	mapper_cparms.act_prop = &params.act_prop;
-	mapper_cparms.class_tid = class_id;
-	mapper_cparms.act_tid = act_tmpl;
-	mapper_cparms.flow_type = BNXT_ULP_FDB_TYPE_REGULAR;
+	bnxt_ulp_init_mapper_params(&mapper_cparms, &params, attr->priority,
+				    class_id, act_tmpl, func_id, fid,
+				    BNXT_ULP_FDB_TYPE_REGULAR);
+	/* Call the ulp mapper to create the flow in the hardware. */
+	ret = ulp_mapper_flow_create(ulp_ctx, &mapper_cparms);
+	if (ret)
+		goto parse_err3;
 
-	/* Get the function id */
-	if (ulp_port_db_port_func_id_get(ulp_ctx,
-					 dev->data->port_id,
-					 &mapper_cparms.func_id)) {
-		BNXT_TF_DBG(ERR, "conversion of port to func id failed\n");
-		goto parse_error;
-	}
-	mapper_cparms.dir_attr = params.dir_attr;
+	bnxt_ulp_cntxt_release_fdb_lock(ulp_ctx);
 
-	/* Call the ulp mapper to create the flow in the hardware. */
-	ret = ulp_mapper_flow_create(ulp_ctx, &mapper_cparms, &fid);
-	if (!ret) {
-		flow_id = (struct rte_flow *)((uintptr_t)fid);
-		return flow_id;
-	}
+	flow_id = (struct rte_flow *)((uintptr_t)fid);
+	return flow_id;
 
-parse_error:
+parse_err3:
+	ulp_flow_db_fid_free(ulp_ctx, BNXT_ULP_FDB_TYPE_REGULAR, fid);
+parse_err2:
+	bnxt_ulp_cntxt_release_fdb_lock(ulp_ctx);
+parse_err1:
 	rte_flow_error_set(error, ret, RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
 			   "Failed to create flow.");
 	return NULL;
@@ -281,6 +321,10 @@ bnxt_ulp_flow_destroy(struct rte_eth_dev *dev,
 		return -EINVAL;
 	}
 
+	if (bnxt_ulp_cntxt_acquire_fdb_lock(ulp_ctx)) {
+		BNXT_TF_DBG(ERR, "Flow db lock acquire failed\n");
+		return -EINVAL;
+	}
 	ret = ulp_mapper_flow_destroy(ulp_ctx, BNXT_ULP_FDB_TYPE_REGULAR,
 				      flow_id);
 	if (ret) {
@@ -290,6 +334,7 @@ bnxt_ulp_flow_destroy(struct rte_eth_dev *dev,
 					   RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
 					   "Failed to destroy flow.");
 	}
+	bnxt_ulp_cntxt_release_fdb_lock(ulp_ctx);
 
 	return ret;
 }
diff --git a/drivers/net/bnxt/tf_ulp/ulp_def_rules.c b/drivers/net/bnxt/tf_ulp/ulp_def_rules.c
index c36d4d4c4..ec504fcf2 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_def_rules.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_def_rules.c
@@ -304,8 +304,8 @@ ulp_default_flow_create(struct rte_eth_dev *eth_dev,
 	struct ulp_rte_act_prop		act_prop;
 	struct ulp_rte_act_bitmap	act = { 0 };
 	struct bnxt_ulp_context		*ulp_ctx;
-	uint32_t type, ulp_flags = 0;
-	int rc;
+	uint32_t type, ulp_flags = 0, fid;
+	int rc = 0;
 
 	memset(&mapper_params, 0, sizeof(mapper_params));
 	memset(hdr_field, 0, sizeof(hdr_field));
@@ -316,6 +316,8 @@ ulp_default_flow_create(struct rte_eth_dev *eth_dev,
 	mapper_params.act = &act;
 	mapper_params.act_prop = &act_prop;
 	mapper_params.comp_fld = comp_fld;
+	mapper_params.class_tid = ulp_class_tid;
+	mapper_params.flow_type = BNXT_ULP_FDB_TYPE_DEFAULT;
 
 	ulp_ctx = bnxt_ulp_eth_dev_ptr2_cntxt_get(eth_dev);
 	if (!ulp_ctx) {
@@ -350,16 +352,43 @@ ulp_default_flow_create(struct rte_eth_dev *eth_dev,
 		type = param_list->type;
 	}
 
-	mapper_params.class_tid = ulp_class_tid;
-	mapper_params.flow_type = BNXT_ULP_FDB_TYPE_DEFAULT;
+	/* Get the function id */
+	if (ulp_port_db_port_func_id_get(ulp_ctx,
+					 eth_dev->data->port_id,
+					 &mapper_params.func_id)) {
+		BNXT_TF_DBG(ERR, "conversion of port to func id failed\n");
+		goto err1;
+	}
+
+	/* Protect flow creation */
+	if (bnxt_ulp_cntxt_acquire_fdb_lock(ulp_ctx)) {
+		BNXT_TF_DBG(ERR, "Flow db lock acquire failed\n");
+		goto err1;
+	}
 
-	rc = ulp_mapper_flow_create(ulp_ctx, &mapper_params, flow_id);
+	rc = ulp_flow_db_fid_alloc(ulp_ctx, BNXT_ULP_FDB_TYPE_DEFAULT,
+				   mapper_params.func_id, &fid);
 	if (rc) {
-		BNXT_TF_DBG(ERR, "Failed to create default flow.\n");
-		return rc;
+		BNXT_TF_DBG(ERR, "Unable to allocate flow table entry\n");
+		goto err2;
 	}
 
+	mapper_params.flow_id = fid;
+	rc = ulp_mapper_flow_create(ulp_ctx, &mapper_params);
+	if (rc)
+		goto err3;
+
+	bnxt_ulp_cntxt_release_fdb_lock(ulp_ctx);
+	*flow_id = fid;
 	return 0;
+
+err3:
+	ulp_flow_db_fid_free(ulp_ctx, BNXT_ULP_FDB_TYPE_DEFAULT, fid);
+err2:
+	bnxt_ulp_cntxt_release_fdb_lock(ulp_ctx);
+err1:
+	BNXT_TF_DBG(ERR, "Failed to create default flow.\n");
+	return rc;
 }
 
 /*
@@ -391,10 +420,15 @@ ulp_default_flow_destroy(struct rte_eth_dev *eth_dev, uint32_t flow_id)
 		return rc;
 	}
 
+	if (bnxt_ulp_cntxt_acquire_fdb_lock(ulp_ctx)) {
+		BNXT_TF_DBG(ERR, "Flow db lock acquire failed\n");
+		return -EINVAL;
+	}
 	rc = ulp_mapper_flow_destroy(ulp_ctx, BNXT_ULP_FDB_TYPE_DEFAULT,
 				     flow_id);
 	if (rc)
 		BNXT_TF_DBG(ERR, "Failed to destroy flow.\n");
+	bnxt_ulp_cntxt_release_fdb_lock(ulp_ctx);
 
 	return rc;
 }
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
index 27b478099..d5c129b3a 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
@@ -2723,15 +2723,9 @@ ulp_mapper_flow_destroy(struct bnxt_ulp_context *ulp_ctx,
 		BNXT_TF_DBG(ERR, "Invalid parms, unable to free flow\n");
 		return -EINVAL;
 	}
-	if (bnxt_ulp_cntxt_acquire_fdb_lock(ulp_ctx)) {
-		BNXT_TF_DBG(ERR, "Flow db lock acquire failed\n");
-		return -EINVAL;
-	}
 
 	rc = ulp_mapper_resources_free(ulp_ctx, flow_type, fid);
-	bnxt_ulp_cntxt_release_fdb_lock(ulp_ctx);
 	return rc;
-
 }
 
 /* Function to handle the default global templates that are allocated during
@@ -2795,8 +2789,7 @@ ulp_mapper_glb_template_table_init(struct bnxt_ulp_context *ulp_ctx)
  */
 int32_t
 ulp_mapper_flow_create(struct bnxt_ulp_context *ulp_ctx,
-		       struct bnxt_ulp_mapper_create_parms *cparms,
-		       uint32_t *flowid)
+		       struct bnxt_ulp_mapper_create_parms *cparms)
 {
 	struct bnxt_ulp_mapper_parms parms;
 	struct ulp_regfile regfile;
@@ -2821,6 +2814,7 @@ ulp_mapper_flow_create(struct bnxt_ulp_context *ulp_ctx,
 	parms.flow_type = cparms->flow_type;
 	parms.parent_flow = cparms->parent_flow;
 	parms.parent_fid = cparms->parent_fid;
+	parms.fid = cparms->flow_id;
 
 	/* Get the device id from the ulp context */
 	if (bnxt_ulp_cntxt_dev_id_get(ulp_ctx, &parms.dev_id)) {
@@ -2861,26 +2855,7 @@ ulp_mapper_flow_create(struct bnxt_ulp_context *ulp_ctx,
 		return -EINVAL;
 	}
 
-	/* Protect flow creation */
-	if (bnxt_ulp_cntxt_acquire_fdb_lock(ulp_ctx)) {
-		BNXT_TF_DBG(ERR, "Flow db lock acquire failed\n");
-		return -EINVAL;
-	}
-
-	/* Allocate a Flow ID for attaching all resources for the flow to.
-	 * Once allocated, all errors have to walk the list of resources and
-	 * free each of them.
-	 */
-	rc = ulp_flow_db_fid_alloc(ulp_ctx,
-				   parms.flow_type,
-				   cparms->func_id,
-				   &parms.fid);
-	if (rc) {
-		BNXT_TF_DBG(ERR, "Unable to allocate flow table entry\n");
-		bnxt_ulp_cntxt_release_fdb_lock(ulp_ctx);
-		return rc;
-	}
-
+	/* Process the action template list from the selected action table*/
 	if (parms.act_tid) {
 		parms.tmpl_type = BNXT_ULP_TEMPLATE_TYPE_ACTION;
 		/* Process the action template tables */
@@ -2911,13 +2886,9 @@ ulp_mapper_flow_create(struct bnxt_ulp_context *ulp_ctx,
 			goto flow_error;
 	}
 
-	*flowid = parms.fid;
-	bnxt_ulp_cntxt_release_fdb_lock(ulp_ctx);
-
 	return rc;
 
 flow_error:
-	bnxt_ulp_cntxt_release_fdb_lock(ulp_ctx);
 	/* Free all resources that were allocated during flow creation */
 	trc = ulp_mapper_flow_destroy(ulp_ctx, BNXT_ULP_FDB_TYPE_REGULAR,
 				      parms.fid);
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.h b/drivers/net/bnxt/tf_ulp/ulp_mapper.h
index 542e41e5a..0595d1555 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.h
@@ -93,6 +93,7 @@ struct bnxt_ulp_mapper_create_parms {
 	uint32_t			dir_attr;
 	enum bnxt_ulp_fdb_type		flow_type;
 
+	uint32_t			flow_id;
 	/* if set then create it as a child flow with parent as parent_fid */
 	uint32_t			parent_fid;
 	/* if set then create a parent flow */
@@ -113,8 +114,7 @@ ulp_mapper_deinit(struct bnxt_ulp_context *ulp_ctx);
  */
 int32_t
 ulp_mapper_flow_create(struct bnxt_ulp_context	*ulp_ctx,
-		       struct bnxt_ulp_mapper_create_parms *parms,
-		       uint32_t *flowid);
+		       struct bnxt_ulp_mapper_create_parms *parms);
 
 /* Function that frees all resources associated with the flow. */
 int32_t
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
index 41f3df998..bb5a8a477 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
@@ -11,6 +11,7 @@
 #include <rte_flow_driver.h>
 #include "ulp_template_db_enum.h"
 #include "ulp_template_struct.h"
+#include "ulp_mapper.h"
 
 /* defines to be used in the tunnel header parsing */
 #define BNXT_ULP_ENCAP_IPV4_VER_HLEN_TOS	2
@@ -34,6 +35,14 @@
 #define	BNXT_ULP_PARSER_IPV6_TC			0x0ff00000
 #define	BNXT_ULP_PARSER_IPV6_FLOW_LABEL		0x000fffff
 
+void
+bnxt_ulp_init_mapper_params(struct bnxt_ulp_mapper_create_parms *mapper_cparms,
+			    struct ulp_rte_parser_params *params,
+			    uint32_t priority, uint32_t class_id,
+			    uint32_t act_tmpl, uint16_t func_id,
+			    uint32_t flow_id,
+			    enum bnxt_ulp_fdb_type flow_type);
+
 /* Function to handle the parsing of the RTE port id. */
 int32_t
 ulp_rte_parser_implicit_match_port_process(struct ulp_rte_parser_params *param);
-- 
2.21.1 (Apple Git-122.3)


^ permalink raw reply	[flat|nested] 32+ messages in thread

* [dpdk-dev] [PATCH v2 10/11] net/bnxt: add support for VXLAN decap templates
  2020-10-20 21:55 ` [dpdk-dev] [PATCH v2 00/11] bnxt fixes and enhancements to TRUFLOW support Ajit Khaparde
                     ` (8 preceding siblings ...)
  2020-10-20 21:55   ` [dpdk-dev] [PATCH v2 09/11] net/bnxt: refactor flow id allocation Ajit Khaparde
@ 2020-10-20 21:55   ` Ajit Khaparde
  2020-10-20 21:55   ` [dpdk-dev] [PATCH v2 11/11] net/bnxt: add VXLAN decap offload support Ajit Khaparde
  2020-10-21  5:31   ` [dpdk-dev] [PATCH v2 00/11] bnxt fixes and enhancements to TRUFLOW support Ajit Khaparde
  11 siblings, 0 replies; 32+ messages in thread
From: Ajit Khaparde @ 2020-10-20 21:55 UTC (permalink / raw)
  To: dev; +Cc: Venkat Duvvuru, Mike Baucom

From: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>

Templates for outer tunnel & inner tunnel flow are added in this patch.

Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
Reviewed-by: Mike Baucom <michael.baucom@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
 drivers/net/bnxt/tf_ulp/ulp_rte_parser.c      |   10 +
 drivers/net/bnxt/tf_ulp/ulp_rte_parser.h      |    5 +
 .../net/bnxt/tf_ulp/ulp_template_db_class.c   |  962 ++++---
 .../net/bnxt/tf_ulp/ulp_template_db_enum.h    |   35 +-
 .../net/bnxt/tf_ulp/ulp_template_db_field.h   |  363 ++-
 .../tf_ulp/ulp_template_db_stingray_act.c     |  116 +-
 .../tf_ulp/ulp_template_db_stingray_class.c   | 2493 ++++++++++++++---
 drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c |    9 +-
 .../bnxt/tf_ulp/ulp_template_db_wh_plus_act.c |  116 +-
 .../tf_ulp/ulp_template_db_wh_plus_class.c    | 2489 +++++++++++++---
 10 files changed, 5127 insertions(+), 1471 deletions(-)

diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
index 770fec55c..42021ae8d 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
@@ -2110,3 +2110,13 @@ ulp_rte_dec_ttl_act_handler(const struct rte_flow_action *act __rte_unused,
 	ULP_BITMAP_SET(params->act_bitmap.bits, BNXT_ULP_ACTION_BIT_DEC_TTL);
 	return BNXT_TF_RC_SUCCESS;
 }
+
+/* Function to handle the parsing of RTE Flow action JUMP */
+int32_t
+ulp_rte_jump_act_handler(const struct rte_flow_action *action_item __rte_unused,
+			    struct ulp_rte_parser_params *params)
+{
+	/* Update the act_bitmap with dec ttl */
+	ULP_BITMAP_SET(params->act_bitmap.bits, BNXT_ULP_ACTION_BIT_JUMP);
+	return BNXT_TF_RC_SUCCESS;
+}
diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
index bb5a8a477..a71aabe5f 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
@@ -233,4 +233,9 @@ int32_t
 ulp_rte_dec_ttl_act_handler(const struct rte_flow_action *action_item,
 			    struct ulp_rte_parser_params *params);
 
+/* Function to handle the parsing of RTE Flow action JUMP .*/
+int32_t
+ulp_rte_jump_act_handler(const struct rte_flow_action *action_item,
+			 struct ulp_rte_parser_params *params);
+
 #endif /* _ULP_RTE_PARSER_H_ */
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c
index c348abe13..fdb26da3e 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c
@@ -157,58 +157,74 @@ uint16_t ulp_class_sig_tbl[BNXT_ULP_CLASS_SIG_TBL_MAX_SZ] = {
 	[BNXT_ULP_CLASS_HID_05b9] = 146,
 	[BNXT_ULP_CLASS_HID_0371] = 147,
 	[BNXT_ULP_CLASS_HID_00e1] = 148,
-	[BNXT_ULP_CLASS_HID_048b] = 149,
-	[BNXT_ULP_CLASS_HID_0749] = 150,
-	[BNXT_ULP_CLASS_HID_05f1] = 151,
-	[BNXT_ULP_CLASS_HID_04b7] = 152,
-	[BNXT_ULP_CLASS_HID_049b] = 153,
-	[BNXT_ULP_CLASS_HID_0759] = 154,
-	[BNXT_ULP_CLASS_HID_05e1] = 155,
-	[BNXT_ULP_CLASS_HID_04a7] = 156,
-	[BNXT_ULP_CLASS_HID_0301] = 157,
-	[BNXT_ULP_CLASS_HID_07f9] = 158,
-	[BNXT_ULP_CLASS_HID_0397] = 159,
-	[BNXT_ULP_CLASS_HID_068f] = 160,
-	[BNXT_ULP_CLASS_HID_02f1] = 161,
-	[BNXT_ULP_CLASS_HID_0609] = 162,
-	[BNXT_ULP_CLASS_HID_0267] = 163,
-	[BNXT_ULP_CLASS_HID_077f] = 164,
-	[BNXT_ULP_CLASS_HID_01e1] = 165,
-	[BNXT_ULP_CLASS_HID_0329] = 166,
-	[BNXT_ULP_CLASS_HID_01c1] = 167,
-	[BNXT_ULP_CLASS_HID_0309] = 168,
-	[BNXT_ULP_CLASS_HID_01d1] = 169,
-	[BNXT_ULP_CLASS_HID_0319] = 170,
-	[BNXT_ULP_CLASS_HID_01e2] = 171,
-	[BNXT_ULP_CLASS_HID_032a] = 172,
-	[BNXT_ULP_CLASS_HID_0650] = 173,
-	[BNXT_ULP_CLASS_HID_0198] = 174,
-	[BNXT_ULP_CLASS_HID_01c2] = 175,
-	[BNXT_ULP_CLASS_HID_030a] = 176,
-	[BNXT_ULP_CLASS_HID_0670] = 177,
-	[BNXT_ULP_CLASS_HID_01b8] = 178,
-	[BNXT_ULP_CLASS_HID_01d2] = 179,
-	[BNXT_ULP_CLASS_HID_031a] = 180,
-	[BNXT_ULP_CLASS_HID_0660] = 181,
-	[BNXT_ULP_CLASS_HID_01a8] = 182,
-	[BNXT_ULP_CLASS_HID_01dd] = 183,
-	[BNXT_ULP_CLASS_HID_0315] = 184,
-	[BNXT_ULP_CLASS_HID_003d] = 185,
-	[BNXT_ULP_CLASS_HID_02f5] = 186,
-	[BNXT_ULP_CLASS_HID_01cd] = 187,
-	[BNXT_ULP_CLASS_HID_0305] = 188,
-	[BNXT_ULP_CLASS_HID_01de] = 189,
-	[BNXT_ULP_CLASS_HID_0316] = 190,
-	[BNXT_ULP_CLASS_HID_066c] = 191,
-	[BNXT_ULP_CLASS_HID_01a4] = 192,
-	[BNXT_ULP_CLASS_HID_003e] = 193,
-	[BNXT_ULP_CLASS_HID_02f6] = 194,
-	[BNXT_ULP_CLASS_HID_078c] = 195,
-	[BNXT_ULP_CLASS_HID_0044] = 196,
-	[BNXT_ULP_CLASS_HID_01ce] = 197,
-	[BNXT_ULP_CLASS_HID_0306] = 198,
-	[BNXT_ULP_CLASS_HID_067c] = 199,
-	[BNXT_ULP_CLASS_HID_01b4] = 200
+	[BNXT_ULP_CLASS_HID_0000] = 149,
+	[BNXT_ULP_CLASS_HID_00ce] = 150,
+	[BNXT_ULP_CLASS_HID_01b6] = 151,
+	[BNXT_ULP_CLASS_HID_0074] = 152,
+	[BNXT_ULP_CLASS_HID_00fe] = 153,
+	[BNXT_ULP_CLASS_HID_03bc] = 154,
+	[BNXT_ULP_CLASS_HID_0206] = 155,
+	[BNXT_ULP_CLASS_HID_02c4] = 156,
+	[BNXT_ULP_CLASS_HID_055a] = 157,
+	[BNXT_ULP_CLASS_HID_045a] = 158,
+	[BNXT_ULP_CLASS_HID_061a] = 159,
+	[BNXT_ULP_CLASS_HID_051a] = 160,
+	[BNXT_ULP_CLASS_HID_074a] = 161,
+	[BNXT_ULP_CLASS_HID_004e] = 162,
+	[BNXT_ULP_CLASS_HID_040a] = 163,
+	[BNXT_ULP_CLASS_HID_010e] = 164,
+	[BNXT_ULP_CLASS_HID_048b] = 165,
+	[BNXT_ULP_CLASS_HID_0749] = 166,
+	[BNXT_ULP_CLASS_HID_05f1] = 167,
+	[BNXT_ULP_CLASS_HID_04b7] = 168,
+	[BNXT_ULP_CLASS_HID_049b] = 169,
+	[BNXT_ULP_CLASS_HID_0759] = 170,
+	[BNXT_ULP_CLASS_HID_05e1] = 171,
+	[BNXT_ULP_CLASS_HID_04a7] = 172,
+	[BNXT_ULP_CLASS_HID_0301] = 173,
+	[BNXT_ULP_CLASS_HID_07f9] = 174,
+	[BNXT_ULP_CLASS_HID_0397] = 175,
+	[BNXT_ULP_CLASS_HID_068f] = 176,
+	[BNXT_ULP_CLASS_HID_02f1] = 177,
+	[BNXT_ULP_CLASS_HID_0609] = 178,
+	[BNXT_ULP_CLASS_HID_0267] = 179,
+	[BNXT_ULP_CLASS_HID_077f] = 180,
+	[BNXT_ULP_CLASS_HID_01e1] = 181,
+	[BNXT_ULP_CLASS_HID_0329] = 182,
+	[BNXT_ULP_CLASS_HID_01c1] = 183,
+	[BNXT_ULP_CLASS_HID_0309] = 184,
+	[BNXT_ULP_CLASS_HID_01d1] = 185,
+	[BNXT_ULP_CLASS_HID_0319] = 186,
+	[BNXT_ULP_CLASS_HID_01e2] = 187,
+	[BNXT_ULP_CLASS_HID_032a] = 188,
+	[BNXT_ULP_CLASS_HID_0650] = 189,
+	[BNXT_ULP_CLASS_HID_0198] = 190,
+	[BNXT_ULP_CLASS_HID_01c2] = 191,
+	[BNXT_ULP_CLASS_HID_030a] = 192,
+	[BNXT_ULP_CLASS_HID_0670] = 193,
+	[BNXT_ULP_CLASS_HID_01b8] = 194,
+	[BNXT_ULP_CLASS_HID_01d2] = 195,
+	[BNXT_ULP_CLASS_HID_031a] = 196,
+	[BNXT_ULP_CLASS_HID_0660] = 197,
+	[BNXT_ULP_CLASS_HID_01a8] = 198,
+	[BNXT_ULP_CLASS_HID_01dd] = 199,
+	[BNXT_ULP_CLASS_HID_0315] = 200,
+	[BNXT_ULP_CLASS_HID_003d] = 201,
+	[BNXT_ULP_CLASS_HID_02f5] = 202,
+	[BNXT_ULP_CLASS_HID_01cd] = 203,
+	[BNXT_ULP_CLASS_HID_0305] = 204,
+	[BNXT_ULP_CLASS_HID_01de] = 205,
+	[BNXT_ULP_CLASS_HID_0316] = 206,
+	[BNXT_ULP_CLASS_HID_066c] = 207,
+	[BNXT_ULP_CLASS_HID_01a4] = 208,
+	[BNXT_ULP_CLASS_HID_003e] = 209,
+	[BNXT_ULP_CLASS_HID_02f6] = 210,
+	[BNXT_ULP_CLASS_HID_078c] = 211,
+	[BNXT_ULP_CLASS_HID_0044] = 212,
+	[BNXT_ULP_CLASS_HID_01ce] = 213,
+	[BNXT_ULP_CLASS_HID_0306] = 214,
+	[BNXT_ULP_CLASS_HID_067c] = 215,
+	[BNXT_ULP_CLASS_HID_01b4] = 216
 };
 
 struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
@@ -2831,305 +2847,617 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 	.wc_pri = 23
 	},
 	[149] = {
-	.class_hid = BNXT_ULP_CLASS_HID_048b,
+	.class_hid = BNXT_ULP_CLASS_HID_0000,
 	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_F1 |
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
 		BNXT_ULP_HDR_BIT_O_UDP |
-		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
+		BNXT_ULP_HF18_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF18_BITMASK_O_ETH_SMAC |
 		BNXT_ULP_HF18_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF18_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF18_BITMASK_O_IPV4_DST_ADDR |
 		BNXT_ULP_HF18_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF18_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF18_BITMASK_O_IPV4_DST_ADDR |
 		BNXT_ULP_HF18_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	.class_tid = 18,
 	.wc_pri = 0
 	},
 	[150] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0749,
+	.class_hid = BNXT_ULP_CLASS_HID_00ce,
 	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_F1 |
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
 		BNXT_ULP_HDR_BIT_O_UDP |
-		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
+		BNXT_ULP_HF18_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF18_BITMASK_O_ETH_SMAC |
 		BNXT_ULP_HF18_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF18_BITMASK_O_IPV4_SRC_ADDR |
 		BNXT_ULP_HF18_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF18_BITMASK_O_UDP_SRC_PORT |
 		BNXT_ULP_HF18_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	.class_tid = 18,
 	.wc_pri = 1
 	},
 	[151] = {
-	.class_hid = BNXT_ULP_CLASS_HID_05f1,
+	.class_hid = BNXT_ULP_CLASS_HID_01b6,
 	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_F1 |
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
 		BNXT_ULP_HDR_BIT_O_UDP |
-		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF18_BITMASK_O_IPV4_SRC_ADDR |
-		BNXT_ULP_HF18_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF18_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF18_BITMASK_O_ETH_SMAC |
 		BNXT_ULP_HF18_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF18_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF18_BITMASK_O_IPV4_DST_ADDR |
 		BNXT_ULP_HF18_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	.class_tid = 18,
 	.wc_pri = 2
 	},
 	[152] = {
-	.class_hid = BNXT_ULP_CLASS_HID_04b7,
+	.class_hid = BNXT_ULP_CLASS_HID_0074,
 	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_F1 |
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
 		BNXT_ULP_HDR_BIT_O_UDP |
-		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF18_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF18_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF18_BITMASK_O_ETH_SMAC |
 		BNXT_ULP_HF18_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF18_BITMASK_O_UDP_SRC_PORT |
 		BNXT_ULP_HF18_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	.class_tid = 18,
 	.wc_pri = 3
 	},
 	[153] = {
-	.class_hid = BNXT_ULP_CLASS_HID_049b,
+	.class_hid = BNXT_ULP_CLASS_HID_00fe,
 	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_F1 |
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_TCP |
-		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF18_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF18_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF18_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF18_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF18_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	.class_tid = 18,
+	.wc_pri = 4
+	},
+	[154] = {
+	.class_hid = BNXT_ULP_CLASS_HID_03bc,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_F1 |
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF18_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF18_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF18_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF18_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	.class_tid = 18,
+	.wc_pri = 5
+	},
+	[155] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0206,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_F1 |
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF18_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF18_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF18_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF18_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	.class_tid = 18,
+	.wc_pri = 6
+	},
+	[156] = {
+	.class_hid = BNXT_ULP_CLASS_HID_02c4,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_F1 |
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF18_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF18_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF18_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	.class_tid = 18,
+	.wc_pri = 7
+	},
+	[157] = {
+	.class_hid = BNXT_ULP_CLASS_HID_055a,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF19_BITMASK_O_ETH_TYPE |
 		BNXT_ULP_HF19_BITMASK_O_IPV4_SRC_ADDR |
 		BNXT_ULP_HF19_BITMASK_O_IPV4_DST_ADDR |
 		BNXT_ULP_HF19_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF19_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF19_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF19_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF19_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF19_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF19_BITMASK_I_ETH_SMAC |
+		BNXT_ULP_HF19_BITMASK_I_ETH_TYPE |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	.class_tid = 19,
 	.wc_pri = 0
 	},
-	[154] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0759,
+	[158] = {
+	.class_hid = BNXT_ULP_CLASS_HID_045a,
 	.hdr_sig = { .bits =
-		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_TCP |
-		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
-		BNXT_ULP_HF19_BITMASK_O_ETH_TYPE |
 		BNXT_ULP_HF19_BITMASK_O_IPV4_SRC_ADDR |
 		BNXT_ULP_HF19_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF19_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF19_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF19_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF19_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF19_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF19_BITMASK_I_ETH_SMAC |
+		BNXT_ULP_HF19_BITMASK_I_ETH_TYPE |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	.class_tid = 19,
 	.wc_pri = 1
 	},
-	[155] = {
-	.class_hid = BNXT_ULP_CLASS_HID_05e1,
+	[159] = {
+	.class_hid = BNXT_ULP_CLASS_HID_061a,
 	.hdr_sig = { .bits =
-		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_TCP |
-		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
 		BNXT_ULP_HF19_BITMASK_O_IPV4_SRC_ADDR |
 		BNXT_ULP_HF19_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF19_BITMASK_O_IPV4_PROTO_ID |
-		BNXT_ULP_HF19_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF19_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF19_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF19_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF19_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF19_BITMASK_I_ETH_SMAC |
+		BNXT_ULP_HF19_BITMASK_I_ETH_TYPE |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	.class_tid = 19,
 	.wc_pri = 2
 	},
-	[156] = {
-	.class_hid = BNXT_ULP_CLASS_HID_04a7,
+	[160] = {
+	.class_hid = BNXT_ULP_CLASS_HID_051a,
 	.hdr_sig = { .bits =
-		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
-		BNXT_ULP_HDR_BIT_O_TCP |
-		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
 	.field_sig = { .bits =
 		BNXT_ULP_HF19_BITMASK_O_IPV4_SRC_ADDR |
 		BNXT_ULP_HF19_BITMASK_O_IPV4_DST_ADDR |
-		BNXT_ULP_HF19_BITMASK_O_TCP_SRC_PORT |
-		BNXT_ULP_HF19_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_HF19_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF19_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF19_BITMASK_I_ETH_SMAC |
+		BNXT_ULP_HF19_BITMASK_I_ETH_TYPE |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	.class_tid = 19,
 	.wc_pri = 3
 	},
-	[157] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0301,
+	[161] = {
+	.class_hid = BNXT_ULP_CLASS_HID_074a,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF19_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF19_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF19_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF19_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF19_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF19_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF19_BITMASK_I_ETH_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	.class_tid = 19,
+	.wc_pri = 4
+	},
+	[162] = {
+	.class_hid = BNXT_ULP_CLASS_HID_004e,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF19_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF19_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF19_BITMASK_O_IPV4_PROTO_ID |
+		BNXT_ULP_HF19_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF19_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF19_BITMASK_I_ETH_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	.class_tid = 19,
+	.wc_pri = 5
+	},
+	[163] = {
+	.class_hid = BNXT_ULP_CLASS_HID_040a,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF19_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF19_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF19_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_HF19_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF19_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF19_BITMASK_I_ETH_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	.class_tid = 19,
+	.wc_pri = 6
+	},
+	[164] = {
+	.class_hid = BNXT_ULP_CLASS_HID_010e,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_HDR_BIT_T_VXLAN |
+		BNXT_ULP_HDR_BIT_I_ETH |
+		BNXT_ULP_HDR_BIT_I_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_ING },
+	.field_sig = { .bits =
+		BNXT_ULP_HF19_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF19_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF19_BITMASK_T_VXLAN_VNI |
+		BNXT_ULP_HF19_BITMASK_I_ETH_DMAC |
+		BNXT_ULP_HF19_BITMASK_I_ETH_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	.class_tid = 19,
+	.wc_pri = 7
+	},
+	[165] = {
+	.class_hid = BNXT_ULP_CLASS_HID_048b,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
 		BNXT_ULP_HF20_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF20_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF20_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF20_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF20_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF20_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF20_BITMASK_O_IPV4_PROTO_ID |
 		BNXT_ULP_HF20_BITMASK_O_UDP_SRC_PORT |
 		BNXT_ULP_HF20_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	.class_tid = 20,
 	.wc_pri = 0
 	},
-	[158] = {
-	.class_hid = BNXT_ULP_CLASS_HID_07f9,
+	[166] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0749,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
 		BNXT_ULP_HF20_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF20_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF20_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF20_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF20_BITMASK_O_IPV4_DST_ADDR |
 		BNXT_ULP_HF20_BITMASK_O_UDP_SRC_PORT |
 		BNXT_ULP_HF20_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	.class_tid = 20,
 	.wc_pri = 1
 	},
-	[159] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0397,
+	[167] = {
+	.class_hid = BNXT_ULP_CLASS_HID_05f1,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF20_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF20_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF20_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF20_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF20_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF20_BITMASK_O_IPV4_PROTO_ID |
 		BNXT_ULP_HF20_BITMASK_O_UDP_SRC_PORT |
 		BNXT_ULP_HF20_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	.class_tid = 20,
 	.wc_pri = 2
 	},
-	[160] = {
-	.class_hid = BNXT_ULP_CLASS_HID_068f,
+	[168] = {
+	.class_hid = BNXT_ULP_CLASS_HID_04b7,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF20_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF20_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF20_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF20_BITMASK_O_IPV4_DST_ADDR |
 		BNXT_ULP_HF20_BITMASK_O_UDP_SRC_PORT |
 		BNXT_ULP_HF20_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	.class_tid = 20,
 	.wc_pri = 3
 	},
-	[161] = {
-	.class_hid = BNXT_ULP_CLASS_HID_02f1,
+	[169] = {
+	.class_hid = BNXT_ULP_CLASS_HID_049b,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
 		BNXT_ULP_HF21_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF21_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF21_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF21_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF21_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF21_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF21_BITMASK_O_IPV4_PROTO_ID |
 		BNXT_ULP_HF21_BITMASK_O_TCP_SRC_PORT |
 		BNXT_ULP_HF21_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	.class_tid = 21,
 	.wc_pri = 0
 	},
-	[162] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0609,
+	[170] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0759,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
 		BNXT_ULP_HF21_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF21_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF21_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF21_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF21_BITMASK_O_IPV4_DST_ADDR |
 		BNXT_ULP_HF21_BITMASK_O_TCP_SRC_PORT |
 		BNXT_ULP_HF21_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	.class_tid = 21,
 	.wc_pri = 1
 	},
-	[163] = {
-	.class_hid = BNXT_ULP_CLASS_HID_0267,
+	[171] = {
+	.class_hid = BNXT_ULP_CLASS_HID_05e1,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF21_BITMASK_O_IPV6_DST_ADDR |
-		BNXT_ULP_HF21_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF21_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF21_BITMASK_O_IPV4_DST_ADDR |
+		BNXT_ULP_HF21_BITMASK_O_IPV4_PROTO_ID |
 		BNXT_ULP_HF21_BITMASK_O_TCP_SRC_PORT |
 		BNXT_ULP_HF21_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	.class_tid = 21,
 	.wc_pri = 2
 	},
-	[164] = {
-	.class_hid = BNXT_ULP_CLASS_HID_077f,
+	[172] = {
+	.class_hid = BNXT_ULP_CLASS_HID_04a7,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF21_BITMASK_O_IPV6_SRC_ADDR |
-		BNXT_ULP_HF21_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF21_BITMASK_O_IPV4_SRC_ADDR |
+		BNXT_ULP_HF21_BITMASK_O_IPV4_DST_ADDR |
 		BNXT_ULP_HF21_BITMASK_O_TCP_SRC_PORT |
 		BNXT_ULP_HF21_BITMASK_O_TCP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	.class_tid = 21,
 	.wc_pri = 3
 	},
-	[165] = {
-	.class_hid = BNXT_ULP_CLASS_HID_01e1,
+	[173] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0301,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
-		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF22_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF22_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_HF22_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF22_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF22_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF22_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF22_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF22_BITMASK_O_UDP_DST_PORT |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
 	.class_tid = 22,
 	.wc_pri = 0
 	},
-	[166] = {
+	[174] = {
+	.class_hid = BNXT_ULP_CLASS_HID_07f9,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF22_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF22_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF22_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF22_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF22_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	.class_tid = 22,
+	.wc_pri = 1
+	},
+	[175] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0397,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF22_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF22_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF22_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF22_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF22_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	.class_tid = 22,
+	.wc_pri = 2
+	},
+	[176] = {
+	.class_hid = BNXT_ULP_CLASS_HID_068f,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_UDP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF22_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF22_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF22_BITMASK_O_UDP_SRC_PORT |
+		BNXT_ULP_HF22_BITMASK_O_UDP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	.class_tid = 22,
+	.wc_pri = 3
+	},
+	[177] = {
+	.class_hid = BNXT_ULP_CLASS_HID_02f1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF23_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF23_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF23_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF23_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF23_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF23_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	.class_tid = 23,
+	.wc_pri = 0
+	},
+	[178] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0609,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF23_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF23_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF23_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF23_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF23_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	.class_tid = 23,
+	.wc_pri = 1
+	},
+	[179] = {
+	.class_hid = BNXT_ULP_CLASS_HID_0267,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF23_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF23_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF23_BITMASK_O_IPV6_PROTO_ID |
+		BNXT_ULP_HF23_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF23_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	.class_tid = 23,
+	.wc_pri = 2
+	},
+	[180] = {
+	.class_hid = BNXT_ULP_CLASS_HID_077f,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV6 |
+		BNXT_ULP_HDR_BIT_O_TCP |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF23_BITMASK_O_IPV6_SRC_ADDR |
+		BNXT_ULP_HF23_BITMASK_O_IPV6_DST_ADDR |
+		BNXT_ULP_HF23_BITMASK_O_TCP_SRC_PORT |
+		BNXT_ULP_HF23_BITMASK_O_TCP_DST_PORT |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	.class_tid = 23,
+	.wc_pri = 3
+	},
+	[181] = {
+	.class_hid = BNXT_ULP_CLASS_HID_01e1,
+	.hdr_sig = { .bits =
+		BNXT_ULP_HDR_BIT_O_ETH |
+		BNXT_ULP_HDR_BIT_O_IPV4 |
+		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+	.field_sig = { .bits =
+		BNXT_ULP_HF24_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF24_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF24_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
+	.class_tid = 24,
+	.wc_pri = 0
+	},
+	[182] = {
 	.class_hid = BNXT_ULP_CLASS_HID_0329,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_O_IPV4 |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF22_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF22_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF24_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF24_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 22,
+	.class_tid = 24,
 	.wc_pri = 1
 	},
-	[167] = {
+	[183] = {
 	.class_hid = BNXT_ULP_CLASS_HID_01c1,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3137,14 +3465,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF22_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF22_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF22_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF24_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF24_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF24_BITMASK_O_ETH_TYPE |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 22,
+	.class_tid = 24,
 	.wc_pri = 2
 	},
-	[168] = {
+	[184] = {
 	.class_hid = BNXT_ULP_CLASS_HID_0309,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3152,13 +3480,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF22_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF22_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF24_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF24_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 22,
+	.class_tid = 24,
 	.wc_pri = 3
 	},
-	[169] = {
+	[185] = {
 	.class_hid = BNXT_ULP_CLASS_HID_01d1,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3166,14 +3494,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF22_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF22_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF22_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF24_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF24_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF24_BITMASK_O_ETH_TYPE |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 22,
+	.class_tid = 24,
 	.wc_pri = 4
 	},
-	[170] = {
+	[186] = {
 	.class_hid = BNXT_ULP_CLASS_HID_0319,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3181,13 +3509,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF22_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF22_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF24_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF24_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 22,
+	.class_tid = 24,
 	.wc_pri = 5
 	},
-	[171] = {
+	[187] = {
 	.class_hid = BNXT_ULP_CLASS_HID_01e2,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3195,14 +3523,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_IPV4 |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF22_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF22_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF22_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF24_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF24_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF24_BITMASK_O_ETH_TYPE |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 22,
+	.class_tid = 24,
 	.wc_pri = 6
 	},
-	[172] = {
+	[188] = {
 	.class_hid = BNXT_ULP_CLASS_HID_032a,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3210,13 +3538,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_IPV4 |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF22_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF22_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF24_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF24_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 22,
+	.class_tid = 24,
 	.wc_pri = 7
 	},
-	[173] = {
+	[189] = {
 	.class_hid = BNXT_ULP_CLASS_HID_0650,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3224,15 +3552,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_IPV4 |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF22_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF22_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF22_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF22_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF24_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF24_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF24_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF24_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 22,
+	.class_tid = 24,
 	.wc_pri = 8
 	},
-	[174] = {
+	[190] = {
 	.class_hid = BNXT_ULP_CLASS_HID_0198,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3240,14 +3568,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_IPV4 |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF22_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF22_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF22_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF24_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF24_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF24_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 22,
+	.class_tid = 24,
 	.wc_pri = 9
 	},
-	[175] = {
+	[191] = {
 	.class_hid = BNXT_ULP_CLASS_HID_01c2,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3256,14 +3584,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF22_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF22_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF22_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF24_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF24_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF24_BITMASK_O_ETH_TYPE |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 22,
+	.class_tid = 24,
 	.wc_pri = 10
 	},
-	[176] = {
+	[192] = {
 	.class_hid = BNXT_ULP_CLASS_HID_030a,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3272,13 +3600,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF22_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF22_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF24_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF24_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 22,
+	.class_tid = 24,
 	.wc_pri = 11
 	},
-	[177] = {
+	[193] = {
 	.class_hid = BNXT_ULP_CLASS_HID_0670,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3287,15 +3615,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF22_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF22_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF22_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF22_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF24_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF24_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF24_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF24_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 22,
+	.class_tid = 24,
 	.wc_pri = 12
 	},
-	[178] = {
+	[194] = {
 	.class_hid = BNXT_ULP_CLASS_HID_01b8,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3304,14 +3632,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF22_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF22_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF22_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF24_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF24_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF24_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 22,
+	.class_tid = 24,
 	.wc_pri = 13
 	},
-	[179] = {
+	[195] = {
 	.class_hid = BNXT_ULP_CLASS_HID_01d2,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3320,14 +3648,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF22_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF22_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF22_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF24_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF24_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF24_BITMASK_O_ETH_TYPE |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 22,
+	.class_tid = 24,
 	.wc_pri = 14
 	},
-	[180] = {
+	[196] = {
 	.class_hid = BNXT_ULP_CLASS_HID_031a,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3336,13 +3664,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF22_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF22_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF24_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF24_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 22,
+	.class_tid = 24,
 	.wc_pri = 15
 	},
-	[181] = {
+	[197] = {
 	.class_hid = BNXT_ULP_CLASS_HID_0660,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3351,15 +3679,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF22_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF22_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF22_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF22_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF24_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF24_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF24_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF24_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 22,
+	.class_tid = 24,
 	.wc_pri = 16
 	},
-	[182] = {
+	[198] = {
 	.class_hid = BNXT_ULP_CLASS_HID_01a8,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3368,41 +3696,41 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF22_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF22_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF22_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF24_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF24_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF24_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 22,
+	.class_tid = 24,
 	.wc_pri = 17
 	},
-	[183] = {
+	[199] = {
 	.class_hid = BNXT_ULP_CLASS_HID_01dd,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF23_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF23_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF23_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF25_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF25_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF25_BITMASK_O_ETH_TYPE |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 23,
+	.class_tid = 25,
 	.wc_pri = 0
 	},
-	[184] = {
+	[200] = {
 	.class_hid = BNXT_ULP_CLASS_HID_0315,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
 		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF23_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF23_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF25_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF25_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 23,
+	.class_tid = 25,
 	.wc_pri = 1
 	},
-	[185] = {
+	[201] = {
 	.class_hid = BNXT_ULP_CLASS_HID_003d,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3410,14 +3738,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF23_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF23_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF23_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF25_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF25_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF25_BITMASK_O_ETH_TYPE |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 23,
+	.class_tid = 25,
 	.wc_pri = 2
 	},
-	[186] = {
+	[202] = {
 	.class_hid = BNXT_ULP_CLASS_HID_02f5,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3425,13 +3753,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF23_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF23_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF25_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF25_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 23,
+	.class_tid = 25,
 	.wc_pri = 3
 	},
-	[187] = {
+	[203] = {
 	.class_hid = BNXT_ULP_CLASS_HID_01cd,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3439,14 +3767,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF23_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF23_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF23_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF25_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF25_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF25_BITMASK_O_ETH_TYPE |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 23,
+	.class_tid = 25,
 	.wc_pri = 4
 	},
-	[188] = {
+	[204] = {
 	.class_hid = BNXT_ULP_CLASS_HID_0305,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3454,13 +3782,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF23_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF23_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF25_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF25_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 23,
+	.class_tid = 25,
 	.wc_pri = 5
 	},
-	[189] = {
+	[205] = {
 	.class_hid = BNXT_ULP_CLASS_HID_01de,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3468,14 +3796,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF23_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF23_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF23_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF25_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF25_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF25_BITMASK_O_ETH_TYPE |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 23,
+	.class_tid = 25,
 	.wc_pri = 6
 	},
-	[190] = {
+	[206] = {
 	.class_hid = BNXT_ULP_CLASS_HID_0316,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3483,13 +3811,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF23_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF23_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF25_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF25_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 23,
+	.class_tid = 25,
 	.wc_pri = 7
 	},
-	[191] = {
+	[207] = {
 	.class_hid = BNXT_ULP_CLASS_HID_066c,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3497,15 +3825,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF23_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF23_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF23_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF23_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF25_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF25_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF25_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF25_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 23,
+	.class_tid = 25,
 	.wc_pri = 8
 	},
-	[192] = {
+	[208] = {
 	.class_hid = BNXT_ULP_CLASS_HID_01a4,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3513,14 +3841,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_IPV6 |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF23_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF23_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF23_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF25_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF25_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF25_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 23,
+	.class_tid = 25,
 	.wc_pri = 9
 	},
-	[193] = {
+	[209] = {
 	.class_hid = BNXT_ULP_CLASS_HID_003e,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3529,14 +3857,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF23_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF23_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF23_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF25_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF25_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF25_BITMASK_O_ETH_TYPE |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 23,
+	.class_tid = 25,
 	.wc_pri = 10
 	},
-	[194] = {
+	[210] = {
 	.class_hid = BNXT_ULP_CLASS_HID_02f6,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3545,13 +3873,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF23_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF23_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF25_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF25_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 23,
+	.class_tid = 25,
 	.wc_pri = 11
 	},
-	[195] = {
+	[211] = {
 	.class_hid = BNXT_ULP_CLASS_HID_078c,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3560,15 +3888,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF23_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF23_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF23_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF23_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF25_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF25_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF25_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF25_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 23,
+	.class_tid = 25,
 	.wc_pri = 12
 	},
-	[196] = {
+	[212] = {
 	.class_hid = BNXT_ULP_CLASS_HID_0044,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3577,14 +3905,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_UDP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF23_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF23_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF23_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF25_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF25_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF25_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 23,
+	.class_tid = 25,
 	.wc_pri = 13
 	},
-	[197] = {
+	[213] = {
 	.class_hid = BNXT_ULP_CLASS_HID_01ce,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3593,14 +3921,14 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF23_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF23_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF23_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF25_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF25_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF25_BITMASK_O_ETH_TYPE |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 23,
+	.class_tid = 25,
 	.wc_pri = 14
 	},
-	[198] = {
+	[214] = {
 	.class_hid = BNXT_ULP_CLASS_HID_0306,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3609,13 +3937,13 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF23_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF23_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF25_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF25_BITMASK_O_ETH_DMAC |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 23,
+	.class_tid = 25,
 	.wc_pri = 15
 	},
-	[199] = {
+	[215] = {
 	.class_hid = BNXT_ULP_CLASS_HID_067c,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3624,15 +3952,15 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF23_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF23_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF23_BITMASK_O_ETH_TYPE |
-		BNXT_ULP_HF23_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF25_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF25_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF25_BITMASK_O_ETH_TYPE |
+		BNXT_ULP_HF25_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 23,
+	.class_tid = 25,
 	.wc_pri = 16
 	},
-	[200] = {
+	[216] = {
 	.class_hid = BNXT_ULP_CLASS_HID_01b4,
 	.hdr_sig = { .bits =
 		BNXT_ULP_HDR_BIT_O_ETH |
@@ -3641,11 +3969,11 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
 		BNXT_ULP_HDR_BIT_O_TCP |
 		BNXT_ULP_FLOW_DIR_BITMASK_EGR },
 	.field_sig = { .bits =
-		BNXT_ULP_HF23_BITMASK_O_ETH_SMAC |
-		BNXT_ULP_HF23_BITMASK_O_ETH_DMAC |
-		BNXT_ULP_HF23_BITMASK_OO_VLAN_VID |
+		BNXT_ULP_HF25_BITMASK_O_ETH_SMAC |
+		BNXT_ULP_HF25_BITMASK_O_ETH_DMAC |
+		BNXT_ULP_HF25_BITMASK_OO_VLAN_VID |
 		BNXT_ULP_MATCH_TYPE_BITMASK_EM },
-	.class_tid = 23,
+	.class_tid = 25,
 	.wc_pri = 17
 	}
 };
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
index 6dade9afd..10838f5cc 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
@@ -11,7 +11,7 @@
 #define BNXT_ULP_LOG2_MAX_NUM_DEV 2
 #define BNXT_ULP_CACHE_TBL_MAX_SZ 4
 #define BNXT_ULP_CLASS_SIG_TBL_MAX_SZ 2048
-#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 201
+#define BNXT_ULP_CLASS_MATCH_LIST_MAX_SZ 217
 #define BNXT_ULP_CLASS_HID_LOW_PRIME 7919
 #define BNXT_ULP_CLASS_HID_HIGH_PRIME 7907
 #define BNXT_ULP_CLASS_HID_SHFTR 32
@@ -52,7 +52,8 @@ enum bnxt_ulp_action_bit {
 	BNXT_ULP_ACTION_BIT_SET_TP_SRC       = 0x0000000000100000,
 	BNXT_ULP_ACTION_BIT_SET_TP_DST       = 0x0000000000200000,
 	BNXT_ULP_ACTION_BIT_VXLAN_ENCAP      = 0x0000000000400000,
-	BNXT_ULP_ACTION_BIT_LAST             = 0x0000000000800000
+	BNXT_ULP_ACTION_BIT_JUMP             = 0x0000000000800000,
+	BNXT_ULP_ACTION_BIT_LAST             = 0x0000000001000000
 };
 
 enum bnxt_ulp_hdr_bit {
@@ -72,7 +73,8 @@ enum bnxt_ulp_hdr_bit {
 	BNXT_ULP_HDR_BIT_I_IPV6              = 0x0000000000002000,
 	BNXT_ULP_HDR_BIT_I_TCP               = 0x0000000000004000,
 	BNXT_ULP_HDR_BIT_I_UDP               = 0x0000000000008000,
-	BNXT_ULP_HDR_BIT_LAST                = 0x0000000000010000
+	BNXT_ULP_HDR_BIT_F1                  = 0x0000000000010000,
+	BNXT_ULP_HDR_BIT_LAST                = 0x0000000000020000
 };
 
 enum bnxt_ulp_act_type {
@@ -341,6 +343,10 @@ enum bnxt_ulp_resource_sub_type {
 enum bnxt_ulp_sym {
 	BNXT_ULP_SYM_PKT_TYPE_IGNORE = 0,
 	BNXT_ULP_SYM_PKT_TYPE_L2 = 0,
+	BNXT_ULP_SYM_PKT_TYPE_0_IGNORE = 0,
+	BNXT_ULP_SYM_PKT_TYPE_0_L2 = 0,
+	BNXT_ULP_SYM_PKT_TYPE_1_IGNORE = 0,
+	BNXT_ULP_SYM_PKT_TYPE_1_L2 = 0,
 	BNXT_ULP_SYM_RECYCLE_CNT_IGNORE = 0,
 	BNXT_ULP_SYM_RECYCLE_CNT_ZERO = 0,
 	BNXT_ULP_SYM_RECYCLE_CNT_ONE = 1,
@@ -551,7 +557,8 @@ enum bnxt_ulp_sym {
 	BNXT_ULP_SYM_IP_PROTO_UDP = 17,
 	BNXT_ULP_SYM_VF_FUNC_PARIF = 15,
 	BNXT_ULP_SYM_NO = 0,
-	BNXT_ULP_SYM_YES = 1
+	BNXT_ULP_SYM_YES = 1,
+	BNXT_ULP_SYM_RECYCLE_DST = 0x800
 };
 
 enum bnxt_ulp_wh_plus {
@@ -600,6 +607,7 @@ enum bnxt_ulp_act_prop_sz {
 	BNXT_ULP_ACT_PROP_SZ_ENCAP_IP_SRC = 16,
 	BNXT_ULP_ACT_PROP_SZ_ENCAP_UDP = 4,
 	BNXT_ULP_ACT_PROP_SZ_ENCAP_TUN = 32,
+	BNXT_ULP_ACT_PROP_SZ_JUMP = 4,
 	BNXT_ULP_ACT_PROP_SZ_LAST = 4
 };
 
@@ -644,7 +652,8 @@ enum bnxt_ulp_act_prop_idx {
 	BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC = 205,
 	BNXT_ULP_ACT_PROP_IDX_ENCAP_UDP = 221,
 	BNXT_ULP_ACT_PROP_IDX_ENCAP_TUN = 225,
-	BNXT_ULP_ACT_PROP_IDX_LAST = 257
+	BNXT_ULP_ACT_PROP_IDX_JUMP = 257,
+	BNXT_ULP_ACT_PROP_IDX_LAST = 261
 };
 
 enum bnxt_ulp_class_hid {
@@ -796,6 +805,22 @@ enum bnxt_ulp_class_hid {
 	BNXT_ULP_CLASS_HID_05b9 = 0x05b9,
 	BNXT_ULP_CLASS_HID_0371 = 0x0371,
 	BNXT_ULP_CLASS_HID_00e1 = 0x00e1,
+	BNXT_ULP_CLASS_HID_0000 = 0x0000,
+	BNXT_ULP_CLASS_HID_00ce = 0x00ce,
+	BNXT_ULP_CLASS_HID_01b6 = 0x01b6,
+	BNXT_ULP_CLASS_HID_0074 = 0x0074,
+	BNXT_ULP_CLASS_HID_00fe = 0x00fe,
+	BNXT_ULP_CLASS_HID_03bc = 0x03bc,
+	BNXT_ULP_CLASS_HID_0206 = 0x0206,
+	BNXT_ULP_CLASS_HID_02c4 = 0x02c4,
+	BNXT_ULP_CLASS_HID_055a = 0x055a,
+	BNXT_ULP_CLASS_HID_045a = 0x045a,
+	BNXT_ULP_CLASS_HID_061a = 0x061a,
+	BNXT_ULP_CLASS_HID_051a = 0x051a,
+	BNXT_ULP_CLASS_HID_074a = 0x074a,
+	BNXT_ULP_CLASS_HID_004e = 0x004e,
+	BNXT_ULP_CLASS_HID_040a = 0x040a,
+	BNXT_ULP_CLASS_HID_010e = 0x010e,
 	BNXT_ULP_CLASS_HID_048b = 0x048b,
 	BNXT_ULP_CLASS_HID_0749 = 0x0749,
 	BNXT_ULP_CLASS_HID_05f1 = 0x05f1,
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h
index 137b7fd13..516f471c0 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h
@@ -382,7 +382,11 @@ enum bnxt_ulp_hf18 {
 	BNXT_ULP_HF18_IDX_O_UDP_SRC_PORT         = 20,
 	BNXT_ULP_HF18_IDX_O_UDP_DST_PORT         = 21,
 	BNXT_ULP_HF18_IDX_O_UDP_LENGTH           = 22,
-	BNXT_ULP_HF18_IDX_O_UDP_CSUM             = 23
+	BNXT_ULP_HF18_IDX_O_UDP_CSUM             = 23,
+	BNXT_ULP_HF18_IDX_T_VXLAN_FLAGS          = 24,
+	BNXT_ULP_HF18_IDX_T_VXLAN_RSVD0          = 25,
+	BNXT_ULP_HF18_IDX_T_VXLAN_VNI            = 26,
+	BNXT_ULP_HF18_IDX_T_VXLAN_RSVD1          = 27
 };
 
 enum bnxt_ulp_hf19 {
@@ -406,15 +410,33 @@ enum bnxt_ulp_hf19 {
 	BNXT_ULP_HF19_IDX_O_IPV4_CSUM            = 17,
 	BNXT_ULP_HF19_IDX_O_IPV4_SRC_ADDR        = 18,
 	BNXT_ULP_HF19_IDX_O_IPV4_DST_ADDR        = 19,
-	BNXT_ULP_HF19_IDX_O_TCP_SRC_PORT         = 20,
-	BNXT_ULP_HF19_IDX_O_TCP_DST_PORT         = 21,
-	BNXT_ULP_HF19_IDX_O_TCP_SENT_SEQ         = 22,
-	BNXT_ULP_HF19_IDX_O_TCP_RECV_ACK         = 23,
-	BNXT_ULP_HF19_IDX_O_TCP_DATA_OFF         = 24,
-	BNXT_ULP_HF19_IDX_O_TCP_TCP_FLAGS        = 25,
-	BNXT_ULP_HF19_IDX_O_TCP_RX_WIN           = 26,
-	BNXT_ULP_HF19_IDX_O_TCP_CSUM             = 27,
-	BNXT_ULP_HF19_IDX_O_TCP_URP              = 28
+	BNXT_ULP_HF19_IDX_O_UDP_SRC_PORT         = 20,
+	BNXT_ULP_HF19_IDX_O_UDP_DST_PORT         = 21,
+	BNXT_ULP_HF19_IDX_O_UDP_LENGTH           = 22,
+	BNXT_ULP_HF19_IDX_O_UDP_CSUM             = 23,
+	BNXT_ULP_HF19_IDX_T_VXLAN_FLAGS          = 24,
+	BNXT_ULP_HF19_IDX_T_VXLAN_RSVD0          = 25,
+	BNXT_ULP_HF19_IDX_T_VXLAN_VNI            = 26,
+	BNXT_ULP_HF19_IDX_T_VXLAN_RSVD1          = 27,
+	BNXT_ULP_HF19_IDX_I_ETH_DMAC             = 28,
+	BNXT_ULP_HF19_IDX_I_ETH_SMAC             = 29,
+	BNXT_ULP_HF19_IDX_I_ETH_TYPE             = 30,
+	BNXT_ULP_HF19_IDX_IO_VLAN_CFI_PRI        = 31,
+	BNXT_ULP_HF19_IDX_IO_VLAN_VID            = 32,
+	BNXT_ULP_HF19_IDX_IO_VLAN_TYPE           = 33,
+	BNXT_ULP_HF19_IDX_II_VLAN_CFI_PRI        = 34,
+	BNXT_ULP_HF19_IDX_II_VLAN_VID            = 35,
+	BNXT_ULP_HF19_IDX_II_VLAN_TYPE           = 36,
+	BNXT_ULP_HF19_IDX_I_IPV4_VER             = 37,
+	BNXT_ULP_HF19_IDX_I_IPV4_TOS             = 38,
+	BNXT_ULP_HF19_IDX_I_IPV4_LEN             = 39,
+	BNXT_ULP_HF19_IDX_I_IPV4_FRAG_ID         = 40,
+	BNXT_ULP_HF19_IDX_I_IPV4_FRAG_OFF        = 41,
+	BNXT_ULP_HF19_IDX_I_IPV4_TTL             = 42,
+	BNXT_ULP_HF19_IDX_I_IPV4_PROTO_ID        = 43,
+	BNXT_ULP_HF19_IDX_I_IPV4_CSUM            = 44,
+	BNXT_ULP_HF19_IDX_I_IPV4_SRC_ADDR        = 45,
+	BNXT_ULP_HF19_IDX_I_IPV4_DST_ADDR        = 46
 };
 
 enum bnxt_ulp_hf20 {
@@ -428,18 +450,20 @@ enum bnxt_ulp_hf20 {
 	BNXT_ULP_HF20_IDX_OI_VLAN_CFI_PRI        = 7,
 	BNXT_ULP_HF20_IDX_OI_VLAN_VID            = 8,
 	BNXT_ULP_HF20_IDX_OI_VLAN_TYPE           = 9,
-	BNXT_ULP_HF20_IDX_O_IPV6_VER             = 10,
-	BNXT_ULP_HF20_IDX_O_IPV6_TC              = 11,
-	BNXT_ULP_HF20_IDX_O_IPV6_FLOW_LABEL      = 12,
-	BNXT_ULP_HF20_IDX_O_IPV6_PAYLOAD_LEN     = 13,
-	BNXT_ULP_HF20_IDX_O_IPV6_PROTO_ID        = 14,
-	BNXT_ULP_HF20_IDX_O_IPV6_TTL             = 15,
-	BNXT_ULP_HF20_IDX_O_IPV6_SRC_ADDR        = 16,
-	BNXT_ULP_HF20_IDX_O_IPV6_DST_ADDR        = 17,
-	BNXT_ULP_HF20_IDX_O_UDP_SRC_PORT         = 18,
-	BNXT_ULP_HF20_IDX_O_UDP_DST_PORT         = 19,
-	BNXT_ULP_HF20_IDX_O_UDP_LENGTH           = 20,
-	BNXT_ULP_HF20_IDX_O_UDP_CSUM             = 21
+	BNXT_ULP_HF20_IDX_O_IPV4_VER             = 10,
+	BNXT_ULP_HF20_IDX_O_IPV4_TOS             = 11,
+	BNXT_ULP_HF20_IDX_O_IPV4_LEN             = 12,
+	BNXT_ULP_HF20_IDX_O_IPV4_FRAG_ID         = 13,
+	BNXT_ULP_HF20_IDX_O_IPV4_FRAG_OFF        = 14,
+	BNXT_ULP_HF20_IDX_O_IPV4_TTL             = 15,
+	BNXT_ULP_HF20_IDX_O_IPV4_PROTO_ID        = 16,
+	BNXT_ULP_HF20_IDX_O_IPV4_CSUM            = 17,
+	BNXT_ULP_HF20_IDX_O_IPV4_SRC_ADDR        = 18,
+	BNXT_ULP_HF20_IDX_O_IPV4_DST_ADDR        = 19,
+	BNXT_ULP_HF20_IDX_O_UDP_SRC_PORT         = 20,
+	BNXT_ULP_HF20_IDX_O_UDP_DST_PORT         = 21,
+	BNXT_ULP_HF20_IDX_O_UDP_LENGTH           = 22,
+	BNXT_ULP_HF20_IDX_O_UDP_CSUM             = 23
 };
 
 enum bnxt_ulp_hf21 {
@@ -453,23 +477,25 @@ enum bnxt_ulp_hf21 {
 	BNXT_ULP_HF21_IDX_OI_VLAN_CFI_PRI        = 7,
 	BNXT_ULP_HF21_IDX_OI_VLAN_VID            = 8,
 	BNXT_ULP_HF21_IDX_OI_VLAN_TYPE           = 9,
-	BNXT_ULP_HF21_IDX_O_IPV6_VER             = 10,
-	BNXT_ULP_HF21_IDX_O_IPV6_TC              = 11,
-	BNXT_ULP_HF21_IDX_O_IPV6_FLOW_LABEL      = 12,
-	BNXT_ULP_HF21_IDX_O_IPV6_PAYLOAD_LEN     = 13,
-	BNXT_ULP_HF21_IDX_O_IPV6_PROTO_ID        = 14,
-	BNXT_ULP_HF21_IDX_O_IPV6_TTL             = 15,
-	BNXT_ULP_HF21_IDX_O_IPV6_SRC_ADDR        = 16,
-	BNXT_ULP_HF21_IDX_O_IPV6_DST_ADDR        = 17,
-	BNXT_ULP_HF21_IDX_O_TCP_SRC_PORT         = 18,
-	BNXT_ULP_HF21_IDX_O_TCP_DST_PORT         = 19,
-	BNXT_ULP_HF21_IDX_O_TCP_SENT_SEQ         = 20,
-	BNXT_ULP_HF21_IDX_O_TCP_RECV_ACK         = 21,
-	BNXT_ULP_HF21_IDX_O_TCP_DATA_OFF         = 22,
-	BNXT_ULP_HF21_IDX_O_TCP_TCP_FLAGS        = 23,
-	BNXT_ULP_HF21_IDX_O_TCP_RX_WIN           = 24,
-	BNXT_ULP_HF21_IDX_O_TCP_CSUM             = 25,
-	BNXT_ULP_HF21_IDX_O_TCP_URP              = 26
+	BNXT_ULP_HF21_IDX_O_IPV4_VER             = 10,
+	BNXT_ULP_HF21_IDX_O_IPV4_TOS             = 11,
+	BNXT_ULP_HF21_IDX_O_IPV4_LEN             = 12,
+	BNXT_ULP_HF21_IDX_O_IPV4_FRAG_ID         = 13,
+	BNXT_ULP_HF21_IDX_O_IPV4_FRAG_OFF        = 14,
+	BNXT_ULP_HF21_IDX_O_IPV4_TTL             = 15,
+	BNXT_ULP_HF21_IDX_O_IPV4_PROTO_ID        = 16,
+	BNXT_ULP_HF21_IDX_O_IPV4_CSUM            = 17,
+	BNXT_ULP_HF21_IDX_O_IPV4_SRC_ADDR        = 18,
+	BNXT_ULP_HF21_IDX_O_IPV4_DST_ADDR        = 19,
+	BNXT_ULP_HF21_IDX_O_TCP_SRC_PORT         = 20,
+	BNXT_ULP_HF21_IDX_O_TCP_DST_PORT         = 21,
+	BNXT_ULP_HF21_IDX_O_TCP_SENT_SEQ         = 22,
+	BNXT_ULP_HF21_IDX_O_TCP_RECV_ACK         = 23,
+	BNXT_ULP_HF21_IDX_O_TCP_DATA_OFF         = 24,
+	BNXT_ULP_HF21_IDX_O_TCP_TCP_FLAGS        = 25,
+	BNXT_ULP_HF21_IDX_O_TCP_RX_WIN           = 26,
+	BNXT_ULP_HF21_IDX_O_TCP_CSUM             = 27,
+	BNXT_ULP_HF21_IDX_O_TCP_URP              = 28
 };
 
 enum bnxt_ulp_hf22 {
@@ -483,16 +509,18 @@ enum bnxt_ulp_hf22 {
 	BNXT_ULP_HF22_IDX_OI_VLAN_CFI_PRI        = 7,
 	BNXT_ULP_HF22_IDX_OI_VLAN_VID            = 8,
 	BNXT_ULP_HF22_IDX_OI_VLAN_TYPE           = 9,
-	BNXT_ULP_HF22_IDX_O_IPV4_VER             = 10,
-	BNXT_ULP_HF22_IDX_O_IPV4_TOS             = 11,
-	BNXT_ULP_HF22_IDX_O_IPV4_LEN             = 12,
-	BNXT_ULP_HF22_IDX_O_IPV4_FRAG_ID         = 13,
-	BNXT_ULP_HF22_IDX_O_IPV4_FRAG_OFF        = 14,
-	BNXT_ULP_HF22_IDX_O_IPV4_TTL             = 15,
-	BNXT_ULP_HF22_IDX_O_IPV4_PROTO_ID        = 16,
-	BNXT_ULP_HF22_IDX_O_IPV4_CSUM            = 17,
-	BNXT_ULP_HF22_IDX_O_IPV4_SRC_ADDR        = 18,
-	BNXT_ULP_HF22_IDX_O_IPV4_DST_ADDR        = 19
+	BNXT_ULP_HF22_IDX_O_IPV6_VER             = 10,
+	BNXT_ULP_HF22_IDX_O_IPV6_TC              = 11,
+	BNXT_ULP_HF22_IDX_O_IPV6_FLOW_LABEL      = 12,
+	BNXT_ULP_HF22_IDX_O_IPV6_PAYLOAD_LEN     = 13,
+	BNXT_ULP_HF22_IDX_O_IPV6_PROTO_ID        = 14,
+	BNXT_ULP_HF22_IDX_O_IPV6_TTL             = 15,
+	BNXT_ULP_HF22_IDX_O_IPV6_SRC_ADDR        = 16,
+	BNXT_ULP_HF22_IDX_O_IPV6_DST_ADDR        = 17,
+	BNXT_ULP_HF22_IDX_O_UDP_SRC_PORT         = 18,
+	BNXT_ULP_HF22_IDX_O_UDP_DST_PORT         = 19,
+	BNXT_ULP_HF22_IDX_O_UDP_LENGTH           = 20,
+	BNXT_ULP_HF22_IDX_O_UDP_CSUM             = 21
 };
 
 enum bnxt_ulp_hf23 {
@@ -513,7 +541,60 @@ enum bnxt_ulp_hf23 {
 	BNXT_ULP_HF23_IDX_O_IPV6_PROTO_ID        = 14,
 	BNXT_ULP_HF23_IDX_O_IPV6_TTL             = 15,
 	BNXT_ULP_HF23_IDX_O_IPV6_SRC_ADDR        = 16,
-	BNXT_ULP_HF23_IDX_O_IPV6_DST_ADDR        = 17
+	BNXT_ULP_HF23_IDX_O_IPV6_DST_ADDR        = 17,
+	BNXT_ULP_HF23_IDX_O_TCP_SRC_PORT         = 18,
+	BNXT_ULP_HF23_IDX_O_TCP_DST_PORT         = 19,
+	BNXT_ULP_HF23_IDX_O_TCP_SENT_SEQ         = 20,
+	BNXT_ULP_HF23_IDX_O_TCP_RECV_ACK         = 21,
+	BNXT_ULP_HF23_IDX_O_TCP_DATA_OFF         = 22,
+	BNXT_ULP_HF23_IDX_O_TCP_TCP_FLAGS        = 23,
+	BNXT_ULP_HF23_IDX_O_TCP_RX_WIN           = 24,
+	BNXT_ULP_HF23_IDX_O_TCP_CSUM             = 25,
+	BNXT_ULP_HF23_IDX_O_TCP_URP              = 26
+};
+
+enum bnxt_ulp_hf24 {
+	BNXT_ULP_HF24_IDX_SVIF_INDEX             = 0,
+	BNXT_ULP_HF24_IDX_O_ETH_DMAC             = 1,
+	BNXT_ULP_HF24_IDX_O_ETH_SMAC             = 2,
+	BNXT_ULP_HF24_IDX_O_ETH_TYPE             = 3,
+	BNXT_ULP_HF24_IDX_OO_VLAN_CFI_PRI        = 4,
+	BNXT_ULP_HF24_IDX_OO_VLAN_VID            = 5,
+	BNXT_ULP_HF24_IDX_OO_VLAN_TYPE           = 6,
+	BNXT_ULP_HF24_IDX_OI_VLAN_CFI_PRI        = 7,
+	BNXT_ULP_HF24_IDX_OI_VLAN_VID            = 8,
+	BNXT_ULP_HF24_IDX_OI_VLAN_TYPE           = 9,
+	BNXT_ULP_HF24_IDX_O_IPV4_VER             = 10,
+	BNXT_ULP_HF24_IDX_O_IPV4_TOS             = 11,
+	BNXT_ULP_HF24_IDX_O_IPV4_LEN             = 12,
+	BNXT_ULP_HF24_IDX_O_IPV4_FRAG_ID         = 13,
+	BNXT_ULP_HF24_IDX_O_IPV4_FRAG_OFF        = 14,
+	BNXT_ULP_HF24_IDX_O_IPV4_TTL             = 15,
+	BNXT_ULP_HF24_IDX_O_IPV4_PROTO_ID        = 16,
+	BNXT_ULP_HF24_IDX_O_IPV4_CSUM            = 17,
+	BNXT_ULP_HF24_IDX_O_IPV4_SRC_ADDR        = 18,
+	BNXT_ULP_HF24_IDX_O_IPV4_DST_ADDR        = 19
+};
+
+enum bnxt_ulp_hf25 {
+	BNXT_ULP_HF25_IDX_SVIF_INDEX             = 0,
+	BNXT_ULP_HF25_IDX_O_ETH_DMAC             = 1,
+	BNXT_ULP_HF25_IDX_O_ETH_SMAC             = 2,
+	BNXT_ULP_HF25_IDX_O_ETH_TYPE             = 3,
+	BNXT_ULP_HF25_IDX_OO_VLAN_CFI_PRI        = 4,
+	BNXT_ULP_HF25_IDX_OO_VLAN_VID            = 5,
+	BNXT_ULP_HF25_IDX_OO_VLAN_TYPE           = 6,
+	BNXT_ULP_HF25_IDX_OI_VLAN_CFI_PRI        = 7,
+	BNXT_ULP_HF25_IDX_OI_VLAN_VID            = 8,
+	BNXT_ULP_HF25_IDX_OI_VLAN_TYPE           = 9,
+	BNXT_ULP_HF25_IDX_O_IPV6_VER             = 10,
+	BNXT_ULP_HF25_IDX_O_IPV6_TC              = 11,
+	BNXT_ULP_HF25_IDX_O_IPV6_FLOW_LABEL      = 12,
+	BNXT_ULP_HF25_IDX_O_IPV6_PAYLOAD_LEN     = 13,
+	BNXT_ULP_HF25_IDX_O_IPV6_PROTO_ID        = 14,
+	BNXT_ULP_HF25_IDX_O_IPV6_TTL             = 15,
+	BNXT_ULP_HF25_IDX_O_IPV6_SRC_ADDR        = 16,
+	BNXT_ULP_HF25_IDX_O_IPV6_DST_ADDR        = 17
 };
 
 enum bnxt_ulp_hf_bitmask1 {
@@ -892,7 +973,11 @@ enum bnxt_ulp_hf_bitmask18 {
 	BNXT_ULP_HF18_BITMASK_O_UDP_SRC_PORT     = 0x0000080000000000,
 	BNXT_ULP_HF18_BITMASK_O_UDP_DST_PORT     = 0x0000040000000000,
 	BNXT_ULP_HF18_BITMASK_O_UDP_LENGTH       = 0x0000020000000000,
-	BNXT_ULP_HF18_BITMASK_O_UDP_CSUM         = 0x0000010000000000
+	BNXT_ULP_HF18_BITMASK_O_UDP_CSUM         = 0x0000010000000000,
+	BNXT_ULP_HF18_BITMASK_T_VXLAN_FLAGS      = 0x0000008000000000,
+	BNXT_ULP_HF18_BITMASK_T_VXLAN_RSVD0      = 0x0000004000000000,
+	BNXT_ULP_HF18_BITMASK_T_VXLAN_VNI        = 0x0000002000000000,
+	BNXT_ULP_HF18_BITMASK_T_VXLAN_RSVD1      = 0x0000001000000000
 };
 
 enum bnxt_ulp_hf_bitmask19 {
@@ -916,15 +1001,33 @@ enum bnxt_ulp_hf_bitmask19 {
 	BNXT_ULP_HF19_BITMASK_O_IPV4_CSUM        = 0x0000400000000000,
 	BNXT_ULP_HF19_BITMASK_O_IPV4_SRC_ADDR    = 0x0000200000000000,
 	BNXT_ULP_HF19_BITMASK_O_IPV4_DST_ADDR    = 0x0000100000000000,
-	BNXT_ULP_HF19_BITMASK_O_TCP_SRC_PORT     = 0x0000080000000000,
-	BNXT_ULP_HF19_BITMASK_O_TCP_DST_PORT     = 0x0000040000000000,
-	BNXT_ULP_HF19_BITMASK_O_TCP_SENT_SEQ     = 0x0000020000000000,
-	BNXT_ULP_HF19_BITMASK_O_TCP_RECV_ACK     = 0x0000010000000000,
-	BNXT_ULP_HF19_BITMASK_O_TCP_DATA_OFF     = 0x0000008000000000,
-	BNXT_ULP_HF19_BITMASK_O_TCP_TCP_FLAGS    = 0x0000004000000000,
-	BNXT_ULP_HF19_BITMASK_O_TCP_RX_WIN       = 0x0000002000000000,
-	BNXT_ULP_HF19_BITMASK_O_TCP_CSUM         = 0x0000001000000000,
-	BNXT_ULP_HF19_BITMASK_O_TCP_URP          = 0x0000000800000000
+	BNXT_ULP_HF19_BITMASK_O_UDP_SRC_PORT     = 0x0000080000000000,
+	BNXT_ULP_HF19_BITMASK_O_UDP_DST_PORT     = 0x0000040000000000,
+	BNXT_ULP_HF19_BITMASK_O_UDP_LENGTH       = 0x0000020000000000,
+	BNXT_ULP_HF19_BITMASK_O_UDP_CSUM         = 0x0000010000000000,
+	BNXT_ULP_HF19_BITMASK_T_VXLAN_FLAGS      = 0x0000008000000000,
+	BNXT_ULP_HF19_BITMASK_T_VXLAN_RSVD0      = 0x0000004000000000,
+	BNXT_ULP_HF19_BITMASK_T_VXLAN_VNI        = 0x0000002000000000,
+	BNXT_ULP_HF19_BITMASK_T_VXLAN_RSVD1      = 0x0000001000000000,
+	BNXT_ULP_HF19_BITMASK_I_ETH_DMAC         = 0x0000000800000000,
+	BNXT_ULP_HF19_BITMASK_I_ETH_SMAC         = 0x0000000400000000,
+	BNXT_ULP_HF19_BITMASK_I_ETH_TYPE         = 0x0000000200000000,
+	BNXT_ULP_HF19_BITMASK_IO_VLAN_CFI_PRI    = 0x0000000100000000,
+	BNXT_ULP_HF19_BITMASK_IO_VLAN_VID        = 0x0000000080000000,
+	BNXT_ULP_HF19_BITMASK_IO_VLAN_TYPE       = 0x0000000040000000,
+	BNXT_ULP_HF19_BITMASK_II_VLAN_CFI_PRI    = 0x0000000020000000,
+	BNXT_ULP_HF19_BITMASK_II_VLAN_VID        = 0x0000000010000000,
+	BNXT_ULP_HF19_BITMASK_II_VLAN_TYPE       = 0x0000000008000000,
+	BNXT_ULP_HF19_BITMASK_I_IPV4_VER         = 0x0000000004000000,
+	BNXT_ULP_HF19_BITMASK_I_IPV4_TOS         = 0x0000000002000000,
+	BNXT_ULP_HF19_BITMASK_I_IPV4_LEN         = 0x0000000001000000,
+	BNXT_ULP_HF19_BITMASK_I_IPV4_FRAG_ID     = 0x0000000000800000,
+	BNXT_ULP_HF19_BITMASK_I_IPV4_FRAG_OFF    = 0x0000000000400000,
+	BNXT_ULP_HF19_BITMASK_I_IPV4_TTL         = 0x0000000000200000,
+	BNXT_ULP_HF19_BITMASK_I_IPV4_PROTO_ID    = 0x0000000000100000,
+	BNXT_ULP_HF19_BITMASK_I_IPV4_CSUM        = 0x0000000000080000,
+	BNXT_ULP_HF19_BITMASK_I_IPV4_SRC_ADDR    = 0x0000000000040000,
+	BNXT_ULP_HF19_BITMASK_I_IPV4_DST_ADDR    = 0x0000000000020000
 };
 
 enum bnxt_ulp_hf_bitmask20 {
@@ -938,18 +1041,20 @@ enum bnxt_ulp_hf_bitmask20 {
 	BNXT_ULP_HF20_BITMASK_OI_VLAN_CFI_PRI    = 0x0100000000000000,
 	BNXT_ULP_HF20_BITMASK_OI_VLAN_VID        = 0x0080000000000000,
 	BNXT_ULP_HF20_BITMASK_OI_VLAN_TYPE       = 0x0040000000000000,
-	BNXT_ULP_HF20_BITMASK_O_IPV6_VER         = 0x0020000000000000,
-	BNXT_ULP_HF20_BITMASK_O_IPV6_TC          = 0x0010000000000000,
-	BNXT_ULP_HF20_BITMASK_O_IPV6_FLOW_LABEL  = 0x0008000000000000,
-	BNXT_ULP_HF20_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0004000000000000,
-	BNXT_ULP_HF20_BITMASK_O_IPV6_PROTO_ID    = 0x0002000000000000,
-	BNXT_ULP_HF20_BITMASK_O_IPV6_TTL         = 0x0001000000000000,
-	BNXT_ULP_HF20_BITMASK_O_IPV6_SRC_ADDR    = 0x0000800000000000,
-	BNXT_ULP_HF20_BITMASK_O_IPV6_DST_ADDR    = 0x0000400000000000,
-	BNXT_ULP_HF20_BITMASK_O_UDP_SRC_PORT     = 0x0000200000000000,
-	BNXT_ULP_HF20_BITMASK_O_UDP_DST_PORT     = 0x0000100000000000,
-	BNXT_ULP_HF20_BITMASK_O_UDP_LENGTH       = 0x0000080000000000,
-	BNXT_ULP_HF20_BITMASK_O_UDP_CSUM         = 0x0000040000000000
+	BNXT_ULP_HF20_BITMASK_O_IPV4_VER         = 0x0020000000000000,
+	BNXT_ULP_HF20_BITMASK_O_IPV4_TOS         = 0x0010000000000000,
+	BNXT_ULP_HF20_BITMASK_O_IPV4_LEN         = 0x0008000000000000,
+	BNXT_ULP_HF20_BITMASK_O_IPV4_FRAG_ID     = 0x0004000000000000,
+	BNXT_ULP_HF20_BITMASK_O_IPV4_FRAG_OFF    = 0x0002000000000000,
+	BNXT_ULP_HF20_BITMASK_O_IPV4_TTL         = 0x0001000000000000,
+	BNXT_ULP_HF20_BITMASK_O_IPV4_PROTO_ID    = 0x0000800000000000,
+	BNXT_ULP_HF20_BITMASK_O_IPV4_CSUM        = 0x0000400000000000,
+	BNXT_ULP_HF20_BITMASK_O_IPV4_SRC_ADDR    = 0x0000200000000000,
+	BNXT_ULP_HF20_BITMASK_O_IPV4_DST_ADDR    = 0x0000100000000000,
+	BNXT_ULP_HF20_BITMASK_O_UDP_SRC_PORT     = 0x0000080000000000,
+	BNXT_ULP_HF20_BITMASK_O_UDP_DST_PORT     = 0x0000040000000000,
+	BNXT_ULP_HF20_BITMASK_O_UDP_LENGTH       = 0x0000020000000000,
+	BNXT_ULP_HF20_BITMASK_O_UDP_CSUM         = 0x0000010000000000
 };
 
 enum bnxt_ulp_hf_bitmask21 {
@@ -963,23 +1068,25 @@ enum bnxt_ulp_hf_bitmask21 {
 	BNXT_ULP_HF21_BITMASK_OI_VLAN_CFI_PRI    = 0x0100000000000000,
 	BNXT_ULP_HF21_BITMASK_OI_VLAN_VID        = 0x0080000000000000,
 	BNXT_ULP_HF21_BITMASK_OI_VLAN_TYPE       = 0x0040000000000000,
-	BNXT_ULP_HF21_BITMASK_O_IPV6_VER         = 0x0020000000000000,
-	BNXT_ULP_HF21_BITMASK_O_IPV6_TC          = 0x0010000000000000,
-	BNXT_ULP_HF21_BITMASK_O_IPV6_FLOW_LABEL  = 0x0008000000000000,
-	BNXT_ULP_HF21_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0004000000000000,
-	BNXT_ULP_HF21_BITMASK_O_IPV6_PROTO_ID    = 0x0002000000000000,
-	BNXT_ULP_HF21_BITMASK_O_IPV6_TTL         = 0x0001000000000000,
-	BNXT_ULP_HF21_BITMASK_O_IPV6_SRC_ADDR    = 0x0000800000000000,
-	BNXT_ULP_HF21_BITMASK_O_IPV6_DST_ADDR    = 0x0000400000000000,
-	BNXT_ULP_HF21_BITMASK_O_TCP_SRC_PORT     = 0x0000200000000000,
-	BNXT_ULP_HF21_BITMASK_O_TCP_DST_PORT     = 0x0000100000000000,
-	BNXT_ULP_HF21_BITMASK_O_TCP_SENT_SEQ     = 0x0000080000000000,
-	BNXT_ULP_HF21_BITMASK_O_TCP_RECV_ACK     = 0x0000040000000000,
-	BNXT_ULP_HF21_BITMASK_O_TCP_DATA_OFF     = 0x0000020000000000,
-	BNXT_ULP_HF21_BITMASK_O_TCP_TCP_FLAGS    = 0x0000010000000000,
-	BNXT_ULP_HF21_BITMASK_O_TCP_RX_WIN       = 0x0000008000000000,
-	BNXT_ULP_HF21_BITMASK_O_TCP_CSUM         = 0x0000004000000000,
-	BNXT_ULP_HF21_BITMASK_O_TCP_URP          = 0x0000002000000000
+	BNXT_ULP_HF21_BITMASK_O_IPV4_VER         = 0x0020000000000000,
+	BNXT_ULP_HF21_BITMASK_O_IPV4_TOS         = 0x0010000000000000,
+	BNXT_ULP_HF21_BITMASK_O_IPV4_LEN         = 0x0008000000000000,
+	BNXT_ULP_HF21_BITMASK_O_IPV4_FRAG_ID     = 0x0004000000000000,
+	BNXT_ULP_HF21_BITMASK_O_IPV4_FRAG_OFF    = 0x0002000000000000,
+	BNXT_ULP_HF21_BITMASK_O_IPV4_TTL         = 0x0001000000000000,
+	BNXT_ULP_HF21_BITMASK_O_IPV4_PROTO_ID    = 0x0000800000000000,
+	BNXT_ULP_HF21_BITMASK_O_IPV4_CSUM        = 0x0000400000000000,
+	BNXT_ULP_HF21_BITMASK_O_IPV4_SRC_ADDR    = 0x0000200000000000,
+	BNXT_ULP_HF21_BITMASK_O_IPV4_DST_ADDR    = 0x0000100000000000,
+	BNXT_ULP_HF21_BITMASK_O_TCP_SRC_PORT     = 0x0000080000000000,
+	BNXT_ULP_HF21_BITMASK_O_TCP_DST_PORT     = 0x0000040000000000,
+	BNXT_ULP_HF21_BITMASK_O_TCP_SENT_SEQ     = 0x0000020000000000,
+	BNXT_ULP_HF21_BITMASK_O_TCP_RECV_ACK     = 0x0000010000000000,
+	BNXT_ULP_HF21_BITMASK_O_TCP_DATA_OFF     = 0x0000008000000000,
+	BNXT_ULP_HF21_BITMASK_O_TCP_TCP_FLAGS    = 0x0000004000000000,
+	BNXT_ULP_HF21_BITMASK_O_TCP_RX_WIN       = 0x0000002000000000,
+	BNXT_ULP_HF21_BITMASK_O_TCP_CSUM         = 0x0000001000000000,
+	BNXT_ULP_HF21_BITMASK_O_TCP_URP          = 0x0000000800000000
 };
 
 enum bnxt_ulp_hf_bitmask22 {
@@ -993,16 +1100,18 @@ enum bnxt_ulp_hf_bitmask22 {
 	BNXT_ULP_HF22_BITMASK_OI_VLAN_CFI_PRI    = 0x0100000000000000,
 	BNXT_ULP_HF22_BITMASK_OI_VLAN_VID        = 0x0080000000000000,
 	BNXT_ULP_HF22_BITMASK_OI_VLAN_TYPE       = 0x0040000000000000,
-	BNXT_ULP_HF22_BITMASK_O_IPV4_VER         = 0x0020000000000000,
-	BNXT_ULP_HF22_BITMASK_O_IPV4_TOS         = 0x0010000000000000,
-	BNXT_ULP_HF22_BITMASK_O_IPV4_LEN         = 0x0008000000000000,
-	BNXT_ULP_HF22_BITMASK_O_IPV4_FRAG_ID     = 0x0004000000000000,
-	BNXT_ULP_HF22_BITMASK_O_IPV4_FRAG_OFF    = 0x0002000000000000,
-	BNXT_ULP_HF22_BITMASK_O_IPV4_TTL         = 0x0001000000000000,
-	BNXT_ULP_HF22_BITMASK_O_IPV4_PROTO_ID    = 0x0000800000000000,
-	BNXT_ULP_HF22_BITMASK_O_IPV4_CSUM        = 0x0000400000000000,
-	BNXT_ULP_HF22_BITMASK_O_IPV4_SRC_ADDR    = 0x0000200000000000,
-	BNXT_ULP_HF22_BITMASK_O_IPV4_DST_ADDR    = 0x0000100000000000
+	BNXT_ULP_HF22_BITMASK_O_IPV6_VER         = 0x0020000000000000,
+	BNXT_ULP_HF22_BITMASK_O_IPV6_TC          = 0x0010000000000000,
+	BNXT_ULP_HF22_BITMASK_O_IPV6_FLOW_LABEL  = 0x0008000000000000,
+	BNXT_ULP_HF22_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0004000000000000,
+	BNXT_ULP_HF22_BITMASK_O_IPV6_PROTO_ID    = 0x0002000000000000,
+	BNXT_ULP_HF22_BITMASK_O_IPV6_TTL         = 0x0001000000000000,
+	BNXT_ULP_HF22_BITMASK_O_IPV6_SRC_ADDR    = 0x0000800000000000,
+	BNXT_ULP_HF22_BITMASK_O_IPV6_DST_ADDR    = 0x0000400000000000,
+	BNXT_ULP_HF22_BITMASK_O_UDP_SRC_PORT     = 0x0000200000000000,
+	BNXT_ULP_HF22_BITMASK_O_UDP_DST_PORT     = 0x0000100000000000,
+	BNXT_ULP_HF22_BITMASK_O_UDP_LENGTH       = 0x0000080000000000,
+	BNXT_ULP_HF22_BITMASK_O_UDP_CSUM         = 0x0000040000000000
 };
 
 enum bnxt_ulp_hf_bitmask23 {
@@ -1023,6 +1132,60 @@ enum bnxt_ulp_hf_bitmask23 {
 	BNXT_ULP_HF23_BITMASK_O_IPV6_PROTO_ID    = 0x0002000000000000,
 	BNXT_ULP_HF23_BITMASK_O_IPV6_TTL         = 0x0001000000000000,
 	BNXT_ULP_HF23_BITMASK_O_IPV6_SRC_ADDR    = 0x0000800000000000,
-	BNXT_ULP_HF23_BITMASK_O_IPV6_DST_ADDR    = 0x0000400000000000
+	BNXT_ULP_HF23_BITMASK_O_IPV6_DST_ADDR    = 0x0000400000000000,
+	BNXT_ULP_HF23_BITMASK_O_TCP_SRC_PORT     = 0x0000200000000000,
+	BNXT_ULP_HF23_BITMASK_O_TCP_DST_PORT     = 0x0000100000000000,
+	BNXT_ULP_HF23_BITMASK_O_TCP_SENT_SEQ     = 0x0000080000000000,
+	BNXT_ULP_HF23_BITMASK_O_TCP_RECV_ACK     = 0x0000040000000000,
+	BNXT_ULP_HF23_BITMASK_O_TCP_DATA_OFF     = 0x0000020000000000,
+	BNXT_ULP_HF23_BITMASK_O_TCP_TCP_FLAGS    = 0x0000010000000000,
+	BNXT_ULP_HF23_BITMASK_O_TCP_RX_WIN       = 0x0000008000000000,
+	BNXT_ULP_HF23_BITMASK_O_TCP_CSUM         = 0x0000004000000000,
+	BNXT_ULP_HF23_BITMASK_O_TCP_URP          = 0x0000002000000000
 };
+
+enum bnxt_ulp_hf_bitmask24 {
+	BNXT_ULP_HF24_BITMASK_SVIF_INDEX         = 0x8000000000000000,
+	BNXT_ULP_HF24_BITMASK_O_ETH_DMAC         = 0x4000000000000000,
+	BNXT_ULP_HF24_BITMASK_O_ETH_SMAC         = 0x2000000000000000,
+	BNXT_ULP_HF24_BITMASK_O_ETH_TYPE         = 0x1000000000000000,
+	BNXT_ULP_HF24_BITMASK_OO_VLAN_CFI_PRI    = 0x0800000000000000,
+	BNXT_ULP_HF24_BITMASK_OO_VLAN_VID        = 0x0400000000000000,
+	BNXT_ULP_HF24_BITMASK_OO_VLAN_TYPE       = 0x0200000000000000,
+	BNXT_ULP_HF24_BITMASK_OI_VLAN_CFI_PRI    = 0x0100000000000000,
+	BNXT_ULP_HF24_BITMASK_OI_VLAN_VID        = 0x0080000000000000,
+	BNXT_ULP_HF24_BITMASK_OI_VLAN_TYPE       = 0x0040000000000000,
+	BNXT_ULP_HF24_BITMASK_O_IPV4_VER         = 0x0020000000000000,
+	BNXT_ULP_HF24_BITMASK_O_IPV4_TOS         = 0x0010000000000000,
+	BNXT_ULP_HF24_BITMASK_O_IPV4_LEN         = 0x0008000000000000,
+	BNXT_ULP_HF24_BITMASK_O_IPV4_FRAG_ID     = 0x0004000000000000,
+	BNXT_ULP_HF24_BITMASK_O_IPV4_FRAG_OFF    = 0x0002000000000000,
+	BNXT_ULP_HF24_BITMASK_O_IPV4_TTL         = 0x0001000000000000,
+	BNXT_ULP_HF24_BITMASK_O_IPV4_PROTO_ID    = 0x0000800000000000,
+	BNXT_ULP_HF24_BITMASK_O_IPV4_CSUM        = 0x0000400000000000,
+	BNXT_ULP_HF24_BITMASK_O_IPV4_SRC_ADDR    = 0x0000200000000000,
+	BNXT_ULP_HF24_BITMASK_O_IPV4_DST_ADDR    = 0x0000100000000000
+};
+
+enum bnxt_ulp_hf_bitmask25 {
+	BNXT_ULP_HF25_BITMASK_SVIF_INDEX         = 0x8000000000000000,
+	BNXT_ULP_HF25_BITMASK_O_ETH_DMAC         = 0x4000000000000000,
+	BNXT_ULP_HF25_BITMASK_O_ETH_SMAC         = 0x2000000000000000,
+	BNXT_ULP_HF25_BITMASK_O_ETH_TYPE         = 0x1000000000000000,
+	BNXT_ULP_HF25_BITMASK_OO_VLAN_CFI_PRI    = 0x0800000000000000,
+	BNXT_ULP_HF25_BITMASK_OO_VLAN_VID        = 0x0400000000000000,
+	BNXT_ULP_HF25_BITMASK_OO_VLAN_TYPE       = 0x0200000000000000,
+	BNXT_ULP_HF25_BITMASK_OI_VLAN_CFI_PRI    = 0x0100000000000000,
+	BNXT_ULP_HF25_BITMASK_OI_VLAN_VID        = 0x0080000000000000,
+	BNXT_ULP_HF25_BITMASK_OI_VLAN_TYPE       = 0x0040000000000000,
+	BNXT_ULP_HF25_BITMASK_O_IPV6_VER         = 0x0020000000000000,
+	BNXT_ULP_HF25_BITMASK_O_IPV6_TC          = 0x0010000000000000,
+	BNXT_ULP_HF25_BITMASK_O_IPV6_FLOW_LABEL  = 0x0008000000000000,
+	BNXT_ULP_HF25_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0004000000000000,
+	BNXT_ULP_HF25_BITMASK_O_IPV6_PROTO_ID    = 0x0002000000000000,
+	BNXT_ULP_HF25_BITMASK_O_IPV6_TTL         = 0x0001000000000000,
+	BNXT_ULP_HF25_BITMASK_O_IPV6_SRC_ADDR    = 0x0000800000000000,
+	BNXT_ULP_HF25_BITMASK_O_IPV6_DST_ADDR    = 0x0000400000000000
+};
+
 #endif
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_act.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_act.c
index 2237ffb94..7a4d49285 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_act.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_act.c
@@ -55,9 +55,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {
 	.result_bit_size = 64,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -72,9 +72,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {
 	.result_bit_size = 32,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_SRC_PTR_0,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_SRC_PTR_0
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -89,9 +89,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {
 	.result_bit_size = 32,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_DST_PTR_0,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_DST_PTR_0
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -105,9 +105,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {
 	.result_bit_size = 0,
 	.result_num_fields = 0,
 	.encap_num_fields = 12,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_GLOBAL,
-	.index_operand = BNXT_ULP_GLB_REGFILE_INDEX_ENCAP_MAC_PTR,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_GLB_REGFILE_INDEX_ENCAP_MAC_PTR
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -121,9 +121,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {
 	.result_bit_size = 128,
 	.result_num_fields = 26,
 	.encap_num_fields = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -137,9 +137,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {
 	.result_bit_size = 128,
 	.result_num_fields = 26,
 	.encap_num_fields = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -154,9 +154,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {
 	.result_bit_size = 64,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -170,9 +170,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {
 	.result_bit_size = 128,
 	.result_num_fields = 26,
 	.encap_num_fields = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -186,9 +186,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {
 	.result_bit_size = 128,
 	.result_num_fields = 26,
 	.encap_num_fields = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -203,9 +203,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {
 	.result_bit_size = 64,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -219,9 +219,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {
 	.result_bit_size = 128,
 	.result_num_fields = 26,
 	.encap_num_fields = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -235,9 +235,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {
 	.result_bit_size = 128,
 	.result_num_fields = 26,
 	.encap_num_fields = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -252,9 +252,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {
 	.result_bit_size = 64,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -269,9 +269,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {
 	.result_bit_size = 0,
 	.result_num_fields = 0,
 	.encap_num_fields = 3,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -286,9 +286,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {
 	.result_bit_size = 0,
 	.result_num_fields = 0,
 	.encap_num_fields = 3,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -301,9 +301,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {
 	.result_bit_size = 0,
 	.result_num_fields = 0,
 	.encap_num_fields = 12,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -317,9 +317,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {
 	.result_bit_size = 128,
 	.result_num_fields = 26,
 	.encap_num_fields = 12,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -333,9 +333,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {
 	.result_bit_size = 128,
 	.result_num_fields = 26,
 	.encap_num_fields = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -350,9 +350,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {
 	.result_bit_size = 64,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -367,9 +367,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {
 	.result_bit_size = 32,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_SRC_PTR_0,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_SRC_PTR_0
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -384,9 +384,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {
 	.result_bit_size = 32,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_DST_PTR_0,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_MODIFY_IPV4_DST_PTR_0
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -400,9 +400,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {
 	.result_bit_size = 0,
 	.result_num_fields = 0,
 	.encap_num_fields = 12,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_GLOBAL,
-	.index_operand = BNXT_ULP_GLB_REGFILE_INDEX_ENCAP_MAC_PTR,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_GLB_REGFILE_INDEX_ENCAP_MAC_PTR
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -416,9 +416,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {
 	.result_bit_size = 128,
 	.result_num_fields = 26,
 	.encap_num_fields = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -432,9 +432,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {
 	.result_bit_size = 128,
 	.result_num_fields = 26,
 	.encap_num_fields = 11,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -449,9 +449,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {
 	.result_bit_size = 64,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -467,9 +467,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {
 	.result_bit_size = 0,
 	.result_num_fields = 0,
 	.encap_num_fields = 12,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -483,9 +483,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {
 	.result_bit_size = 128,
 	.result_num_fields = 26,
 	.encap_num_fields = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -501,9 +501,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {
 	.result_bit_size = 128,
 	.result_num_fields = 26,
 	.encap_num_fields = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@@ -519,9 +519,9 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {
 	.result_bit_size = 128,
 	.result_num_fields = 26,
 	.encap_num_fields = 11,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
-	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+	.index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR
 	}
 };
 
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_class.c
index 62b940daa..346e15581 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_class.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_class.c
@@ -96,33 +96,43 @@ struct bnxt_ulp_mapper_tbl_list_info ulp_stingray_class_tmpl_list[] = {
 	},
 	[18] = {
 	.device_name = BNXT_ULP_DEVICE_ID_STINGRAY,
-	.num_tbls = 6,
+	.num_tbls = 5,
 	.start_tbl_idx = 92
 	},
 	[19] = {
 	.device_name = BNXT_ULP_DEVICE_ID_STINGRAY,
-	.num_tbls = 6,
-	.start_tbl_idx = 98
+	.num_tbls = 5,
+	.start_tbl_idx = 97
 	},
 	[20] = {
 	.device_name = BNXT_ULP_DEVICE_ID_STINGRAY,
 	.num_tbls = 6,
-	.start_tbl_idx = 104
+	.start_tbl_idx = 102
 	},
 	[21] = {
 	.device_name = BNXT_ULP_DEVICE_ID_STINGRAY,
 	.num_tbls = 6,
-	.start_tbl_idx = 110
+	.start_tbl_idx = 108
 	},
 	[22] = {
 	.device_name = BNXT_ULP_DEVICE_ID_STINGRAY,
-	.num_tbls = 5,
-	.start_tbl_idx = 116
+	.num_tbls = 6,
+	.start_tbl_idx = 114
 	},
 	[23] = {
 	.device_name = BNXT_ULP_DEVICE_ID_STINGRAY,
+	.num_tbls = 6,
+	.start_tbl_idx = 120
+	},
+	[24] = {
+	.device_name = BNXT_ULP_DEVICE_ID_STINGRAY,
+	.num_tbls = 5,
+	.start_tbl_idx = 126
+	},
+	[25] = {
+	.device_name = BNXT_ULP_DEVICE_ID_STINGRAY,
 	.num_tbls = 5,
-	.start_tbl_idx = 121
+	.start_tbl_idx = 131
 	}
 };
 
@@ -133,6 +143,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL,
 	.direction = TF_DIR_RX,
+	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
 	.result_start_idx = 0,
 	.result_bit_size = 128,
 	.result_num_fields = 26,
@@ -162,8 +173,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 1,
 	.blob_key_bit_size = 171,
 	.key_bit_size = 171,
@@ -216,6 +227,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_VFR_CFA_ACTION,
 	.direction = TF_DIR_TX,
+	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
 	.result_start_idx = 43,
 	.result_bit_size = 128,
 	.result_num_fields = 26,
@@ -230,8 +242,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.cond_opcode = BNXT_ULP_COND_OPCODE_COMP_FIELD_IS_SET,
 	.cond_operand = BNXT_ULP_CF_IDX_VFR_MODE,
 	.direction = TF_DIR_TX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 14,
 	.blob_key_bit_size = 171,
 	.key_bit_size = 171,
@@ -270,8 +282,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.cond_opcode = BNXT_ULP_COND_OPCODE_COMP_FIELD_NOT_SET,
 	.cond_operand = BNXT_ULP_CF_IDX_VFR_MODE,
 	.direction = TF_DIR_TX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 28,
 	.blob_key_bit_size = 171,
 	.key_bit_size = 171,
@@ -324,6 +336,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL,
 	.direction = TF_DIR_TX,
+	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
 	.result_start_idx = 99,
 	.result_bit_size = 0,
 	.result_num_fields = 0,
@@ -338,6 +351,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_VFR_CFA_ACTION,
 	.direction = TF_DIR_TX,
+	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
 	.result_start_idx = 111,
 	.result_bit_size = 128,
 	.result_num_fields = 26,
@@ -367,8 +381,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
 	.direction = TF_DIR_TX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 42,
 	.blob_key_bit_size = 171,
 	.key_bit_size = 171,
@@ -388,6 +402,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL,
 	.direction = TF_DIR_RX,
+	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
 	.result_start_idx = 150,
 	.result_bit_size = 128,
 	.result_num_fields = 26,
@@ -400,8 +415,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 55,
 	.blob_key_bit_size = 171,
 	.key_bit_size = 171,
@@ -419,8 +434,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 68,
 	.blob_key_bit_size = 171,
 	.key_bit_size = 171,
@@ -455,8 +470,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
 	.direction = TF_DIR_TX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 82,
 	.blob_key_bit_size = 171,
 	.key_bit_size = 171,
@@ -509,6 +524,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL,
 	.direction = TF_DIR_RX,
+	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
 	.result_start_idx = 219,
 	.result_bit_size = 128,
 	.result_num_fields = 26,
@@ -521,8 +537,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 95,
 	.blob_key_bit_size = 171,
 	.key_bit_size = 171,
@@ -542,6 +558,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_VFR_CFA_ACTION,
 	.direction = TF_DIR_TX,
+	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
 	.result_start_idx = 258,
 	.result_bit_size = 128,
 	.result_num_fields = 26,
@@ -554,8 +571,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 108,
 	.blob_key_bit_size = 171,
 	.key_bit_size = 171,
@@ -590,8 +607,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_1,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_1,
 	.key_start_idx = 124,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
@@ -645,8 +662,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 189,
 	.blob_key_bit_size = 171,
 	.key_bit_size = 171,
@@ -681,8 +698,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_1,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_1,
 	.key_start_idx = 205,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
@@ -753,8 +770,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 271,
 	.blob_key_bit_size = 171,
 	.key_bit_size = 171,
@@ -789,8 +806,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 287,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
@@ -861,8 +878,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 353,
 	.blob_key_bit_size = 171,
 	.key_bit_size = 171,
@@ -897,8 +914,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 369,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
@@ -969,8 +986,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 435,
 	.blob_key_bit_size = 171,
 	.key_bit_size = 171,
@@ -1005,8 +1022,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 451,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
@@ -1077,8 +1094,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 517,
 	.blob_key_bit_size = 171,
 	.key_bit_size = 171,
@@ -1113,8 +1130,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 533,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
@@ -1168,8 +1185,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 598,
 	.blob_key_bit_size = 171,
 	.key_bit_size = 171,
@@ -1204,8 +1221,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 614,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
@@ -1259,8 +1276,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 679,
 	.blob_key_bit_size = 171,
 	.key_bit_size = 171,
@@ -1295,8 +1312,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 695,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
@@ -1350,8 +1367,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 760,
 	.blob_key_bit_size = 171,
 	.key_bit_size = 171,
@@ -1386,8 +1403,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 776,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
@@ -1441,8 +1458,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 841,
 	.blob_key_bit_size = 171,
 	.key_bit_size = 171,
@@ -1477,8 +1494,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 857,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
@@ -1532,8 +1549,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 922,
 	.blob_key_bit_size = 171,
 	.key_bit_size = 171,
@@ -1568,8 +1585,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 938,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
@@ -1623,8 +1640,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 1003,
 	.blob_key_bit_size = 171,
 	.key_bit_size = 171,
@@ -1659,8 +1676,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
 	.direction = TF_DIR_RX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.key_start_idx = 1019,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
@@ -1711,29 +1728,29 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES
 	},
 	{
-	.resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE,
-	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+	.resource_type = TF_TBL_TYPE_ACT_STATS_64,
 	.resource_sub_type =
-		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM,
-	.direction = TF_DIR_TX,
-	.key_start_idx = 1084,
-	.blob_key_bit_size = 12,
-	.key_bit_size = 12,
-	.key_num_fields = 1,
+		BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT_ACC,
+	.cond_opcode = BNXT_ULP_COND_OPCODE_ACTION_BIT_IS_SET,
+	.cond_operand = BNXT_ULP_ACTION_BIT_COUNT,
+	.direction = TF_DIR_RX,
+	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
 	.result_start_idx = 768,
-	.result_bit_size = 10,
+	.result_bit_size = 64,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
-	.ident_start_idx = 27,
-	.ident_nums = 1
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
+	.index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
+	.index_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
-	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
-	.direction = TF_DIR_TX,
+	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+	.direction = TF_DIR_RX,
+	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP,
 	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
-	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 1085,
+	.key_start_idx = 1084,
 	.blob_key_bit_size = 171,
 	.key_bit_size = 171,
 	.key_num_fields = 13,
@@ -1741,8 +1758,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.result_bit_size = 64,
 	.result_num_fields = 13,
 	.encap_num_fields = 0,
-	.ident_start_idx = 28,
-	.ident_nums = 0,
+	.ident_start_idx = 27,
+	.ident_nums = 1,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
 	},
@@ -1751,71 +1768,145 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
-	.direction = TF_DIR_TX,
-	.key_start_idx = 1098,
+	.direction = TF_DIR_RX,
+	.key_start_idx = 1097,
 	.blob_key_bit_size = 16,
 	.key_bit_size = 16,
 	.key_num_fields = 3,
 	.result_start_idx = 782,
-	.result_bit_size = 10,
-	.result_num_fields = 1,
+	.result_bit_size = 20,
+	.result_num_fields = 2,
 	.encap_num_fields = 0,
 	.ident_start_idx = 28,
-	.ident_nums = 1
+	.ident_nums = 2
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
-	.direction = TF_DIR_TX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
+	.direction = TF_DIR_RX,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 1101,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
+	.key_start_idx = 1100,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
 	.key_num_fields = 43,
-	.result_start_idx = 783,
+	.result_start_idx = 784,
 	.result_bit_size = 38,
 	.result_num_fields = 8,
 	.encap_num_fields = 0,
-	.ident_start_idx = 29,
+	.ident_start_idx = 30,
 	.ident_nums = 0,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
 	},
 	{
-	.resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE,
-	.resource_type = TF_MEM_EXTERNAL,
-	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT,
-	.direction = TF_DIR_TX,
-	.key_start_idx = 1144,
-	.blob_key_bit_size = 448,
-	.key_bit_size = 448,
-	.key_num_fields = 11,
-	.result_start_idx = 791,
-	.result_bit_size = 64,
-	.result_num_fields = 9,
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+	.resource_type = TF_TCAM_TBL_TYPE_WC_TCAM,
+	.direction = TF_DIR_RX,
+	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
+	.key_start_idx = 1143,
+	.blob_key_bit_size = 192,
+	.key_bit_size = 160,
+	.key_num_fields = 5,
+	.result_start_idx = 792,
+	.result_bit_size = 19,
+	.result_num_fields = 3,
 	.encap_num_fields = 0,
-	.ident_start_idx = 29,
+	.ident_start_idx = 30,
 	.ident_nums = 0,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES
 	},
 	{
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
+	.direction = TF_DIR_RX,
+	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_SKIP,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
+	.key_start_idx = 1148,
+	.blob_key_bit_size = 171,
+	.key_bit_size = 171,
+	.key_num_fields = 13,
+	.result_start_idx = 795,
+	.result_bit_size = 64,
+	.result_num_fields = 13,
+	.encap_num_fields = 0,
+	.ident_start_idx = 30,
+	.ident_nums = 1,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
+	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
+	},
+	{
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE,
+	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+	.resource_sub_type =
+		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
+	.direction = TF_DIR_RX,
+	.key_start_idx = 1161,
+	.blob_key_bit_size = 16,
+	.key_bit_size = 16,
+	.key_num_fields = 3,
+	.result_start_idx = 808,
+	.result_bit_size = 20,
+	.result_num_fields = 2,
+	.encap_num_fields = 0,
+	.ident_start_idx = 31,
+	.ident_nums = 2
+	},
+	{
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+	.direction = TF_DIR_RX,
+	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
+	.key_start_idx = 1164,
+	.blob_key_bit_size = 81,
+	.key_bit_size = 81,
+	.key_num_fields = 43,
+	.result_start_idx = 810,
+	.result_bit_size = 38,
+	.result_num_fields = 8,
+	.encap_num_fields = 0,
+	.ident_start_idx = 33,
+	.ident_nums = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
+	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
+	},
+	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE,
 	.resource_type = TF_MEM_INTERNAL,
 	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT,
-	.direction = TF_DIR_TX,
-	.key_start_idx = 1155,
-	.blob_key_bit_size = 200,
-	.key_bit_size = 200,
-	.key_num_fields = 11,
-	.result_start_idx = 800,
+	.direction = TF_DIR_RX,
+	.key_start_idx = 1207,
+	.blob_key_bit_size = 112,
+	.key_bit_size = 112,
+	.key_num_fields = 8,
+	.result_start_idx = 818,
 	.result_bit_size = 64,
 	.result_num_fields = 9,
 	.encap_num_fields = 0,
-	.ident_start_idx = 29,
+	.ident_start_idx = 33,
 	.ident_nums = 0,
-	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
+	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES
+	},
+	{
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE,
+	.resource_type = TF_MEM_EXTERNAL,
+	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT,
+	.direction = TF_DIR_RX,
+	.key_start_idx = 1215,
+	.blob_key_bit_size = 448,
+	.key_bit_size = 448,
+	.key_num_fields = 8,
+	.result_start_idx = 827,
+	.result_bit_size = 64,
+	.result_num_fields = 9,
+	.encap_num_fields = 0,
+	.ident_start_idx = 33,
+	.ident_nums = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES
 	},
 	{
@@ -1824,32 +1915,32 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1166,
+	.key_start_idx = 1223,
 	.blob_key_bit_size = 12,
 	.key_bit_size = 12,
 	.key_num_fields = 1,
-	.result_start_idx = 809,
+	.result_start_idx = 836,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
-	.ident_start_idx = 29,
+	.ident_start_idx = 33,
 	.ident_nums = 1
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
 	.direction = TF_DIR_TX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 1167,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
+	.key_start_idx = 1224,
 	.blob_key_bit_size = 171,
 	.key_bit_size = 171,
 	.key_num_fields = 13,
-	.result_start_idx = 810,
+	.result_start_idx = 837,
 	.result_bit_size = 64,
 	.result_num_fields = 13,
 	.encap_num_fields = 0,
-	.ident_start_idx = 30,
+	.ident_start_idx = 34,
 	.ident_nums = 0,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
@@ -1860,32 +1951,32 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1180,
+	.key_start_idx = 1237,
 	.blob_key_bit_size = 16,
 	.key_bit_size = 16,
 	.key_num_fields = 3,
-	.result_start_idx = 823,
+	.result_start_idx = 850,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
-	.ident_start_idx = 30,
+	.ident_start_idx = 34,
 	.ident_nums = 1
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
 	.direction = TF_DIR_TX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 1183,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
+	.key_start_idx = 1240,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
 	.key_num_fields = 43,
-	.result_start_idx = 824,
+	.result_start_idx = 851,
 	.result_bit_size = 38,
 	.result_num_fields = 8,
 	.encap_num_fields = 0,
-	.ident_start_idx = 31,
+	.ident_start_idx = 35,
 	.ident_nums = 0,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
@@ -1895,15 +1986,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_type = TF_MEM_EXTERNAL,
 	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1226,
+	.key_start_idx = 1283,
 	.blob_key_bit_size = 448,
 	.key_bit_size = 448,
 	.key_num_fields = 11,
-	.result_start_idx = 832,
+	.result_start_idx = 859,
 	.result_bit_size = 64,
 	.result_num_fields = 9,
 	.encap_num_fields = 0,
-	.ident_start_idx = 31,
+	.ident_start_idx = 35,
 	.ident_nums = 0,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES
@@ -1913,15 +2004,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_type = TF_MEM_INTERNAL,
 	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1237,
+	.key_start_idx = 1294,
 	.blob_key_bit_size = 200,
 	.key_bit_size = 200,
 	.key_num_fields = 11,
-	.result_start_idx = 841,
+	.result_start_idx = 868,
 	.result_bit_size = 64,
 	.result_num_fields = 9,
 	.encap_num_fields = 0,
-	.ident_start_idx = 31,
+	.ident_start_idx = 35,
 	.ident_nums = 0,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES
@@ -1932,32 +2023,32 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1248,
+	.key_start_idx = 1305,
 	.blob_key_bit_size = 12,
 	.key_bit_size = 12,
 	.key_num_fields = 1,
-	.result_start_idx = 850,
+	.result_start_idx = 877,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
-	.ident_start_idx = 31,
+	.ident_start_idx = 35,
 	.ident_nums = 1
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
 	.direction = TF_DIR_TX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 1249,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
+	.key_start_idx = 1306,
 	.blob_key_bit_size = 171,
 	.key_bit_size = 171,
 	.key_num_fields = 13,
-	.result_start_idx = 851,
+	.result_start_idx = 878,
 	.result_bit_size = 64,
 	.result_num_fields = 13,
 	.encap_num_fields = 0,
-	.ident_start_idx = 32,
+	.ident_start_idx = 36,
 	.ident_nums = 0,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
@@ -1968,32 +2059,32 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1262,
+	.key_start_idx = 1319,
 	.blob_key_bit_size = 16,
 	.key_bit_size = 16,
 	.key_num_fields = 3,
-	.result_start_idx = 864,
+	.result_start_idx = 891,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
-	.ident_start_idx = 32,
+	.ident_start_idx = 36,
 	.ident_nums = 1
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
 	.direction = TF_DIR_TX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 1265,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
+	.key_start_idx = 1322,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
 	.key_num_fields = 43,
-	.result_start_idx = 865,
+	.result_start_idx = 892,
 	.result_bit_size = 38,
 	.result_num_fields = 8,
 	.encap_num_fields = 0,
-	.ident_start_idx = 33,
+	.ident_start_idx = 37,
 	.ident_nums = 0,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
@@ -2003,15 +2094,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_type = TF_MEM_EXTERNAL,
 	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1308,
+	.key_start_idx = 1365,
 	.blob_key_bit_size = 448,
 	.key_bit_size = 448,
 	.key_num_fields = 11,
-	.result_start_idx = 873,
+	.result_start_idx = 900,
 	.result_bit_size = 64,
 	.result_num_fields = 9,
 	.encap_num_fields = 0,
-	.ident_start_idx = 33,
+	.ident_start_idx = 37,
 	.ident_nums = 0,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES
@@ -2021,15 +2112,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_type = TF_MEM_INTERNAL,
 	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1319,
-	.blob_key_bit_size = 392,
-	.key_bit_size = 392,
+	.key_start_idx = 1376,
+	.blob_key_bit_size = 200,
+	.key_bit_size = 200,
 	.key_num_fields = 11,
-	.result_start_idx = 882,
+	.result_start_idx = 909,
 	.result_bit_size = 64,
 	.result_num_fields = 9,
 	.encap_num_fields = 0,
-	.ident_start_idx = 33,
+	.ident_start_idx = 37,
 	.ident_nums = 0,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES
@@ -2040,32 +2131,32 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1330,
+	.key_start_idx = 1387,
 	.blob_key_bit_size = 12,
 	.key_bit_size = 12,
 	.key_num_fields = 1,
-	.result_start_idx = 891,
+	.result_start_idx = 918,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
-	.ident_start_idx = 33,
+	.ident_start_idx = 37,
 	.ident_nums = 1
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
 	.direction = TF_DIR_TX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 1331,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
+	.key_start_idx = 1388,
 	.blob_key_bit_size = 171,
 	.key_bit_size = 171,
 	.key_num_fields = 13,
-	.result_start_idx = 892,
+	.result_start_idx = 919,
 	.result_bit_size = 64,
 	.result_num_fields = 13,
 	.encap_num_fields = 0,
-	.ident_start_idx = 34,
+	.ident_start_idx = 38,
 	.ident_nums = 0,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
@@ -2076,32 +2167,140 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1344,
+	.key_start_idx = 1401,
 	.blob_key_bit_size = 16,
 	.key_bit_size = 16,
 	.key_num_fields = 3,
-	.result_start_idx = 905,
+	.result_start_idx = 932,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
-	.ident_start_idx = 34,
+	.ident_start_idx = 38,
 	.ident_nums = 1
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
 	.direction = TF_DIR_TX,
+	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
+	.key_start_idx = 1404,
+	.blob_key_bit_size = 81,
+	.key_bit_size = 81,
+	.key_num_fields = 43,
+	.result_start_idx = 933,
+	.result_bit_size = 38,
+	.result_num_fields = 8,
+	.encap_num_fields = 0,
+	.ident_start_idx = 39,
+	.ident_nums = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
+	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
+	},
+	{
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE,
+	.resource_type = TF_MEM_EXTERNAL,
+	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT,
+	.direction = TF_DIR_TX,
+	.key_start_idx = 1447,
+	.blob_key_bit_size = 448,
+	.key_bit_size = 448,
+	.key_num_fields = 11,
+	.result_start_idx = 941,
+	.result_bit_size = 64,
+	.result_num_fields = 9,
+	.encap_num_fields = 0,
+	.ident_start_idx = 39,
+	.ident_nums = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION,
+	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES
+	},
+	{
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE,
+	.resource_type = TF_MEM_INTERNAL,
+	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT,
+	.direction = TF_DIR_TX,
+	.key_start_idx = 1458,
+	.blob_key_bit_size = 392,
+	.key_bit_size = 392,
+	.key_num_fields = 11,
+	.result_start_idx = 950,
+	.result_bit_size = 64,
+	.result_num_fields = 9,
+	.encap_num_fields = 0,
+	.ident_start_idx = 39,
+	.ident_nums = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION,
+	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES
+	},
+	{
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE,
+	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+	.resource_sub_type =
+		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM,
+	.direction = TF_DIR_TX,
+	.key_start_idx = 1469,
+	.blob_key_bit_size = 12,
+	.key_bit_size = 12,
+	.key_num_fields = 1,
+	.result_start_idx = 959,
+	.result_bit_size = 10,
+	.result_num_fields = 1,
+	.encap_num_fields = 0,
+	.ident_start_idx = 39,
+	.ident_nums = 1
+	},
+	{
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
+	.direction = TF_DIR_TX,
+	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
 	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
+	.key_start_idx = 1470,
+	.blob_key_bit_size = 171,
+	.key_bit_size = 171,
+	.key_num_fields = 13,
+	.result_start_idx = 960,
+	.result_bit_size = 64,
+	.result_num_fields = 13,
+	.encap_num_fields = 0,
+	.ident_start_idx = 40,
+	.ident_nums = 0,
+	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
+	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
+	},
+	{
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE,
+	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+	.resource_sub_type =
+		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
+	.direction = TF_DIR_TX,
+	.key_start_idx = 1483,
+	.blob_key_bit_size = 16,
+	.key_bit_size = 16,
+	.key_num_fields = 3,
+	.result_start_idx = 973,
+	.result_bit_size = 10,
+	.result_num_fields = 1,
+	.encap_num_fields = 0,
+	.ident_start_idx = 40,
+	.ident_nums = 1
+	},
+	{
+	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+	.direction = TF_DIR_TX,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 1347,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
+	.key_start_idx = 1486,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
 	.key_num_fields = 43,
-	.result_start_idx = 906,
+	.result_start_idx = 974,
 	.result_bit_size = 38,
 	.result_num_fields = 8,
 	.encap_num_fields = 0,
-	.ident_start_idx = 35,
+	.ident_start_idx = 41,
 	.ident_nums = 0,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
@@ -2111,15 +2310,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_type = TF_MEM_EXTERNAL,
 	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1390,
+	.key_start_idx = 1529,
 	.blob_key_bit_size = 448,
 	.key_bit_size = 448,
 	.key_num_fields = 11,
-	.result_start_idx = 914,
+	.result_start_idx = 982,
 	.result_bit_size = 64,
 	.result_num_fields = 9,
 	.encap_num_fields = 0,
-	.ident_start_idx = 35,
+	.ident_start_idx = 41,
 	.ident_nums = 0,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES
@@ -2129,15 +2328,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_type = TF_MEM_INTERNAL,
 	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1401,
+	.key_start_idx = 1540,
 	.blob_key_bit_size = 392,
 	.key_bit_size = 392,
 	.key_num_fields = 11,
-	.result_start_idx = 923,
+	.result_start_idx = 991,
 	.result_bit_size = 64,
 	.result_num_fields = 9,
 	.encap_num_fields = 0,
-	.ident_start_idx = 35,
+	.ident_start_idx = 41,
 	.ident_nums = 0,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES
@@ -2146,17 +2345,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
 	.direction = TF_DIR_TX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_UPDATE,
-	.key_start_idx = 1412,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
+	.key_start_idx = 1551,
 	.blob_key_bit_size = 171,
 	.key_bit_size = 171,
 	.key_num_fields = 13,
-	.result_start_idx = 932,
+	.result_start_idx = 1000,
 	.result_bit_size = 64,
 	.result_num_fields = 13,
 	.encap_num_fields = 0,
-	.ident_start_idx = 35,
+	.ident_start_idx = 41,
 	.ident_nums = 1,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
@@ -2167,32 +2366,32 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1425,
+	.key_start_idx = 1564,
 	.blob_key_bit_size = 16,
 	.key_bit_size = 16,
 	.key_num_fields = 3,
-	.result_start_idx = 945,
+	.result_start_idx = 1013,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
-	.ident_start_idx = 36,
+	.ident_start_idx = 42,
 	.ident_nums = 1
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
 	.direction = TF_DIR_TX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 1428,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
+	.key_start_idx = 1567,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
 	.key_num_fields = 43,
-	.result_start_idx = 946,
+	.result_start_idx = 1014,
 	.result_bit_size = 38,
 	.result_num_fields = 8,
 	.encap_num_fields = 0,
-	.ident_start_idx = 37,
+	.ident_start_idx = 43,
 	.ident_nums = 0,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
@@ -2202,15 +2401,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_type = TF_MEM_EXTERNAL,
 	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1471,
+	.key_start_idx = 1610,
 	.blob_key_bit_size = 448,
 	.key_bit_size = 448,
 	.key_num_fields = 7,
-	.result_start_idx = 954,
+	.result_start_idx = 1022,
 	.result_bit_size = 64,
 	.result_num_fields = 9,
 	.encap_num_fields = 0,
-	.ident_start_idx = 37,
+	.ident_start_idx = 43,
 	.ident_nums = 0,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES
@@ -2220,15 +2419,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_type = TF_MEM_INTERNAL,
 	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1478,
+	.key_start_idx = 1617,
 	.blob_key_bit_size = 104,
 	.key_bit_size = 104,
 	.key_num_fields = 7,
-	.result_start_idx = 963,
+	.result_start_idx = 1031,
 	.result_bit_size = 64,
 	.result_num_fields = 9,
 	.encap_num_fields = 0,
-	.ident_start_idx = 37,
+	.ident_start_idx = 43,
 	.ident_nums = 0,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES
@@ -2237,17 +2436,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH,
 	.direction = TF_DIR_TX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_SEARCH_IF_HIT_UPDATE,
-	.key_start_idx = 1485,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
+	.key_start_idx = 1624,
 	.blob_key_bit_size = 171,
 	.key_bit_size = 171,
 	.key_num_fields = 13,
-	.result_start_idx = 972,
+	.result_start_idx = 1040,
 	.result_bit_size = 64,
 	.result_num_fields = 13,
 	.encap_num_fields = 0,
-	.ident_start_idx = 37,
+	.ident_start_idx = 43,
 	.ident_nums = 1,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
@@ -2258,32 +2457,32 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_sub_type =
 		BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1498,
+	.key_start_idx = 1637,
 	.blob_key_bit_size = 16,
 	.key_bit_size = 16,
 	.key_num_fields = 3,
-	.result_start_idx = 985,
+	.result_start_idx = 1053,
 	.result_bit_size = 10,
 	.result_num_fields = 1,
 	.encap_num_fields = 0,
-	.ident_start_idx = 38,
+	.ident_start_idx = 44,
 	.ident_nums = 1
 	},
 	{
 	.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
 	.resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
 	.direction = TF_DIR_TX,
-	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
 	.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
-	.key_start_idx = 1501,
+	.priority = BNXT_ULP_PRIORITY_LEVEL_0,
+	.key_start_idx = 1640,
 	.blob_key_bit_size = 81,
 	.key_bit_size = 81,
 	.key_num_fields = 43,
-	.result_start_idx = 986,
+	.result_start_idx = 1054,
 	.result_bit_size = 38,
 	.result_num_fields = 8,
 	.encap_num_fields = 0,
-	.ident_start_idx = 39,
+	.ident_start_idx = 45,
 	.ident_nums = 0,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
@@ -2293,15 +2492,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_type = TF_MEM_EXTERNAL,
 	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_EXT,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1544,
+	.key_start_idx = 1683,
 	.blob_key_bit_size = 448,
 	.key_bit_size = 448,
 	.key_num_fields = 7,
-	.result_start_idx = 994,
+	.result_start_idx = 1062,
 	.result_bit_size = 64,
 	.result_num_fields = 9,
 	.encap_num_fields = 0,
-	.ident_start_idx = 39,
+	.ident_start_idx = 45,
 	.ident_nums = 0,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES
@@ -2311,15 +2510,15 @@ struct bnxt_ulp_mapper_tbl_info ulp_stingray_class_tbl_list[] = {
 	.resource_type = TF_MEM_INTERNAL,
 	.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPCODE_EXECUTE_IF_INT,
 	.direction = TF_DIR_TX,
-	.key_start_idx = 1551,
+	.key_start_idx = 1690,
 	.blob_key_bit_size = 104,
 	.key_bit_size = 104,
 	.key_num_fields = 7,
-	.result_start_idx = 1003,
+	.result_start_idx = 1071,
 	.result_bit_size = 64,
 	.result_num_fields = 9,
 	.encap_num_fields = 0,
-	.ident_start_idx = 39,
+	.ident_start_idx = 45,
 	.ident_nums = 0,
 	.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
 	.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES
@@ -9156,68 +9355,1047 @@ struct bnxt_ulp_mapper_key_field_info ulp_stingray_class_key_field_list[] = {
 	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
 	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
 	.spec_operand = {
-		(BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
-		BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
+		(BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
+		BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 3,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 3,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 16,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 16,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 8,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_operand = {
+		BNXT_ULP_SYM_IP_PROTO_UDP,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 32,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+	.spec_operand = {
+		(BNXT_ULP_HF16_IDX_O_IPV4_DST_ADDR >> 8) & 0xff,
+		BNXT_ULP_HF16_IDX_O_IPV4_DST_ADDR & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 32,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 48,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 24,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 10,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+	.spec_operand = {
+		(BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
+		BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 8,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+	.spec_operand = {
+		(BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
+		BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 12,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 12,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 48,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+	.spec_operand = {
+		(BNXT_ULP_HF17_IDX_O_ETH_DMAC >> 8) & 0xff,
+		BNXT_ULP_HF17_IDX_O_ETH_DMAC & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 12,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+	.mask_operand = {
+		(BNXT_ULP_HF17_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF17_IDX_SVIF_INDEX & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+	.spec_operand = {
+		(BNXT_ULP_HF17_IDX_SVIF_INDEX >> 8) & 0xff,
+		BNXT_ULP_HF17_IDX_SVIF_INDEX & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 12,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+	.mask_operand = {
+		(BNXT_ULP_HF17_IDX_OO_VLAN_VID >> 8) & 0xff,
+		BNXT_ULP_HF17_IDX_OO_VLAN_VID & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+	.spec_operand = {
+		(BNXT_ULP_HF17_IDX_OO_VLAN_VID >> 8) & 0xff,
+		BNXT_ULP_HF17_IDX_OO_VLAN_VID & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 12,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 48,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD,
+	.spec_operand = {
+		(BNXT_ULP_CF_IDX_O_VTAG_NUM >> 8) & 0xff,
+		BNXT_ULP_CF_IDX_O_VTAG_NUM & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 4,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 4,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 7,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE,
+	.spec_operand = {
+		(BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID >> 8) & 0xff,
+		BNXT_ULP_GLB_REGFILE_INDEX_VXLAN_PROF_FUNC_ID & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 8,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+	.spec_operand = {
+		(BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff,
+		BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 4,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 4,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 2,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 3,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 4,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_operand = {
+		BNXT_ULP_SYM_TUN_HDR_VALID_YES,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+	},
+	{
+	.field_bit_size = 4,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+		0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+	.spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.spec_operand = {
+		BNXT_ULP_SYM_TL4_HDR_TYPE_UDP,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+	},
+	{
+	.field_bit_size = 1,
+	.mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+	.mask_operand = {0xff, 0xff, 0xff, 0xff,