From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2015DA04DD; Thu, 22 Oct 2020 14:24:53 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 940FDA9DE; Thu, 22 Oct 2020 14:24:39 +0200 (CEST) Received: from dispatch1-us1.ppe-hosted.com (dispatch1-us1.ppe-hosted.com [148.163.129.52]) by dpdk.org (Postfix) with ESMTP id 151C1A9D0 for ; Thu, 22 Oct 2020 14:24:35 +0200 (CEST) Received: from mx1-us1.ppe-hosted.com (unknown [10.7.65.64]) by dispatch1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTP id 6D23860058 for ; Thu, 22 Oct 2020 12:24:33 +0000 (UTC) Received: from us4-mdac16-57.ut7.mdlocal (unknown [10.7.66.28]) by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTP id 6BA902009B for ; Thu, 22 Oct 2020 12:24:33 +0000 (UTC) X-Virus-Scanned: Proofpoint Essentials engine Received: from mx1-us1.ppe-hosted.com (unknown [10.7.65.174]) by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTPS id E1EB622005A for ; Thu, 22 Oct 2020 12:24:32 +0000 (UTC) Received: from webmail.solarflare.com (uk.solarflare.com [193.34.186.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits)) (No client certificate requested) by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTPS id 97CB71C006C for ; Thu, 22 Oct 2020 12:24:32 +0000 (UTC) Received: from ukex01.SolarFlarecom.com (10.17.10.4) by ukex01.SolarFlarecom.com (10.17.10.4) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 22 Oct 2020 13:24:28 +0100 Received: from opal.uk.solarflarecom.com (10.17.10.1) by ukex01.SolarFlarecom.com (10.17.10.4) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 22 Oct 2020 13:24:28 +0100 Received: from ukv-loginhost.uk.solarflarecom.com (ukv-loginhost.uk.solarflarecom.com [10.17.10.39]) by opal.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id 09MCOS1r029638 for ; Thu, 22 Oct 2020 13:24:28 +0100 Received: from ukv-loginhost.uk.solarflarecom.com (localhost [127.0.0.1]) by ukv-loginhost.uk.solarflarecom.com (Postfix) with ESMTP id 85E4E1613A9 for ; Thu, 22 Oct 2020 13:24:28 +0100 (BST) From: Andrew Rybchenko To: Date: Thu, 22 Oct 2020 13:24:05 +0100 Message-ID: <1603369447-28388-1-git-send-email-arybchenko@solarflare.com> X-Mailer: git-send-email 1.8.3.1 MIME-Version: 1.0 Content-Type: text/plain X-TM-AS-Product-Ver: SMEX-12.5.0.1300-8.6.1012-25740.003 X-TM-AS-Result: No-2.693700-8.000000-10 X-TMASE-MatchedRID: 1raMuI08qFAkliX1XDb78v3HILfxLV/92zgw5RT/BrZwkdIrVt8X1VDT Kayi2ZF67TB5f11dq/CS0G1KLf4rriHhSBQfglfsA9lly13c/gEs9Im7mOi/ZkdmDSBYfnJR1dW 4zIn6LEQRfYKA8Vd86IAy6p60ZV62fJ5/bZ6npdjGVuWouVipck7l+O/PfELscK2hp1tASaFjo5 netu8UbU7a78OFV7U2jvYNl5oMTtSAtV8gOt8g9sYC1/CHK1Rp8sNzf98zgzs5niWVN5NzK0+9n KAUfbd9OiMMfiztpo/4XWZPvl2TZLAodBnVXNL5k0Q6cxt5OvU= X-TM-AS-User-Approved-Sender: Yes X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--2.693700-8.000000 X-TMASE-Version: SMEX-12.5.0.1300-8.6.1012-25740.003 X-MDID: 1603369473-tfKesUTbPIGW X-PPE-DISP: 1603369473;tfKesUTbPIGW Subject: [dpdk-dev] [PATCH 1/3] common/sfc_efx: introduce 128-bit unsigned integer compat X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Intel SSE has __m128i, but ARMv8 has __uint128_t. So, add compat efsys_uint128_t to be used in driver source and have either __u128i or __uint128_t behind. Signed-off-by: Andrew Rybchenko Reviewed-by: Andy Moreton --- drivers/common/sfc_efx/base/efx_types.h | 8 ++++---- drivers/common/sfc_efx/efsys.h | 19 ++++++++++--------- 2 files changed, 14 insertions(+), 13 deletions(-) diff --git a/drivers/common/sfc_efx/base/efx_types.h b/drivers/common/sfc_efx/base/efx_types.h index f7ec9a7..d67d07b 100644 --- a/drivers/common/sfc_efx/base/efx_types.h +++ b/drivers/common/sfc_efx/base/efx_types.h @@ -221,8 +221,8 @@ efx_word_t eo_word[8]; efx_dword_t eo_dword[4]; efx_qword_t eo_qword[2]; -#if EFSYS_HAS_SSE2_M128 - __m128i eo_u128[1]; +#if EFSYS_HAS_UINT128 + efsys_uint128_t eo_u128[1]; #endif #if EFSYS_HAS_UINT64 uint64_t eo_u64[2]; @@ -243,8 +243,8 @@ efx_dword_t ex_dword[8]; efx_qword_t ex_qword[4]; efx_oword_t ex_oword[2]; -#if EFSYS_HAS_SSE2_M128 - __m128i ex_u128[2]; +#if EFSYS_HAS_UINT128 + efsys_uint128_t ex_u128[2]; #endif #if EFSYS_HAS_UINT64 uint64_t ex_u64[4]; diff --git a/drivers/common/sfc_efx/efsys.h b/drivers/common/sfc_efx/efsys.h index bbe9f2e..139f4d8 100644 --- a/drivers/common/sfc_efx/efsys.h +++ b/drivers/common/sfc_efx/efsys.h @@ -39,7 +39,8 @@ #define EFSYS_HAS_UINT64 1 #define EFSYS_USE_UINT64 1 -#define EFSYS_HAS_SSE2_M128 1 +#define EFSYS_HAS_UINT128 1 +typedef __m128i efsys_uint128_t; #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN #define EFSYS_IS_BIG_ENDIAN 1 @@ -272,13 +273,13 @@ #define EFSYS_MEM_READO(_esmp, _offset, _eop) \ do { \ volatile uint8_t *_base = (_esmp)->esm_base; \ - volatile __m128i *_addr; \ + volatile efsys_uint128_t *_addr; \ \ _NOTE(CONSTANTCONDITION); \ SFC_EFX_ASSERT(EFX_IS_P2ALIGNED(size_t, _offset, \ sizeof(efx_oword_t))); \ \ - _addr = (volatile __m128i *)(_base + (_offset)); \ + _addr = (volatile efsys_uint128_t *)(_base + (_offset));\ (_eop)->eo_u128[0] = _addr[0]; \ \ EFSYS_PROBE5(mem_reado, unsigned int, (_offset), \ @@ -331,7 +332,7 @@ #define EFSYS_MEM_WRITEO(_esmp, _offset, _eop) \ do { \ volatile uint8_t *_base = (_esmp)->esm_base; \ - volatile __m128i *_addr; \ + volatile efsys_uint128_t *_addr; \ \ _NOTE(CONSTANTCONDITION); \ SFC_EFX_ASSERT(EFX_IS_P2ALIGNED(size_t, _offset, \ @@ -344,7 +345,7 @@ uint32_t, (_eop)->eo_u32[1], \ uint32_t, (_eop)->eo_u32[0]); \ \ - _addr = (volatile __m128i *)(_base + (_offset)); \ + _addr = (volatile efsys_uint128_t *)(_base + (_offset));\ _addr[0] = (_eop)->eo_u128[0]; \ \ _NOTE(CONSTANTCONDITION); \ @@ -445,7 +446,7 @@ #define EFSYS_BAR_READO(_esbp, _offset, _eop, _lock) \ do { \ volatile uint8_t *_base = (_esbp)->esb_base; \ - volatile __m128i *_addr; \ + volatile efsys_uint128_t *_addr; \ \ _NOTE(CONSTANTCONDITION); \ SFC_EFX_ASSERT(EFX_IS_P2ALIGNED(size_t, _offset, \ @@ -455,7 +456,7 @@ if (_lock) \ SFC_BAR_LOCK(_esbp); \ \ - _addr = (volatile __m128i *)(_base + (_offset)); \ + _addr = (volatile efsys_uint128_t *)(_base + (_offset));\ rte_rmb(); \ /* There is no rte_read128_relaxed() yet */ \ (_eop)->eo_u128[0] = _addr[0]; \ @@ -537,7 +538,7 @@ #define EFSYS_BAR_WRITEO(_esbp, _offset, _eop, _lock) \ do { \ volatile uint8_t *_base = (_esbp)->esb_base; \ - volatile __m128i *_addr; \ + volatile efsys_uint128_t *_addr; \ \ _NOTE(CONSTANTCONDITION); \ SFC_EFX_ASSERT(EFX_IS_P2ALIGNED(size_t, _offset, \ @@ -553,7 +554,7 @@ uint32_t, (_eop)->eo_u32[1], \ uint32_t, (_eop)->eo_u32[0]); \ \ - _addr = (volatile __m128i *)(_base + (_offset)); \ + _addr = (volatile efsys_uint128_t *)(_base + (_offset));\ /* There is no rte_write128_relaxed() yet */ \ _addr[0] = (_eop)->eo_u128[0]; \ rte_wmb(); \ -- 1.8.3.1