From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 358A3A04DD; Thu, 5 Nov 2020 15:23:03 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 3092FC80C; Thu, 5 Nov 2020 15:23:01 +0100 (CET) Received: from szxga05-in.huawei.com (szxga05-in.huawei.com [45.249.212.191]) by dpdk.org (Postfix) with ESMTP id 3001ABE45 for ; Thu, 5 Nov 2020 15:23:00 +0100 (CET) Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.60]) by szxga05-in.huawei.com (SkyGuard) with ESMTP id 4CRm2L255XzLrG1 for ; Thu, 5 Nov 2020 22:22:50 +0800 (CST) Received: from localhost.localdomain (10.69.192.56) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.487.0; Thu, 5 Nov 2020 22:22:47 +0800 From: Lijun Ou To: CC: , Date: Thu, 5 Nov 2020 22:23:13 +0800 Message-ID: <1604586194-29523-5-git-send-email-oulijun@huawei.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1604586194-29523-1-git-send-email-oulijun@huawei.com> References: <1604586194-29523-1-git-send-email-oulijun@huawei.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.69.192.56] X-CFilter-Loop: Reflected Subject: [dpdk-dev] [PATCH 4/5] net/hns3: check PCI config space writes X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Here adds a check for the return value when calling rte_pci_wirte_config. Coverity issue: 363714 Fixes: cea37e513329 ("net/hns3: fix FLR reset") Cc: stable@dpdk.org Signed-off-by: Lijun Ou --- drivers/net/hns3/hns3_ethdev_vf.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c index 2e9bfda..2f6d91b 100644 --- a/drivers/net/hns3/hns3_ethdev_vf.c +++ b/drivers/net/hns3/hns3_ethdev_vf.c @@ -139,7 +139,7 @@ hns3vf_enable_msix(const struct rte_pci_device *device, bool op) ret = rte_pci_read_config(device, &control, sizeof(control), (pos + PCI_MSIX_FLAGS)); if (ret < 0) { - PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", + PMD_INIT_LOG(ERR, "failed to read PCI offset 0x%x", (pos + PCI_MSIX_FLAGS)); return -ENXIO; } @@ -148,8 +148,12 @@ hns3vf_enable_msix(const struct rte_pci_device *device, bool op) control |= PCI_MSIX_FLAGS_ENABLE; else control &= ~PCI_MSIX_FLAGS_ENABLE; - rte_pci_write_config(device, &control, sizeof(control), - (pos + PCI_MSIX_FLAGS)); + ret = rte_pci_write_config(device, &control, sizeof(control), + (pos + PCI_MSIX_FLAGS)); + if (ret < 0) { + PMD_INIT_LOG(ERR, "failed to write PCI offset 0x%x", + (pos + PCI_MSIX_FLAGS)); + } return 0; } return -ENXIO; -- 2.7.4