From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id E7BFCA04DD; Tue, 10 Nov 2020 17:04:30 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id BB1E9F64; Tue, 10 Nov 2020 17:04:29 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by dpdk.org (Postfix) with ESMTP id 5F44EF64 for ; Tue, 10 Nov 2020 17:04:27 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from viacheslavo@nvidia.com) with SMTP; 10 Nov 2020 18:04:23 +0200 Received: from nvidia.com (pegasus12.mtr.labs.mlnx [10.210.17.40]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 0AAG4L94012156; Tue, 10 Nov 2020 18:04:23 +0200 From: Viacheslav Ovsiienko To: dev@dpdk.org Cc: rasland@nvidia.com, matan@nvidia.com, stable@dpdk.org Date: Tue, 10 Nov 2020 16:04:17 +0000 Message-Id: <1605024259-18318-2-git-send-email-viacheslavo@nvidia.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1605024259-18318-1-git-send-email-viacheslavo@nvidia.com> References: <1605024259-18318-1-git-send-email-viacheslavo@nvidia.com> Subject: [dpdk-dev] [PATCH 2/4] regex/mlx5: fix UAR allocation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch provides the UAR allocation workaround for the hosts where UAR allocation with Write-Combining memory mapping type fails. Fixes: b34d816363b5 ("regex/mlx5: support rules import") Cc: stable@dpdk.org Signed-off-by: Viacheslav Ovsiienko Acked-by: Matan Azrad --- drivers/regex/mlx5/mlx5_regex.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/regex/mlx5/mlx5_regex.c b/drivers/regex/mlx5/mlx5_regex.c index 17590b9..05048e7 100644 --- a/drivers/regex/mlx5/mlx5_regex.c +++ b/drivers/regex/mlx5/mlx5_regex.c @@ -176,7 +176,12 @@ rte_errno = ENOMEM; goto error; } - priv->uar = mlx5_glue->devx_alloc_uar(ctx, 0); + /* + * This PMD always claims the write memory barrier on UAR + * registers writings, it is safe to allocate UAR with any + * memory mapping type. + */ + priv->uar = mlx5_devx_alloc_uar(ctx, -1); if (!priv->uar) { DRV_LOG(ERR, "can't allocate uar."); rte_errno = ENOMEM; -- 1.8.3.1