[dpdk-dev] [PATCH v2 27/27] event/dlb2: Change device name to dlb_event

[Timothy McDaniel <timothy.mcdaniel@intel.com>]

Updated eventdev device name to be dlb_event instead of
dlb2_event.  The new name will be used for all versions
of the DLB hardware. This change required corresponding changes
to the the directory name that contains the PMD, as well
as the documentation files, build infrastructure, and PMD
specific APIs.

Signed-off-by: Timothy McDaniel <timothy.mcdaniel@intel.com>
---
 MAINTAINERS                                   |   6 +-
 app/test/test_eventdev.c                      |   6 +-
 config/rte_config.h                           |  11 +-
 doc/api/doxy-api-index.md                     |   2 +-
 doc/api/doxy-api.conf.in                      |   2 +-
 doc/guides/eventdevs/dlb.rst                  | 390 ++++++++++++++++++
 doc/guides/eventdevs/index.rst                |   2 +-
 doc/guides/rel_notes/release_21_05.rst        |   5 +
 drivers/event/{dlb2 => dlb}/dlb2.c            |  25 +-
 drivers/event/{dlb2 => dlb}/dlb2_iface.c      |   0
 drivers/event/{dlb2 => dlb}/dlb2_iface.h      |   0
 drivers/event/{dlb2 => dlb}/dlb2_inline_fns.h |   0
 drivers/event/{dlb2 => dlb}/dlb2_log.h        |   0
 drivers/event/{dlb2 => dlb}/dlb2_priv.h       |   7 +-
 drivers/event/{dlb2 => dlb}/dlb2_selftest.c   |   8 +-
 drivers/event/{dlb2 => dlb}/dlb2_user.h       |   0
 drivers/event/{dlb2 => dlb}/dlb2_xstats.c     |   0
 drivers/event/{dlb2 => dlb}/meson.build       |   4 +-
 .../{dlb2 => dlb}/pf/base/dlb2_hw_types.h     |   0
 .../event/{dlb2 => dlb}/pf/base/dlb2_osdep.h  |   0
 .../{dlb2 => dlb}/pf/base/dlb2_osdep_bitmap.h |   0
 .../{dlb2 => dlb}/pf/base/dlb2_osdep_list.h   |   0
 .../{dlb2 => dlb}/pf/base/dlb2_osdep_types.h  |   0
 .../event/{dlb2 => dlb}/pf/base/dlb2_regs.h   |   0
 .../{dlb2 => dlb}/pf/base/dlb2_resource.c     |   0
 .../{dlb2 => dlb}/pf/base/dlb2_resource.h     |   0
 drivers/event/{dlb2 => dlb}/pf/dlb2_main.c    |   0
 drivers/event/{dlb2 => dlb}/pf/dlb2_main.h    |   0
 drivers/event/{dlb2 => dlb}/pf/dlb2_pf.c      |   0
 .../rte_pmd_dlb2.c => dlb/rte_pmd_dlb.c}      |   6 +-
 .../rte_pmd_dlb2.h => dlb/rte_pmd_dlb.h}      |  12 +-
 drivers/event/{dlb2 => dlb}/version.map       |   2 +-
 drivers/event/meson.build                     |   2 +-
 33 files changed, 440 insertions(+), 50 deletions(-)
 create mode 100644 doc/guides/eventdevs/dlb.rst
 rename drivers/event/{dlb2 => dlb}/dlb2.c (99%)
 rename drivers/event/{dlb2 => dlb}/dlb2_iface.c (100%)
 rename drivers/event/{dlb2 => dlb}/dlb2_iface.h (100%)
 rename drivers/event/{dlb2 => dlb}/dlb2_inline_fns.h (100%)
 rename drivers/event/{dlb2 => dlb}/dlb2_log.h (100%)
 rename drivers/event/{dlb2 => dlb}/dlb2_priv.h (99%)
 rename drivers/event/{dlb2 => dlb}/dlb2_selftest.c (99%)
 rename drivers/event/{dlb2 => dlb}/dlb2_user.h (100%)
 rename drivers/event/{dlb2 => dlb}/dlb2_xstats.c (100%)
 rename drivers/event/{dlb2 => dlb}/meson.build (89%)
 rename drivers/event/{dlb2 => dlb}/pf/base/dlb2_hw_types.h (100%)
 rename drivers/event/{dlb2 => dlb}/pf/base/dlb2_osdep.h (100%)
 rename drivers/event/{dlb2 => dlb}/pf/base/dlb2_osdep_bitmap.h (100%)
 rename drivers/event/{dlb2 => dlb}/pf/base/dlb2_osdep_list.h (100%)
 rename drivers/event/{dlb2 => dlb}/pf/base/dlb2_osdep_types.h (100%)
 rename drivers/event/{dlb2 => dlb}/pf/base/dlb2_regs.h (100%)
 rename drivers/event/{dlb2 => dlb}/pf/base/dlb2_resource.c (100%)
 rename drivers/event/{dlb2 => dlb}/pf/base/dlb2_resource.h (100%)
 rename drivers/event/{dlb2 => dlb}/pf/dlb2_main.c (100%)
 rename drivers/event/{dlb2 => dlb}/pf/dlb2_main.h (100%)
 rename drivers/event/{dlb2 => dlb}/pf/dlb2_pf.c (100%)
 rename drivers/event/{dlb2/rte_pmd_dlb2.c => dlb/rte_pmd_dlb.c} (88%)
 rename drivers/event/{dlb2/rte_pmd_dlb2.h => dlb/rte_pmd_dlb.h} (88%)
 rename drivers/event/{dlb2 => dlb}/version.map (60%)

diff --git a/MAINTAINERS b/MAINTAINERS
index fa143160d..40610e169 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1196,10 +1196,10 @@ Cavium OCTEON TX timvf
 M: Pavan Nikhilesh <pbhagavatula@marvell.com>
 F: drivers/event/octeontx/timvf_*
 
-Intel DLB2
+Intel DLB
 M: Timothy McDaniel <timothy.mcdaniel@intel.com>
-F: drivers/event/dlb2/
-F: doc/guides/eventdevs/dlb2.rst
+F: drivers/event/dlb/
+F: doc/guides/eventdevs/dlb.rst
 
 Marvell OCTEON TX2
 M: Pavan Nikhilesh <pbhagavatula@marvell.com>
diff --git a/app/test/test_eventdev.c b/app/test/test_eventdev.c
index bcfaa53cb..ba27bed02 100644
--- a/app/test/test_eventdev.c
+++ b/app/test/test_eventdev.c
@@ -1031,9 +1031,9 @@ test_eventdev_selftest_dpaa2(void)
 }
 
 static int
-test_eventdev_selftest_dlb2(void)
+test_eventdev_selftest_dlb(void)
 {
-	return test_eventdev_selftest_impl("dlb2_event", "");
+	return test_eventdev_selftest_impl("dlb_event", "");
 }
 
 REGISTER_TEST_COMMAND(eventdev_common_autotest, test_eventdev_common);
@@ -1043,4 +1043,4 @@ REGISTER_TEST_COMMAND(eventdev_selftest_octeontx,
 REGISTER_TEST_COMMAND(eventdev_selftest_octeontx2,
 		test_eventdev_selftest_octeontx2);
 REGISTER_TEST_COMMAND(eventdev_selftest_dpaa2, test_eventdev_selftest_dpaa2);
-REGISTER_TEST_COMMAND(eventdev_selftest_dlb2, test_eventdev_selftest_dlb2);
+REGISTER_TEST_COMMAND(eventdev_selftest_dlb, test_eventdev_selftest_dlb);
diff --git a/config/rte_config.h b/config/rte_config.h
index b13c0884b..1aa852cd7 100644
--- a/config/rte_config.h
+++ b/config/rte_config.h
@@ -139,11 +139,10 @@
 /* QEDE PMD defines */
 #define RTE_LIBRTE_QEDE_FW ""
 
-/* DLB2 defines */
-#define RTE_LIBRTE_PMD_DLB2_POLL_INTERVAL 1000
-#define RTE_LIBRTE_PMD_DLB2_UMWAIT_CTL_STATE  0
-#undef RTE_LIBRTE_PMD_DLB2_QUELL_STATS
-#define RTE_LIBRTE_PMD_DLB2_SW_CREDIT_QUANTA 32
-#define RTE_PMD_DLB2_DEFAULT_DEPTH_THRESH 256
+/* DLB defines */
+#define RTE_LIBRTE_PMD_DLB_POLL_INTERVAL 1000
+#undef RTE_LIBRTE_PMD_DLB_QUELL_STATS
+#define RTE_LIBRTE_PMD_DLB_SW_CREDIT_QUANTA 32
+#define RTE_LIBRTE_PMD_DLB_DEFAULT_DEPTH_THRESH 256
 
 #endif /* _RTE_CONFIG_H_ */
diff --git a/doc/api/doxy-api-index.md b/doc/api/doxy-api-index.md
index ca2c2f6e0..1c2865525 100644
--- a/doc/api/doxy-api-index.md
+++ b/doc/api/doxy-api-index.md
@@ -55,7 +55,7 @@ The public API headers are grouped by topics:
   [dpaa2_cmdif]        (@ref rte_pmd_dpaa2_cmdif.h),
   [dpaa2_qdma]         (@ref rte_pmd_dpaa2_qdma.h),
   [crypto_scheduler]   (@ref rte_cryptodev_scheduler.h),
-  [dlb2]               (@ref rte_pmd_dlb2.h),
+  [dlb]                (@ref rte_pmd_dlb.h),
   [ifpga]              (@ref rte_pmd_ifpga.h)
 
 - **memory**:
diff --git a/doc/api/doxy-api.conf.in b/doc/api/doxy-api.conf.in
index 3c7ee4608..9aebec419 100644
--- a/doc/api/doxy-api.conf.in
+++ b/doc/api/doxy-api.conf.in
@@ -7,7 +7,7 @@ USE_MDFILE_AS_MAINPAGE  = @TOPDIR@/doc/api/doxy-api-index.md
 INPUT                   = @TOPDIR@/doc/api/doxy-api-index.md \
                           @TOPDIR@/drivers/bus/vdev \
                           @TOPDIR@/drivers/crypto/scheduler \
-                          @TOPDIR@/drivers/event/dlb2 \
+                          @TOPDIR@/drivers/event/dlb \
                           @TOPDIR@/drivers/mempool/dpaa2 \
                           @TOPDIR@/drivers/net/ark \
                           @TOPDIR@/drivers/net/bnxt \
diff --git a/doc/guides/eventdevs/dlb.rst b/doc/guides/eventdevs/dlb.rst
new file mode 100644
index 000000000..94e46ea7d
--- /dev/null
+++ b/doc/guides/eventdevs/dlb.rst
@@ -0,0 +1,390 @@
+..  SPDX-License-Identifier: BSD-3-Clause
+    Copyright(c) 2020 Intel Corporation.
+
+Driver for the Intel® Dynamic Load Balancer (DLB2)
+==================================================
+
+The DPDK dlb poll mode driver supports the Intel® Dynamic Load Balancer,
+hardware versions 2.0 and 2.5.
+
+Prerequisites
+-------------
+
+Follow the DPDK :ref:`Getting Started Guide for Linux <linux_gsg>` to setup
+the basic DPDK environment.
+
+Configuration
+-------------
+
+The DLB2 PF PMD is a user-space PMD that uses VFIO to gain direct
+device access. To use this operation mode, the PCIe PF device must be bound
+to a DPDK-compatible VFIO driver, such as vfio-pci.
+
+Eventdev API Notes
+------------------
+
+The DLB2 provides the functions of a DPDK event device; specifically, it
+supports atomic, ordered, and parallel scheduling events from queues to ports.
+However, the DLB2 hardware is not a perfect match to the eventdev API. Some DLB2
+features are abstracted by the PMD such as directed ports.
+
+In general the dlb PMD is designed for ease-of-use and does not require a
+detailed understanding of the hardware, but these details are important when
+writing high-performance code. This section describes the places where the
+eventdev API and DLB2 misalign.
+
+Scheduling Domain Configuration
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+DLB2 supports 32 scheduling domains.
+When one is configured, it allocates load-balanced and
+directed queues, ports, credits, and other hardware resources. Some
+resource allocations are user-controlled -- the number of queues, for example
+-- and others, like credit pools (one directed and one load-balanced pool per
+scheduling domain), are not.
+
+The DLB2 is a closed system eventdev, and as such the ``nb_events_limit`` device
+setup argument and the per-port ``new_event_threshold`` argument apply as
+defined in the eventdev header file. The limit is applied to all enqueues,
+regardless of whether it will consume a directed or load-balanced credit.
+
+Load-Balanced Queues
+~~~~~~~~~~~~~~~~~~~~
+
+A load-balanced queue can support atomic and ordered scheduling, or atomic and
+unordered scheduling, but not atomic and unordered and ordered scheduling. A
+queue's scheduling types are controlled by the event queue configuration.
+
+If the user sets the ``RTE_EVENT_QUEUE_CFG_ALL_TYPES`` flag, the
+``nb_atomic_order_sequences`` determines the supported scheduling types.
+With non-zero ``nb_atomic_order_sequences``, the queue is configured for atomic
+and ordered scheduling. In this case, ``RTE_SCHED_TYPE_PARALLEL`` scheduling is
+supported by scheduling those events as ordered events.  Note that when the
+event is dequeued, its sched_type will be ``RTE_SCHED_TYPE_ORDERED``. Else if
+``nb_atomic_order_sequences`` is zero, the queue is configured for atomic and
+unordered scheduling. In this case, ``RTE_SCHED_TYPE_ORDERED`` is unsupported.
+
+If the ``RTE_EVENT_QUEUE_CFG_ALL_TYPES`` flag is not set, schedule_type
+dictates the queue's scheduling type.
+
+The ``nb_atomic_order_sequences`` queue configuration field sets the ordered
+queue's reorder buffer size.  DLB2 has 2 groups of ordered queues, where each
+group is configured to contain either 1 queue with 1024 reorder entries, 2
+queues with 512 reorder entries, and so on down to 32 queues with 32 entries.
+
+When a load-balanced queue is created, the PMD will configure a new sequence
+number group on-demand if num_sequence_numbers does not match a pre-existing
+group with available reorder buffer entries. If all sequence number groups are
+in use, no new group will be created and queue configuration will fail. (Note
+that when the PMD is used with a virtual DLB2 device, it cannot change the
+sequence number configuration.)
+
+The queue's ``nb_atomic_flows`` parameter is ignored by the DLB2 PMD, because
+the DLB2 does not limit the number of flows a queue can track. In the DLB2, all
+load-balanced queues can use the full 16-bit flow ID range.
+
+Load-balanced and Directed Ports
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+DLB2 ports come in two flavors: load-balanced and directed. The eventdev API
+does not have the same concept, but it has a similar one: ports and queues that
+are singly-linked (i.e. linked to a single queue or port, respectively).
+
+The ``rte_event_dev_info_get()`` function reports the number of available
+event ports and queues (among other things). For the DLB2 PMD, max_event_ports
+and max_event_queues report the number of available load-balanced ports and
+queues, and max_single_link_event_port_queue_pairs reports the number of
+available directed ports and queues.
+
+When a scheduling domain is created in ``rte_event_dev_configure()``, the user
+specifies ``nb_event_ports`` and ``nb_single_link_event_port_queues``, which
+control the total number of ports (load-balanced and directed) and the number
+of directed ports. Hence, the number of requested load-balanced ports is
+``nb_event_ports - nb_single_link_event_ports``. The ``nb_event_queues`` field
+specifies the total number of queues (load-balanced and directed). The number
+of directed queues comes from ``nb_single_link_event_port_queues``, since
+directed ports and queues come in pairs.
+
+When a port is setup, the ``RTE_EVENT_PORT_CFG_SINGLE_LINK`` flag determines
+whether it should be configured as a directed (the flag is set) or a
+load-balanced (the flag is unset) port. Similarly, the
+``RTE_EVENT_QUEUE_CFG_SINGLE_LINK`` queue configuration flag controls
+whether it is a directed or load-balanced queue.
+
+Load-balanced ports can only be linked to load-balanced queues, and directed
+ports can only be linked to directed queues. Furthermore, directed ports can
+only be linked to a single directed queue (and vice versa), and that link
+cannot change after the eventdev is started.
+
+The eventdev API does not have a directed scheduling type. To support directed
+traffic, the dlb PMD detects when an event is being sent to a directed queue
+and overrides its scheduling type. Note that the originally selected scheduling
+type (atomic, ordered, or parallel) is not preserved, and an event's sched_type
+will be set to ``RTE_SCHED_TYPE_ATOMIC`` when it is dequeued from a directed
+port.
+
+Finally, even though all 3 event types are supported on the same QID by
+converting unordered events to ordered, such use should be discouraged as much
+as possible, since mixing types on the same queue uses valuable reorder
+resources, and orders events which do not require ordering.
+
+Flow ID
+~~~~~~~
+
+The flow ID field is preserved in the event when it is scheduled in the
+DLB2.
+
+Hardware Credits
+~~~~~~~~~~~~~~~~
+
+DLB2 uses a hardware credit scheme to prevent software from overflowing hardware
+event storage, with each unit of storage represented by a credit. A port spends
+a credit to enqueue an event, and hardware refills the ports with credits as the
+events are scheduled to ports. Refills come from credit pools.
+
+For DLB v2.5, there is a single credit pool used for both load balanced and
+directed traffic.
+
+For DLB v2.0, each port is a member of both a load-balanced credit pool and a
+directed credit pool. The load-balanced credits are used to enqueue to
+load-balanced queues, and directed credits are used for directed queues.
+These pools' sizes are controlled by the nb_events_limit field in struct
+rte_event_dev_config. The load-balanced pool is sized to contain
+nb_events_limit credits, and the directed pool is sized to contain
+nb_events_limit/4 credits. The directed pool size can be overridden with the
+num_dir_credits vdev argument, like so:
+
+    .. code-block:: console
+
+       --vdev=dlb1_event,num_dir_credits=<value>
+
+This can be used if the default allocation is too low or too high for the
+specific application needs. The PMD also supports a vdev arg that limits the
+max_num_events reported by rte_event_dev_info_get():
+
+    .. code-block:: console
+
+       --vdev=dlb1_event,max_num_events=<value>
+
+By default, max_num_events is reported as the total available load-balanced
+credits. If multiple DLB2-based applications are being used, it may be desirable
+to control how many load-balanced credits each application uses, particularly
+when application(s) are written to configure nb_events_limit equal to the
+reported max_num_events.
+
+Each port is a member of both credit pools. A port's credit allocation is
+defined by its low watermark, high watermark, and refill quanta. These three
+parameters are calculated by the dlb PMD like so:
+
+- The load-balanced high watermark is set to the port's enqueue_depth.
+  The directed high watermark is set to the minimum of the enqueue_depth and
+  the directed pool size divided by the total number of ports.
+- The refill quanta is set to half the high watermark.
+- The low watermark is set to the minimum of 16 and the refill quanta.
+
+When the eventdev is started, each port is pre-allocated a high watermark's
+worth of credits. For example, if an eventdev contains four ports with enqueue
+depths of 32 and a load-balanced credit pool size of 4096, each port will start
+with 32 load-balanced credits, and there will be 3968 credits available to
+replenish the ports. Thus, a single port is not capable of enqueueing up to the
+nb_events_limit (without any events being dequeued), since the other ports are
+retaining their initial credit allocation; in short, all ports must enqueue in
+order to reach the limit.
+
+If a port attempts to enqueue and has no credits available, the enqueue
+operation will fail and the application must retry the enqueue. Credits are
+replenished asynchronously by the DLB2 hardware.
+
+Software Credits
+~~~~~~~~~~~~~~~~
+
+The DLB2 is a "closed system" event dev, and the DLB2 PMD layers a software
+credit scheme on top of the hardware credit scheme in order to comply with
+the per-port backpressure described in the eventdev API.
+
+The DLB2's hardware scheme is local to a queue/pipeline stage: a port spends a
+credit when it enqueues to a queue, and credits are later replenished after the
+events are dequeued and released.
+
+In the software credit scheme, a credit is consumed when a new (.op =
+RTE_EVENT_OP_NEW) event is injected into the system, and the credit is
+replenished when the event is released from the system (either explicitly with
+RTE_EVENT_OP_RELEASE or implicitly in dequeue_burst()).
+
+In this model, an event is "in the system" from its first enqueue into eventdev
+until it is last dequeued. If the event goes through multiple event queues, it
+is still considered "in the system" while a worker thread is processing it.
+
+A port will fail to enqueue if the number of events in the system exceeds its
+``new_event_threshold`` (specified at port setup time). A port will also fail
+to enqueue if it lacks enough hardware credits to enqueue; load-balanced
+credits are used to enqueue to a load-balanced queue, and directed credits are
+used to enqueue to a directed queue.
+
+The out-of-credit situations are typically transient, and an eventdev
+application using the DLB2 ought to retry its enqueues if they fail.
+If enqueue fails, DLB2 PMD sets rte_errno as follows:
+
+- -ENOSPC: Credit exhaustion (either hardware or software)
+- -EINVAL: Invalid argument, such as port ID, queue ID, or sched_type.
+
+Depending on the pipeline the application has constructed, it's possible to
+enter a credit deadlock scenario wherein the worker thread lacks the credit
+to enqueue an event, and it must dequeue an event before it can recover the
+credit. If the worker thread retries its enqueue indefinitely, it will not
+make forward progress. Such deadlock is possible if the application has event
+"loops", in which an event in dequeued from queue A and later enqueued back to
+queue A.
+
+Due to this, workers should stop retrying after a time, release the events it
+is attempting to enqueue, and dequeue more events. It is important that the
+worker release the events and don't simply set them aside to retry the enqueue
+again later, because the port has limited history list size (by default, twice
+the port's dequeue_depth).
+
+Priority
+~~~~~~~~
+
+The DLB2 supports event priority and per-port queue service priority, as
+described in the eventdev header file. The DLB2 does not support 'global' event
+queue priority established at queue creation time.
+
+DLB2 supports 4 event and queue service priority levels. For both priority types,
+the PMD uses the upper three bits of the priority field to determine the DLB2
+priority, discarding the 5 least significant bits. But least significant bit out
+of 3 priority bits is effectively ignored for binning into 4 priorities. The
+discarded 5 least significant event priority bits are not preserved when an event
+is enqueued.
+
+Note that event priority only works within the same event type.
+When atomic and ordered or unordered events are enqueued to same QID, priority
+across the types is always equal, and both types are served in a round robin manner.
+
+Reconfiguration
+~~~~~~~~~~~~~~~
+
+The Eventdev API allows one to reconfigure a device, its ports, and its queues
+by first stopping the device, calling the configuration function(s), then
+restarting the device. The DLB2 does not support configuring an individual queue
+or port without first reconfiguring the entire device, however, so there are
+certain reconfiguration sequences that are valid in the eventdev API but not
+supported by the PMD.
+
+Specifically, the PMD supports the following configuration sequence:
+1. Configure and start the device
+2. Stop the device
+3. (Optional) Reconfigure the device
+4. (Optional) If step 3 is run:
+
+   a. Setup queue(s). The reconfigured queue(s) lose their previous port links.
+   b. The reconfigured port(s) lose their previous queue links.
+
+5. (Optional, only if steps 4a and 4b are run) Link port(s) to queue(s)
+6. Restart the device. If the device is reconfigured in step 3 but one or more
+   of its ports or queues are not, the PMD will apply their previous
+   configuration (including port->queue links) at this time.
+
+The PMD does not support the following configuration sequences:
+1. Configure and start the device
+2. Stop the device
+3. Setup queue or setup port
+4. Start the device
+
+This sequence is not supported because the event device must be reconfigured
+before its ports or queues can be.
+
+Deferred Scheduling
+~~~~~~~~~~~~~~~~~~~
+
+The DLB2 PMD's default behavior for managing a CQ is to "pop" the CQ once per
+dequeued event before returning from rte_event_dequeue_burst(). This frees the
+corresponding entries in the CQ, which enables the DLB2 to schedule more events
+to it.
+
+To support applications seeking finer-grained scheduling control -- for example
+deferring scheduling to get the best possible priority scheduling and
+load-balancing -- the PMD supports a deferred scheduling mode. In this mode,
+the CQ entry is not popped until the *subsequent* rte_event_dequeue_burst()
+call. This mode only applies to load-balanced event ports with dequeue depth of
+1.
+
+To enable deferred scheduling, use the defer_sched vdev argument like so:
+
+    .. code-block:: console
+
+       --vdev=dlb1_event,defer_sched=on
+
+Atomic Inflights Allocation
+~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+In the last stage prior to scheduling an atomic event to a CQ, DLB2 holds the
+inflight event in a temporary buffer that is divided among load-balanced
+queues. If a queue's atomic buffer storage fills up, this can result in
+head-of-line-blocking. For example:
+
+- An LDB queue allocated N atomic buffer entries
+- All N entries are filled with events from flow X, which is pinned to CQ 0.
+
+Until CQ 0 releases 1+ events, no other atomic flows for that LDB queue can be
+scheduled. The likelihood of this case depends on the eventdev configuration,
+traffic behavior, event processing latency, potential for a worker to be
+interrupted or otherwise delayed, etc.
+
+By default, the PMD allocates 16 buffer entries for each load-balanced queue,
+which provides an even division across all 128 queues but potentially wastes
+buffer space (e.g. if not all queues are used, or aren't used for atomic
+scheduling).
+
+The PMD provides a dev arg to override the default per-queue allocation. To
+increase a vdev's per-queue atomic-inflight allocation to (for example) 64:
+
+    .. code-block:: console
+
+       --vdev=dlb1_event,atm_inflights=64
+
+QID Depth Threshold
+~~~~~~~~~~~~~~~~~~~
+
+DLB2 supports setting and tracking queue depth thresholds. Hardware uses
+the thresholds to track how full a queue is compared to its threshold.
+Four buckets are used
+
+- Less than or equal to 50% of queue depth threshold
+- Greater than 50%, but less than or equal to 75% of depth threshold
+- Greater than 75%, but less than or equal to 100% of depth threshold
+- Greater than 100% of depth thresholds
+
+Per queue threshold metrics are tracked in the DLB2 xstats, and are also
+returned in the impl_opaque field of each received event.
+
+The per qid threshold can be specified as part of the device args, and
+can be applied to all queue, a range of queues, or a single queue, as
+shown below.
+
+    .. code-block:: console
+
+       --vdev=dlb2_event,qid_depth_thresh=all:<threshold_value>
+       --vdev=dlb2_event,qid_depth_thresh=qidA-qidB:<threshold_value>
+       --vdev=dlb2_event,qid_depth_thresh=qid:<threshold_value>
+
+Class of service
+~~~~~~~~~~~~~~~~
+
+DLB2 supports provisioning the DLB2 bandwidth into 4 classes of service.
+
+- Class 4 corresponds to 40% of the DLB2 hardware bandwidth
+- Class 3 corresponds to 30% of the DLB2 hardware bandwidth
+- Class 2 corresponds to 20% of the DLB2 hardware bandwidth
+- Class 1 corresponds to 10% of the DLB2 hardware bandwidth
+- Class 0 corresponds to don't care
+
+The classes are applied globally to the set of ports contained in this
+scheduling domain, which is more appropriate for the bifurcated
+PMD than for the PF PMD, since the PF PMD supports just 1 scheduling
+domain.
+
+Class of service can be specified in the devargs, as follows
+
+    .. code-block:: console
+
+       --vdev=dlb2_event,cos=<0..4>
diff --git a/doc/guides/eventdevs/index.rst b/doc/guides/eventdevs/index.rst
index 738788d9e..4b915bf3e 100644
--- a/doc/guides/eventdevs/index.rst
+++ b/doc/guides/eventdevs/index.rst
@@ -11,7 +11,7 @@ application through the eventdev API.
     :maxdepth: 2
     :numbered:
 
-    dlb2
+    dlb
     dpaa
     dpaa2
     dsw
diff --git a/doc/guides/rel_notes/release_21_05.rst b/doc/guides/rel_notes/release_21_05.rst
index 8a601e0a7..5b25f1479 100644
--- a/doc/guides/rel_notes/release_21_05.rst
+++ b/doc/guides/rel_notes/release_21_05.rst
@@ -94,6 +94,11 @@ New Features
 
   * Added support for preferred busy polling.
 
+* **Updated DLB driver.**
+
+  * Added support for v2.5 hardware.
+  * Renamed DLB2 to DLB, which supports all HW versions v2.0 and v2.5.
+
 * **Updated testpmd.**
 
   * Added a command line option to configure forced speed for Ethernet port.
diff --git a/drivers/event/dlb2/dlb2.c b/drivers/event/dlb/dlb2.c
similarity index 99%
rename from drivers/event/dlb2/dlb2.c
rename to drivers/event/dlb/dlb2.c
index cc6495b76..e5def9357 100644
--- a/drivers/event/dlb2/dlb2.c
+++ b/drivers/event/dlb/dlb2.c
@@ -667,15 +667,8 @@ dlb2_eventdev_configure(const struct rte_eventdev *dev)
 	}
 
 	/* Does this platform support umonitor/umwait? */
-	if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_WAITPKG)) {
-		if (RTE_LIBRTE_PMD_DLB2_UMWAIT_CTL_STATE != 0 &&
-		    RTE_LIBRTE_PMD_DLB2_UMWAIT_CTL_STATE != 1) {
-			DLB2_LOG_ERR("invalid value (%d) for RTE_LIBRTE_PMD_DLB2_UMWAIT_CTL_STATE, must be 0 or 1.\n",
-				     RTE_LIBRTE_PMD_DLB2_UMWAIT_CTL_STATE);
-			return -EINVAL;
-		}
+	if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_WAITPKG))
 		dlb2->umwait_allowed = true;
-	}
 
 	rsrcs->num_dir_ports = config->nb_single_link_event_port_queues;
 	rsrcs->num_ldb_ports  = config->nb_event_ports - rsrcs->num_dir_ports;
@@ -930,8 +923,9 @@ dlb2_hw_create_ldb_queue(struct dlb2_eventdev *dlb2,
 	}
 
 	if (ev_queue->depth_threshold == 0) {
-		cfg.depth_threshold = RTE_PMD_DLB2_DEFAULT_DEPTH_THRESH;
-		ev_queue->depth_threshold = RTE_PMD_DLB2_DEFAULT_DEPTH_THRESH;
+		cfg.depth_threshold = RTE_LIBRTE_PMD_DLB_DEFAULT_DEPTH_THRESH;
+		ev_queue->depth_threshold =
+			RTE_LIBRTE_PMD_DLB_DEFAULT_DEPTH_THRESH;
 	} else
 		cfg.depth_threshold = ev_queue->depth_threshold;
 
@@ -1623,7 +1617,7 @@ dlb2_eventdev_port_setup(struct rte_eventdev *dev,
 		  RTE_EVENT_PORT_CFG_DISABLE_IMPL_REL);
 	ev_port->outstanding_releases = 0;
 	ev_port->inflight_credits = 0;
-	ev_port->credit_update_quanta = RTE_LIBRTE_PMD_DLB2_SW_CREDIT_QUANTA;
+	ev_port->credit_update_quanta = RTE_LIBRTE_PMD_DLB_SW_CREDIT_QUANTA;
 	ev_port->dlb2 = dlb2; /* reverse link */
 
 	/* Tear down pre-existing port->queue links */
@@ -1718,8 +1712,9 @@ dlb2_hw_create_dir_queue(struct dlb2_eventdev *dlb2,
 	cfg.port_id = qm_port_id;
 
 	if (ev_queue->depth_threshold == 0) {
-		cfg.depth_threshold = RTE_PMD_DLB2_DEFAULT_DEPTH_THRESH;
-		ev_queue->depth_threshold = RTE_PMD_DLB2_DEFAULT_DEPTH_THRESH;
+		cfg.depth_threshold = RTE_LIBRTE_PMD_DLB_DEFAULT_DEPTH_THRESH;
+		ev_queue->depth_threshold =
+			RTE_LIBRTE_PMD_DLB_DEFAULT_DEPTH_THRESH;
 	} else
 		cfg.depth_threshold = ev_queue->depth_threshold;
 
@@ -2747,7 +2742,7 @@ dlb2_event_enqueue_prep(struct dlb2_eventdev_port *ev_port,
 	DLB2_INC_STAT(ev_port->stats.tx_op_cnt[ev->op], 1);
 	DLB2_INC_STAT(ev_port->stats.traffic.tx_ok, 1);
 
-#ifndef RTE_LIBRTE_PMD_DLB2_QUELL_STATS
+#ifndef RTE_LIBRTE_PMD_DLB_QUELL_STATS
 	if (ev->op != RTE_EVENT_OP_RELEASE) {
 		DLB2_INC_STAT(ev_port->stats.queue[ev->queue_id].enq_ok, 1);
 		DLB2_INC_STAT(ev_port->stats.tx_sched_cnt[*sched_type], 1);
@@ -3070,7 +3065,7 @@ dlb2_dequeue_wait(struct dlb2_eventdev *dlb2,
 
 		DLB2_INC_STAT(ev_port->stats.traffic.rx_umonitor_umwait, 1);
 	} else {
-		uint64_t poll_interval = RTE_LIBRTE_PMD_DLB2_POLL_INTERVAL;
+		uint64_t poll_interval = RTE_LIBRTE_PMD_DLB_POLL_INTERVAL;
 		uint64_t curr_ticks = rte_get_timer_cycles();
 		uint64_t init_ticks = curr_ticks;
 
diff --git a/drivers/event/dlb2/dlb2_iface.c b/drivers/event/dlb/dlb2_iface.c
similarity index 100%
rename from drivers/event/dlb2/dlb2_iface.c
rename to drivers/event/dlb/dlb2_iface.c
diff --git a/drivers/event/dlb2/dlb2_iface.h b/drivers/event/dlb/dlb2_iface.h
similarity index 100%
rename from drivers/event/dlb2/dlb2_iface.h
rename to drivers/event/dlb/dlb2_iface.h
diff --git a/drivers/event/dlb2/dlb2_inline_fns.h b/drivers/event/dlb/dlb2_inline_fns.h
similarity index 100%
rename from drivers/event/dlb2/dlb2_inline_fns.h
rename to drivers/event/dlb/dlb2_inline_fns.h
diff --git a/drivers/event/dlb2/dlb2_log.h b/drivers/event/dlb/dlb2_log.h
similarity index 100%
rename from drivers/event/dlb2/dlb2_log.h
rename to drivers/event/dlb/dlb2_log.h
diff --git a/drivers/event/dlb2/dlb2_priv.h b/drivers/event/dlb/dlb2_priv.h
similarity index 99%
rename from drivers/event/dlb2/dlb2_priv.h
rename to drivers/event/dlb/dlb2_priv.h
index f3a9fe0aa..f11e08fca 100644
--- a/drivers/event/dlb2/dlb2_priv.h
+++ b/drivers/event/dlb/dlb2_priv.h
@@ -12,7 +12,7 @@
 #include <rte_config.h>
 #include "dlb2_user.h"
 #include "dlb2_log.h"
-#include "rte_pmd_dlb2.h"
+#include "rte_pmd_dlb.h"
 
 #ifndef RTE_LIBRTE_PMD_DLB2_QUELL_STATS
 #define DLB2_INC_STAT(_stat, _incr_val) ((_stat) += _incr_val)
@@ -20,7 +20,8 @@
 #define DLB2_INC_STAT(_stat, _incr_val)
 #endif
 
-#define EVDEV_DLB2_NAME_PMD dlb2_event
+/* common name for all dlb devs (dlb v2.0, dlb v2.5 ...) */
+#define EVDEV_DLB2_NAME_PMD dlb_event
 
 /*  command line arg strings */
 #define NUMA_NODE_ARG "numa_node"
@@ -320,7 +321,7 @@ struct dlb2_port {
 	bool gen_bit;
 	uint16_t dir_credits;
 	uint32_t dequeue_depth;
-	enum dlb2_token_pop_mode token_pop_mode;
+	enum dlb_token_pop_mode token_pop_mode;
 	union dlb2_port_config cfg;
 	uint32_t *credit_pool[DLB2_NUM_QUEUE_TYPES]; /* use __atomic builtins */
 	union {
diff --git a/drivers/event/dlb2/dlb2_selftest.c b/drivers/event/dlb/dlb2_selftest.c
similarity index 99%
rename from drivers/event/dlb2/dlb2_selftest.c
rename to drivers/event/dlb/dlb2_selftest.c
index 5cf66c552..019cbecdc 100644
--- a/drivers/event/dlb2/dlb2_selftest.c
+++ b/drivers/event/dlb/dlb2_selftest.c
@@ -22,7 +22,7 @@
 #include <rte_pause.h>
 
 #include "dlb2_priv.h"
-#include "rte_pmd_dlb2.h"
+#include "rte_pmd_dlb.h"
 
 #define MAX_PORTS 32
 #define MAX_QIDS 32
@@ -1105,13 +1105,13 @@ test_deferred_sched(void)
 		return -1;
 	}
 
-	ret = rte_pmd_dlb2_set_token_pop_mode(evdev, 0, DEFERRED_POP);
+	ret = rte_pmd_dlb_set_token_pop_mode(evdev, 0, DEFERRED_POP);
 	if (ret < 0) {
 		printf("%d: Error setting deferred scheduling\n", __LINE__);
 		goto err;
 	}
 
-	ret = rte_pmd_dlb2_set_token_pop_mode(evdev, 1, DEFERRED_POP);
+	ret = rte_pmd_dlb_set_token_pop_mode(evdev, 1, DEFERRED_POP);
 	if (ret < 0) {
 		printf("%d: Error setting deferred scheduling\n", __LINE__);
 		goto err;
@@ -1257,7 +1257,7 @@ test_delayed_pop(void)
 		return -1;
 	}
 
-	ret = rte_pmd_dlb2_set_token_pop_mode(evdev, 0, DELAYED_POP);
+	ret = rte_pmd_dlb_set_token_pop_mode(evdev, 0, DELAYED_POP);
 	if (ret < 0) {
 		printf("%d: Error setting deferred scheduling\n", __LINE__);
 		goto err;
diff --git a/drivers/event/dlb2/dlb2_user.h b/drivers/event/dlb/dlb2_user.h
similarity index 100%
rename from drivers/event/dlb2/dlb2_user.h
rename to drivers/event/dlb/dlb2_user.h
diff --git a/drivers/event/dlb2/dlb2_xstats.c b/drivers/event/dlb/dlb2_xstats.c
similarity index 100%
rename from drivers/event/dlb2/dlb2_xstats.c
rename to drivers/event/dlb/dlb2_xstats.c
diff --git a/drivers/event/dlb2/meson.build b/drivers/event/dlb/meson.build
similarity index 89%
rename from drivers/event/dlb2/meson.build
rename to drivers/event/dlb/meson.build
index f22638b8e..4a4aed931 100644
--- a/drivers/event/dlb2/meson.build
+++ b/drivers/event/dlb/meson.build
@@ -14,10 +14,10 @@ sources = files('dlb2.c',
 		'pf/dlb2_main.c',
 		'pf/dlb2_pf.c',
 		'pf/base/dlb2_resource.c',
-		'rte_pmd_dlb2.c',
+		'rte_pmd_dlb.c',
 		'dlb2_selftest.c'
 )
 
-headers = files('rte_pmd_dlb2.h')
+headers = files('rte_pmd_dlb.h')
 
 deps += ['mbuf', 'mempool', 'ring', 'pci', 'bus_pci']
diff --git a/drivers/event/dlb2/pf/base/dlb2_hw_types.h b/drivers/event/dlb/pf/base/dlb2_hw_types.h
similarity index 100%
rename from drivers/event/dlb2/pf/base/dlb2_hw_types.h
rename to drivers/event/dlb/pf/base/dlb2_hw_types.h
diff --git a/drivers/event/dlb2/pf/base/dlb2_osdep.h b/drivers/event/dlb/pf/base/dlb2_osdep.h
similarity index 100%
rename from drivers/event/dlb2/pf/base/dlb2_osdep.h
rename to drivers/event/dlb/pf/base/dlb2_osdep.h
diff --git a/drivers/event/dlb2/pf/base/dlb2_osdep_bitmap.h b/drivers/event/dlb/pf/base/dlb2_osdep_bitmap.h
similarity index 100%
rename from drivers/event/dlb2/pf/base/dlb2_osdep_bitmap.h
rename to drivers/event/dlb/pf/base/dlb2_osdep_bitmap.h
diff --git a/drivers/event/dlb2/pf/base/dlb2_osdep_list.h b/drivers/event/dlb/pf/base/dlb2_osdep_list.h
similarity index 100%
rename from drivers/event/dlb2/pf/base/dlb2_osdep_list.h
rename to drivers/event/dlb/pf/base/dlb2_osdep_list.h
diff --git a/drivers/event/dlb2/pf/base/dlb2_osdep_types.h b/drivers/event/dlb/pf/base/dlb2_osdep_types.h
similarity index 100%
rename from drivers/event/dlb2/pf/base/dlb2_osdep_types.h
rename to drivers/event/dlb/pf/base/dlb2_osdep_types.h
diff --git a/drivers/event/dlb2/pf/base/dlb2_regs.h b/drivers/event/dlb/pf/base/dlb2_regs.h
similarity index 100%
rename from drivers/event/dlb2/pf/base/dlb2_regs.h
rename to drivers/event/dlb/pf/base/dlb2_regs.h
diff --git a/drivers/event/dlb2/pf/base/dlb2_resource.c b/drivers/event/dlb/pf/base/dlb2_resource.c
similarity index 100%
rename from drivers/event/dlb2/pf/base/dlb2_resource.c
rename to drivers/event/dlb/pf/base/dlb2_resource.c
diff --git a/drivers/event/dlb2/pf/base/dlb2_resource.h b/drivers/event/dlb/pf/base/dlb2_resource.h
similarity index 100%
rename from drivers/event/dlb2/pf/base/dlb2_resource.h
rename to drivers/event/dlb/pf/base/dlb2_resource.h
diff --git a/drivers/event/dlb2/pf/dlb2_main.c b/drivers/event/dlb/pf/dlb2_main.c
similarity index 100%
rename from drivers/event/dlb2/pf/dlb2_main.c
rename to drivers/event/dlb/pf/dlb2_main.c
diff --git a/drivers/event/dlb2/pf/dlb2_main.h b/drivers/event/dlb/pf/dlb2_main.h
similarity index 100%
rename from drivers/event/dlb2/pf/dlb2_main.h
rename to drivers/event/dlb/pf/dlb2_main.h
diff --git a/drivers/event/dlb2/pf/dlb2_pf.c b/drivers/event/dlb/pf/dlb2_pf.c
similarity index 100%
rename from drivers/event/dlb2/pf/dlb2_pf.c
rename to drivers/event/dlb/pf/dlb2_pf.c
diff --git a/drivers/event/dlb2/rte_pmd_dlb2.c b/drivers/event/dlb/rte_pmd_dlb.c
similarity index 88%
rename from drivers/event/dlb2/rte_pmd_dlb2.c
rename to drivers/event/dlb/rte_pmd_dlb.c
index 43990e46a..82d203366 100644
--- a/drivers/event/dlb2/rte_pmd_dlb2.c
+++ b/drivers/event/dlb/rte_pmd_dlb.c
@@ -5,14 +5,14 @@
 #include <rte_eventdev.h>
 #include <eventdev_pmd.h>
 
-#include "rte_pmd_dlb2.h"
+#include "rte_pmd_dlb.h"
 #include "dlb2_priv.h"
 #include "dlb2_inline_fns.h"
 
 int
-rte_pmd_dlb2_set_token_pop_mode(uint8_t dev_id,
+rte_pmd_dlb_set_token_pop_mode(uint8_t dev_id,
 				uint8_t port_id,
-				enum dlb2_token_pop_mode mode)
+				enum dlb_token_pop_mode mode)
 {
 	struct dlb2_eventdev *dlb2;
 	struct rte_eventdev *dev;
diff --git a/drivers/event/dlb2/rte_pmd_dlb2.h b/drivers/event/dlb/rte_pmd_dlb.h
similarity index 88%
rename from drivers/event/dlb2/rte_pmd_dlb2.h
rename to drivers/event/dlb/rte_pmd_dlb.h
index 74399db01..d42b1f52a 100644
--- a/drivers/event/dlb2/rte_pmd_dlb2.h
+++ b/drivers/event/dlb/rte_pmd_dlb.h
@@ -3,13 +3,13 @@
  */
 
 /*!
- *  @file      rte_pmd_dlb2.h
+ *  @file      rte_pmd_dlb.h
  *
  *  @brief     DLB PMD-specific functions
  */
 
-#ifndef _RTE_PMD_DLB2_H_
-#define _RTE_PMD_DLB2_H_
+#ifndef _RTE_PMD_DLB_H_
+#define _RTE_PMD_DLB_H_
 
 #ifdef __cplusplus
 extern "C" {
@@ -23,7 +23,7 @@ extern "C" {
  *
  * Selects the token pop mode for a DLB2 port.
  */
-enum dlb2_token_pop_mode {
+enum dlb_token_pop_mode {
 	/* Pop the CQ tokens immediately after dequeueing. */
 	AUTO_POP,
 	/* Pop CQ tokens after (dequeue_depth - 1) events are released.
@@ -61,9 +61,9 @@ enum dlb2_token_pop_mode {
 
 __rte_experimental
 int
-rte_pmd_dlb2_set_token_pop_mode(uint8_t dev_id,
+rte_pmd_dlb_set_token_pop_mode(uint8_t dev_id,
 				uint8_t port_id,
-				enum dlb2_token_pop_mode mode);
+				enum dlb_token_pop_mode mode);
 
 #ifdef __cplusplus
 }
diff --git a/drivers/event/dlb2/version.map b/drivers/event/dlb/version.map
similarity index 60%
rename from drivers/event/dlb2/version.map
rename to drivers/event/dlb/version.map
index b1e4dff0f..3338a22c1 100644
--- a/drivers/event/dlb2/version.map
+++ b/drivers/event/dlb/version.map
@@ -5,5 +5,5 @@ DPDK_21 {
 EXPERIMENTAL {
 	global:
 
-	rte_pmd_dlb2_set_token_pop_mode;
+	rte_pmd_dlb_set_token_pop_mode;
 };
diff --git a/drivers/event/meson.build b/drivers/event/meson.build
index b7f9bf7c6..e9b0433f2 100644
--- a/drivers/event/meson.build
+++ b/drivers/event/meson.build
@@ -5,7 +5,7 @@ if is_windows
 	subdir_done()
 endif
 
-drivers = ['dlb2', 'dpaa', 'dpaa2', 'octeontx2', 'opdl', 'skeleton', 'sw',
+drivers = ['dlb', 'dpaa', 'dpaa2', 'octeontx2', 'opdl', 'skeleton', 'sw',
 	   'dsw']
 if not (toolchain == 'gcc' and cc.version().version_compare('<4.8.6') and
 	dpdk_conf.has('RTE_ARCH_ARM64'))
-- 
2.23.0