From: Timothy McDaniel <timothy.mcdaniel@intel.com>
Cc: dev@dpdk.org, erik.g.carrillo@intel.com, gage.eads@intel.com,
harry.van.haaren@intel.com, jerinj@marvell.com,
thomas@monjalon.net
Subject: [dpdk-dev] [PATCH v3 05/26] event/dlb2: add v2.5 create sched domain
Date: Tue, 13 Apr 2021 15:14:35 -0500 [thread overview]
Message-ID: <1618344896-2090-6-git-send-email-timothy.mcdaniel@intel.com> (raw)
In-Reply-To: <1618344896-2090-1-git-send-email-timothy.mcdaniel@intel.com>
Update domain creation logic to account for DLB v2.5
credit scheme, new register map, and new register access
macros.
Signed-off-by: Timothy McDaniel <timothy.mcdaniel@intel.com>
---
drivers/event/dlb2/dlb2_user.h | 13 +-
drivers/event/dlb2/pf/base/dlb2_resource.c | 645 ----------------
.../event/dlb2/pf/base/dlb2_resource_new.c | 696 ++++++++++++++++++
3 files changed, 707 insertions(+), 647 deletions(-)
diff --git a/drivers/event/dlb2/dlb2_user.h b/drivers/event/dlb2/dlb2_user.h
index b7d125dec..9760e9bda 100644
--- a/drivers/event/dlb2/dlb2_user.h
+++ b/drivers/event/dlb2/dlb2_user.h
@@ -18,6 +18,7 @@ enum dlb2_error {
DLB2_ST_LDB_QUEUES_UNAVAILABLE,
DLB2_ST_LDB_CREDITS_UNAVAILABLE,
DLB2_ST_DIR_CREDITS_UNAVAILABLE,
+ DLB2_ST_CREDITS_UNAVAILABLE,
DLB2_ST_SEQUENCE_NUMBERS_UNAVAILABLE,
DLB2_ST_INVALID_DOMAIN_ID,
DLB2_ST_INVALID_QID_INFLIGHT_ALLOCATION,
@@ -57,6 +58,7 @@ static const char dlb2_error_strings[][128] = {
"DLB2_ST_LDB_QUEUES_UNAVAILABLE",
"DLB2_ST_LDB_CREDITS_UNAVAILABLE",
"DLB2_ST_DIR_CREDITS_UNAVAILABLE",
+ "DLB2_ST_CREDITS_UNAVAILABLE",
"DLB2_ST_SEQUENCE_NUMBERS_UNAVAILABLE",
"DLB2_ST_INVALID_DOMAIN_ID",
"DLB2_ST_INVALID_QID_INFLIGHT_ALLOCATION",
@@ -170,8 +172,15 @@ struct dlb2_create_sched_domain_args {
__u32 num_dir_ports;
__u32 num_atomic_inflights;
__u32 num_hist_list_entries;
- __u32 num_ldb_credits;
- __u32 num_dir_credits;
+ union {
+ struct {
+ __u32 num_ldb_credits;
+ __u32 num_dir_credits;
+ };
+ struct {
+ __u32 num_credits;
+ };
+ };
__u8 cos_strict;
__u8 padding1[3];
};
diff --git a/drivers/event/dlb2/pf/base/dlb2_resource.c b/drivers/event/dlb2/pf/base/dlb2_resource.c
index eda983d85..99c3d031d 100644
--- a/drivers/event/dlb2/pf/base/dlb2_resource.c
+++ b/drivers/event/dlb2/pf/base/dlb2_resource.c
@@ -32,21 +32,6 @@
#define DLB2_FUNC_LIST_FOR_SAFE(head, ptr, ptr_tmp, it, it_tmp) \
DLB2_LIST_FOR_EACH_SAFE((head), ptr, ptr_tmp, func_list, it, it_tmp)
-static void dlb2_init_domain_rsrc_lists(struct dlb2_hw_domain *domain)
-{
- int i;
-
- dlb2_list_init_head(&domain->used_ldb_queues);
- dlb2_list_init_head(&domain->used_dir_pq_pairs);
- dlb2_list_init_head(&domain->avail_ldb_queues);
- dlb2_list_init_head(&domain->avail_dir_pq_pairs);
-
- for (i = 0; i < DLB2_NUM_COS_DOMAINS; i++)
- dlb2_list_init_head(&domain->used_ldb_ports[i]);
- for (i = 0; i < DLB2_NUM_COS_DOMAINS; i++)
- dlb2_list_init_head(&domain->avail_ldb_ports[i]);
-}
-
void dlb2_hw_enable_sparse_dir_cq_mode(struct dlb2_hw *hw)
{
union dlb2_chp_cfg_chp_csr_ctrl r0;
@@ -69,636 +54,6 @@ void dlb2_hw_enable_sparse_ldb_cq_mode(struct dlb2_hw *hw)
DLB2_CSR_WR(hw, DLB2_CHP_CFG_CHP_CSR_CTRL, r0.val);
}
-static void dlb2_configure_domain_credits(struct dlb2_hw *hw,
- struct dlb2_hw_domain *domain)
-{
- union dlb2_chp_cfg_ldb_vas_crd r0 = { {0} };
- union dlb2_chp_cfg_dir_vas_crd r1 = { {0} };
-
- r0.field.count = domain->num_ldb_credits;
-
- DLB2_CSR_WR(hw, DLB2_CHP_CFG_LDB_VAS_CRD(domain->id.phys_id), r0.val);
-
- r1.field.count = domain->num_dir_credits;
-
- DLB2_CSR_WR(hw, DLB2_CHP_CFG_DIR_VAS_CRD(domain->id.phys_id), r1.val);
-}
-
-static struct dlb2_ldb_port *
-dlb2_get_next_ldb_port(struct dlb2_hw *hw,
- struct dlb2_function_resources *rsrcs,
- u32 domain_id,
- u32 cos_id)
-{
- struct dlb2_list_entry *iter;
- struct dlb2_ldb_port *port;
- RTE_SET_USED(iter);
- /*
- * To reduce the odds of consecutive load-balanced ports mapping to the
- * same queue(s), the driver attempts to allocate ports whose neighbors
- * are owned by a different domain.
- */
- DLB2_FUNC_LIST_FOR(rsrcs->avail_ldb_ports[cos_id], port, iter) {
- u32 next, prev;
- u32 phys_id;
-
- phys_id = port->id.phys_id;
- next = phys_id + 1;
- prev = phys_id - 1;
-
- if (phys_id == DLB2_MAX_NUM_LDB_PORTS - 1)
- next = 0;
- if (phys_id == 0)
- prev = DLB2_MAX_NUM_LDB_PORTS - 1;
-
- if (!hw->rsrcs.ldb_ports[next].owned ||
- hw->rsrcs.ldb_ports[next].domain_id.phys_id == domain_id)
- continue;
-
- if (!hw->rsrcs.ldb_ports[prev].owned ||
- hw->rsrcs.ldb_ports[prev].domain_id.phys_id == domain_id)
- continue;
-
- return port;
- }
-
- /*
- * Failing that, the driver looks for a port with one neighbor owned by
- * a different domain and the other unallocated.
- */
- DLB2_FUNC_LIST_FOR(rsrcs->avail_ldb_ports[cos_id], port, iter) {
- u32 next, prev;
- u32 phys_id;
-
- phys_id = port->id.phys_id;
- next = phys_id + 1;
- prev = phys_id - 1;
-
- if (phys_id == DLB2_MAX_NUM_LDB_PORTS - 1)
- next = 0;
- if (phys_id == 0)
- prev = DLB2_MAX_NUM_LDB_PORTS - 1;
-
- if (!hw->rsrcs.ldb_ports[prev].owned &&
- hw->rsrcs.ldb_ports[next].owned &&
- hw->rsrcs.ldb_ports[next].domain_id.phys_id != domain_id)
- return port;
-
- if (!hw->rsrcs.ldb_ports[next].owned &&
- hw->rsrcs.ldb_ports[prev].owned &&
- hw->rsrcs.ldb_ports[prev].domain_id.phys_id != domain_id)
- return port;
- }
-
- /*
- * Failing that, the driver looks for a port with both neighbors
- * unallocated.
- */
- DLB2_FUNC_LIST_FOR(rsrcs->avail_ldb_ports[cos_id], port, iter) {
- u32 next, prev;
- u32 phys_id;
-
- phys_id = port->id.phys_id;
- next = phys_id + 1;
- prev = phys_id - 1;
-
- if (phys_id == DLB2_MAX_NUM_LDB_PORTS - 1)
- next = 0;
- if (phys_id == 0)
- prev = DLB2_MAX_NUM_LDB_PORTS - 1;
-
- if (!hw->rsrcs.ldb_ports[prev].owned &&
- !hw->rsrcs.ldb_ports[next].owned)
- return port;
- }
-
- /* If all else fails, the driver returns the next available port. */
- return DLB2_FUNC_LIST_HEAD(rsrcs->avail_ldb_ports[cos_id],
- typeof(*port));
-}
-
-static int __dlb2_attach_ldb_ports(struct dlb2_hw *hw,
- struct dlb2_function_resources *rsrcs,
- struct dlb2_hw_domain *domain,
- u32 num_ports,
- u32 cos_id,
- struct dlb2_cmd_response *resp)
-{
- unsigned int i;
-
- if (rsrcs->num_avail_ldb_ports[cos_id] < num_ports) {
- resp->status = DLB2_ST_LDB_PORTS_UNAVAILABLE;
- return -EINVAL;
- }
-
- for (i = 0; i < num_ports; i++) {
- struct dlb2_ldb_port *port;
-
- port = dlb2_get_next_ldb_port(hw, rsrcs,
- domain->id.phys_id, cos_id);
- if (port == NULL) {
- DLB2_HW_ERR(hw,
- "[%s()] Internal error: domain validation failed\n",
- __func__);
- return -EFAULT;
- }
-
- dlb2_list_del(&rsrcs->avail_ldb_ports[cos_id],
- &port->func_list);
-
- port->domain_id = domain->id;
- port->owned = true;
-
- dlb2_list_add(&domain->avail_ldb_ports[cos_id],
- &port->domain_list);
- }
-
- rsrcs->num_avail_ldb_ports[cos_id] -= num_ports;
-
- return 0;
-}
-
-static int dlb2_attach_ldb_ports(struct dlb2_hw *hw,
- struct dlb2_function_resources *rsrcs,
- struct dlb2_hw_domain *domain,
- struct dlb2_create_sched_domain_args *args,
- struct dlb2_cmd_response *resp)
-{
- unsigned int i, j;
- int ret;
-
- if (args->cos_strict) {
- for (i = 0; i < DLB2_NUM_COS_DOMAINS; i++) {
- u32 num = args->num_cos_ldb_ports[i];
-
- /* Allocate ports from specific classes-of-service */
- ret = __dlb2_attach_ldb_ports(hw,
- rsrcs,
- domain,
- num,
- i,
- resp);
- if (ret)
- return ret;
- }
- } else {
- unsigned int k;
- u32 cos_id;
-
- /*
- * Attempt to allocate from specific class-of-service, but
- * fallback to the other classes if that fails.
- */
- for (i = 0; i < DLB2_NUM_COS_DOMAINS; i++) {
- for (j = 0; j < args->num_cos_ldb_ports[i]; j++) {
- for (k = 0; k < DLB2_NUM_COS_DOMAINS; k++) {
- cos_id = (i + k) % DLB2_NUM_COS_DOMAINS;
-
- ret = __dlb2_attach_ldb_ports(hw,
- rsrcs,
- domain,
- 1,
- cos_id,
- resp);
- if (ret == 0)
- break;
- }
-
- if (ret < 0)
- return ret;
- }
- }
- }
-
- /* Allocate num_ldb_ports from any class-of-service */
- for (i = 0; i < args->num_ldb_ports; i++) {
- for (j = 0; j < DLB2_NUM_COS_DOMAINS; j++) {
- ret = __dlb2_attach_ldb_ports(hw,
- rsrcs,
- domain,
- 1,
- j,
- resp);
- if (ret == 0)
- break;
- }
-
- if (ret < 0)
- return ret;
- }
-
- return 0;
-}
-
-static int dlb2_attach_dir_ports(struct dlb2_hw *hw,
- struct dlb2_function_resources *rsrcs,
- struct dlb2_hw_domain *domain,
- u32 num_ports,
- struct dlb2_cmd_response *resp)
-{
- unsigned int i;
-
- if (rsrcs->num_avail_dir_pq_pairs < num_ports) {
- resp->status = DLB2_ST_DIR_PORTS_UNAVAILABLE;
- return -EINVAL;
- }
-
- for (i = 0; i < num_ports; i++) {
- struct dlb2_dir_pq_pair *port;
-
- port = DLB2_FUNC_LIST_HEAD(rsrcs->avail_dir_pq_pairs,
- typeof(*port));
- if (port == NULL) {
- DLB2_HW_ERR(hw,
- "[%s()] Internal error: domain validation failed\n",
- __func__);
- return -EFAULT;
- }
-
- dlb2_list_del(&rsrcs->avail_dir_pq_pairs, &port->func_list);
-
- port->domain_id = domain->id;
- port->owned = true;
-
- dlb2_list_add(&domain->avail_dir_pq_pairs, &port->domain_list);
- }
-
- rsrcs->num_avail_dir_pq_pairs -= num_ports;
-
- return 0;
-}
-
-static int dlb2_attach_ldb_credits(struct dlb2_function_resources *rsrcs,
- struct dlb2_hw_domain *domain,
- u32 num_credits,
- struct dlb2_cmd_response *resp)
-{
- if (rsrcs->num_avail_qed_entries < num_credits) {
- resp->status = DLB2_ST_LDB_CREDITS_UNAVAILABLE;
- return -EINVAL;
- }
-
- rsrcs->num_avail_qed_entries -= num_credits;
- domain->num_ldb_credits += num_credits;
- return 0;
-}
-
-static int dlb2_attach_dir_credits(struct dlb2_function_resources *rsrcs,
- struct dlb2_hw_domain *domain,
- u32 num_credits,
- struct dlb2_cmd_response *resp)
-{
- if (rsrcs->num_avail_dqed_entries < num_credits) {
- resp->status = DLB2_ST_DIR_CREDITS_UNAVAILABLE;
- return -EINVAL;
- }
-
- rsrcs->num_avail_dqed_entries -= num_credits;
- domain->num_dir_credits += num_credits;
- return 0;
-}
-
-static int dlb2_attach_atomic_inflights(struct dlb2_function_resources *rsrcs,
- struct dlb2_hw_domain *domain,
- u32 num_atomic_inflights,
- struct dlb2_cmd_response *resp)
-{
- if (rsrcs->num_avail_aqed_entries < num_atomic_inflights) {
- resp->status = DLB2_ST_ATOMIC_INFLIGHTS_UNAVAILABLE;
- return -EINVAL;
- }
-
- rsrcs->num_avail_aqed_entries -= num_atomic_inflights;
- domain->num_avail_aqed_entries += num_atomic_inflights;
- return 0;
-}
-
-static int
-dlb2_attach_domain_hist_list_entries(struct dlb2_function_resources *rsrcs,
- struct dlb2_hw_domain *domain,
- u32 num_hist_list_entries,
- struct dlb2_cmd_response *resp)
-{
- struct dlb2_bitmap *bitmap;
- int base;
-
- if (num_hist_list_entries) {
- bitmap = rsrcs->avail_hist_list_entries;
-
- base = dlb2_bitmap_find_set_bit_range(bitmap,
- num_hist_list_entries);
- if (base < 0)
- goto error;
-
- domain->total_hist_list_entries = num_hist_list_entries;
- domain->avail_hist_list_entries = num_hist_list_entries;
- domain->hist_list_entry_base = base;
- domain->hist_list_entry_offset = 0;
-
- dlb2_bitmap_clear_range(bitmap, base, num_hist_list_entries);
- }
- return 0;
-
-error:
- resp->status = DLB2_ST_HIST_LIST_ENTRIES_UNAVAILABLE;
- return -EINVAL;
-}
-
-static int dlb2_attach_ldb_queues(struct dlb2_hw *hw,
- struct dlb2_function_resources *rsrcs,
- struct dlb2_hw_domain *domain,
- u32 num_queues,
- struct dlb2_cmd_response *resp)
-{
- unsigned int i;
-
- if (rsrcs->num_avail_ldb_queues < num_queues) {
- resp->status = DLB2_ST_LDB_QUEUES_UNAVAILABLE;
- return -EINVAL;
- }
-
- for (i = 0; i < num_queues; i++) {
- struct dlb2_ldb_queue *queue;
-
- queue = DLB2_FUNC_LIST_HEAD(rsrcs->avail_ldb_queues,
- typeof(*queue));
- if (queue == NULL) {
- DLB2_HW_ERR(hw,
- "[%s()] Internal error: domain validation failed\n",
- __func__);
- return -EFAULT;
- }
-
- dlb2_list_del(&rsrcs->avail_ldb_queues, &queue->func_list);
-
- queue->domain_id = domain->id;
- queue->owned = true;
-
- dlb2_list_add(&domain->avail_ldb_queues, &queue->domain_list);
- }
-
- rsrcs->num_avail_ldb_queues -= num_queues;
-
- return 0;
-}
-
-static int
-dlb2_domain_attach_resources(struct dlb2_hw *hw,
- struct dlb2_function_resources *rsrcs,
- struct dlb2_hw_domain *domain,
- struct dlb2_create_sched_domain_args *args,
- struct dlb2_cmd_response *resp)
-{
- int ret;
-
- ret = dlb2_attach_ldb_queues(hw,
- rsrcs,
- domain,
- args->num_ldb_queues,
- resp);
- if (ret < 0)
- return ret;
-
- ret = dlb2_attach_ldb_ports(hw,
- rsrcs,
- domain,
- args,
- resp);
- if (ret < 0)
- return ret;
-
- ret = dlb2_attach_dir_ports(hw,
- rsrcs,
- domain,
- args->num_dir_ports,
- resp);
- if (ret < 0)
- return ret;
-
- ret = dlb2_attach_ldb_credits(rsrcs,
- domain,
- args->num_ldb_credits,
- resp);
- if (ret < 0)
- return ret;
-
- ret = dlb2_attach_dir_credits(rsrcs,
- domain,
- args->num_dir_credits,
- resp);
- if (ret < 0)
- return ret;
-
- ret = dlb2_attach_domain_hist_list_entries(rsrcs,
- domain,
- args->num_hist_list_entries,
- resp);
- if (ret < 0)
- return ret;
-
- ret = dlb2_attach_atomic_inflights(rsrcs,
- domain,
- args->num_atomic_inflights,
- resp);
- if (ret < 0)
- return ret;
-
- dlb2_configure_domain_credits(hw, domain);
-
- domain->configured = true;
-
- domain->started = false;
-
- rsrcs->num_avail_domains--;
-
- return 0;
-}
-
-static int
-dlb2_verify_create_sched_dom_args(struct dlb2_function_resources *rsrcs,
- struct dlb2_create_sched_domain_args *args,
- struct dlb2_cmd_response *resp)
-{
- u32 num_avail_ldb_ports, req_ldb_ports;
- struct dlb2_bitmap *avail_hl_entries;
- unsigned int max_contig_hl_range;
- int i;
-
- avail_hl_entries = rsrcs->avail_hist_list_entries;
-
- max_contig_hl_range = dlb2_bitmap_longest_set_range(avail_hl_entries);
-
- num_avail_ldb_ports = 0;
- req_ldb_ports = 0;
- for (i = 0; i < DLB2_NUM_COS_DOMAINS; i++) {
- num_avail_ldb_ports += rsrcs->num_avail_ldb_ports[i];
-
- req_ldb_ports += args->num_cos_ldb_ports[i];
- }
-
- req_ldb_ports += args->num_ldb_ports;
-
- if (rsrcs->num_avail_domains < 1) {
- resp->status = DLB2_ST_DOMAIN_UNAVAILABLE;
- return -EINVAL;
- }
-
- if (rsrcs->num_avail_ldb_queues < args->num_ldb_queues) {
- resp->status = DLB2_ST_LDB_QUEUES_UNAVAILABLE;
- return -EINVAL;
- }
-
- if (req_ldb_ports > num_avail_ldb_ports) {
- resp->status = DLB2_ST_LDB_PORTS_UNAVAILABLE;
- return -EINVAL;
- }
-
- for (i = 0; args->cos_strict && i < DLB2_NUM_COS_DOMAINS; i++) {
- if (args->num_cos_ldb_ports[i] >
- rsrcs->num_avail_ldb_ports[i]) {
- resp->status = DLB2_ST_LDB_PORTS_UNAVAILABLE;
- return -EINVAL;
- }
- }
-
- if (args->num_ldb_queues > 0 && req_ldb_ports == 0) {
- resp->status = DLB2_ST_LDB_PORT_REQUIRED_FOR_LDB_QUEUES;
- return -EINVAL;
- }
-
- if (rsrcs->num_avail_dir_pq_pairs < args->num_dir_ports) {
- resp->status = DLB2_ST_DIR_PORTS_UNAVAILABLE;
- return -EINVAL;
- }
-
- if (rsrcs->num_avail_qed_entries < args->num_ldb_credits) {
- resp->status = DLB2_ST_LDB_CREDITS_UNAVAILABLE;
- return -EINVAL;
- }
-
- if (rsrcs->num_avail_dqed_entries < args->num_dir_credits) {
- resp->status = DLB2_ST_DIR_CREDITS_UNAVAILABLE;
- return -EINVAL;
- }
-
- if (rsrcs->num_avail_aqed_entries < args->num_atomic_inflights) {
- resp->status = DLB2_ST_ATOMIC_INFLIGHTS_UNAVAILABLE;
- return -EINVAL;
- }
-
- if (max_contig_hl_range < args->num_hist_list_entries) {
- resp->status = DLB2_ST_HIST_LIST_ENTRIES_UNAVAILABLE;
- return -EINVAL;
- }
-
- return 0;
-}
-
-static void
-dlb2_log_create_sched_domain_args(struct dlb2_hw *hw,
- struct dlb2_create_sched_domain_args *args,
- bool vdev_req,
- unsigned int vdev_id)
-{
- DLB2_HW_DBG(hw, "DLB2 create sched domain arguments:\n");
- if (vdev_req)
- DLB2_HW_DBG(hw, "(Request from vdev %d)\n", vdev_id);
- DLB2_HW_DBG(hw, "\tNumber of LDB queues: %d\n",
- args->num_ldb_queues);
- DLB2_HW_DBG(hw, "\tNumber of LDB ports (any CoS): %d\n",
- args->num_ldb_ports);
- DLB2_HW_DBG(hw, "\tNumber of LDB ports (CoS 0): %d\n",
- args->num_cos_ldb_ports[0]);
- DLB2_HW_DBG(hw, "\tNumber of LDB ports (CoS 1): %d\n",
- args->num_cos_ldb_ports[1]);
- DLB2_HW_DBG(hw, "\tNumber of LDB ports (CoS 2): %d\n",
- args->num_cos_ldb_ports[1]);
- DLB2_HW_DBG(hw, "\tNumber of LDB ports (CoS 3): %d\n",
- args->num_cos_ldb_ports[1]);
- DLB2_HW_DBG(hw, "\tStrict CoS allocation: %d\n",
- args->cos_strict);
- DLB2_HW_DBG(hw, "\tNumber of DIR ports: %d\n",
- args->num_dir_ports);
- DLB2_HW_DBG(hw, "\tNumber of ATM inflights: %d\n",
- args->num_atomic_inflights);
- DLB2_HW_DBG(hw, "\tNumber of hist list entries: %d\n",
- args->num_hist_list_entries);
- DLB2_HW_DBG(hw, "\tNumber of LDB credits: %d\n",
- args->num_ldb_credits);
- DLB2_HW_DBG(hw, "\tNumber of DIR credits: %d\n",
- args->num_dir_credits);
-}
-
-/**
- * dlb2_hw_create_sched_domain() - Allocate and initialize a DLB scheduling
- * domain and its resources.
- * @hw: Contains the current state of the DLB2 hardware.
- * @args: User-provided arguments.
- * @resp: Response to user.
- * @vdev_req: Request came from a virtual device.
- * @vdev_id: If vdev_req is true, this contains the virtual device's ID.
- *
- * Return: returns < 0 on error, 0 otherwise. If the driver is unable to
- * satisfy a request, resp->status will be set accordingly.
- */
-int dlb2_hw_create_sched_domain(struct dlb2_hw *hw,
- struct dlb2_create_sched_domain_args *args,
- struct dlb2_cmd_response *resp,
- bool vdev_req,
- unsigned int vdev_id)
-{
- struct dlb2_function_resources *rsrcs;
- struct dlb2_hw_domain *domain;
- int ret;
-
- rsrcs = (vdev_req) ? &hw->vdev[vdev_id] : &hw->pf;
-
- dlb2_log_create_sched_domain_args(hw, args, vdev_req, vdev_id);
-
- /*
- * Verify that hardware resources are available before attempting to
- * satisfy the request. This simplifies the error unwinding code.
- */
- ret = dlb2_verify_create_sched_dom_args(rsrcs, args, resp);
- if (ret)
- return ret;
-
- domain = DLB2_FUNC_LIST_HEAD(rsrcs->avail_domains, typeof(*domain));
- if (domain == NULL) {
- DLB2_HW_ERR(hw,
- "[%s():%d] Internal error: no available domains\n",
- __func__, __LINE__);
- return -EFAULT;
- }
-
- if (domain->configured) {
- DLB2_HW_ERR(hw,
- "[%s()] Internal error: avail_domains contains configured domains.\n",
- __func__);
- return -EFAULT;
- }
-
- dlb2_init_domain_rsrc_lists(domain);
-
- ret = dlb2_domain_attach_resources(hw, rsrcs, domain, args, resp);
- if (ret < 0) {
- DLB2_HW_ERR(hw,
- "[%s()] Internal error: failed to verify args.\n",
- __func__);
-
- return ret;
- }
-
- dlb2_list_del(&rsrcs->avail_domains, &domain->func_list);
-
- dlb2_list_add(&rsrcs->used_domains, &domain->func_list);
-
- resp->id = (vdev_req) ? domain->id.virt_id : domain->id.phys_id;
- resp->status = 0;
-
- return 0;
-}
-
/*
* The PF driver cannot assume that a register write will affect subsequent HCW
* writes. To ensure a write completes, the driver must read back a CSR. This
diff --git a/drivers/event/dlb2/pf/base/dlb2_resource_new.c b/drivers/event/dlb2/pf/base/dlb2_resource_new.c
index 14b97dbf9..8f97dd865 100644
--- a/drivers/event/dlb2/pf/base/dlb2_resource_new.c
+++ b/drivers/event/dlb2/pf/base/dlb2_resource_new.c
@@ -323,3 +323,699 @@ int dlb2_hw_get_num_resources(struct dlb2_hw *hw,
}
return 0;
}
+
+static void dlb2_configure_domain_credits_v2_5(struct dlb2_hw *hw,
+ struct dlb2_hw_domain *domain)
+{
+ u32 reg = 0;
+
+ DLB2_BITS_SET(reg, domain->num_credits, DLB2_CHP_CFG_LDB_VAS_CRD_COUNT);
+ DLB2_CSR_WR(hw, DLB2_CHP_CFG_VAS_CRD(domain->id.phys_id), reg);
+}
+
+static void dlb2_configure_domain_credits_v2(struct dlb2_hw *hw,
+ struct dlb2_hw_domain *domain)
+{
+ u32 reg = 0;
+
+ DLB2_BITS_SET(reg, domain->num_ldb_credits,
+ DLB2_CHP_CFG_LDB_VAS_CRD_COUNT);
+ DLB2_CSR_WR(hw, DLB2_CHP_CFG_LDB_VAS_CRD(domain->id.phys_id), reg);
+
+ reg = 0;
+ DLB2_BITS_SET(reg, domain->num_dir_credits,
+ DLB2_CHP_CFG_DIR_VAS_CRD_COUNT);
+ DLB2_CSR_WR(hw, DLB2_CHP_CFG_DIR_VAS_CRD(domain->id.phys_id), reg);
+}
+
+static void dlb2_configure_domain_credits(struct dlb2_hw *hw,
+ struct dlb2_hw_domain *domain)
+{
+ if (hw->ver == DLB2_HW_V2)
+ dlb2_configure_domain_credits_v2(hw, domain);
+ else
+ dlb2_configure_domain_credits_v2_5(hw, domain);
+}
+
+static int dlb2_attach_credits(struct dlb2_function_resources *rsrcs,
+ struct dlb2_hw_domain *domain,
+ u32 num_credits,
+ struct dlb2_cmd_response *resp)
+{
+ if (rsrcs->num_avail_entries < num_credits) {
+ resp->status = DLB2_ST_CREDITS_UNAVAILABLE;
+ return -EINVAL;
+ }
+
+ rsrcs->num_avail_entries -= num_credits;
+ domain->num_credits += num_credits;
+ return 0;
+}
+
+static struct dlb2_ldb_port *
+dlb2_get_next_ldb_port(struct dlb2_hw *hw,
+ struct dlb2_function_resources *rsrcs,
+ u32 domain_id,
+ u32 cos_id)
+{
+ struct dlb2_list_entry *iter;
+ struct dlb2_ldb_port *port;
+ RTE_SET_USED(iter);
+
+ /*
+ * To reduce the odds of consecutive load-balanced ports mapping to the
+ * same queue(s), the driver attempts to allocate ports whose neighbors
+ * are owned by a different domain.
+ */
+ DLB2_FUNC_LIST_FOR(rsrcs->avail_ldb_ports[cos_id], port, iter) {
+ u32 next, prev;
+ u32 phys_id;
+
+ phys_id = port->id.phys_id;
+ next = phys_id + 1;
+ prev = phys_id - 1;
+
+ if (phys_id == DLB2_MAX_NUM_LDB_PORTS - 1)
+ next = 0;
+ if (phys_id == 0)
+ prev = DLB2_MAX_NUM_LDB_PORTS - 1;
+
+ if (!hw->rsrcs.ldb_ports[next].owned ||
+ hw->rsrcs.ldb_ports[next].domain_id.phys_id == domain_id)
+ continue;
+
+ if (!hw->rsrcs.ldb_ports[prev].owned ||
+ hw->rsrcs.ldb_ports[prev].domain_id.phys_id == domain_id)
+ continue;
+
+ return port;
+ }
+
+ /*
+ * Failing that, the driver looks for a port with one neighbor owned by
+ * a different domain and the other unallocated.
+ */
+ DLB2_FUNC_LIST_FOR(rsrcs->avail_ldb_ports[cos_id], port, iter) {
+ u32 next, prev;
+ u32 phys_id;
+
+ phys_id = port->id.phys_id;
+ next = phys_id + 1;
+ prev = phys_id - 1;
+
+ if (phys_id == DLB2_MAX_NUM_LDB_PORTS - 1)
+ next = 0;
+ if (phys_id == 0)
+ prev = DLB2_MAX_NUM_LDB_PORTS - 1;
+
+ if (!hw->rsrcs.ldb_ports[prev].owned &&
+ hw->rsrcs.ldb_ports[next].owned &&
+ hw->rsrcs.ldb_ports[next].domain_id.phys_id != domain_id)
+ return port;
+
+ if (!hw->rsrcs.ldb_ports[next].owned &&
+ hw->rsrcs.ldb_ports[prev].owned &&
+ hw->rsrcs.ldb_ports[prev].domain_id.phys_id != domain_id)
+ return port;
+ }
+
+ /*
+ * Failing that, the driver looks for a port with both neighbors
+ * unallocated.
+ */
+ DLB2_FUNC_LIST_FOR(rsrcs->avail_ldb_ports[cos_id], port, iter) {
+ u32 next, prev;
+ u32 phys_id;
+
+ phys_id = port->id.phys_id;
+ next = phys_id + 1;
+ prev = phys_id - 1;
+
+ if (phys_id == DLB2_MAX_NUM_LDB_PORTS - 1)
+ next = 0;
+ if (phys_id == 0)
+ prev = DLB2_MAX_NUM_LDB_PORTS - 1;
+
+ if (!hw->rsrcs.ldb_ports[prev].owned &&
+ !hw->rsrcs.ldb_ports[next].owned)
+ return port;
+ }
+
+ /* If all else fails, the driver returns the next available port. */
+ return DLB2_FUNC_LIST_HEAD(rsrcs->avail_ldb_ports[cos_id],
+ typeof(*port));
+}
+
+static int __dlb2_attach_ldb_ports(struct dlb2_hw *hw,
+ struct dlb2_function_resources *rsrcs,
+ struct dlb2_hw_domain *domain,
+ u32 num_ports,
+ u32 cos_id,
+ struct dlb2_cmd_response *resp)
+{
+ unsigned int i;
+
+ if (rsrcs->num_avail_ldb_ports[cos_id] < num_ports) {
+ resp->status = DLB2_ST_LDB_PORTS_UNAVAILABLE;
+ return -EINVAL;
+ }
+
+ for (i = 0; i < num_ports; i++) {
+ struct dlb2_ldb_port *port;
+
+ port = dlb2_get_next_ldb_port(hw, rsrcs,
+ domain->id.phys_id, cos_id);
+ if (port == NULL) {
+ DLB2_HW_ERR(hw,
+ "[%s()] Internal error: domain validation failed\n",
+ __func__);
+ return -EFAULT;
+ }
+
+ dlb2_list_del(&rsrcs->avail_ldb_ports[cos_id],
+ &port->func_list);
+
+ port->domain_id = domain->id;
+ port->owned = true;
+
+ dlb2_list_add(&domain->avail_ldb_ports[cos_id],
+ &port->domain_list);
+ }
+
+ rsrcs->num_avail_ldb_ports[cos_id] -= num_ports;
+
+ return 0;
+}
+
+
+static int dlb2_attach_ldb_ports(struct dlb2_hw *hw,
+ struct dlb2_function_resources *rsrcs,
+ struct dlb2_hw_domain *domain,
+ struct dlb2_create_sched_domain_args *args,
+ struct dlb2_cmd_response *resp)
+{
+ unsigned int i, j;
+ int ret;
+
+ if (args->cos_strict) {
+ for (i = 0; i < DLB2_NUM_COS_DOMAINS; i++) {
+ u32 num = args->num_cos_ldb_ports[i];
+
+ /* Allocate ports from specific classes-of-service */
+ ret = __dlb2_attach_ldb_ports(hw,
+ rsrcs,
+ domain,
+ num,
+ i,
+ resp);
+ if (ret)
+ return ret;
+ }
+ } else {
+ unsigned int k;
+ u32 cos_id;
+
+ /*
+ * Attempt to allocate from specific class-of-service, but
+ * fallback to the other classes if that fails.
+ */
+ for (i = 0; i < DLB2_NUM_COS_DOMAINS; i++) {
+ for (j = 0; j < args->num_cos_ldb_ports[i]; j++) {
+ for (k = 0; k < DLB2_NUM_COS_DOMAINS; k++) {
+ cos_id = (i + k) % DLB2_NUM_COS_DOMAINS;
+
+ ret = __dlb2_attach_ldb_ports(hw,
+ rsrcs,
+ domain,
+ 1,
+ cos_id,
+ resp);
+ if (ret == 0)
+ break;
+ }
+
+ if (ret)
+ return ret;
+ }
+ }
+ }
+
+ /* Allocate num_ldb_ports from any class-of-service */
+ for (i = 0; i < args->num_ldb_ports; i++) {
+ for (j = 0; j < DLB2_NUM_COS_DOMAINS; j++) {
+ ret = __dlb2_attach_ldb_ports(hw,
+ rsrcs,
+ domain,
+ 1,
+ j,
+ resp);
+ if (ret == 0)
+ break;
+ }
+
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int dlb2_attach_dir_ports(struct dlb2_hw *hw,
+ struct dlb2_function_resources *rsrcs,
+ struct dlb2_hw_domain *domain,
+ u32 num_ports,
+ struct dlb2_cmd_response *resp)
+{
+ unsigned int i;
+
+ if (rsrcs->num_avail_dir_pq_pairs < num_ports) {
+ resp->status = DLB2_ST_DIR_PORTS_UNAVAILABLE;
+ return -EINVAL;
+ }
+
+ for (i = 0; i < num_ports; i++) {
+ struct dlb2_dir_pq_pair *port;
+
+ port = DLB2_FUNC_LIST_HEAD(rsrcs->avail_dir_pq_pairs,
+ typeof(*port));
+ if (port == NULL) {
+ DLB2_HW_ERR(hw,
+ "[%s()] Internal error: domain validation failed\n",
+ __func__);
+ return -EFAULT;
+ }
+
+ dlb2_list_del(&rsrcs->avail_dir_pq_pairs, &port->func_list);
+
+ port->domain_id = domain->id;
+ port->owned = true;
+
+ dlb2_list_add(&domain->avail_dir_pq_pairs, &port->domain_list);
+ }
+
+ rsrcs->num_avail_dir_pq_pairs -= num_ports;
+
+ return 0;
+}
+
+static int dlb2_attach_ldb_credits(struct dlb2_function_resources *rsrcs,
+ struct dlb2_hw_domain *domain,
+ u32 num_credits,
+ struct dlb2_cmd_response *resp)
+{
+ if (rsrcs->num_avail_qed_entries < num_credits) {
+ resp->status = DLB2_ST_LDB_CREDITS_UNAVAILABLE;
+ return -EINVAL;
+ }
+
+ rsrcs->num_avail_qed_entries -= num_credits;
+ domain->num_ldb_credits += num_credits;
+ return 0;
+}
+
+static int dlb2_attach_dir_credits(struct dlb2_function_resources *rsrcs,
+ struct dlb2_hw_domain *domain,
+ u32 num_credits,
+ struct dlb2_cmd_response *resp)
+{
+ if (rsrcs->num_avail_dqed_entries < num_credits) {
+ resp->status = DLB2_ST_DIR_CREDITS_UNAVAILABLE;
+ return -EINVAL;
+ }
+
+ rsrcs->num_avail_dqed_entries -= num_credits;
+ domain->num_dir_credits += num_credits;
+ return 0;
+}
+
+
+static int dlb2_attach_atomic_inflights(struct dlb2_function_resources *rsrcs,
+ struct dlb2_hw_domain *domain,
+ u32 num_atomic_inflights,
+ struct dlb2_cmd_response *resp)
+{
+ if (rsrcs->num_avail_aqed_entries < num_atomic_inflights) {
+ resp->status = DLB2_ST_ATOMIC_INFLIGHTS_UNAVAILABLE;
+ return -EINVAL;
+ }
+
+ rsrcs->num_avail_aqed_entries -= num_atomic_inflights;
+ domain->num_avail_aqed_entries += num_atomic_inflights;
+ return 0;
+}
+
+static int
+dlb2_attach_domain_hist_list_entries(struct dlb2_function_resources *rsrcs,
+ struct dlb2_hw_domain *domain,
+ u32 num_hist_list_entries,
+ struct dlb2_cmd_response *resp)
+{
+ struct dlb2_bitmap *bitmap;
+ int base;
+
+ if (num_hist_list_entries) {
+ bitmap = rsrcs->avail_hist_list_entries;
+
+ base = dlb2_bitmap_find_set_bit_range(bitmap,
+ num_hist_list_entries);
+ if (base < 0)
+ goto error;
+
+ domain->total_hist_list_entries = num_hist_list_entries;
+ domain->avail_hist_list_entries = num_hist_list_entries;
+ domain->hist_list_entry_base = base;
+ domain->hist_list_entry_offset = 0;
+
+ dlb2_bitmap_clear_range(bitmap, base, num_hist_list_entries);
+ }
+ return 0;
+
+error:
+ resp->status = DLB2_ST_HIST_LIST_ENTRIES_UNAVAILABLE;
+ return -EINVAL;
+}
+
+static int dlb2_attach_ldb_queues(struct dlb2_hw *hw,
+ struct dlb2_function_resources *rsrcs,
+ struct dlb2_hw_domain *domain,
+ u32 num_queues,
+ struct dlb2_cmd_response *resp)
+{
+ unsigned int i;
+
+ if (rsrcs->num_avail_ldb_queues < num_queues) {
+ resp->status = DLB2_ST_LDB_QUEUES_UNAVAILABLE;
+ return -EINVAL;
+ }
+
+ for (i = 0; i < num_queues; i++) {
+ struct dlb2_ldb_queue *queue;
+
+ queue = DLB2_FUNC_LIST_HEAD(rsrcs->avail_ldb_queues,
+ typeof(*queue));
+ if (queue == NULL) {
+ DLB2_HW_ERR(hw,
+ "[%s()] Internal error: domain validation failed\n",
+ __func__);
+ return -EFAULT;
+ }
+
+ dlb2_list_del(&rsrcs->avail_ldb_queues, &queue->func_list);
+
+ queue->domain_id = domain->id;
+ queue->owned = true;
+
+ dlb2_list_add(&domain->avail_ldb_queues, &queue->domain_list);
+ }
+
+ rsrcs->num_avail_ldb_queues -= num_queues;
+
+ return 0;
+}
+
+static int
+dlb2_domain_attach_resources(struct dlb2_hw *hw,
+ struct dlb2_function_resources *rsrcs,
+ struct dlb2_hw_domain *domain,
+ struct dlb2_create_sched_domain_args *args,
+ struct dlb2_cmd_response *resp)
+{
+ int ret;
+
+ ret = dlb2_attach_ldb_queues(hw,
+ rsrcs,
+ domain,
+ args->num_ldb_queues,
+ resp);
+ if (ret)
+ return ret;
+
+ ret = dlb2_attach_ldb_ports(hw,
+ rsrcs,
+ domain,
+ args,
+ resp);
+ if (ret)
+ return ret;
+
+ ret = dlb2_attach_dir_ports(hw,
+ rsrcs,
+ domain,
+ args->num_dir_ports,
+ resp);
+ if (ret)
+ return ret;
+
+ if (hw->ver == DLB2_HW_V2) {
+ ret = dlb2_attach_ldb_credits(rsrcs,
+ domain,
+ args->num_ldb_credits,
+ resp);
+ if (ret)
+ return ret;
+
+ ret = dlb2_attach_dir_credits(rsrcs,
+ domain,
+ args->num_dir_credits,
+ resp);
+ if (ret)
+ return ret;
+ } else { /* DLB 2.5 */
+ ret = dlb2_attach_credits(rsrcs,
+ domain,
+ args->num_credits,
+ resp);
+ if (ret)
+ return ret;
+ }
+
+ ret = dlb2_attach_domain_hist_list_entries(rsrcs,
+ domain,
+ args->num_hist_list_entries,
+ resp);
+ if (ret)
+ return ret;
+
+ ret = dlb2_attach_atomic_inflights(rsrcs,
+ domain,
+ args->num_atomic_inflights,
+ resp);
+ if (ret)
+ return ret;
+
+ dlb2_configure_domain_credits(hw, domain);
+
+ domain->configured = true;
+
+ domain->started = false;
+
+ rsrcs->num_avail_domains--;
+
+ return 0;
+}
+
+static int
+dlb2_verify_create_sched_dom_args(struct dlb2_function_resources *rsrcs,
+ struct dlb2_create_sched_domain_args *args,
+ struct dlb2_cmd_response *resp,
+ struct dlb2_hw *hw,
+ struct dlb2_hw_domain **out_domain)
+{
+ u32 num_avail_ldb_ports, req_ldb_ports;
+ struct dlb2_bitmap *avail_hl_entries;
+ unsigned int max_contig_hl_range;
+ struct dlb2_hw_domain *domain;
+ int i;
+
+ avail_hl_entries = rsrcs->avail_hist_list_entries;
+
+ max_contig_hl_range = dlb2_bitmap_longest_set_range(avail_hl_entries);
+
+ num_avail_ldb_ports = 0;
+ req_ldb_ports = 0;
+ for (i = 0; i < DLB2_NUM_COS_DOMAINS; i++) {
+ num_avail_ldb_ports += rsrcs->num_avail_ldb_ports[i];
+
+ req_ldb_ports += args->num_cos_ldb_ports[i];
+ }
+
+ req_ldb_ports += args->num_ldb_ports;
+
+ if (rsrcs->num_avail_domains < 1) {
+ resp->status = DLB2_ST_DOMAIN_UNAVAILABLE;
+ return -EINVAL;
+ }
+
+ domain = DLB2_FUNC_LIST_HEAD(rsrcs->avail_domains, typeof(*domain));
+ if (domain == NULL) {
+ resp->status = DLB2_ST_DOMAIN_UNAVAILABLE;
+ return -EFAULT;
+ }
+
+ if (rsrcs->num_avail_ldb_queues < args->num_ldb_queues) {
+ resp->status = DLB2_ST_LDB_QUEUES_UNAVAILABLE;
+ return -EINVAL;
+ }
+
+ if (req_ldb_ports > num_avail_ldb_ports) {
+ resp->status = DLB2_ST_LDB_PORTS_UNAVAILABLE;
+ return -EINVAL;
+ }
+
+ for (i = 0; args->cos_strict && i < DLB2_NUM_COS_DOMAINS; i++) {
+ if (args->num_cos_ldb_ports[i] >
+ rsrcs->num_avail_ldb_ports[i]) {
+ resp->status = DLB2_ST_LDB_PORTS_UNAVAILABLE;
+ return -EINVAL;
+ }
+ }
+
+ if (args->num_ldb_queues > 0 && req_ldb_ports == 0) {
+ resp->status = DLB2_ST_LDB_PORT_REQUIRED_FOR_LDB_QUEUES;
+ return -EINVAL;
+ }
+
+ if (rsrcs->num_avail_dir_pq_pairs < args->num_dir_ports) {
+ resp->status = DLB2_ST_DIR_PORTS_UNAVAILABLE;
+ return -EINVAL;
+ }
+ if (hw->ver == DLB2_HW_V2_5) {
+ if (rsrcs->num_avail_entries < args->num_credits) {
+ resp->status = DLB2_ST_CREDITS_UNAVAILABLE;
+ return -EINVAL;
+ }
+ } else {
+ if (rsrcs->num_avail_qed_entries < args->num_ldb_credits) {
+ resp->status = DLB2_ST_LDB_CREDITS_UNAVAILABLE;
+ return -EINVAL;
+ }
+ if (rsrcs->num_avail_dqed_entries < args->num_dir_credits) {
+ resp->status = DLB2_ST_DIR_CREDITS_UNAVAILABLE;
+ return -EINVAL;
+ }
+ }
+
+ if (rsrcs->num_avail_aqed_entries < args->num_atomic_inflights) {
+ resp->status = DLB2_ST_ATOMIC_INFLIGHTS_UNAVAILABLE;
+ return -EINVAL;
+ }
+
+ if (max_contig_hl_range < args->num_hist_list_entries) {
+ resp->status = DLB2_ST_HIST_LIST_ENTRIES_UNAVAILABLE;
+ return -EINVAL;
+ }
+
+ *out_domain = domain;
+
+ return 0;
+}
+
+static void
+dlb2_log_create_sched_domain_args(struct dlb2_hw *hw,
+ struct dlb2_create_sched_domain_args *args,
+ bool vdev_req,
+ unsigned int vdev_id)
+{
+ DLB2_HW_DBG(hw, "DLB2 create sched domain arguments:\n");
+ if (vdev_req)
+ DLB2_HW_DBG(hw, "(Request from vdev %d)\n", vdev_id);
+ DLB2_HW_DBG(hw, "\tNumber of LDB queues: %d\n",
+ args->num_ldb_queues);
+ DLB2_HW_DBG(hw, "\tNumber of LDB ports (any CoS): %d\n",
+ args->num_ldb_ports);
+ DLB2_HW_DBG(hw, "\tNumber of LDB ports (CoS 0): %d\n",
+ args->num_cos_ldb_ports[0]);
+ DLB2_HW_DBG(hw, "\tNumber of LDB ports (CoS 1): %d\n",
+ args->num_cos_ldb_ports[1]);
+ DLB2_HW_DBG(hw, "\tNumber of LDB ports (CoS 2): %d\n",
+ args->num_cos_ldb_ports[2]);
+ DLB2_HW_DBG(hw, "\tNumber of LDB ports (CoS 3): %d\n",
+ args->num_cos_ldb_ports[3]);
+ DLB2_HW_DBG(hw, "\tStrict CoS allocation: %d\n",
+ args->cos_strict);
+ DLB2_HW_DBG(hw, "\tNumber of DIR ports: %d\n",
+ args->num_dir_ports);
+ DLB2_HW_DBG(hw, "\tNumber of ATM inflights: %d\n",
+ args->num_atomic_inflights);
+ DLB2_HW_DBG(hw, "\tNumber of hist list entries: %d\n",
+ args->num_hist_list_entries);
+ if (hw->ver == DLB2_HW_V2) {
+ DLB2_HW_DBG(hw, "\tNumber of LDB credits: %d\n",
+ args->num_ldb_credits);
+ DLB2_HW_DBG(hw, "\tNumber of DIR credits: %d\n",
+ args->num_dir_credits);
+ } else {
+ DLB2_HW_DBG(hw, "\tNumber of credits: %d\n",
+ args->num_credits);
+ }
+}
+
+/**
+ * dlb2_hw_create_sched_domain() - create a scheduling domain
+ * @hw: dlb2_hw handle for a particular device.
+ * @args: scheduling domain creation arguments.
+ * @resp: response structure.
+ * @vdev_req: indicates whether this request came from a vdev.
+ * @vdev_id: If vdev_req is true, this contains the vdev's ID.
+ *
+ * This function creates a scheduling domain containing the resources specified
+ * in args. The individual resources (queues, ports, credits) can be configured
+ * after creating a scheduling domain.
+ *
+ * A vdev can be either an SR-IOV virtual function or a Scalable IOV virtual
+ * device.
+ *
+ * Return:
+ * Returns 0 upon success, < 0 otherwise. If an error occurs, resp->status is
+ * assigned a detailed error code from enum dlb2_error. If successful, resp->id
+ * contains the domain ID.
+ *
+ * resp->id contains a virtual ID if vdev_req is true.
+ *
+ * Errors:
+ * EINVAL - A requested resource is unavailable, or the requested domain name
+ * is already in use.
+ * EFAULT - Internal error (resp->status not set).
+ */
+int dlb2_hw_create_sched_domain(struct dlb2_hw *hw,
+ struct dlb2_create_sched_domain_args *args,
+ struct dlb2_cmd_response *resp,
+ bool vdev_req,
+ unsigned int vdev_id)
+{
+ struct dlb2_function_resources *rsrcs;
+ struct dlb2_hw_domain *domain;
+ int ret;
+
+ rsrcs = (vdev_req) ? &hw->vdev[vdev_id] : &hw->pf;
+
+ dlb2_log_create_sched_domain_args(hw, args, vdev_req, vdev_id);
+
+ /*
+ * Verify that hardware resources are available before attempting to
+ * satisfy the request. This simplifies the error unwinding code.
+ */
+ ret = dlb2_verify_create_sched_dom_args(rsrcs, args, resp, hw, &domain);
+ if (ret)
+ return ret;
+
+ dlb2_init_domain_rsrc_lists(domain);
+
+ ret = dlb2_domain_attach_resources(hw, rsrcs, domain, args, resp);
+ if (ret) {
+ DLB2_HW_ERR(hw,
+ "[%s()] Internal error: failed to verify args.\n",
+ __func__);
+
+ return ret;
+ }
+
+ dlb2_list_del(&rsrcs->avail_domains, &domain->func_list);
+
+ dlb2_list_add(&rsrcs->used_domains, &domain->func_list);
+
+ resp->id = (vdev_req) ? domain->id.virt_id : domain->id.phys_id;
+ resp->status = 0;
+
+ return 0;
+}
--
2.23.0
next prev parent reply other threads:[~2021-04-13 20:16 UTC|newest]
Thread overview: 174+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-16 22:18 [dpdk-dev] [PATCH 00/25] Add Support for DLB v2.5 Timothy McDaniel
2021-03-16 22:18 ` [dpdk-dev] [PATCH 01/25] event/dlb2: add dlb v2.5 probe Timothy McDaniel
2021-03-21 9:48 ` Jerin Jacob
2021-03-24 19:31 ` McDaniel, Timothy
2021-03-26 11:01 ` Jerin Jacob
2021-03-26 14:03 ` McDaniel, Timothy
2021-03-26 14:33 ` Jerin Jacob
2021-03-29 15:00 ` McDaniel, Timothy
2021-03-29 15:51 ` Jerin Jacob
2021-03-29 15:55 ` McDaniel, Timothy
2021-03-30 19:35 ` [dpdk-dev] [PATCH v2 00/27] Add DLB V2.5 Timothy McDaniel
2021-03-30 19:35 ` [dpdk-dev] [PATCH v2 01/27] event/dlb2: add v2.5 probe Timothy McDaniel
2021-03-30 19:35 ` [dpdk-dev] [PATCH v2 02/27] event/dlb2: add v2.5 HW init Timothy McDaniel
2021-04-03 10:18 ` Jerin Jacob
2021-03-30 19:35 ` [dpdk-dev] [PATCH v2 03/27] event/dlb2: add v2.5 get_resources Timothy McDaniel
2021-03-30 19:35 ` [dpdk-dev] [PATCH v2 04/27] event/dlb2: add v2.5 create sched domain Timothy McDaniel
2021-03-30 19:35 ` [dpdk-dev] [PATCH v2 05/27] event/dlb2: add v2.5 domain reset Timothy McDaniel
2021-03-30 19:35 ` [dpdk-dev] [PATCH v2 06/27] event/dlb2: add V2.5 create ldb queue Timothy McDaniel
2021-04-14 19:20 ` Jerin Jacob
2021-04-14 19:41 ` McDaniel, Timothy
2021-03-30 19:35 ` [dpdk-dev] [PATCH v2 07/27] event/dlb2: add v2.5 create ldb port Timothy McDaniel
2021-03-30 19:35 ` [dpdk-dev] [PATCH v2 08/27] event/dlb2: add v2.5 create dir port Timothy McDaniel
2021-03-30 19:35 ` [dpdk-dev] [PATCH v2 09/27] event/dlb2: add v2.5 create dir queue Timothy McDaniel
2021-04-03 10:26 ` Jerin Jacob
2021-03-30 19:35 ` [dpdk-dev] [PATCH v2 10/27] event/dlb2: add v2.5 map qid Timothy McDaniel
2021-03-30 19:35 ` [dpdk-dev] [PATCH v2 11/27] event/dlb2: add v2.5 unmap queue Timothy McDaniel
2021-03-30 19:35 ` [dpdk-dev] [PATCH v2 12/27] event/dlb2: add v2.5 start domain Timothy McDaniel
2021-04-14 19:23 ` Jerin Jacob
2021-04-14 19:42 ` McDaniel, Timothy
2021-03-30 19:35 ` [dpdk-dev] [PATCH v2 13/27] event/dlb2: add v2.5 credit scheme Timothy McDaniel
2021-03-30 19:35 ` [dpdk-dev] [PATCH v2 14/27] event/dlb2: add v2.5 queue depth functions Timothy McDaniel
2021-03-30 19:35 ` [dpdk-dev] [PATCH v2 15/27] event/dlb2: add v2.5 finish map/unmap Timothy McDaniel
2021-03-30 19:35 ` [dpdk-dev] [PATCH v2 16/27] event/dlb2: add v2.5 sparse cq mode Timothy McDaniel
2021-03-30 19:35 ` [dpdk-dev] [PATCH v2 17/27] event/dlb2: add v2.5 sequence number management Timothy McDaniel
2021-03-30 19:35 ` [dpdk-dev] [PATCH v2 18/27] event/dlb2: consolidate resource header files into one file Timothy McDaniel
2021-03-30 19:35 ` [dpdk-dev] [PATCH v2 19/27] event/dlb2: delete old dlb2_resource.c file Timothy McDaniel
2021-03-30 19:35 ` [dpdk-dev] [PATCH v2 20/27] event/dlb2: move dlb_resource_new.c to dlb_resource.c Timothy McDaniel
2021-04-03 10:29 ` Jerin Jacob
2021-03-30 19:35 ` [dpdk-dev] [PATCH v2 21/27] event/dlb2: remove temporary file, dlb_hw_types.h Timothy McDaniel
2021-03-30 19:35 ` [dpdk-dev] [PATCH v2 22/27] event/dlb2: move dlb2_hw_type_new.h to dlb2_hw_types.h Timothy McDaniel
2021-03-30 19:35 ` [dpdk-dev] [PATCH v2 23/27] event/dlb2: delete old register map file, dlb2_regs.h Timothy McDaniel
2021-03-30 19:35 ` [dpdk-dev] [PATCH v2 24/27] event/dlb2: rename dlb2_regs_new.h to dlb2_regs.h Timothy McDaniel
2021-03-30 19:35 ` [dpdk-dev] [PATCH v2 25/27] event/dlb2: update xstats for v2.5 Timothy McDaniel
2021-03-30 19:35 ` [dpdk-dev] [PATCH v2 26/27] doc/dlb2: update documentation " Timothy McDaniel
2021-03-30 19:35 ` [dpdk-dev] [PATCH v2 27/27] event/dlb2: Change device name to dlb_event Timothy McDaniel
2021-04-03 10:39 ` Jerin Jacob
2021-04-03 9:51 ` [dpdk-dev] [PATCH v2 00/27] Add DLB V2.5 Jerin Jacob
2021-04-13 20:14 ` [dpdk-dev] [PATCH v3 00/26] " Timothy McDaniel
2021-04-13 20:14 ` [dpdk-dev] [PATCH v3 01/26] event/dlb2: add v2.5 probe Timothy McDaniel
2021-04-14 19:16 ` Jerin Jacob
2021-04-14 19:41 ` McDaniel, Timothy
2021-04-14 19:47 ` Jerin Jacob
2021-04-13 20:14 ` [dpdk-dev] [PATCH v3 02/26] event/dlb2: add v2.5 HW register definitions Timothy McDaniel
2021-04-13 20:14 ` [dpdk-dev] [PATCH v3 03/26] event/dlb2: add v2.5 HW init Timothy McDaniel
2021-04-13 20:14 ` [dpdk-dev] [PATCH v3 04/26] event/dlb2: add v2.5 get resources Timothy McDaniel
2021-04-13 20:14 ` Timothy McDaniel [this message]
2021-04-13 20:14 ` [dpdk-dev] [PATCH v3 06/26] event/dlb2: add v2.5 domain reset Timothy McDaniel
2021-04-13 20:14 ` [dpdk-dev] [PATCH v3 07/26] event/dlb2: add V2.5 create ldb queue Timothy McDaniel
2021-04-13 20:14 ` [dpdk-dev] [PATCH v3 08/26] event/dlb2: add v2.5 create ldb port Timothy McDaniel
2021-04-13 20:14 ` [dpdk-dev] [PATCH v3 09/26] event/dlb2: add v2.5 create dir port Timothy McDaniel
2021-04-13 20:14 ` [dpdk-dev] [PATCH v3 10/26] event/dlb2: add v2.5 create dir queue Timothy McDaniel
2021-04-13 20:14 ` [dpdk-dev] [PATCH v3 11/26] event/dlb2: add v2.5 map qid Timothy McDaniel
2021-04-13 20:14 ` [dpdk-dev] [PATCH v3 12/26] event/dlb2: add v2.5 unmap queue Timothy McDaniel
2021-04-13 20:14 ` [dpdk-dev] [PATCH v3 13/26] event/dlb2: add v2.5 start domain Timothy McDaniel
2021-04-13 20:14 ` [dpdk-dev] [PATCH v3 14/26] event/dlb2: add v2.5 credit scheme Timothy McDaniel
2021-04-13 20:14 ` [dpdk-dev] [PATCH v3 15/26] event/dlb2: add v2.5 queue depth functions Timothy McDaniel
2021-04-13 20:14 ` [dpdk-dev] [PATCH v3 16/26] event/dlb2: add v2.5 finish map/unmap Timothy McDaniel
2021-04-13 20:14 ` [dpdk-dev] [PATCH v3 17/26] event/dlb2: add v2.5 sparse cq mode Timothy McDaniel
2021-04-13 20:14 ` [dpdk-dev] [PATCH v3 18/26] event/dlb2: add v2.5 sequence number management Timothy McDaniel
2021-04-13 20:14 ` [dpdk-dev] [PATCH v3 19/26] event/dlb2: use new implementation of resource header Timothy McDaniel
2021-04-13 20:14 ` [dpdk-dev] [PATCH v3 20/26] event/dlb2: use new implementation of resource file Timothy McDaniel
2021-04-13 20:14 ` [dpdk-dev] [PATCH v3 21/26] event/dlb2: use new implementation of HW types header Timothy McDaniel
2021-04-13 20:14 ` [dpdk-dev] [PATCH v3 22/26] event/dlb2: use new combined register map Timothy McDaniel
2021-04-13 20:14 ` [dpdk-dev] [PATCH v3 23/26] event/dlb2: update xstats for v2.5 Timothy McDaniel
2021-04-13 20:14 ` [dpdk-dev] [PATCH v3 24/26] doc/dlb2: update documentation " Timothy McDaniel
2021-04-13 20:14 ` [dpdk-dev] [PATCH v3 25/26] event/dlb: remove version from device name Timothy McDaniel
2021-04-14 19:31 ` Jerin Jacob
2021-04-14 19:42 ` McDaniel, Timothy
2021-04-14 19:44 ` Jerin Jacob
2021-04-14 20:33 ` Thomas Monjalon
2021-04-15 3:22 ` McDaniel, Timothy
2021-04-15 5:47 ` Jerin Jacob
2021-04-15 7:48 ` Thomas Monjalon
2021-04-15 7:56 ` Jerin Jacob
2021-04-13 20:14 ` [dpdk-dev] [PATCH v3 26/26] event/dlb: move rte config defines to runtime devargs Timothy McDaniel
2021-04-14 19:11 ` Jerin Jacob
2021-04-14 19:38 ` McDaniel, Timothy
2021-04-14 19:52 ` Jerin Jacob
2021-04-15 1:48 ` [dpdk-dev] [PATCH v4 00/27] Add DLB v2.5 Timothy McDaniel
2021-04-15 1:48 ` [dpdk-dev] [PATCH v4 01/27] event/dlb2: minor code cleanup Timothy McDaniel
2021-04-15 1:48 ` [dpdk-dev] [PATCH v4 02/27] event/dlb2: add v2.5 probe Timothy McDaniel
2021-04-29 7:09 ` Jerin Jacob
2021-04-29 13:46 ` McDaniel, Timothy
2021-04-15 1:48 ` [dpdk-dev] [PATCH v4 03/27] event/dlb2: add v2.5 HW register definitions Timothy McDaniel
2021-04-15 1:48 ` [dpdk-dev] [PATCH v4 04/27] event/dlb2: add v2.5 HW init Timothy McDaniel
2021-04-15 1:48 ` [dpdk-dev] [PATCH v4 05/27] event/dlb2: add v2.5 get resources Timothy McDaniel
2021-04-15 1:48 ` [dpdk-dev] [PATCH v4 06/27] event/dlb2: add v2.5 create sched domain Timothy McDaniel
2021-04-15 1:48 ` [dpdk-dev] [PATCH v4 07/27] event/dlb2: add v2.5 domain reset Timothy McDaniel
2021-04-15 1:49 ` [dpdk-dev] [PATCH v4 08/27] event/dlb2: add v2.5 create ldb queue Timothy McDaniel
2021-04-15 1:49 ` [dpdk-dev] [PATCH v4 09/27] event/dlb2: add v2.5 create ldb port Timothy McDaniel
2021-04-15 1:49 ` [dpdk-dev] [PATCH v4 10/27] event/dlb2: add v2.5 create dir port Timothy McDaniel
2021-04-15 1:49 ` [dpdk-dev] [PATCH v4 11/27] event/dlb2: add v2.5 create dir queue Timothy McDaniel
2021-04-15 1:49 ` [dpdk-dev] [PATCH v4 12/27] event/dlb2: add v2.5 map qid Timothy McDaniel
2021-04-15 1:49 ` [dpdk-dev] [PATCH v4 13/27] event/dlb2: add v2.5 unmap queue Timothy McDaniel
2021-04-15 1:49 ` [dpdk-dev] [PATCH v4 14/27] event/dlb2: add v2.5 start domain Timothy McDaniel
2021-04-15 1:49 ` [dpdk-dev] [PATCH v4 15/27] event/dlb2: add v2.5 credit scheme Timothy McDaniel
2021-04-15 1:49 ` [dpdk-dev] [PATCH v4 16/27] event/dlb2: add v2.5 queue depth functions Timothy McDaniel
2021-04-15 1:49 ` [dpdk-dev] [PATCH v4 17/27] event/dlb2: add v2.5 finish map/unmap Timothy McDaniel
2021-04-15 1:49 ` [dpdk-dev] [PATCH v4 18/27] event/dlb2: add v2.5 sparse cq mode Timothy McDaniel
2021-04-15 1:49 ` [dpdk-dev] [PATCH v4 19/27] event/dlb2: add v2.5 sequence number management Timothy McDaniel
2021-04-15 1:49 ` [dpdk-dev] [PATCH v4 20/27] event/dlb2: use new implementation of resource header Timothy McDaniel
2021-04-15 1:49 ` [dpdk-dev] [PATCH v4 21/27] event/dlb2: use new implementation of resource file Timothy McDaniel
2021-04-15 1:49 ` [dpdk-dev] [PATCH v4 22/27] event/dlb2: use new implementation of HW types header Timothy McDaniel
2021-04-15 1:49 ` [dpdk-dev] [PATCH v4 23/27] event/dlb2: use new combined register map Timothy McDaniel
2021-04-15 1:49 ` [dpdk-dev] [PATCH v4 24/27] event/dlb2: update xstats for v2.5 Timothy McDaniel
2021-04-15 1:49 ` [dpdk-dev] [PATCH v4 25/27] doc/dlb2: update documentation " Timothy McDaniel
2021-04-15 1:49 ` [dpdk-dev] [PATCH v4 26/27] event/dlb: rename dlb2 driver Timothy McDaniel
2021-04-15 1:49 ` [dpdk-dev] [PATCH v4 27/27] event/dlb: move rte config defines to runtime devargs Timothy McDaniel
2021-05-01 19:03 ` [dpdk-dev] [PATCH v5 00/26] Add DLB v2.5 McDaniel, Timothy
2021-05-01 19:03 ` [dpdk-dev] [PATCH v5 01/26] event/dlb2: minor code cleanup McDaniel, Timothy
2021-05-01 19:03 ` [dpdk-dev] [PATCH v5 02/26] event/dlb2: add v2.5 probe McDaniel, Timothy
2021-05-01 19:03 ` [dpdk-dev] [PATCH v5 03/26] event/dlb2: add v2.5 HW register definitions McDaniel, Timothy
2021-05-01 19:03 ` [dpdk-dev] [PATCH v5 04/26] event/dlb2: add v2.5 HW init McDaniel, Timothy
2021-05-01 19:03 ` [dpdk-dev] [PATCH v5 05/26] event/dlb2: add v2.5 get resources McDaniel, Timothy
2021-05-01 19:03 ` [dpdk-dev] [PATCH v5 06/26] event/dlb2: add v2.5 create sched domain McDaniel, Timothy
2021-05-01 19:03 ` [dpdk-dev] [PATCH v5 07/26] event/dlb2: add v2.5 domain reset McDaniel, Timothy
2021-05-01 19:03 ` [dpdk-dev] [PATCH v5 08/26] event/dlb2: add v2.5 create ldb queue McDaniel, Timothy
2021-05-01 19:03 ` [dpdk-dev] [PATCH v5 09/26] event/dlb2: add v2.5 create ldb port McDaniel, Timothy
2021-05-01 19:03 ` [dpdk-dev] [PATCH v5 10/26] event/dlb2: add v2.5 create dir port McDaniel, Timothy
2021-05-01 19:03 ` [dpdk-dev] [PATCH v5 11/26] event/dlb2: add v2.5 create dir queue McDaniel, Timothy
2021-05-01 19:03 ` [dpdk-dev] [PATCH v5 12/26] event/dlb2: add v2.5 map qid McDaniel, Timothy
2021-05-01 19:03 ` [dpdk-dev] [PATCH v5 13/26] event/dlb2: add v2.5 unmap queue McDaniel, Timothy
2021-05-01 19:03 ` [dpdk-dev] [PATCH v5 14/26] event/dlb2: add v2.5 start domain McDaniel, Timothy
2021-05-01 19:03 ` [dpdk-dev] [PATCH v5 15/26] event/dlb2: add v2.5 credit scheme McDaniel, Timothy
2021-05-01 19:03 ` [dpdk-dev] [PATCH v5 16/26] event/dlb2: add v2.5 queue depth functions McDaniel, Timothy
2021-05-01 19:03 ` [dpdk-dev] [PATCH v5 17/26] event/dlb2: add v2.5 finish map/unmap McDaniel, Timothy
2021-05-01 19:03 ` [dpdk-dev] [PATCH v5 18/26] event/dlb2: add v2.5 sparse cq mode McDaniel, Timothy
2021-05-01 19:03 ` [dpdk-dev] [PATCH v5 19/26] event/dlb2: add v2.5 sequence number management McDaniel, Timothy
2021-05-01 19:03 ` [dpdk-dev] [PATCH v5 20/26] event/dlb2: use new implementation of resource header McDaniel, Timothy
2021-05-01 19:03 ` [dpdk-dev] [PATCH v5 21/26] event/dlb2: use new implementation of resource file McDaniel, Timothy
2021-05-01 19:03 ` [dpdk-dev] [PATCH v5 22/26] event/dlb2: use new implementation of HW types header McDaniel, Timothy
2021-05-01 19:03 ` [dpdk-dev] [PATCH v5 23/26] event/dlb2: use new combined register map McDaniel, Timothy
2021-05-01 19:03 ` [dpdk-dev] [PATCH v5 24/26] event/dlb2: update xstats for v2.5 McDaniel, Timothy
2021-05-01 19:04 ` [dpdk-dev] [PATCH v5 25/26] event/dlb2: move rte config defines to runtime devargs McDaniel, Timothy
2021-05-01 19:04 ` [dpdk-dev] [PATCH v5 26/26] doc/dlb2: update documentation for v2.5 McDaniel, Timothy
2021-05-04 8:28 ` [dpdk-dev] [PATCH v5 00/26] Add DLB v2.5 Jerin Jacob
2021-03-16 22:18 ` [dpdk-dev] [PATCH 02/25] event/dlb2: add DLB v2.5 probe-time hardware init Timothy McDaniel
2021-03-21 10:30 ` [dpdk-dev] [EXT] " Jerin Jacob Kollanukkaran
2021-03-26 16:37 ` McDaniel, Timothy
2021-03-16 22:18 ` [dpdk-dev] [PATCH 03/25] event/dlb2: add DLB v2.5 support to get_resources Timothy McDaniel
2021-03-16 22:18 ` [dpdk-dev] [PATCH 04/25] event/dlb2: add DLB v2.5 support to create sched domain Timothy McDaniel
2021-04-03 10:22 ` Jerin Jacob
2021-03-16 22:18 ` [dpdk-dev] [PATCH 05/25] event/dlb2: add DLB v2.5 support to domain reset Timothy McDaniel
2021-03-16 22:18 ` [dpdk-dev] [PATCH 06/25] event/dlb2: add DLB V2.5 support to create ldb queue Timothy McDaniel
2021-03-16 22:18 ` [dpdk-dev] [PATCH 07/25] event/dlb2: add DLB v2.5 support to create ldb port Timothy McDaniel
2021-03-16 22:18 ` [dpdk-dev] [PATCH 08/25] event/dlb2: add DLB v2.5 support to create dir port Timothy McDaniel
2021-03-16 22:18 ` [dpdk-dev] [PATCH 09/25] event/dlb2: add DLB v2.5 support to create dir queue Timothy McDaniel
2021-03-16 22:18 ` [dpdk-dev] [PATCH 10/25] event/dlb2: add DLB v2.5 support to map qid Timothy McDaniel
2021-03-16 22:18 ` [dpdk-dev] [PATCH 11/25] event/dlb2: add DLB v2.5 support to unmap queue Timothy McDaniel
2021-03-16 22:18 ` [dpdk-dev] [PATCH 12/25] event/dlb2: add DLB v2.5 support to start domain Timothy McDaniel
2021-03-16 22:18 ` [dpdk-dev] [PATCH 13/25] event/dlb2: add DLB v2.5 credit scheme Timothy McDaniel
2021-03-16 22:18 ` [dpdk-dev] [PATCH 14/25] event/dlb2: Add DLB v2.5 support to get queue depth functions Timothy McDaniel
2021-03-16 22:18 ` [dpdk-dev] [PATCH 15/25] event/dlb2: add DLB v2.5 finish map/unmap interfaces Timothy McDaniel
2021-03-16 22:18 ` [dpdk-dev] [PATCH 16/25] event/dlb2: add DLB v2.5 sparse cq mode Timothy McDaniel
2021-03-16 22:18 ` [dpdk-dev] [PATCH 17/25] event/dlb2: add DLB v2.5 support to sequence number management Timothy McDaniel
2021-03-16 22:18 ` [dpdk-dev] [PATCH 18/25] event/dlb2: consolidate dlb resource header files into one file Timothy McDaniel
2021-03-16 22:18 ` [dpdk-dev] [PATCH 19/25] event/dlb2: delete old dlb2_resource.c file Timothy McDaniel
2021-03-16 22:18 ` [dpdk-dev] [PATCH 20/25] event/dlb2: move dlb_resource_new.c to dlb_resource.c Timothy McDaniel
2021-03-16 22:18 ` [dpdk-dev] [PATCH 21/25] event/dlb2: remove temporary file, dlb_hw_types.h Timothy McDaniel
2021-03-16 22:18 ` [dpdk-dev] [PATCH 22/25] event/dlb2: move dlb2_hw_type_new.h to dlb2_hw_types.h Timothy McDaniel
2021-03-16 22:18 ` [dpdk-dev] [PATCH 23/25] event/dlb2: delete old register map file, dlb2_regs.h Timothy McDaniel
2021-03-16 22:18 ` [dpdk-dev] [PATCH 24/25] event/dlb2: rename dlb2_regs_new.h to dlb2_regs.h Timothy McDaniel
2021-03-16 22:18 ` [dpdk-dev] [PATCH 25/25] event/dlb2: update xstats for DLB v2.5 Timothy McDaniel
2021-03-21 10:50 ` [dpdk-dev] [PATCH 00/25] Add Support " Jerin Jacob
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for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).