From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8D3FCA0524; Wed, 2 Jun 2021 17:56:47 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4BF024069F; Wed, 2 Jun 2021 17:56:47 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 3E9B040689 for ; Wed, 2 Jun 2021 17:56:45 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 152FoB6F002559; Wed, 2 Jun 2021 08:56:43 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=Fbz/THXAQ1o1uHkkEpFuNZxGsAzVWi8+MRMxBPhXJ1g=; b=k0eS3QZaVgZZL6ZN1xjsYAczrr5QjxvM1QMEPNAnQXofvlaTjo/VlwLWQ3Vc9FsLLEdh F+mqtoK3kq4rozIFPNNaW3amS3fAaFQdwOhJ0HcC+4LeEdkB3T/O10JQ7XP6okkuYgHR Ilx3CBHOMLt5Tv9INm9XzfXa9PNNIusuJo9PGepPobX9Lms4aXwkwOefav94bmTfm/hf qYIx70I3LswGCLyXjBnkznjR8RUF2UaDzzcgua1bISQTnzKEDMIgvc4QZn0fqwWfa107 tIIht6Ct37lOqrhZPn4actfZ54gygcypmfwwzYHuBZbWM2yBhgNn6n9pDY97i2IDKoL7 UA== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com with ESMTP id 38wug73n7v-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 02 Jun 2021 08:56:43 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 2 Jun 2021 08:56:42 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 2 Jun 2021 08:56:42 -0700 Received: from HY-LT1002.marvell.com (unknown [10.193.70.1]) by maili.marvell.com (Postfix) with ESMTP id 8FCE03F703F; Wed, 2 Jun 2021 08:56:39 -0700 (PDT) From: Anoob Joseph To: Akhil Goyal , Thomas Monjalon CC: Anoob Joseph , Jerin Jacob , "Ankur Dwivedi" , Tejasree Kondoj , Date: Wed, 2 Jun 2021 21:26:14 +0530 Message-ID: <1622649385-22652-1-git-send-email-anoobj@marvell.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: WBF9vaKlFNBy4Hyu3sbV-6ZUz6ilZ8sN X-Proofpoint-GUID: WBF9vaKlFNBy4Hyu3sbV-6ZUz6ilZ8sN X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-06-02_08:2021-06-02, 2021-06-02 signatures=0 Subject: [dpdk-dev] [PATCH 00/11] Add CPT in Marvell CNXK common driver X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patchset adds initial support for CPT in common code for Marvell CN10K SoC. CPT is the hardware cryptographic block available in 'cnxk' family SoC. CPT, with its microcoded engines can support symmetric, asymmetric and IPsec operations. CPT can associate with NIX (rte_ethdev) to enable inline IPsec functionality. Similarly, CPT can associate with SSO (rte_eventdev) to enable crypto adapter. Based on CNXK common driver, new crypto PMDs would be added under 'crypto/cnxk'. Aakash Sasidharan (2): common/cnxk: add CPT diagnostics common/cnxk: add CPT LF flush Anoob Joseph (2): common/cnxk: add CPT dev config routines common/cnxk: add lmtline init Archana Muniganti (1): common/cnxk: add CPT LF config Kiran Kumar Kokkilagadda (3): common/cnxk: add SE microcode defines common/cnxk: add AE microcode defines common/cnxk: add fpm tables Srujana Challa (1): common/cnxk: add IE microcode defines Vidya Sagar Velumuri (2): common/cnxk: add CPT HW defines common/cnxk: add mbox to configure RXC drivers/common/cnxk/hw/cpt.h | 201 ++++++ drivers/common/cnxk/meson.build | 2 + drivers/common/cnxk/roc_ae.h | 56 ++ drivers/common/cnxk/roc_ae_fpm_tables.c | 1140 +++++++++++++++++++++++++++++++ drivers/common/cnxk/roc_ae_fpm_tables.h | 13 + drivers/common/cnxk/roc_api.h | 14 + drivers/common/cnxk/roc_cpt.c | 782 +++++++++++++++++++++ drivers/common/cnxk/roc_cpt.h | 99 +++ drivers/common/cnxk/roc_cpt_priv.h | 28 + drivers/common/cnxk/roc_dev.c | 2 + drivers/common/cnxk/roc_dev_priv.h | 1 + drivers/common/cnxk/roc_ie.h | 19 + drivers/common/cnxk/roc_ie_on.h | 18 + drivers/common/cnxk/roc_ie_ot.h | 588 ++++++++++++++++ drivers/common/cnxk/roc_platform.c | 1 + drivers/common/cnxk/roc_platform.h | 3 + drivers/common/cnxk/roc_priv.h | 3 + drivers/common/cnxk/roc_se.h | 287 ++++++++ drivers/common/cnxk/version.map | 16 + 19 files changed, 3273 insertions(+) create mode 100644 drivers/common/cnxk/hw/cpt.h create mode 100644 drivers/common/cnxk/roc_ae.h create mode 100644 drivers/common/cnxk/roc_ae_fpm_tables.c create mode 100644 drivers/common/cnxk/roc_ae_fpm_tables.h create mode 100644 drivers/common/cnxk/roc_cpt.c create mode 100644 drivers/common/cnxk/roc_cpt.h create mode 100644 drivers/common/cnxk/roc_cpt_priv.h create mode 100644 drivers/common/cnxk/roc_ie.h create mode 100644 drivers/common/cnxk/roc_ie_on.h create mode 100644 drivers/common/cnxk/roc_ie_ot.h create mode 100644 drivers/common/cnxk/roc_se.h -- 2.7.4