From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7E894A0524; Wed, 2 Jun 2021 17:56:53 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5F53F410E0; Wed, 2 Jun 2021 17:56:53 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id A90B8410DF for ; Wed, 2 Jun 2021 17:56:51 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 152FpJqY019768; Wed, 2 Jun 2021 08:56:50 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=8noq4biWFTi7jYNzcE4xaJzPn4W7X8tkICKyMxBa29A=; b=C5PAHbiL6pNB1KkkD41y1oITjTZM0VbF3rcAMLjCxNGW2X3UHNhlxbONnMfa4/4S7/gF rwjVzUPlBC26REgJKO4ZinZzUQvi35jkaJ08ueV/CcqHxi4dqkWRp9BCYV2OCewFzfKV UFMp15Tl8JmBg/kw/+vEcFAOFyo9hVkYBxIOt65OdtQjNhGkng6X2sZr1vNERqDHwmYy Yonu2AaKdmElG47IN6bHFuO++KxUEZByLmGyt/s4ue9Ja4j361Z6TffA0/pubccAUPaB H2wwrew4BS8LSR2C0zd609Wif43TZ/+noYInPr2tYh7ga+NvY+aAxG04ZPPqUvnroz4c 1A== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 38wufguhan-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 02 Jun 2021 08:56:50 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 2 Jun 2021 08:56:48 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 2 Jun 2021 08:56:48 -0700 Received: from HY-LT1002.marvell.com (unknown [10.193.70.1]) by maili.marvell.com (Postfix) with ESMTP id 049C63F703F; Wed, 2 Jun 2021 08:56:44 -0700 (PDT) From: Anoob Joseph To: Akhil Goyal , Thomas Monjalon CC: Vidya Sagar Velumuri , Jerin Jacob , Ankur Dwivedi , Tejasree Kondoj , , Anoob Joseph Date: Wed, 2 Jun 2021 21:26:15 +0530 Message-ID: <1622649385-22652-2-git-send-email-anoobj@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1622649385-22652-1-git-send-email-anoobj@marvell.com> References: <1622649385-22652-1-git-send-email-anoobj@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: Y0JUfMo-iXqe9GvBNFnSzy5AezWFPVcT X-Proofpoint-GUID: Y0JUfMo-iXqe9GvBNFnSzy5AezWFPVcT X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-06-02_08:2021-06-02, 2021-06-02 signatures=0 Subject: [dpdk-dev] [PATCH 01/11] common/cnxk: add CPT HW defines X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Vidya Sagar Velumuri Add CPT hardware definitions. CPT is the hardware block on cnxk family of processors, that can be used to offload cryptographic operations. Signed-off-by: Anoob Joseph Signed-off-by: Vidya Sagar Velumuri --- drivers/common/cnxk/hw/cpt.h | 201 ++++++++++++++++++++++++++++++++++++++++++ drivers/common/cnxk/roc_api.h | 6 ++ 2 files changed, 207 insertions(+) create mode 100644 drivers/common/cnxk/hw/cpt.h diff --git a/drivers/common/cnxk/hw/cpt.h b/drivers/common/cnxk/hw/cpt.h new file mode 100644 index 0000000..d6a935c --- /dev/null +++ b/drivers/common/cnxk/hw/cpt.h @@ -0,0 +1,201 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#ifndef __CPT_HW_H__ +#define __CPT_HW_H__ + +/* Register offsets */ + +#define CPT_COMP_NOT_DONE (0x0ull) +#define CPT_COMP_GOOD (0x1ull) +#define CPT_COMP_FAULT (0x2ull) +#define CPT_COMP_SWERR (0x3ull) +#define CPT_COMP_HWERR (0x4ull) +#define CPT_COMP_INSTERR (0x5ull) +#define CPT_COMP_WARN (0x6ull) /* [CN10K, .) */ + +#define CPT_LF_INT_VEC_MISC (0x0ull) +#define CPT_LF_INT_VEC_DONE (0x1ull) +#define CPT_LF_CTL (0x10ull) +#define CPT_LF_DONE_WAIT (0x30ull) +#define CPT_LF_INPROG (0x40ull) +#define CPT_LF_DONE (0x50ull) +#define CPT_LF_DONE_ACK (0x60ull) +#define CPT_LF_DONE_INT_ENA_W1S (0x90ull) +#define CPT_LF_DONE_INT_ENA_W1C (0xa0ull) +#define CPT_LF_MISC_INT (0xb0ull) +#define CPT_LF_MISC_INT_W1S (0xc0ull) +#define CPT_LF_MISC_INT_ENA_W1S (0xd0ull) +#define CPT_LF_MISC_INT_ENA_W1C (0xe0ull) +#define CPT_LF_Q_BASE (0xf0ull) +#define CPT_LF_Q_SIZE (0x100ull) +#define CPT_LF_Q_INST_PTR (0x110ull) +#define CPT_LF_Q_GRP_PTR (0x120ull) +#define CPT_LF_NQX(a) (0x400ull | (uint64_t)(a) << 3) +#define CPT_LF_CTX_CTL (0x500ull) +#define CPT_LF_CTX_FLUSH (0x510ull) +#define CPT_LF_CTX_ERR (0x520ull) +#define CPT_LF_CTX_ENC_BYTE_CNT (0x530ull) +#define CPT_LF_CTX_ENC_PKT_CNT (0x540ull) +#define CPT_LF_CTX_DEC_BYTE_CNT (0x550ull) +#define CPT_LF_CTX_DEC_PKT_CNT (0x560ull) + +#define CPT_AF_LFX_CTL(a) (0x27000ull | (uint64_t)(a) << 3) +#define CPT_AF_LFX_CTL2(a) (0x29000ull | (uint64_t)(a) << 3) + +/* Structures definitions */ + +union cpt_lf_ctl { + uint64_t u; + struct cpt_lf_ctl_s { + uint64_t ena : 1; + uint64_t fc_ena : 1; + uint64_t fc_up_crossing : 1; + uint64_t reserved_3_3 : 1; + uint64_t fc_hyst_bits : 4; + uint64_t reserved_8_63 : 56; + } s; +}; + +union cpt_lf_ctx_flush { + uint64_t u; + struct { + uint64_t cptr : 46; + uint64_t inval : 1; + uint64_t res : 1; + uint64_t pf_func : 16; + } s; +}; + +union cpt_lf_inprog { + uint64_t u; + struct cpt_lf_inprog_s { + uint64_t inflight : 9; + uint64_t reserved_9_15 : 7; + uint64_t eena : 1; + uint64_t grp_drp : 1; + uint64_t reserved_18_30 : 13; + uint64_t grb_partial : 1; + uint64_t grb_cnt : 8; + uint64_t gwb_cnt : 8; + uint64_t reserved_48_63 : 16; + } s; +}; + +union cpt_lf_q_base { + uint64_t u; + struct cpt_lf_q_base_s { + uint64_t fault : 1; + uint64_t stopped : 1; + uint64_t reserved_2_6 : 5; + uint64_t addr : 46; + uint64_t reserved_53_63 : 11; + } s; +}; + +union cpt_lf_q_size { + uint64_t u; + struct cpt_lf_q_size_s { + uint64_t size_div40 : 15; + uint64_t reserved_15_63 : 49; + } s; +}; + +union cpt_lf_misc_int { + uint64_t u; + struct cpt_lf_misc_int_s { + uint64_t reserved_0_0 : 1; + uint64_t nqerr : 1; + uint64_t irde : 1; + uint64_t nwrp : 1; + uint64_t reserved_4_4 : 1; + uint64_t hwerr : 1; + uint64_t fault : 1; + uint64_t reserved_7_63 : 57; + } s; +}; + +union cpt_inst_w4 { + uint64_t u64; + struct { + uint64_t dlen : 16; + uint64_t param2 : 16; + uint64_t param1 : 16; + uint64_t opcode_major : 8; + uint64_t opcode_minor : 8; + } s; +}; + +union cpt_inst_w7 { + uint64_t u64; + struct { + uint64_t cptr : 60; + uint64_t ctx_val : 1; + uint64_t egrp : 3; + } s; +}; + +struct cpt_inst_s { + union cpt_inst_w0 { + struct { + uint64_t nixtxl : 3; + uint64_t doneint : 1; + uint64_t nixtx_addr : 60; + } s; + uint64_t u64; + } w0; + + uint64_t res_addr; + + union cpt_inst_w2 { + struct { + uint64_t tag : 32; + uint64_t tt : 2; + uint64_t grp : 10; + uint64_t reserved_172_175 : 4; + uint64_t rvu_pf_func : 16; + } s; + uint64_t u64; + } w2; + + union cpt_inst_w3 { + struct { + uint64_t qord : 1; + uint64_t reserved_194_193 : 2; + uint64_t wqe_ptr : 61; + } s; + uint64_t u64; + } w3; + + union cpt_inst_w4 w4; + + uint64_t dptr; + + uint64_t rptr; + + union cpt_inst_w7 w7; +}; + +union cpt_res_s { + struct cpt_cn10k_res_s { + uint64_t compcode : 7; + uint64_t doneint : 1; + uint64_t uc_compcode : 8; + uint64_t rlen : 16; + uint64_t spi : 32; + + uint64_t esn; + } cn10k; + + struct cpt_cn9k_res_s { + uint64_t compcode : 8; + uint64_t uc_compcode : 8; + uint64_t doneint : 1; + uint64_t reserved_17_63 : 47; + + uint64_t reserved_64_127; + } cn9k; +}; + +#endif /* __CPT_HW_H__ */ diff --git a/drivers/common/cnxk/roc_api.h b/drivers/common/cnxk/roc_api.h index 67f5d13..049854d 100644 --- a/drivers/common/cnxk/roc_api.h +++ b/drivers/common/cnxk/roc_api.h @@ -54,6 +54,11 @@ #define PCI_DEVID_CN9K_CGX 0xA059 #define PCI_DEVID_CN10K_RPM 0xA060 +#define PCI_DEVID_CN9K_RVU_CPT_PF 0xA0FD +#define PCI_DEVID_CN9K_RVU_CPT_VF 0xA0FE +#define PCI_DEVID_CN10K_RVU_CPT_PF 0xA0F2 +#define PCI_DEVID_CN10K_RVU_CPT_VF 0xA0F3 + #define PCI_SUBSYSTEM_DEVID_CN10KA 0xB900 #define PCI_SUBSYSTEM_DEVID_CN10KAS 0xB900 @@ -64,6 +69,7 @@ #define PCI_SUBSYSTEM_DEVID_CN9KE 0xB100 /* HW structure definition */ +#include "hw/cpt.h" #include "hw/nix.h" #include "hw/npa.h" #include "hw/npc.h" -- 2.7.4