From: Anoob Joseph <anoobj@marvell.com>
To: Akhil Goyal <gakhil@marvell.com>, Thomas Monjalon <thomas@monjalon.net>
Cc: Srujana Challa <schalla@marvell.com>,
Jerin Jacob <jerinj@marvell.com>,
Ankur Dwivedi <adwivedi@marvell.com>,
Tejasree Kondoj <ktejasree@marvell.com>, <dev@dpdk.org>,
Anoob Joseph <anoobj@marvell.com>
Subject: [dpdk-dev] [PATCH v2 11/17] common/cnxk: add IE microcode defines
Date: Fri, 25 Jun 2021 11:06:43 +0530 [thread overview]
Message-ID: <1624599410-29689-12-git-send-email-anoobj@marvell.com> (raw)
In-Reply-To: <1624599410-29689-1-git-send-email-anoobj@marvell.com>
From: Srujana Challa <schalla@marvell.com>
Microcode IE opcodes support IPsec operations. Add defines
and structs defined by microcode.
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Srujana Challa <schalla@marvell.com>
Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
---
drivers/common/cnxk/roc_api.h | 2 +
drivers/common/cnxk/roc_ie.h | 19 ++
drivers/common/cnxk/roc_ie_on.h | 152 +++++++++++
drivers/common/cnxk/roc_ie_ot.h | 534 +++++++++++++++++++++++++++++++++++++
drivers/common/cnxk/roc_platform.h | 1 +
5 files changed, 708 insertions(+)
create mode 100644 drivers/common/cnxk/roc_ie.h
create mode 100644 drivers/common/cnxk/roc_ie_on.h
create mode 100644 drivers/common/cnxk/roc_ie_ot.h
diff --git a/drivers/common/cnxk/roc_api.h b/drivers/common/cnxk/roc_api.h
index 6511614..d545bb9 100644
--- a/drivers/common/cnxk/roc_api.h
+++ b/drivers/common/cnxk/roc_api.h
@@ -110,6 +110,8 @@
#include "roc_cpt.h"
/* CPT microcode */
+#include "roc_ie_on.h"
+#include "roc_ie_ot.h"
#include "roc_se.h"
#endif /* _ROC_API_H_ */
diff --git a/drivers/common/cnxk/roc_ie.h b/drivers/common/cnxk/roc_ie.h
new file mode 100644
index 0000000..a330ea1
--- /dev/null
+++ b/drivers/common/cnxk/roc_ie.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef __ROC_IE_H__
+#define __ROC_IE_H__
+
+/* CNXK IPSEC helper macros */
+#define ROC_IE_AH_HDR_LEN 12
+#define ROC_IE_AES_GCM_IV_LEN 8
+#define ROC_IE_AES_GCM_MAC_LEN 16
+#define ROC_IE_AES_CBC_IV_LEN 16
+#define ROC_IE_SHA1_HMAC_LEN 12
+#define ROC_IE_AUTH_KEY_LEN_MAX 64
+
+#define ROC_IE_AES_GCM_ROUNDUP_BYTE_LEN 4
+#define ROC_IE_AES_CBC_ROUNDUP_BYTE_LEN 16
+
+#endif /* __ROC_IE_H__ */
diff --git a/drivers/common/cnxk/roc_ie_on.h b/drivers/common/cnxk/roc_ie_on.h
new file mode 100644
index 0000000..508654a
--- /dev/null
+++ b/drivers/common/cnxk/roc_ie_on.h
@@ -0,0 +1,152 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef __ROC_IE_ON_H__
+#define __ROC_IE_ON_H__
+
+/* CN9K IPSEC LA opcodes */
+#define ROC_IE_ONL_MAJOR_OP_WRITE_IPSEC_OUTBOUND 0x20
+#define ROC_IE_ONL_MAJOR_OP_WRITE_IPSEC_INBOUND 0x21
+#define ROC_IE_ONL_MAJOR_OP_PROCESS_OUTBOUND_IPSEC 0x23
+#define ROC_IE_ONL_MAJOR_OP_PROCESS_INBOUND_IPSEC 0x24
+
+/* CN9K IPSEC FP opcodes */
+#define ROC_IE_ONF_MAJOR_OP_PROCESS_OUTBOUND_IPSEC 0x25UL
+#define ROC_IE_ONF_MAJOR_OP_PROCESS_INBOUND_IPSEC 0x26UL
+
+/* Ucode completion codes */
+#define ROC_IE_ONF_UCC_SUCCESS 0
+
+enum {
+ ROC_IE_ON_SA_DIR_INBOUND = 0,
+ ROC_IE_ON_SA_DIR_OUTBOUND = 1,
+};
+
+enum {
+ ROC_IE_ON_SA_IP_VERSION_4 = 0,
+ ROC_IE_ON_SA_IP_VERSION_6 = 1,
+};
+
+enum {
+ ROC_IE_ON_SA_MODE_TRANSPORT = 0,
+ ROC_IE_ON_SA_MODE_TUNNEL = 1,
+};
+
+enum {
+ ROC_IE_ON_SA_PROTOCOL_AH = 0,
+ ROC_IE_ON_SA_PROTOCOL_ESP = 1,
+};
+
+enum {
+ ROC_IE_ON_SA_AES_KEY_LEN_128 = 1,
+ ROC_IE_ON_SA_AES_KEY_LEN_192 = 2,
+ ROC_IE_ON_SA_AES_KEY_LEN_256 = 3,
+};
+
+enum {
+ ROC_IE_ON_SA_ENC_NULL = 0,
+ ROC_IE_ON_SA_ENC_DES_CBC = 1,
+ ROC_IE_ON_SA_ENC_3DES_CBC = 2,
+ ROC_IE_ON_SA_ENC_AES_CBC = 3,
+ ROC_IE_ON_SA_ENC_AES_CTR = 4,
+ ROC_IE_ON_SA_ENC_AES_GCM = 5,
+ ROC_IE_ON_SA_ENC_AES_CCM = 6,
+};
+
+enum {
+ ROC_IE_ON_SA_AUTH_NULL = 0,
+ ROC_IE_ON_SA_AUTH_MD5 = 1,
+ ROC_IE_ON_SA_AUTH_SHA1 = 2,
+ ROC_IE_ON_SA_AUTH_SHA2_224 = 3,
+ ROC_IE_ON_SA_AUTH_SHA2_256 = 4,
+ ROC_IE_ON_SA_AUTH_SHA2_384 = 5,
+ ROC_IE_ON_SA_AUTH_SHA2_512 = 6,
+ ROC_IE_ON_SA_AUTH_AES_GMAC = 7,
+ ROC_IE_ON_SA_AUTH_AES_XCBC_128 = 8,
+};
+
+enum {
+ ROC_IE_ON_SA_FRAG_POST = 0,
+ ROC_IE_ON_SA_FRAG_PRE = 1,
+};
+
+enum {
+ ROC_IE_ON_SA_ENCAP_NONE = 0,
+ ROC_IE_ON_SA_ENCAP_UDP = 1,
+};
+
+struct roc_ie_onf_sa_ctl {
+ uint32_t spi;
+ uint64_t exp_proto_inter_frag : 8;
+ uint64_t rsvd_41_40 : 2;
+ /* Disable SPI, SEQ data in RPTR for Inbound inline */
+ uint64_t spi_seq_dis : 1;
+ uint64_t esn_en : 1;
+ uint64_t rsvd_44_45 : 2;
+ uint64_t encap_type : 2;
+ uint64_t enc_type : 3;
+ uint64_t rsvd_48 : 1;
+ uint64_t auth_type : 4;
+ uint64_t valid : 1;
+ uint64_t direction : 1;
+ uint64_t outer_ip_ver : 1;
+ uint64_t inner_ip_ver : 1;
+ uint64_t ipsec_mode : 1;
+ uint64_t ipsec_proto : 1;
+ uint64_t aes_key_len : 2;
+};
+
+struct roc_onf_ipsec_outb_sa {
+ /* w0 */
+ struct roc_ie_onf_sa_ctl ctl;
+
+ /* w1 */
+ uint8_t nonce[4];
+ uint16_t udp_src;
+ uint16_t udp_dst;
+
+ /* w2 */
+ uint32_t ip_src;
+ uint32_t ip_dst;
+
+ /* w3-w6 */
+ uint8_t cipher_key[32];
+
+ /* w7-w12 */
+ uint8_t hmac_key[48];
+};
+
+struct roc_onf_ipsec_inb_sa {
+ /* w0 */
+ struct roc_ie_onf_sa_ctl ctl;
+
+ /* w1 */
+ uint8_t nonce[4]; /* Only for AES-GCM */
+ uint32_t unused;
+
+ /* w2 */
+ uint32_t esn_hi;
+ uint32_t esn_low;
+
+ /* w3-w6 */
+ uint8_t cipher_key[32];
+
+ /* w7-w12 */
+ uint8_t hmac_key[48];
+};
+
+#define ROC_ONF_IPSEC_INB_MAX_L2_SZ 32UL
+#define ROC_ONF_IPSEC_OUTB_MAX_L2_SZ 30UL
+#define ROC_ONF_IPSEC_OUTB_MAX_L2_INFO_SZ (ROC_ONF_IPSEC_OUTB_MAX_L2_SZ + 2)
+
+#define ROC_ONF_IPSEC_INB_RES_OFF 80
+#define ROC_ONF_IPSEC_INB_SPI_SEQ_SZ 16
+
+struct roc_onf_ipsec_outb_hdr {
+ uint32_t ip_id;
+ uint32_t seq;
+ uint8_t iv[16];
+};
+
+#endif /* __ROC_IE_ON_H__ */
diff --git a/drivers/common/cnxk/roc_ie_ot.h b/drivers/common/cnxk/roc_ie_ot.h
new file mode 100644
index 0000000..aeb4be2
--- /dev/null
+++ b/drivers/common/cnxk/roc_ie_ot.h
@@ -0,0 +1,534 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef __ROC_IE_OT_H__
+#define __ROC_IE_OT_H__
+
+/* PKIND to be used for CPT Meta parsing */
+#define ROC_OT_CPT_META_PKIND 58
+
+/* CN10K IPSEC opcodes */
+#define ROC_IE_OT_MAJOR_OP_PROCESS_OUTBOUND_IPSEC 0x28UL
+#define ROC_IE_OT_MAJOR_OP_PROCESS_INBOUND_IPSEC 0x29UL
+
+enum roc_ie_ot_ucc_ipsec {
+ ROC_IE_OT_UCC_SUCCESS = 0x00,
+ ROC_IE_OT_UCC_SUCCESS_PKT_IP_GOODCSUM = 0x02,
+ ROC_IE_OT_UCC_ERR_SA_INVAL = 0x03,
+ ROC_IE_OT_UCC_SUCCESS_PKT_IP_BADCSUM = 0x04,
+ ROC_IE_OT_UCC_ERR_SA_EXPIRED = 0x05,
+ ROC_IE_OT_UCC_SUCCESS_PKT_L4_GOODCSUM = 0x06,
+ ROC_IE_OT_UCC_ERR_SA_OVERFLOW = 0x07,
+ ROC_IE_OT_UCC_SUCCESS_PKT_L4_BADCSUM = 0x08,
+ ROC_IE_OT_UCC_ERR_SA_ESP_BAD_ALGO = 0x09,
+ ROC_IE_OT_UCC_SUCCESS_PKT_UDPESP_NZCSUM = 0x0a,
+ ROC_IE_OT_UCC_ERR_SA_ESP_BAD_KEYS = 0x0b,
+ ROC_IE_OT_UCC_SUCCESS_SA_SOFTEXP_FIRST = 0x0c,
+ ROC_IE_OT_UCC_ERR_SA_AH_BAD_ALGO = 0x0d,
+ ROC_IE_OT_UCC_SUCCESS_SA_SOFTEXP_AGAIN = 0x0e,
+ ROC_IE_OT_UCC_ERR_SA_AH_BAD_KEYS = 0x0f,
+ ROC_IE_OT_UCC_ERR_SA_BAD_IP = 0x11,
+ ROC_IE_OT_UCC_ERR_SA_BAD_CTX = 0x13,
+ ROC_IE_OT_UCC_ERR_AOP_IPSEC = 0x17,
+ ROC_IE_OT_UCC_ERR_PKT_IP = 0x23,
+ ROC_IE_OT_UCC_ERR_PKT_IP6_BAD_EXT = 0x25,
+ ROC_IE_OT_UCC_ERR_PKT_IP6_HBH = 0x27,
+ ROC_IE_OT_UCC_ERR_PKT_IP6_BIGEXT = 0x29,
+ ROC_IE_OT_UCC_ERR_PKT_IP_FRAG = 0x2b,
+ ROC_IE_OT_UCC_ERR_PKT_IP_ULP = 0x2d,
+ ROC_IE_OT_UCC_ERR_PKT_SA_MISMATCH = 0x2f,
+ ROC_IE_OT_UCC_ERR_PKT_SPI_MISMATCH = 0x31,
+ ROC_IE_OT_UCC_ERR_PKT_ESP_BADPAD = 0x33,
+ ROC_IE_OT_UCC_ERR_PKT_BADICV = 0x35,
+ ROC_IE_OT_UCC_ERR_PKT_REPLAY_SEQ = 0x37,
+ ROC_IE_OT_UCC_ERR_PKT_REPLAY_WINDOW = 0x39,
+ ROC_IE_OT_UCC_ERR_PKT_BADNH = 0x3b,
+ ROC_IE_OT_UCC_ERR_PKT_SA_PORT_MISMATCH = 0x3d,
+};
+
+enum {
+ ROC_IE_OT_SA_AR_WIN_DISABLED = 0,
+ ROC_IE_OT_SA_AR_WIN_64 = 1,
+ ROC_IE_OT_SA_AR_WIN_128 = 2,
+ ROC_IE_OT_SA_AR_WIN_256 = 3,
+ ROC_IE_OT_SA_AR_WIN_512 = 4,
+ ROC_IE_OT_SA_AR_WIN_1024 = 5,
+ ROC_IE_OT_SA_AR_WIN_2048 = 6,
+ ROC_IE_OT_SA_AR_WIN_4096 = 7,
+};
+
+enum {
+ ROC_IE_OT_SA_PKT_FMT_FULL = 0,
+ ROC_IE_OT_SA_PKT_FMT_META = 1,
+};
+
+enum {
+ ROC_IE_OT_SA_PKT_OUTPUT_DECRYPTED = 0,
+ ROC_IE_OT_SA_PKT_OUTPUT_NO_FRAG = 1,
+ ROC_IE_OT_SA_PKT_OUTPUT_HW_BASED_DEFRAG = 2,
+ ROC_IE_OT_SA_PKT_OUTPUT_UCODE_BASED_DEFRAG = 3,
+};
+
+enum {
+ ROC_IE_OT_SA_DEFRAG_ALL = 0,
+ ROC_IE_OT_SA_DEFRAG_IN_ORDER = 1,
+ ROC_IE_OT_SA_DEFRAG_IN_REV_ORDER = 2,
+};
+
+enum {
+ ROC_IE_OT_SA_IV_SRC_DEFAULT = 0,
+ ROC_IE_OT_SA_IV_SRC_ENC_CTR = 1,
+ ROC_IE_OT_SA_IV_SRC_FROM_SA = 2,
+};
+
+enum {
+ ROC_IE_OT_SA_COPY_FROM_SA = 0,
+ ROC_IE_OT_SA_COPY_FROM_INNER_IP_HDR = 1,
+};
+
+enum {
+ ROC_IE_OT_SA_INNER_PKT_IP_CSUM_ENABLE = 0,
+ ROC_IE_OT_SA_INNER_PKT_IP_CSUM_DISABLE = 1,
+};
+
+enum {
+ ROC_IE_OT_SA_INNER_PKT_L4_CSUM_ENABLE = 0,
+ ROC_IE_OT_SA_INNER_PKT_L4_CSUM_DISABLE = 1,
+};
+
+enum {
+ ROC_IE_OT_SA_DIR_INBOUND = 0,
+ ROC_IE_OT_SA_DIR_OUTBOUND = 1,
+};
+
+enum {
+ ROC_IE_OT_SA_IP_VERSION_4 = 0,
+ ROC_IE_OT_SA_IP_VERSION_6 = 1,
+};
+
+enum {
+ ROC_IE_OT_SA_MODE_TRANSPORT = 0,
+ ROC_IE_OT_SA_MODE_TUNNEL = 1,
+};
+
+enum {
+ ROC_IE_OT_SA_PROTOCOL_AH = 0,
+ ROC_IE_OT_SA_PROTOCOL_ESP = 1,
+};
+
+enum {
+ ROC_IE_OT_SA_AES_KEY_LEN_128 = 1,
+ ROC_IE_OT_SA_AES_KEY_LEN_192 = 2,
+ ROC_IE_OT_SA_AES_KEY_LEN_256 = 3,
+};
+
+enum {
+ ROC_IE_OT_SA_ENC_NULL = 0,
+ ROC_IE_OT_SA_ENC_3DES_CBC = 2,
+ ROC_IE_OT_SA_ENC_AES_CBC = 3,
+ ROC_IE_OT_SA_ENC_AES_CTR = 4,
+ ROC_IE_OT_SA_ENC_AES_GCM = 5,
+ ROC_IE_OT_SA_ENC_AES_CCM = 6,
+};
+
+enum {
+ ROC_IE_OT_SA_AUTH_NULL = 0,
+ ROC_IE_OT_SA_AUTH_SHA1 = 2,
+ ROC_IE_OT_SA_AUTH_SHA2_256 = 4,
+ ROC_IE_OT_SA_AUTH_SHA2_384 = 5,
+ ROC_IE_OT_SA_AUTH_SHA2_512 = 6,
+ ROC_IE_OT_SA_AUTH_AES_GMAC = 7,
+ ROC_IE_OT_SA_AUTH_AES_XCBC_128 = 8,
+};
+
+enum {
+ ROC_IE_OT_SA_ENCAP_NONE = 0,
+ ROC_IE_OT_SA_ENCAP_UDP = 1,
+ ROC_IE_OT_SA_ENCAP_TCP = 2,
+};
+
+enum {
+ ROC_IE_OT_SA_LIFE_UNIT_OCTETS = 0,
+ ROC_IE_OT_SA_LIFE_UNIT_PKTS = 1,
+};
+
+enum {
+ ROC_IE_OT_SA_IP_HDR_VERIFY_DISABLED = 0,
+ ROC_IE_OT_SA_IP_HDR_VERIFY_DST_ADDR = 1,
+ ROC_IE_OT_SA_IP_HDR_VERIFY_SRC_DST_ADDR = 2,
+};
+
+enum {
+ ROC_IE_OT_REAS_STS_SUCCESS = 0,
+ ROC_IE_OT_REAS_STS_TIMEOUT = 1,
+ ROC_IE_OT_REAS_STS_EVICT = 2,
+ ROC_IE_OT_REAS_STS_BAD_ORDER = 3,
+ ROC_IE_OT_REAS_STS_TOO_MANY = 4,
+ ROC_IE_OT_REAS_STS_HSH_EVICT = 5,
+ ROC_IE_OT_REAS_STS_OVERLAP = 6,
+ ROC_IE_OT_REAS_STS_ZOMBIE = 7,
+ ROC_IE_OT_REAS_STS_L3P_ERR = 8,
+ ROC_IE_OT_REAS_STS_MAX = 9
+};
+/* Context units in bytes */
+#define ROC_CTX_UNIT_8B 8
+#define ROC_CTX_UNIT_128B 128
+#define ROC_CTX_MAX_CKEY_LEN 32
+#define ROC_CTX_MAX_OPAD_IPAD_LEN 128
+
+/* Anti reply window size supported */
+#define ROC_AR_WIN_SIZE_MIN 64
+#define ROC_AR_WIN_SIZE_MAX 4096
+#define ROC_LOG_MIN_AR_WIN_SIZE_M1 5
+
+/* u64 array size to fit anti replay window bits */
+#define ROC_AR_WINBITS_SZ \
+ (PLT_ALIGN_CEIL(ROC_AR_WIN_SIZE_MAX, BITS_PER_LONG_LONG) / \
+ BITS_PER_LONG_LONG)
+
+/* Common bit fields between inbound and outbound SA */
+union roc_ot_ipsec_sa_word2 {
+ struct {
+ uint64_t valid : 1;
+ uint64_t dir : 1;
+ uint64_t outer_ip_ver : 1;
+ uint64_t rsvd0 : 1;
+ uint64_t mode : 1;
+ uint64_t protocol : 1;
+ uint64_t aes_key_len : 2;
+
+ uint64_t enc_type : 3;
+ uint64_t life_unit : 1;
+ uint64_t auth_type : 4;
+
+ uint64_t encap_type : 2;
+ uint64_t rsvd1 : 6;
+
+ uint64_t rsvd2 : 7;
+ uint64_t async_mode : 1;
+
+ uint64_t spi : 32;
+ } s;
+ uint64_t u64;
+};
+
+PLT_STATIC_ASSERT(sizeof(union roc_ot_ipsec_sa_word2) == 1 * sizeof(uint64_t));
+
+union roc_ot_ipsec_outer_ip_hdr {
+ struct {
+ uint32_t dst_addr;
+ uint32_t src_addr;
+ } ipv4;
+ struct {
+ uint8_t src_addr[16];
+ uint8_t dst_addr[16];
+ } ipv6;
+};
+
+struct roc_ot_ipsec_inb_ctx_update_reg {
+ uint64_t ar_base;
+ uint64_t ar_valid_mask;
+ uint64_t hard_life;
+ uint64_t soft_life;
+ uint64_t mib_octs;
+ uint64_t mib_pkts;
+ uint64_t ar_winbits[ROC_AR_WINBITS_SZ];
+};
+
+union roc_ot_ipsec_outb_iv {
+ uint64_t u64[2];
+ uint8_t iv_dbg[16];
+ struct {
+ uint8_t iv_dbg1[4];
+ uint8_t salt[4];
+
+ uint32_t rsvd;
+ uint8_t iv_dbg2[4];
+ } s;
+};
+
+struct roc_ot_ipsec_outb_ctx_update_reg {
+ uint64_t rsvd;
+ uint64_t esn_val;
+ uint64_t hard_life;
+ uint64_t soft_life;
+ uint64_t mib_octs;
+ uint64_t mib_pkts;
+};
+
+union roc_ot_ipsec_outb_param1 {
+ uint16_t u16;
+ struct {
+ uint16_t l4_csum_disable : 1;
+ uint16_t ip_csum_disable : 1;
+ uint16_t ttl_or_hop_limit : 1;
+ uint16_t dummy_pkt : 1;
+ uint16_t rfc_or_override_mode : 1;
+ uint16_t reserved_5_15 : 11;
+ } s;
+};
+
+union roc_ot_ipsec_inb_param1 {
+ uint16_t u16;
+ struct {
+ uint16_t l4_csum_disable : 1;
+ uint16_t ip_csum_disable : 1;
+ uint16_t esp_trailer_disable : 1;
+ uint16_t reserved_3_15 : 13;
+ } s;
+};
+
+struct roc_ot_ipsec_inb_sa {
+ /* Word0 */
+ union {
+ struct {
+ uint64_t ar_win : 3;
+ uint64_t hard_life_dec : 1;
+ uint64_t soft_life_dec : 1;
+ uint64_t count_glb_octets : 1;
+ uint64_t count_glb_pkts : 1;
+ uint64_t count_mib_bytes : 1;
+
+ uint64_t count_mib_pkts : 1;
+ uint64_t hw_ctx_off : 7;
+
+ uint64_t ctx_id : 16;
+
+ uint64_t orig_pkt_fabs : 1;
+ uint64_t orig_pkt_free : 1;
+ uint64_t pkind : 6;
+
+ uint64_t rsvd0 : 1;
+ uint64_t et_ovrwr : 1;
+ uint64_t pkt_output : 2;
+ uint64_t pkt_format : 1;
+ uint64_t defrag_opt : 2;
+ uint64_t x2p_dst : 1;
+
+ uint64_t ctx_push_size : 7;
+ uint64_t rsvd1 : 1;
+
+ uint64_t ctx_hdr_size : 2;
+ uint64_t aop_valid : 1;
+ uint64_t rsvd2 : 1;
+ uint64_t ctx_size : 4;
+ } s;
+ uint64_t u64;
+ } w0;
+
+ /* Word1 */
+ union {
+ struct {
+ uint64_t orig_pkt_aura : 20;
+ uint64_t rsvd3 : 4;
+ uint64_t orig_pkt_foff : 8;
+ uint64_t cookie : 32;
+ } s;
+ uint64_t u64;
+ } w1;
+
+ /* Word 2 */
+ union {
+ struct {
+ uint64_t valid : 1;
+ uint64_t dir : 1;
+ uint64_t outer_ip_ver : 1;
+ uint64_t rsvd4 : 1;
+ uint64_t ipsec_mode : 1;
+ uint64_t ipsec_protocol : 1;
+ uint64_t aes_key_len : 2;
+
+ uint64_t enc_type : 3;
+ uint64_t life_unit : 1;
+ uint64_t auth_type : 4;
+
+ uint64_t encap_type : 2;
+ uint64_t et_ovrwr_ddr_en : 1;
+ uint64_t esn_en : 1;
+ uint64_t tport_l4_incr_csum : 1;
+ uint64_t ip_hdr_verify : 2;
+ uint64_t rsvd5 : 1;
+
+ uint64_t rsvd6 : 7;
+ uint64_t async_mode : 1;
+
+ uint64_t spi : 32;
+ } s;
+ uint64_t u64;
+ } w2;
+
+ /* Word3 */
+ uint64_t rsvd7;
+
+ /* Word4 - Word7 */
+ uint8_t cipher_key[ROC_CTX_MAX_CKEY_LEN];
+
+ /* Word8 - Word9 */
+ union {
+ struct {
+ uint32_t rsvd8;
+ uint8_t salt[4];
+ } s;
+ uint64_t u64;
+ } w8;
+ uint64_t rsvd9;
+
+ /* Word10 */
+ union {
+ struct {
+ uint64_t rsvd10 : 32;
+ uint64_t udp_src_port : 16;
+ uint64_t udp_dst_port : 16;
+ } s;
+ uint64_t u64;
+ } w10;
+
+ /* Word11 - Word14 */
+ union roc_ot_ipsec_outer_ip_hdr outer_hdr;
+
+ /* Word15 - Word30 */
+ uint8_t hmac_opad_ipad[ROC_CTX_MAX_OPAD_IPAD_LEN];
+
+ /* Word31 - Word100 */
+ struct roc_ot_ipsec_inb_ctx_update_reg ctx;
+};
+
+PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_inb_sa, w1) ==
+ 1 * sizeof(uint64_t));
+PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_inb_sa, w2) ==
+ 2 * sizeof(uint64_t));
+PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_inb_sa, cipher_key) ==
+ 4 * sizeof(uint64_t));
+PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_inb_sa, w8) ==
+ 8 * sizeof(uint64_t));
+PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_inb_sa, w10) ==
+ 10 * sizeof(uint64_t));
+PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_inb_sa, outer_hdr) ==
+ 11 * sizeof(uint64_t));
+PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_inb_sa, hmac_opad_ipad) ==
+ 15 * sizeof(uint64_t));
+PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_inb_sa, ctx) ==
+ 31 * sizeof(uint64_t));
+
+struct roc_ot_ipsec_outb_sa {
+ /* Word0 */
+ union {
+ struct {
+ uint64_t esn_en : 1;
+ uint64_t ip_id : 1;
+ uint64_t rsvd0 : 1;
+ uint64_t hard_life_dec : 1;
+ uint64_t soft_life_dec : 1;
+ uint64_t count_glb_octets : 1;
+ uint64_t count_glb_pkts : 1;
+ uint64_t count_mib_bytes : 1;
+
+ uint64_t count_mib_pkts : 1;
+ uint64_t hw_ctx_off : 7;
+
+ uint64_t rsvd1 : 32;
+
+ uint64_t ctx_push_size : 7;
+ uint64_t rsvd2 : 1;
+
+ uint64_t ctx_hdr_size : 2;
+ uint64_t aop_valid : 1;
+ uint64_t rsvd3 : 1;
+ uint64_t ctx_size : 4;
+ } s;
+ uint64_t u64;
+ } w0;
+
+ /* Word1 */
+ union {
+ struct {
+ uint64_t rsvd4 : 32;
+ uint64_t cookie : 32;
+ } s;
+ uint64_t u64;
+ } w1;
+
+ /* Word 2 */
+ union {
+ struct {
+ uint64_t valid : 1;
+ uint64_t dir : 1;
+ uint64_t outer_ip_ver : 1;
+ uint64_t rsvd5 : 1;
+ uint64_t ipsec_mode : 1;
+ uint64_t ipsec_protocol : 1;
+ uint64_t aes_key_len : 2;
+
+ uint64_t enc_type : 3;
+ uint64_t life_unit : 1;
+ uint64_t auth_type : 4;
+
+ uint64_t encap_type : 2;
+ uint64_t ipv4_df_src_or_ipv6_flw_lbl_src : 1;
+ uint64_t dscp_src : 1;
+ uint64_t iv_src : 2;
+ uint64_t ipid_gen : 1;
+ uint64_t rsvd6 : 1;
+
+ uint64_t rsvd7 : 7;
+ uint64_t async_mode : 1;
+
+ uint64_t spi : 32;
+ } s;
+ uint64_t u64;
+ } w2;
+
+ /* Word3 */
+ uint64_t rsvd8;
+
+ /* Word4 - Word7 */
+ uint8_t cipher_key[ROC_CTX_MAX_CKEY_LEN];
+
+ /* Word8 - Word9 */
+ union roc_ot_ipsec_outb_iv iv;
+
+ /* Word10 */
+ union {
+ struct {
+ uint64_t rsvd9 : 4;
+ uint64_t ipv4_df_or_ipv6_flw_lbl : 20;
+
+ uint64_t dscp : 6;
+ uint64_t rsvd10 : 2;
+
+ uint64_t udp_dst_port : 16;
+
+ uint64_t udp_src_port : 16;
+ } s;
+ uint64_t u64;
+ } w10;
+
+ /* Word11 - Word14 */
+ union roc_ot_ipsec_outer_ip_hdr outer_hdr;
+
+ /* Word15 - Word30 */
+ uint8_t hmac_opad_ipad[ROC_CTX_MAX_OPAD_IPAD_LEN];
+
+ /* Word31 - Word36 */
+ struct roc_ot_ipsec_outb_ctx_update_reg ctx;
+};
+
+PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_outb_sa, w1) ==
+ 1 * sizeof(uint64_t));
+PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_outb_sa, w2) ==
+ 2 * sizeof(uint64_t));
+PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_outb_sa, cipher_key) ==
+ 4 * sizeof(uint64_t));
+PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_outb_sa, iv) ==
+ 8 * sizeof(uint64_t));
+PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_outb_sa, w10) ==
+ 10 * sizeof(uint64_t));
+PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_outb_sa, outer_hdr) ==
+ 11 * sizeof(uint64_t));
+PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_outb_sa, hmac_opad_ipad) ==
+ 15 * sizeof(uint64_t));
+PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_outb_sa, ctx) ==
+ 31 * sizeof(uint64_t));
+
+#endif /* __ROC_IE_OT_H__ */
diff --git a/drivers/common/cnxk/roc_platform.h b/drivers/common/cnxk/roc_platform.h
index daee100..685ec29 100644
--- a/drivers/common/cnxk/roc_platform.h
+++ b/drivers/common/cnxk/roc_platform.h
@@ -49,6 +49,7 @@
#define PLT_MODEL_MZ_NAME "roc_model_mz"
#define PLT_CACHE_LINE_SIZE RTE_CACHE_LINE_SIZE
#define BITMASK_ULL GENMASK_ULL
+#define PLT_ALIGN_CEIL RTE_ALIGN_CEIL
/** Divide ceil */
#define PLT_DIV_CEIL(x, y) \
--
2.7.4
next prev parent reply other threads:[~2021-06-25 5:38 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <patches.dpdk.org/project/dpdk/patch/1622649385-22652-1-git-send-email-anoobj@marvell.com/>
2021-06-25 5:36 ` [dpdk-dev] [PATCH v2 00/17] Add CPT in Marvell CNXK common driver Anoob Joseph
2021-06-25 5:36 ` [dpdk-dev] [PATCH v2 01/17] common/cnxk: add CPT HW defines Anoob Joseph
2021-06-25 5:36 ` [dpdk-dev] [PATCH v2 02/17] common/cnxk: update Rx inline IPsec mbox message format Anoob Joseph
2021-06-25 5:36 ` [dpdk-dev] [PATCH v2 03/17] common/cnxk: add CPT dev config routines Anoob Joseph
2021-06-25 5:36 ` [dpdk-dev] [PATCH v2 04/17] common/cnxk: add idev CPT set - get Anoob Joseph
2021-06-25 5:36 ` [dpdk-dev] [PATCH v2 05/17] common/cnxk: add mbox to configure RXC Anoob Joseph
2021-06-25 5:36 ` [dpdk-dev] [PATCH v2 06/17] common/cnxk: add CPT LF config Anoob Joseph
2021-06-25 5:36 ` [dpdk-dev] [PATCH v2 07/17] common/cnxk: add CPT diagnostics Anoob Joseph
2021-06-25 5:36 ` [dpdk-dev] [PATCH v2 08/17] common/cnxk: add CPT LF flush Anoob Joseph
2021-06-25 5:36 ` [dpdk-dev] [PATCH v2 09/17] common/cnxk: add inline IPsec configuration mbox Anoob Joseph
2021-06-25 5:36 ` [dpdk-dev] [PATCH v2 10/17] common/cnxk: add SE microcode defines Anoob Joseph
2021-06-25 5:36 ` Anoob Joseph [this message]
2021-06-25 5:36 ` [dpdk-dev] [PATCH v2 12/17] common/cnxk: add AE " Anoob Joseph
2021-06-25 5:36 ` [dpdk-dev] [PATCH v2 13/17] common/cnxk: add lmtline init Anoob Joseph
2021-06-25 5:36 ` [dpdk-dev] [PATCH v2 14/17] common/cnxk: add fpm tables Anoob Joseph
2021-06-25 5:36 ` [dpdk-dev] [PATCH v2 15/17] common/cnxk: add EC grp static vectors Anoob Joseph
2021-06-25 5:36 ` [dpdk-dev] [PATCH v2 16/17] common/cnxk: add IPsec common code Anoob Joseph
2021-06-25 5:36 ` [dpdk-dev] [PATCH v2 17/17] common/cnxk: add SE set key functions in roc Anoob Joseph
2021-06-28 8:56 ` [dpdk-dev] [PATCH v2 00/17] Add CPT in Marvell CNXK common driver Akhil Goyal
2021-06-28 9:06 ` Akhil Goyal
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