[dpdk-dev] [PATCH v2 00/17] Add CPT in Marvell CNXK common driver

[dpdk-dev] [PATCH v2 00/17] Add CPT in Marvell CNXK common driver

[Anoob Joseph]

This patchset adds initial support for CPT in common code for Marvell CN10K SoC.

CPT is the hardware cryptographic block available in 'cnxk' family SoC. CPT,
with its microcoded engines can support symmetric, asymmetric and IPsec
operations. CPT can associate with NIX (rte_ethdev) to enable inline IPsec
functionality. Similarly, CPT can associate with SSO (rte_eventdev) to
enable crypto adapter.

Based on CNXK common driver, new crypto PMDs would be added under 'crypto/cnxk'.

Changes in v2
- Moved FPM & EC tables to RoC
- Moved set_key routines to RoC
- Added inline IPsec required mboxes and framework
- Added security common code
- Added plt_dp_* log based on Akhil's comment

Aakash Sasidharan (2):
  common/cnxk: add CPT diagnostics
  common/cnxk: add CPT LF flush

Ankur Dwivedi (1):
  common/cnxk: add SE set key functions in roc

Anoob Joseph (3):
  common/cnxk: add CPT dev config routines
  common/cnxk: add idev CPT set - get
  common/cnxk: add lmtline init

Archana Muniganti (1):
  common/cnxk: add CPT LF config

Kiran Kumar Kokkilagadda (4):
  common/cnxk: add SE microcode defines
  common/cnxk: add AE microcode defines
  common/cnxk: add fpm tables
  common/cnxk: add EC grp static vectors

Srujana Challa (3):
  common/cnxk: update Rx inline IPsec mbox message format
  common/cnxk: add IE microcode defines
  common/cnxk: add IPsec common code

Vidya Sagar Velumuri (3):
  common/cnxk: add CPT HW defines
  common/cnxk: add mbox to configure RXC
  common/cnxk: add inline IPsec configuration mbox

 drivers/common/cnxk/cnxk_security.c     |  468 +++++++++++++
 drivers/common/cnxk/cnxk_security.h     |   49 ++
 drivers/common/cnxk/hw/cpt.h            |  291 ++++++++
 drivers/common/cnxk/meson.build         |   11 +-
 drivers/common/cnxk/roc_ae.c            |  142 ++++
 drivers/common/cnxk/roc_ae.h            |   63 ++
 drivers/common/cnxk/roc_ae_fpm_tables.c | 1140 +++++++++++++++++++++++++++++++
 drivers/common/cnxk/roc_ae_fpm_tables.h |   13 +
 drivers/common/cnxk/roc_api.h           |   16 +
 drivers/common/cnxk/roc_cpt.c           |  828 ++++++++++++++++++++++
 drivers/common/cnxk/roc_cpt.h           |  145 ++++
 drivers/common/cnxk/roc_cpt_debug.c     |  167 +++++
 drivers/common/cnxk/roc_cpt_priv.h      |   41 ++
 drivers/common/cnxk/roc_dev.c           |    2 +
 drivers/common/cnxk/roc_dev_priv.h      |    1 +
 drivers/common/cnxk/roc_idev.c          |   21 +
 drivers/common/cnxk/roc_idev.h          |    3 +
 drivers/common/cnxk/roc_idev_priv.h     |    2 +
 drivers/common/cnxk/roc_ie.h            |   19 +
 drivers/common/cnxk/roc_ie_on.h         |  152 +++++
 drivers/common/cnxk/roc_ie_ot.h         |  534 +++++++++++++++
 drivers/common/cnxk/roc_mbox.h          |    3 +
 drivers/common/cnxk/roc_platform.c      |    1 +
 drivers/common/cnxk/roc_platform.h      |    9 +
 drivers/common/cnxk/roc_priv.h          |    3 +
 drivers/common/cnxk/roc_se.c            |  342 ++++++++++
 drivers/common/cnxk/roc_se.h            |  275 ++++++++
 drivers/common/cnxk/version.map         |   32 +
 28 files changed, 4772 insertions(+), 1 deletion(-)
 create mode 100644 drivers/common/cnxk/cnxk_security.c
 create mode 100644 drivers/common/cnxk/cnxk_security.h
 create mode 100644 drivers/common/cnxk/hw/cpt.h
 create mode 100644 drivers/common/cnxk/roc_ae.c
 create mode 100644 drivers/common/cnxk/roc_ae.h
 create mode 100644 drivers/common/cnxk/roc_ae_fpm_tables.c
 create mode 100644 drivers/common/cnxk/roc_ae_fpm_tables.h
 create mode 100644 drivers/common/cnxk/roc_cpt.c
 create mode 100644 drivers/common/cnxk/roc_cpt.h
 create mode 100644 drivers/common/cnxk/roc_cpt_debug.c
 create mode 100644 drivers/common/cnxk/roc_cpt_priv.h
 create mode 100644 drivers/common/cnxk/roc_ie.h
 create mode 100644 drivers/common/cnxk/roc_ie_on.h
 create mode 100644 drivers/common/cnxk/roc_ie_ot.h
 create mode 100644 drivers/common/cnxk/roc_se.c
 create mode 100644 drivers/common/cnxk/roc_se.h

-- 
2.7.4

[dpdk-dev] [PATCH v2 01/17] common/cnxk: add CPT HW defines

[Anoob Joseph]

From: Vidya Sagar Velumuri <vvelumuri@marvell.com>

Add CPT hardware definitions. CPT is the hardware block on
cnxk family of processors, that can be used to offload
cryptographic operations.

Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Vidya Sagar Velumuri <vvelumuri@marvell.com>

---
 drivers/common/cnxk/hw/cpt.h  | 291 ++++++++++++++++++++++++++++++++++++++++++
 drivers/common/cnxk/roc_api.h |   6 +
 2 files changed, 297 insertions(+)
 create mode 100644 drivers/common/cnxk/hw/cpt.h

diff --git a/drivers/common/cnxk/hw/cpt.h b/drivers/common/cnxk/hw/cpt.h
new file mode 100644
index 0000000..84ebf2d
--- /dev/null
+++ b/drivers/common/cnxk/hw/cpt.h
@@ -0,0 +1,291 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef __CPT_HW_H__
+#define __CPT_HW_H__
+
+/* Register offsets */
+
+#define CPT_COMP_NOT_DONE (0x0ull)
+#define CPT_COMP_GOOD	  (0x1ull)
+#define CPT_COMP_FAULT	  (0x2ull)
+#define CPT_COMP_SWERR	  (0x3ull)
+#define CPT_COMP_HWERR	  (0x4ull)
+#define CPT_COMP_INSTERR  (0x5ull)
+#define CPT_COMP_WARN	  (0x6ull) /* [CN10K, .) */
+
+#define CPT_LF_INT_VEC_MISC	(0x0ull)
+#define CPT_LF_INT_VEC_DONE	(0x1ull)
+#define CPT_LF_CTL		(0x10ull)
+#define CPT_LF_DONE_WAIT	(0x30ull)
+#define CPT_LF_INPROG		(0x40ull)
+#define CPT_LF_DONE		(0x50ull)
+#define CPT_LF_DONE_ACK		(0x60ull)
+#define CPT_LF_DONE_INT_ENA_W1S (0x90ull)
+#define CPT_LF_DONE_INT_ENA_W1C (0xa0ull)
+#define CPT_LF_MISC_INT		(0xb0ull)
+#define CPT_LF_MISC_INT_W1S	(0xc0ull)
+#define CPT_LF_MISC_INT_ENA_W1S (0xd0ull)
+#define CPT_LF_MISC_INT_ENA_W1C (0xe0ull)
+#define CPT_LF_Q_BASE		(0xf0ull)
+#define CPT_LF_Q_SIZE		(0x100ull)
+#define CPT_LF_Q_INST_PTR	(0x110ull)
+#define CPT_LF_Q_GRP_PTR	(0x120ull)
+#define CPT_LF_NQX(a)		(0x400ull | (uint64_t)(a) << 3)
+#define CPT_LF_CTX_CTL		(0x500ull)
+#define CPT_LF_CTX_FLUSH	(0x510ull)
+#define CPT_LF_CTX_ERR		(0x520ull)
+#define CPT_LF_CTX_ENC_BYTE_CNT (0x530ull)
+#define CPT_LF_CTX_ENC_PKT_CNT	(0x540ull)
+#define CPT_LF_CTX_DEC_BYTE_CNT (0x550ull)
+#define CPT_LF_CTX_DEC_PKT_CNT	(0x560ull)
+
+#define CPT_AF_LFX_CTL(a)  (0x27000ull | (uint64_t)(a) << 3)
+#define CPT_AF_LFX_CTL2(a) (0x29000ull | (uint64_t)(a) << 3)
+
+/* Structures definitions */
+
+union cpt_lf_ctl {
+	uint64_t u;
+	struct cpt_lf_ctl_s {
+		uint64_t ena : 1;
+		uint64_t fc_ena : 1;
+		uint64_t fc_up_crossing : 1;
+		uint64_t reserved_3_3 : 1;
+		uint64_t fc_hyst_bits : 4;
+		uint64_t reserved_8_63 : 56;
+	} s;
+};
+
+union cpt_lf_ctx_flush {
+	uint64_t u;
+	struct {
+		uint64_t cptr : 46;
+		uint64_t inval : 1;
+		uint64_t res : 1;
+		uint64_t pf_func : 16;
+	} s;
+};
+
+union cpt_lf_inprog {
+	uint64_t u;
+	struct cpt_lf_inprog_s {
+		uint64_t inflight : 9;
+		uint64_t reserved_9_15 : 7;
+		uint64_t eena : 1;
+		uint64_t grp_drp : 1;
+		uint64_t reserved_18_30 : 13;
+		uint64_t grb_partial : 1;
+		uint64_t grb_cnt : 8;
+		uint64_t gwb_cnt : 8;
+		uint64_t reserved_48_63 : 16;
+	} s;
+};
+
+union cpt_lf_q_base {
+	uint64_t u;
+	struct cpt_lf_q_base_s {
+		uint64_t fault : 1;
+		uint64_t stopped : 1;
+		uint64_t reserved_2_6 : 5;
+		uint64_t addr : 46;
+		uint64_t reserved_53_63 : 11;
+	} s;
+};
+
+union cpt_lf_q_size {
+	uint64_t u;
+	struct cpt_lf_q_size_s {
+		uint64_t size_div40 : 15;
+		uint64_t reserved_15_63 : 49;
+	} s;
+};
+
+union cpt_lf_misc_int {
+	uint64_t u;
+	struct cpt_lf_misc_int_s {
+		uint64_t reserved_0_0 : 1;
+		uint64_t nqerr : 1;
+		uint64_t irde : 1;
+		uint64_t nwrp : 1;
+		uint64_t reserved_4_4 : 1;
+		uint64_t hwerr : 1;
+		uint64_t fault : 1;
+		uint64_t reserved_7_63 : 57;
+	} s;
+};
+
+union cpt_inst_w4 {
+	uint64_t u64;
+	struct {
+		uint64_t dlen : 16;
+		uint64_t param2 : 16;
+		uint64_t param1 : 16;
+		uint64_t opcode_major : 8;
+		uint64_t opcode_minor : 8;
+	} s;
+};
+
+union cpt_inst_w7 {
+	uint64_t u64;
+	struct {
+		uint64_t cptr : 60;
+		uint64_t ctx_val : 1;
+		uint64_t egrp : 3;
+	} s;
+};
+
+struct cpt_inst_s {
+	union cpt_inst_w0 {
+		struct {
+			uint64_t nixtxl : 3;
+			uint64_t doneint : 1;
+			uint64_t nixtx_addr : 60;
+		} s;
+		uint64_t u64;
+	} w0;
+
+	uint64_t res_addr;
+
+	union cpt_inst_w2 {
+		struct {
+			uint64_t tag : 32;
+			uint64_t tt : 2;
+			uint64_t grp : 10;
+			uint64_t reserved_172_175 : 4;
+			uint64_t rvu_pf_func : 16;
+		} s;
+		uint64_t u64;
+	} w2;
+
+	union cpt_inst_w3 {
+		struct {
+			uint64_t qord : 1;
+			uint64_t reserved_194_193 : 2;
+			uint64_t wqe_ptr : 61;
+		} s;
+		uint64_t u64;
+	} w3;
+
+	union cpt_inst_w4 w4;
+
+	uint64_t dptr;
+
+	uint64_t rptr;
+
+	union cpt_inst_w7 w7;
+};
+
+union cpt_res_s {
+	struct cpt_cn10k_res_s {
+		uint64_t compcode : 7;
+		uint64_t doneint : 1;
+		uint64_t uc_compcode : 8;
+		uint64_t rlen : 16;
+		uint64_t spi : 32;
+
+		uint64_t esn;
+	} cn10k;
+
+	struct cpt_cn9k_res_s {
+		uint64_t compcode : 8;
+		uint64_t uc_compcode : 8;
+		uint64_t doneint : 1;
+		uint64_t reserved_17_63 : 47;
+
+		uint64_t reserved_64_127;
+	} cn9k;
+};
+
+/* [CN10K, .) */
+struct cpt_parse_hdr_s {
+	/* WORD 0 */
+	union {
+		uint64_t u64;
+		struct {
+			uint8_t pad_len : 3;
+			uint8_t num_frags : 3;
+			uint8_t pkt_out : 2;
+
+			uint8_t err_sum : 1;
+			uint8_t reas_sts : 4;
+			uint8_t reserved_53 : 1;
+			uint8_t et_owr : 1;
+			uint8_t pkt_fmt : 1;
+
+			uint16_t match_id : 16;
+
+			uint32_t cookie : 32;
+		};
+	} w0;
+
+	/* WORD 1 */
+	uint64_t wqe_ptr;
+
+	/* WORD 2 */
+	union {
+		uint64_t u64;
+		struct {
+			uint8_t fi_pad : 3;
+			uint8_t fi_offset : 5;
+			uint8_t il3_off;
+			uint16_t orig_pf_func;
+			uint16_t reserved_145_160;
+			uint16_t frag_age;
+		};
+	} w2;
+
+	/* WORD 3 */
+	union {
+		uint64_t u64;
+		struct {
+			uint32_t spi;
+			uint16_t reserved_209_224;
+			uint8_t uc_ccode;
+			uint8_t hw_ccode;
+		};
+	} w3;
+
+	/* WORD 4 */
+	union {
+		uint64_t u64;
+		uint64_t esn;
+		uint64_t frag1_wqe_ptr;
+	};
+};
+
+union cpt_frag_info {
+	uint16_t info;
+	struct {
+		uint16_t f_off : 13;
+		uint16_t f_mf : 1;
+		uint16_t f_rsv : 2;
+	};
+};
+
+struct cpt_frag_info_s {
+	/* WORD 0 */
+	union {
+		uint64_t u64;
+		struct {
+			union cpt_frag_info f3;
+			union cpt_frag_info f2;
+			union cpt_frag_info f1;
+			union cpt_frag_info f0;
+		};
+	} w0;
+
+	/* WORD 1 */
+	union {
+		uint64_t u64;
+		struct {
+			uint16_t frag_size3;
+			uint16_t frag_size2;
+			uint16_t frag_size1;
+			uint16_t frag_size0;
+		};
+	} w1;
+};
+
+#endif /* __CPT_HW_H__ */
diff --git a/drivers/common/cnxk/roc_api.h b/drivers/common/cnxk/roc_api.h
index 67f5d13..049854d 100644
--- a/drivers/common/cnxk/roc_api.h
+++ b/drivers/common/cnxk/roc_api.h
@@ -54,6 +54,11 @@
 #define PCI_DEVID_CN9K_CGX  0xA059
 #define PCI_DEVID_CN10K_RPM 0xA060
 
+#define PCI_DEVID_CN9K_RVU_CPT_PF  0xA0FD
+#define PCI_DEVID_CN9K_RVU_CPT_VF  0xA0FE
+#define PCI_DEVID_CN10K_RVU_CPT_PF 0xA0F2
+#define PCI_DEVID_CN10K_RVU_CPT_VF 0xA0F3
+
 #define PCI_SUBSYSTEM_DEVID_CN10KA  0xB900
 #define PCI_SUBSYSTEM_DEVID_CN10KAS 0xB900
 
@@ -64,6 +69,7 @@
 #define PCI_SUBSYSTEM_DEVID_CN9KE 0xB100
 
 /* HW structure definition */
+#include "hw/cpt.h"
 #include "hw/nix.h"
 #include "hw/npa.h"
 #include "hw/npc.h"
-- 
2.7.4

[dpdk-dev] [PATCH v2 02/17] common/cnxk: update Rx inline IPsec mbox message format

[Anoob Joseph]

From: Srujana Challa <schalla@marvell.com>

Updates Rx inline IPSEC mailbox message format to make it
sync with latest CPT PF driver.

Signed-off-by: Srujana Challa <schalla@marvell.com>
---
 drivers/common/cnxk/roc_mbox.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h
index f6b11b6..fe4df21 100644
--- a/drivers/common/cnxk/roc_mbox.h
+++ b/drivers/common/cnxk/roc_mbox.h
@@ -1328,6 +1328,9 @@ struct cpt_rxc_time_cfg_req {
 struct cpt_rx_inline_lf_cfg_msg {
 	struct mbox_msghdr hdr;
 	uint16_t __io sso_pf_func;
+	uint16_t __io param1;
+	uint16_t __io param2;
+	uint16_t __io reserved;
 };
 
 enum cpt_eng_type {
-- 
2.7.4

[dpdk-dev] [PATCH v2 03/17] common/cnxk: add CPT dev config routines

[Anoob Joseph]

Add routines to init, fini, configure & clear CPT device.

Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Archana Muniganti <marchana@marvell.com>
Signed-off-by: Vidya Sagar Velumuri <vvelumuri@marvell.com>

---
 drivers/common/cnxk/meson.build    |   1 +
 drivers/common/cnxk/roc_api.h      |   3 +
 drivers/common/cnxk/roc_cpt.c      | 308 +++++++++++++++++++++++++++++++++++++
 drivers/common/cnxk/roc_cpt.h      |  37 +++++
 drivers/common/cnxk/roc_cpt_priv.h |  37 +++++
 drivers/common/cnxk/roc_dev.c      |   2 +
 drivers/common/cnxk/roc_dev_priv.h |   1 +
 drivers/common/cnxk/roc_platform.c |   1 +
 drivers/common/cnxk/roc_platform.h |   8 +
 drivers/common/cnxk/roc_priv.h     |   3 +
 drivers/common/cnxk/version.map    |   6 +
 11 files changed, 407 insertions(+)
 create mode 100644 drivers/common/cnxk/roc_cpt.c
 create mode 100644 drivers/common/cnxk/roc_cpt.h
 create mode 100644 drivers/common/cnxk/roc_cpt_priv.h

diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build
index 178bce7..739e0e4 100644
--- a/drivers/common/cnxk/meson.build
+++ b/drivers/common/cnxk/meson.build
@@ -11,6 +11,7 @@ endif
 config_flag_fmt = 'RTE_LIBRTE_@0@_COMMON'
 deps = ['eal', 'pci', 'bus_pci', 'mbuf']
 sources = files(
+        'roc_cpt.c',
         'roc_dev.c',
         'roc_idev.c',
         'roc_irq.c',
diff --git a/drivers/common/cnxk/roc_api.h b/drivers/common/cnxk/roc_api.h
index 049854d..88a5611 100644
--- a/drivers/common/cnxk/roc_api.h
+++ b/drivers/common/cnxk/roc_api.h
@@ -106,4 +106,7 @@
 /* Idev */
 #include "roc_idev.h"
 
+/* CPT */
+#include "roc_cpt.h"
+
 #endif /* _ROC_API_H_ */
diff --git a/drivers/common/cnxk/roc_cpt.c b/drivers/common/cnxk/roc_cpt.c
new file mode 100644
index 0000000..2376125
--- /dev/null
+++ b/drivers/common/cnxk/roc_cpt.c
@@ -0,0 +1,308 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#include "roc_api.h"
+#include "roc_priv.h"
+
+int
+cpt_get_msix_offset(struct dev *dev, struct msix_offset_rsp **msix_rsp)
+{
+	struct mbox *mbox = dev->mbox;
+	int rc;
+
+	/* Get MSIX vector offsets */
+	mbox_alloc_msg_msix_offset(mbox);
+	rc = mbox_process_msg(mbox, (void *)msix_rsp);
+
+	return rc;
+}
+
+int
+cpt_lfs_attach(struct dev *dev, uint8_t blkaddr, bool modify, uint16_t nb_lf)
+{
+	struct mbox *mbox = dev->mbox;
+	struct rsrc_attach_req *req;
+
+	if (blkaddr != RVU_BLOCK_ADDR_CPT0 && blkaddr != RVU_BLOCK_ADDR_CPT1)
+		return -EINVAL;
+
+	/* Attach CPT(lf) */
+	req = mbox_alloc_msg_attach_resources(mbox);
+	if (req == NULL)
+		return -ENOSPC;
+
+	req->cptlfs = nb_lf;
+	req->modify = modify;
+	req->cpt_blkaddr = blkaddr;
+
+	return mbox_process(mbox);
+}
+
+int
+cpt_lfs_detach(struct dev *dev)
+{
+	struct mbox *mbox = dev->mbox;
+	struct rsrc_detach_req *req;
+
+	req = mbox_alloc_msg_detach_resources(mbox);
+	if (req == NULL)
+		return -ENOSPC;
+
+	req->cptlfs = 1;
+	req->partial = 1;
+
+	return mbox_process(mbox);
+}
+
+static int
+cpt_available_lfs_get(struct dev *dev, uint16_t *nb_lf)
+{
+	struct mbox *mbox = dev->mbox;
+	struct free_rsrcs_rsp *rsp;
+	int rc;
+
+	mbox_alloc_msg_free_rsrc_cnt(mbox);
+
+	rc = mbox_process_msg(mbox, (void *)&rsp);
+	if (rc)
+		return -EIO;
+
+	*nb_lf = rsp->cpt;
+	return 0;
+}
+
+int
+cpt_lfs_alloc(struct dev *dev, uint8_t eng_grpmsk, uint8_t blkaddr,
+	      bool inl_dev_sso)
+{
+	struct cpt_lf_alloc_req_msg *req;
+	struct mbox *mbox = dev->mbox;
+
+	if (blkaddr != RVU_BLOCK_ADDR_CPT0 && blkaddr != RVU_BLOCK_ADDR_CPT1)
+		return -EINVAL;
+
+	PLT_SET_USED(inl_dev_sso);
+
+	req = mbox_alloc_msg_cpt_lf_alloc(mbox);
+	req->nix_pf_func = 0;
+	req->sso_pf_func = idev_sso_pffunc_get();
+	req->eng_grpmsk = eng_grpmsk;
+	req->blkaddr = blkaddr;
+
+	return mbox_process(mbox);
+}
+
+int
+cpt_lfs_free(struct dev *dev)
+{
+	mbox_alloc_msg_cpt_lf_free(dev->mbox);
+
+	return mbox_process(dev->mbox);
+}
+
+static int
+cpt_hardware_caps_get(struct dev *dev, union cpt_eng_caps *hw_caps)
+{
+	struct cpt_caps_rsp_msg *rsp;
+	int ret;
+
+	mbox_alloc_msg_cpt_caps_get(dev->mbox);
+
+	ret = mbox_process_msg(dev->mbox, (void *)&rsp);
+	if (ret)
+		return -EIO;
+
+	mbox_memcpy(hw_caps, rsp->eng_caps,
+		    sizeof(union cpt_eng_caps) * CPT_MAX_ENG_TYPES);
+
+	return 0;
+}
+
+int
+roc_cpt_dev_configure(struct roc_cpt *roc_cpt, int nb_lf)
+{
+	struct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt);
+	uint8_t blkaddr = RVU_BLOCK_ADDR_CPT0;
+	struct msix_offset_rsp *rsp;
+	uint8_t eng_grpmsk;
+	int rc, i;
+
+	/* Request LF resources */
+	rc = cpt_lfs_attach(&cpt->dev, blkaddr, false, nb_lf);
+	if (rc)
+		return rc;
+
+	eng_grpmsk = (1 << roc_cpt->eng_grp[CPT_ENG_TYPE_AE]) |
+		     (1 << roc_cpt->eng_grp[CPT_ENG_TYPE_SE]) |
+		     (1 << roc_cpt->eng_grp[CPT_ENG_TYPE_IE]);
+
+	rc = cpt_lfs_alloc(&cpt->dev, eng_grpmsk, blkaddr, false);
+	if (rc)
+		goto lfs_detach;
+
+	rc = cpt_get_msix_offset(&cpt->dev, &rsp);
+	if (rc)
+		goto lfs_free;
+
+	for (i = 0; i < nb_lf; i++)
+		cpt->lf_msix_off[i] =
+			(cpt->lf_blkaddr[i] == RVU_BLOCK_ADDR_CPT1) ?
+				rsp->cpt1_lf_msixoff[i] :
+				rsp->cptlf_msixoff[i];
+
+	roc_cpt->nb_lf = nb_lf;
+
+	return 0;
+
+lfs_free:
+	cpt_lfs_free(&cpt->dev);
+lfs_detach:
+	cpt_lfs_detach(&cpt->dev);
+	return rc;
+}
+
+uint64_t
+cpt_get_blkaddr(struct dev *dev)
+{
+	uint64_t reg;
+	uint64_t off;
+
+	/* Reading the discovery register to know which CPT is the LF
+	 * attached to. Assume CPT LF's of only one block are attached
+	 * to a pffunc.
+	 */
+	if (dev_is_vf(dev))
+		off = RVU_VF_BLOCK_ADDRX_DISC(RVU_BLOCK_ADDR_CPT1);
+	else
+		off = RVU_PF_BLOCK_ADDRX_DISC(RVU_BLOCK_ADDR_CPT1);
+
+	reg = plt_read64(dev->bar2 + off);
+
+	return reg & 0x1FFULL ? RVU_BLOCK_ADDR_CPT1 : RVU_BLOCK_ADDR_CPT0;
+}
+
+int
+roc_cpt_dev_init(struct roc_cpt *roc_cpt)
+{
+	struct plt_pci_device *pci_dev;
+	uint16_t nb_lf_avail;
+	struct dev *dev;
+	struct cpt *cpt;
+	int rc;
+
+	if (roc_cpt == NULL || roc_cpt->pci_dev == NULL)
+		return -EINVAL;
+
+	PLT_STATIC_ASSERT(sizeof(struct cpt) <= ROC_CPT_MEM_SZ);
+
+	cpt = roc_cpt_to_cpt_priv(roc_cpt);
+	memset(cpt, 0, sizeof(*cpt));
+	pci_dev = roc_cpt->pci_dev;
+	dev = &cpt->dev;
+
+	/* Initialize device  */
+	rc = dev_init(dev, pci_dev);
+	if (rc) {
+		plt_err("Failed to init roc device");
+		goto fail;
+	}
+
+	cpt->pci_dev = pci_dev;
+	roc_cpt->lmt_base = dev->lmt_base;
+
+	rc = cpt_hardware_caps_get(dev, roc_cpt->hw_caps);
+	if (rc) {
+		plt_err("Could not determine hardware capabilities");
+		goto fail;
+	}
+
+	rc = cpt_available_lfs_get(&cpt->dev, &nb_lf_avail);
+	if (rc) {
+		plt_err("Could not get available lfs");
+		goto fail;
+	}
+
+	/* Reserve 1 CPT LF for inline inbound */
+	nb_lf_avail = PLT_MIN(nb_lf_avail, ROC_CPT_MAX_LFS - 1);
+
+	roc_cpt->nb_lf_avail = nb_lf_avail;
+
+	dev->roc_cpt = roc_cpt;
+
+	return 0;
+
+fail:
+	return rc;
+}
+
+int
+roc_cpt_dev_fini(struct roc_cpt *roc_cpt)
+{
+	struct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt);
+
+	if (cpt == NULL)
+		return -EINVAL;
+
+	roc_cpt->nb_lf_avail = 0;
+
+	roc_cpt->lmt_base = 0;
+
+	return dev_fini(&cpt->dev, cpt->pci_dev);
+}
+
+void
+roc_cpt_dev_clear(struct roc_cpt *roc_cpt)
+{
+	struct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt);
+	int i;
+
+	if (cpt == NULL)
+		return;
+
+	for (i = 0; i < roc_cpt->nb_lf; i++)
+		cpt->lf_msix_off[i] = 0;
+
+	roc_cpt->nb_lf = 0;
+
+	cpt_lfs_free(&cpt->dev);
+
+	cpt_lfs_detach(&cpt->dev);
+}
+
+int
+roc_cpt_eng_grp_add(struct roc_cpt *roc_cpt, enum cpt_eng_type eng_type)
+{
+	struct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt);
+	struct dev *dev = &cpt->dev;
+	struct cpt_eng_grp_req *req;
+	struct cpt_eng_grp_rsp *rsp;
+	int ret;
+
+	req = mbox_alloc_msg_cpt_eng_grp_get(dev->mbox);
+	if (req == NULL)
+		return -EIO;
+
+	switch (eng_type) {
+	case CPT_ENG_TYPE_AE:
+	case CPT_ENG_TYPE_SE:
+	case CPT_ENG_TYPE_IE:
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	req->eng_type = eng_type;
+	ret = mbox_process_msg(dev->mbox, (void *)&rsp);
+	if (ret)
+		return -EIO;
+
+	if (rsp->eng_grp_num > 8) {
+		plt_err("Invalid CPT engine group");
+		return -ENOTSUP;
+	}
+
+	roc_cpt->eng_grp[eng_type] = rsp->eng_grp_num;
+
+	return rsp->eng_grp_num;
+}
diff --git a/drivers/common/cnxk/roc_cpt.h b/drivers/common/cnxk/roc_cpt.h
new file mode 100644
index 0000000..4e1cf84
--- /dev/null
+++ b/drivers/common/cnxk/roc_cpt.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef _ROC_CPT_H_
+#define _ROC_CPT_H_
+
+#include "roc_api.h"
+
+/* Default engine groups */
+#define ROC_CPT_DFLT_ENG_GRP_SE	   0UL
+#define ROC_CPT_DFLT_ENG_GRP_SE_IE 1UL
+#define ROC_CPT_DFLT_ENG_GRP_AE	   2UL
+
+#define ROC_CPT_MAX_LFS 64
+
+struct roc_cpt {
+	struct plt_pci_device *pci_dev;
+	struct roc_cpt_lf *lf[ROC_CPT_MAX_LFS];
+	uint16_t nb_lf;
+	uint16_t nb_lf_avail;
+	uintptr_t lmt_base;
+	/**< CPT device capabilities */
+	union cpt_eng_caps hw_caps[CPT_MAX_ENG_TYPES];
+	uint8_t eng_grp[CPT_MAX_ENG_TYPES];
+
+#define ROC_CPT_MEM_SZ (6 * 1024)
+	uint8_t reserved[ROC_CPT_MEM_SZ] __plt_cache_aligned;
+} __plt_cache_aligned;
+
+int __roc_api roc_cpt_dev_init(struct roc_cpt *roc_cpt);
+int __roc_api roc_cpt_dev_fini(struct roc_cpt *roc_cpt);
+int __roc_api roc_cpt_eng_grp_add(struct roc_cpt *roc_cpt,
+				  enum cpt_eng_type eng_type);
+int __roc_api roc_cpt_dev_configure(struct roc_cpt *roc_cpt, int nb_lf);
+void __roc_api roc_cpt_dev_clear(struct roc_cpt *roc_cpt);
+#endif /* _ROC_CPT_H_ */
diff --git a/drivers/common/cnxk/roc_cpt_priv.h b/drivers/common/cnxk/roc_cpt_priv.h
new file mode 100644
index 0000000..0ef6774
--- /dev/null
+++ b/drivers/common/cnxk/roc_cpt_priv.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef _ROC_CPT_PRIV_H_
+#define _ROC_CPT_PRIV_H_
+
+/* Set number of hystbits to 6.
+ * This will trigger the FC writes whenever number of outstanding commands in
+ * the queue becomes multiple of 32.
+ */
+#define CPT_FC_NUM_HYST_BITS 6
+
+struct cpt {
+	struct plt_pci_device *pci_dev;
+	struct dev dev;
+	uint16_t lf_msix_off[ROC_CPT_MAX_LFS];
+	uint8_t lf_blkaddr[ROC_CPT_MAX_LFS];
+} __plt_cache_aligned;
+
+static inline struct cpt *
+roc_cpt_to_cpt_priv(struct roc_cpt *roc_cpt)
+{
+	return (struct cpt *)&roc_cpt->reserved[0];
+}
+
+int cpt_lfs_attach(struct dev *dev, uint8_t blkaddr, bool modify,
+		   uint16_t nb_lf);
+int cpt_lfs_detach(struct dev *dev);
+int cpt_lfs_alloc(struct dev *dev, uint8_t eng_grpmsk, uint8_t blk,
+		  bool inl_dev_sso);
+int cpt_lfs_free(struct dev *dev);
+
+int cpt_get_msix_offset(struct dev *dev, struct msix_offset_rsp **msix_rsp);
+uint64_t cpt_get_blkaddr(struct dev *dev);
+
+#endif /* _ROC_CPT_PRIV_H_ */
diff --git a/drivers/common/cnxk/roc_dev.c b/drivers/common/cnxk/roc_dev.c
index a39acc9..052ebe0 100644
--- a/drivers/common/cnxk/roc_dev.c
+++ b/drivers/common/cnxk/roc_dev.c
@@ -870,6 +870,8 @@ dev_vf_hwcap_update(struct plt_pci_device *pci_dev, struct dev *dev)
 		break;
 	case PCI_DEVID_CNXK_RVU_SSO_TIM_VF:
 	case PCI_DEVID_CNXK_RVU_NPA_VF:
+	case PCI_DEVID_CN10K_RVU_CPT_VF:
+	case PCI_DEVID_CN9K_RVU_CPT_VF:
 	case PCI_DEVID_CNXK_RVU_AF_VF:
 	case PCI_DEVID_CNXK_RVU_VF:
 	case PCI_DEVID_CNXK_RVU_SDP_VF:
diff --git a/drivers/common/cnxk/roc_dev_priv.h b/drivers/common/cnxk/roc_dev_priv.h
index 910cfb6..f8277fb 100644
--- a/drivers/common/cnxk/roc_dev_priv.h
+++ b/drivers/common/cnxk/roc_dev_priv.h
@@ -83,6 +83,7 @@ struct dev {
 	uint16_t maxvf;
 	struct dev_ops *ops;
 	void *roc_nix;
+	void *roc_cpt;
 	bool disable_shared_lmt; /* false(default): shared lmt mode enabled */
 } __plt_cache_aligned;
 
diff --git a/drivers/common/cnxk/roc_platform.c b/drivers/common/cnxk/roc_platform.c
index 3999fce..74dbdec 100644
--- a/drivers/common/cnxk/roc_platform.c
+++ b/drivers/common/cnxk/roc_platform.c
@@ -58,6 +58,7 @@ roc_plt_init(void)
 
 RTE_LOG_REGISTER(cnxk_logtype_base, pmd.cnxk.base, NOTICE);
 RTE_LOG_REGISTER(cnxk_logtype_mbox, pmd.cnxk.mbox, NOTICE);
+RTE_LOG_REGISTER(cnxk_logtype_cpt, pmd.crypto.cnxk, NOTICE);
 RTE_LOG_REGISTER(cnxk_logtype_npa, pmd.mempool.cnxk, NOTICE);
 RTE_LOG_REGISTER(cnxk_logtype_nix, pmd.net.cnxk, NOTICE);
 RTE_LOG_REGISTER(cnxk_logtype_npc, pmd.net.cnxk.flow, NOTICE);
diff --git a/drivers/common/cnxk/roc_platform.h b/drivers/common/cnxk/roc_platform.h
index 7864fa4..daee100 100644
--- a/drivers/common/cnxk/roc_platform.h
+++ b/drivers/common/cnxk/roc_platform.h
@@ -139,6 +139,7 @@
 /* Log */
 extern int cnxk_logtype_base;
 extern int cnxk_logtype_mbox;
+extern int cnxk_logtype_cpt;
 extern int cnxk_logtype_npa;
 extern int cnxk_logtype_nix;
 extern int cnxk_logtype_npc;
@@ -161,6 +162,7 @@ extern int cnxk_logtype_tm;
 		##args)
 
 #define plt_base_dbg(fmt, ...)	plt_dbg(base, fmt, ##__VA_ARGS__)
+#define plt_cpt_dbg(fmt, ...)	plt_dbg(cpt, fmt, ##__VA_ARGS__)
 #define plt_mbox_dbg(fmt, ...)	plt_dbg(mbox, fmt, ##__VA_ARGS__)
 #define plt_npa_dbg(fmt, ...)	plt_dbg(npa, fmt, ##__VA_ARGS__)
 #define plt_nix_dbg(fmt, ...)	plt_dbg(nix, fmt, ##__VA_ARGS__)
@@ -169,6 +171,12 @@ extern int cnxk_logtype_tm;
 #define plt_tim_dbg(fmt, ...)	plt_dbg(tim, fmt, ##__VA_ARGS__)
 #define plt_tm_dbg(fmt, ...)	plt_dbg(tm, fmt, ##__VA_ARGS__)
 
+/* Datapath logs */
+#define plt_dp_err(fmt, args...)                                               \
+	RTE_LOG_DP(ERR, PMD, "%s():%u " fmt "\n", __func__, __LINE__, ##args)
+#define plt_dp_info(fmt, args...)                                              \
+	RTE_LOG_DP(INFO, PMD, "%s():%u " fmt "\n", __func__, __LINE__, ##args)
+
 #ifdef __cplusplus
 #define CNXK_PCI_ID(subsystem_dev, dev)                                        \
 	{                                                                      \
diff --git a/drivers/common/cnxk/roc_priv.h b/drivers/common/cnxk/roc_priv.h
index 5e7564c..54c28fc 100644
--- a/drivers/common/cnxk/roc_priv.h
+++ b/drivers/common/cnxk/roc_priv.h
@@ -32,4 +32,7 @@
 /* TIM */
 #include "roc_tim_priv.h"
 
+/* CPT */
+#include "roc_cpt_priv.h"
+
 #endif /* _ROC_PRIV_H_ */
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 8e67c83..f8e286e 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -2,6 +2,7 @@ INTERNAL {
 	global:
 
 	cnxk_logtype_base;
+	cnxk_logtype_cpt;
 	cnxk_logtype_mbox;
 	cnxk_logtype_nix;
 	cnxk_logtype_npa;
@@ -10,6 +11,11 @@ INTERNAL {
 	cnxk_logtype_tim;
 	cnxk_logtype_tm;
 	roc_clk_freq_get;
+	roc_cpt_dev_clear;
+	roc_cpt_dev_configure;
+	roc_cpt_dev_fini;
+	roc_cpt_dev_init;
+	roc_cpt_eng_grp_add;
 	roc_error_msg_get;
 	roc_idev_lmt_base_addr_get;
 	roc_idev_npa_maxpools_get;
-- 
2.7.4

[dpdk-dev] [PATCH v2 04/17] common/cnxk: add idev CPT set - get

[Anoob Joseph]

Add APIs to set & get CPT device.

Signed-off-by: Anoob Joseph <anoobj@marvell.com>
---
 drivers/common/cnxk/roc_cpt.c       |  8 ++++++++
 drivers/common/cnxk/roc_idev.c      | 21 +++++++++++++++++++++
 drivers/common/cnxk/roc_idev.h      |  3 +++
 drivers/common/cnxk/roc_idev_priv.h |  2 ++
 drivers/common/cnxk/version.map     |  2 ++
 5 files changed, 36 insertions(+)

diff --git a/drivers/common/cnxk/roc_cpt.c b/drivers/common/cnxk/roc_cpt.c
index 2376125..d891a3b 100644
--- a/drivers/common/cnxk/roc_cpt.c
+++ b/drivers/common/cnxk/roc_cpt.c
@@ -230,6 +230,10 @@ roc_cpt_dev_init(struct roc_cpt *roc_cpt)
 
 	dev->roc_cpt = roc_cpt;
 
+	/* Set it to idev if not already present */
+	if (!roc_idev_cpt_get())
+		roc_idev_cpt_set(roc_cpt);
+
 	return 0;
 
 fail:
@@ -244,6 +248,10 @@ roc_cpt_dev_fini(struct roc_cpt *roc_cpt)
 	if (cpt == NULL)
 		return -EINVAL;
 
+	/* Remove idev references */
+	if (roc_idev_cpt_get() == roc_cpt)
+		roc_idev_cpt_set(NULL);
+
 	roc_cpt->nb_lf_avail = 0;
 
 	roc_cpt->lmt_base = 0;
diff --git a/drivers/common/cnxk/roc_idev.c b/drivers/common/cnxk/roc_idev.c
index 63cc040..b40ae82 100644
--- a/drivers/common/cnxk/roc_idev.c
+++ b/drivers/common/cnxk/roc_idev.c
@@ -36,6 +36,7 @@ idev_set_defaults(struct idev_cfg *idev)
 	idev->lmt_pf_func = 0;
 	idev->lmt_base_addr = 0;
 	idev->num_lmtlines = 0;
+	idev->cpt = NULL;
 	__atomic_store_n(&idev->npa_refcnt, 0, __ATOMIC_RELEASE);
 }
 
@@ -170,6 +171,26 @@ roc_idev_num_lmtlines_get(void)
 	return num_lmtlines;
 }
 
+struct roc_cpt *
+roc_idev_cpt_get(void)
+{
+	struct idev_cfg *idev = idev_get_cfg();
+
+	if (idev != NULL)
+		return idev->cpt;
+
+	return NULL;
+}
+
+void
+roc_idev_cpt_set(struct roc_cpt *cpt)
+{
+	struct idev_cfg *idev = idev_get_cfg();
+
+	if (idev != NULL)
+		__atomic_store_n(&idev->cpt, cpt, __ATOMIC_RELEASE);
+}
+
 struct roc_nix *
 roc_idev_npa_nix_get(void)
 {
diff --git a/drivers/common/cnxk/roc_idev.h b/drivers/common/cnxk/roc_idev.h
index 043e8af..16793c2 100644
--- a/drivers/common/cnxk/roc_idev.h
+++ b/drivers/common/cnxk/roc_idev.h
@@ -12,6 +12,9 @@ void __roc_api roc_idev_npa_maxpools_set(uint32_t max_pools);
 uint64_t __roc_api roc_idev_lmt_base_addr_get(void);
 uint16_t __roc_api roc_idev_num_lmtlines_get(void);
 
+struct roc_cpt *__roc_api roc_idev_cpt_get(void);
+void __roc_api roc_idev_cpt_set(struct roc_cpt *cpt);
+
 struct roc_nix *__roc_api roc_idev_npa_nix_get(void);
 
 #endif /* _ROC_IDEV_H_ */
diff --git a/drivers/common/cnxk/roc_idev_priv.h b/drivers/common/cnxk/roc_idev_priv.h
index ff10a90..95b2389 100644
--- a/drivers/common/cnxk/roc_idev_priv.h
+++ b/drivers/common/cnxk/roc_idev_priv.h
@@ -7,6 +7,7 @@
 
 /* Intra device related functions */
 struct npa_lf;
+struct roc_cpt;
 struct idev_cfg {
 	uint16_t sso_pf_func;
 	uint16_t npa_pf_func;
@@ -16,6 +17,7 @@ struct idev_cfg {
 	uint16_t lmt_pf_func;
 	uint16_t num_lmtlines;
 	uint64_t lmt_base_addr;
+	struct roc_cpt *cpt;
 };
 
 /* Generic */
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index f8e286e..f36127c 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -17,6 +17,8 @@ INTERNAL {
 	roc_cpt_dev_init;
 	roc_cpt_eng_grp_add;
 	roc_error_msg_get;
+	roc_idev_cpt_get;
+	roc_idev_cpt_set;
 	roc_idev_lmt_base_addr_get;
 	roc_idev_npa_maxpools_get;
 	roc_idev_npa_maxpools_set;
-- 
2.7.4

[dpdk-dev] [PATCH v2 05/17] common/cnxk: add mbox to configure RXC

[Anoob Joseph]

From: Vidya Sagar Velumuri <vvelumuri@marvell.com>

Add mailbox to configure tiemouts and thresholds in
CPT RXC unit.

Signed-off-by: Aakash Sasidharan <asasidharan@marvell.com>
Signed-off-by: Vidya Sagar Velumuri <vvelumuri@marvell.com>

---
 drivers/common/cnxk/roc_cpt.c   | 27 +++++++++++++++++++++++++++
 drivers/common/cnxk/roc_cpt.h   | 10 ++++++++++
 drivers/common/cnxk/version.map |  1 +
 3 files changed, 38 insertions(+)

diff --git a/drivers/common/cnxk/roc_cpt.c b/drivers/common/cnxk/roc_cpt.c
index d891a3b..e723ee7 100644
--- a/drivers/common/cnxk/roc_cpt.c
+++ b/drivers/common/cnxk/roc_cpt.c
@@ -6,6 +6,33 @@
 #include "roc_priv.h"
 
 int
+roc_cpt_rxc_time_cfg(struct roc_cpt *roc_cpt, struct roc_cpt_rxc_time_cfg *cfg)
+{
+	struct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt);
+	struct cpt_rxc_time_cfg_req *req;
+	struct dev *dev = &cpt->dev;
+
+	req = mbox_alloc_msg_cpt_rxc_time_cfg(dev->mbox);
+	if (req == NULL)
+		return -ENOSPC;
+
+	req->blkaddr = 0;
+
+	/* The step value is in microseconds. */
+	req->step = cfg->step;
+
+	/* The timeout will be: limit * step microseconds */
+	req->zombie_limit = cfg->zombie_limit;
+	req->zombie_thres = cfg->zombie_thres;
+
+	/* The timeout will be: limit * step microseconds */
+	req->active_limit = cfg->active_limit;
+	req->active_thres = cfg->active_thres;
+
+	return mbox_process(dev->mbox);
+}
+
+int
 cpt_get_msix_offset(struct dev *dev, struct msix_offset_rsp **msix_rsp)
 {
 	struct mbox *mbox = dev->mbox;
diff --git a/drivers/common/cnxk/roc_cpt.h b/drivers/common/cnxk/roc_cpt.h
index 4e1cf84..bae472f 100644
--- a/drivers/common/cnxk/roc_cpt.h
+++ b/drivers/common/cnxk/roc_cpt.h
@@ -28,6 +28,16 @@ struct roc_cpt {
 	uint8_t reserved[ROC_CPT_MEM_SZ] __plt_cache_aligned;
 } __plt_cache_aligned;
 
+struct roc_cpt_rxc_time_cfg {
+	uint32_t step;
+	uint16_t active_limit;
+	uint16_t active_thres;
+	uint16_t zombie_limit;
+	uint16_t zombie_thres;
+};
+
+int __roc_api roc_cpt_rxc_time_cfg(struct roc_cpt *roc_cpt,
+				   struct roc_cpt_rxc_time_cfg *cfg);
 int __roc_api roc_cpt_dev_init(struct roc_cpt *roc_cpt);
 int __roc_api roc_cpt_dev_fini(struct roc_cpt *roc_cpt);
 int __roc_api roc_cpt_eng_grp_add(struct roc_cpt *roc_cpt,
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index f36127c..13fd026 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -16,6 +16,7 @@ INTERNAL {
 	roc_cpt_dev_fini;
 	roc_cpt_dev_init;
 	roc_cpt_eng_grp_add;
+	roc_cpt_rxc_time_cfg;
 	roc_error_msg_get;
 	roc_idev_cpt_get;
 	roc_idev_cpt_set;
-- 
2.7.4

[dpdk-dev] [PATCH v2 06/17] common/cnxk: add CPT LF config

[Anoob Joseph]

From: Archana Muniganti <marchana@marvell.com>

Add routines to init & fini CPT LFs. CPT LFs are
queues to the hardware enabling instruction submissions.

Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Archana Muniganti <marchana@marvell.com>
Signed-off-by: Vidya Sagar Velumuri <vvelumuri@marvell.com>

---
 drivers/common/cnxk/roc_cpt.c      | 357 +++++++++++++++++++++++++++++++++++++
 drivers/common/cnxk/roc_cpt.h      |  20 +++
 drivers/common/cnxk/roc_cpt_priv.h |   2 +
 drivers/common/cnxk/version.map    |   3 +
 4 files changed, 382 insertions(+)

diff --git a/drivers/common/cnxk/roc_cpt.c b/drivers/common/cnxk/roc_cpt.c
index e723ee7..02062c1 100644
--- a/drivers/common/cnxk/roc_cpt.c
+++ b/drivers/common/cnxk/roc_cpt.c
@@ -5,6 +5,189 @@
 #include "roc_api.h"
 #include "roc_priv.h"
 
+#define CPT_IQ_FC_LEN  128
+#define CPT_IQ_GRP_LEN 16
+
+#define CPT_IQ_NB_DESC_MULTIPLIER 40
+
+/* The effective queue size to software is (CPT_LF_Q_SIZE[SIZE_DIV40] - 1 - 8).
+ *
+ * CPT requires 320 free entries (+8). And 40 entries are required for
+ * allowing CPT to discard packet when the queues are full (+1).
+ */
+#define CPT_IQ_NB_DESC_SIZE_DIV40(nb_desc)                                     \
+	(PLT_DIV_CEIL(nb_desc, CPT_IQ_NB_DESC_MULTIPLIER) + 1 + 8)
+
+#define CPT_IQ_GRP_SIZE(nb_desc)                                               \
+	(CPT_IQ_NB_DESC_SIZE_DIV40(nb_desc) * CPT_IQ_GRP_LEN)
+
+#define CPT_LF_MAX_NB_DESC     128000
+#define CPT_LF_DEFAULT_NB_DESC 1024
+
+static void
+cpt_lf_misc_intr_enb_dis(struct roc_cpt_lf *lf, bool enb)
+{
+	/* Enable all cpt lf error irqs except RQ_DISABLED and CQ_DISABLED */
+	if (enb)
+		plt_write64((BIT_ULL(6) | BIT_ULL(5) | BIT_ULL(3) | BIT_ULL(2) |
+			     BIT_ULL(1)),
+			    lf->rbase + CPT_LF_MISC_INT_ENA_W1S);
+	else
+		plt_write64((BIT_ULL(6) | BIT_ULL(5) | BIT_ULL(3) | BIT_ULL(2) |
+			     BIT_ULL(1)),
+			    lf->rbase + CPT_LF_MISC_INT_ENA_W1C);
+}
+
+static void
+cpt_lf_misc_irq(void *param)
+{
+	struct roc_cpt_lf *lf = (struct roc_cpt_lf *)param;
+	struct dev *dev = lf->dev;
+	uint64_t intr;
+
+	intr = plt_read64(lf->rbase + CPT_LF_MISC_INT);
+	if (intr == 0)
+		return;
+
+	plt_err("Err_irq=0x%" PRIx64 " pf=%d, vf=%d", intr, dev->pf, dev->vf);
+
+	/* Clear interrupt */
+	plt_write64(intr, lf->rbase + CPT_LF_MISC_INT);
+}
+
+static int
+cpt_lf_register_misc_irq(struct roc_cpt_lf *lf)
+{
+	struct plt_pci_device *pci_dev = lf->pci_dev;
+	struct plt_intr_handle *handle;
+	int rc, vec;
+
+	handle = &pci_dev->intr_handle;
+
+	vec = lf->msixoff + CPT_LF_INT_VEC_MISC;
+	/* Clear err interrupt */
+	cpt_lf_misc_intr_enb_dis(lf, false);
+	/* Set used interrupt vectors */
+	rc = dev_irq_register(handle, cpt_lf_misc_irq, lf, vec);
+	/* Enable all dev interrupt except for RQ_DISABLED */
+	cpt_lf_misc_intr_enb_dis(lf, true);
+
+	return rc;
+}
+
+static void
+cpt_lf_unregister_misc_irq(struct roc_cpt_lf *lf)
+{
+	struct plt_pci_device *pci_dev = lf->pci_dev;
+	struct plt_intr_handle *handle;
+	int vec;
+
+	handle = &pci_dev->intr_handle;
+
+	vec = lf->msixoff + CPT_LF_INT_VEC_MISC;
+	/* Clear err interrupt */
+	cpt_lf_misc_intr_enb_dis(lf, false);
+	dev_irq_unregister(handle, cpt_lf_misc_irq, lf, vec);
+}
+
+static void
+cpt_lf_done_intr_enb_dis(struct roc_cpt_lf *lf, bool enb)
+{
+	if (enb)
+		plt_write64(0x1, lf->rbase + CPT_LF_DONE_INT_ENA_W1S);
+	else
+		plt_write64(0x1, lf->rbase + CPT_LF_DONE_INT_ENA_W1C);
+}
+
+static void
+cpt_lf_done_irq(void *param)
+{
+	struct roc_cpt_lf *lf = param;
+	uint64_t done_wait;
+	uint64_t intr;
+
+	/* Read the number of completed requests */
+	intr = plt_read64(lf->rbase + CPT_LF_DONE);
+	if (intr == 0)
+		return;
+
+	done_wait = plt_read64(lf->rbase + CPT_LF_DONE_WAIT);
+
+	/* Acknowledge the number of completed requests */
+	plt_write64(intr, lf->rbase + CPT_LF_DONE_ACK);
+
+	plt_write64(done_wait, lf->rbase + CPT_LF_DONE_WAIT);
+}
+
+static int
+cpt_lf_register_done_irq(struct roc_cpt_lf *lf)
+{
+	struct plt_pci_device *pci_dev = lf->pci_dev;
+	struct plt_intr_handle *handle;
+	int rc, vec;
+
+	handle = &pci_dev->intr_handle;
+
+	vec = lf->msixoff + CPT_LF_INT_VEC_DONE;
+
+	/* Clear done interrupt */
+	cpt_lf_done_intr_enb_dis(lf, false);
+
+	/* Set used interrupt vectors */
+	rc = dev_irq_register(handle, cpt_lf_done_irq, lf, vec);
+
+	/* Enable done interrupt */
+	cpt_lf_done_intr_enb_dis(lf, true);
+
+	return rc;
+}
+
+static void
+cpt_lf_unregister_done_irq(struct roc_cpt_lf *lf)
+{
+	struct plt_pci_device *pci_dev = lf->pci_dev;
+	struct plt_intr_handle *handle;
+	int vec;
+
+	handle = &pci_dev->intr_handle;
+
+	vec = lf->msixoff + CPT_LF_INT_VEC_DONE;
+
+	/* Clear done interrupt */
+	cpt_lf_done_intr_enb_dis(lf, false);
+	dev_irq_unregister(handle, cpt_lf_done_irq, lf, vec);
+}
+
+static int
+cpt_lf_register_irqs(struct roc_cpt_lf *lf)
+{
+	int rc;
+
+	if (lf->msixoff == MSIX_VECTOR_INVALID) {
+		plt_err("Invalid CPTLF MSIX vector offset vector: 0x%x",
+			lf->msixoff);
+		return -EINVAL;
+	}
+
+	/* Register lf err interrupt */
+	rc = cpt_lf_register_misc_irq(lf);
+	if (rc)
+		plt_err("Error registering IRQs");
+
+	rc = cpt_lf_register_done_irq(lf);
+	if (rc)
+		plt_err("Error registering IRQs");
+
+	return rc;
+}
+
+static void
+cpt_lf_unregister_irqs(struct roc_cpt_lf *lf)
+{
+	cpt_lf_unregister_misc_irq(lf);
+	cpt_lf_unregister_done_irq(lf);
+}
+
 int
 roc_cpt_rxc_time_cfg(struct roc_cpt *roc_cpt, struct roc_cpt_rxc_time_cfg *cfg)
 {
@@ -146,6 +329,69 @@ cpt_hardware_caps_get(struct dev *dev, union cpt_eng_caps *hw_caps)
 	return 0;
 }
 
+static uint32_t
+cpt_lf_iq_mem_calc(uint32_t nb_desc)
+{
+	uint32_t len;
+
+	/* Space for instruction group memory */
+	len = CPT_IQ_GRP_SIZE(nb_desc);
+
+	/* Align to 128B */
+	len = PLT_ALIGN(len, ROC_ALIGN);
+
+	/* Space for FC */
+	len += CPT_IQ_FC_LEN;
+
+	/* For instruction queues */
+	len += CPT_IQ_NB_DESC_SIZE_DIV40(nb_desc) * CPT_IQ_NB_DESC_MULTIPLIER *
+	       sizeof(struct cpt_inst_s);
+
+	return len;
+}
+
+static inline void
+cpt_iq_init(struct roc_cpt_lf *lf)
+{
+	union cpt_lf_q_size lf_q_size = {.u = 0x0};
+	union cpt_lf_q_base lf_q_base = {.u = 0x0};
+	union cpt_lf_inprog lf_inprog;
+	union cpt_lf_ctl lf_ctl;
+	uintptr_t addr;
+
+	lf->io_addr = lf->rbase + CPT_LF_NQX(0);
+
+	/* Disable command queue */
+	roc_cpt_iq_disable(lf);
+
+	/* Set command queue base address */
+	addr = (uintptr_t)lf->iq_vaddr +
+	       PLT_ALIGN(CPT_IQ_GRP_SIZE(lf->nb_desc), ROC_ALIGN);
+
+	lf_q_base.u = addr;
+
+	plt_write64(lf_q_base.u, lf->rbase + CPT_LF_Q_BASE);
+
+	/* Set command queue size */
+	lf_q_size.s.size_div40 = CPT_IQ_NB_DESC_SIZE_DIV40(lf->nb_desc);
+	plt_write64(lf_q_size.u, lf->rbase + CPT_LF_Q_SIZE);
+
+	/* Enable command queue execution */
+	lf_inprog.u = plt_read64(lf->rbase + CPT_LF_INPROG);
+	lf_inprog.s.eena = 1;
+	plt_write64(lf_inprog.u, lf->rbase + CPT_LF_INPROG);
+
+	/* Enable instruction queue enqueuing */
+	lf_ctl.u = plt_read64(lf->rbase + CPT_LF_CTL);
+	lf_ctl.s.ena = 1;
+	lf_ctl.s.fc_ena = 1;
+	lf_ctl.s.fc_up_crossing = 1;
+	lf_ctl.s.fc_hyst_bits = CPT_FC_NUM_HYST_BITS;
+	plt_write64(lf_ctl.u, lf->rbase + CPT_LF_CTL);
+
+	lf->fc_addr = (uint64_t *)addr;
+}
+
 int
 roc_cpt_dev_configure(struct roc_cpt *roc_cpt, int nb_lf)
 {
@@ -210,6 +456,63 @@ cpt_get_blkaddr(struct dev *dev)
 }
 
 int
+cpt_lf_init(struct roc_cpt_lf *lf)
+{
+	struct dev *dev = lf->dev;
+	uint64_t blkaddr;
+	void *iq_mem;
+	int rc;
+
+	if (lf->nb_desc == 0 || lf->nb_desc > CPT_LF_MAX_NB_DESC)
+		lf->nb_desc = CPT_LF_DEFAULT_NB_DESC;
+
+	/* Allocate memory for instruction queue for CPT LF. */
+	iq_mem = plt_zmalloc(cpt_lf_iq_mem_calc(lf->nb_desc), ROC_ALIGN);
+	if (iq_mem == NULL)
+		return -ENOMEM;
+
+	blkaddr = cpt_get_blkaddr(dev);
+	lf->rbase = dev->bar2 + ((blkaddr << 20) | (lf->lf_id << 12));
+	lf->iq_vaddr = iq_mem;
+	lf->lmt_base = dev->lmt_base;
+	lf->pf_func = dev->pf_func;
+
+	/* Initialize instruction queue */
+	cpt_iq_init(lf);
+
+	rc = cpt_lf_register_irqs(lf);
+	if (rc)
+		goto disable_iq;
+
+	return 0;
+
+disable_iq:
+	roc_cpt_iq_disable(lf);
+	plt_free(iq_mem);
+	return rc;
+}
+
+int
+roc_cpt_lf_init(struct roc_cpt *roc_cpt, struct roc_cpt_lf *lf)
+{
+	struct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt);
+	int rc;
+
+	lf->dev = &cpt->dev;
+	lf->roc_cpt = roc_cpt;
+	lf->msixoff = cpt->lf_msix_off[lf->lf_id];
+	lf->pci_dev = cpt->pci_dev;
+
+	rc = cpt_lf_init(lf);
+	if (rc)
+		return rc;
+
+	/* LF init successful */
+	roc_cpt->lf[lf->lf_id] = lf;
+	return rc;
+}
+
+int
 roc_cpt_dev_init(struct roc_cpt *roc_cpt)
 {
 	struct plt_pci_device *pci_dev;
@@ -267,6 +570,29 @@ roc_cpt_dev_init(struct roc_cpt *roc_cpt)
 	return rc;
 }
 
+void
+cpt_lf_fini(struct roc_cpt_lf *lf)
+{
+	/* Unregister IRQ's */
+	cpt_lf_unregister_irqs(lf);
+
+	/* Disable IQ */
+	roc_cpt_iq_disable(lf);
+
+	/* Free memory */
+	plt_free(lf->iq_vaddr);
+	lf->iq_vaddr = NULL;
+}
+
+void
+roc_cpt_lf_fini(struct roc_cpt_lf *lf)
+{
+	if (lf == NULL)
+		return;
+	lf->roc_cpt->lf[lf->lf_id] = NULL;
+	cpt_lf_fini(lf);
+}
+
 int
 roc_cpt_dev_fini(struct roc_cpt *roc_cpt)
 {
@@ -341,3 +667,34 @@ roc_cpt_eng_grp_add(struct roc_cpt *roc_cpt, enum cpt_eng_type eng_type)
 
 	return rsp->eng_grp_num;
 }
+
+void
+roc_cpt_iq_disable(struct roc_cpt_lf *lf)
+{
+	union cpt_lf_ctl lf_ctl = {.u = 0x0};
+	union cpt_lf_inprog lf_inprog;
+	int timeout = 20;
+
+	/* Disable instructions enqueuing */
+	plt_write64(lf_ctl.u, lf->rbase + CPT_LF_CTL);
+
+	/* Wait for instruction queue to become empty */
+	do {
+		lf_inprog.u = plt_read64(lf->rbase + CPT_LF_INPROG);
+		if (!lf_inprog.s.inflight)
+			break;
+
+		plt_delay_ms(20);
+		if (timeout-- < 0) {
+			plt_err("CPT LF %d is still busy", lf->lf_id);
+			break;
+		}
+
+	} while (1);
+
+	/* Disable executions in the LF's queue.
+	 * The queue should be empty at this point
+	 */
+	lf_inprog.s.eena = 0x0;
+	plt_write64(lf_inprog.u, lf->rbase + CPT_LF_INPROG);
+}
diff --git a/drivers/common/cnxk/roc_cpt.h b/drivers/common/cnxk/roc_cpt.h
index bae472f..e258ca5 100644
--- a/drivers/common/cnxk/roc_cpt.h
+++ b/drivers/common/cnxk/roc_cpt.h
@@ -14,6 +14,23 @@
 
 #define ROC_CPT_MAX_LFS 64
 
+struct roc_cpt_lf {
+	/* Input parameters */
+	uint16_t lf_id;
+	uint32_t nb_desc;
+	/* End of Input parameters */
+	struct plt_pci_device *pci_dev;
+	struct dev *dev;
+	struct roc_cpt *roc_cpt;
+	uintptr_t rbase;
+	uintptr_t lmt_base;
+	uint16_t msixoff;
+	uint16_t pf_func;
+	uint64_t *fc_addr;
+	uint64_t io_addr;
+	uint8_t *iq_vaddr;
+} __plt_cache_aligned;
+
 struct roc_cpt {
 	struct plt_pci_device *pci_dev;
 	struct roc_cpt_lf *lf[ROC_CPT_MAX_LFS];
@@ -44,4 +61,7 @@ int __roc_api roc_cpt_eng_grp_add(struct roc_cpt *roc_cpt,
 				  enum cpt_eng_type eng_type);
 int __roc_api roc_cpt_dev_configure(struct roc_cpt *roc_cpt, int nb_lf);
 void __roc_api roc_cpt_dev_clear(struct roc_cpt *roc_cpt);
+int __roc_api roc_cpt_lf_init(struct roc_cpt *roc_cpt, struct roc_cpt_lf *lf);
+void __roc_api roc_cpt_lf_fini(struct roc_cpt_lf *lf);
+void __roc_api roc_cpt_iq_disable(struct roc_cpt_lf *lf);
 #endif /* _ROC_CPT_H_ */
diff --git a/drivers/common/cnxk/roc_cpt_priv.h b/drivers/common/cnxk/roc_cpt_priv.h
index 0ef6774..6cfa4df 100644
--- a/drivers/common/cnxk/roc_cpt_priv.h
+++ b/drivers/common/cnxk/roc_cpt_priv.h
@@ -30,6 +30,8 @@ int cpt_lfs_detach(struct dev *dev);
 int cpt_lfs_alloc(struct dev *dev, uint8_t eng_grpmsk, uint8_t blk,
 		  bool inl_dev_sso);
 int cpt_lfs_free(struct dev *dev);
+int cpt_lf_init(struct roc_cpt_lf *lf);
+void cpt_lf_fini(struct roc_cpt_lf *lf);
 
 int cpt_get_msix_offset(struct dev *dev, struct msix_offset_rsp **msix_rsp);
 uint64_t cpt_get_blkaddr(struct dev *dev);
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 13fd026..128997e 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -16,6 +16,9 @@ INTERNAL {
 	roc_cpt_dev_fini;
 	roc_cpt_dev_init;
 	roc_cpt_eng_grp_add;
+	roc_cpt_iq_disable;
+	roc_cpt_lf_init;
+	roc_cpt_lf_fini;
 	roc_cpt_rxc_time_cfg;
 	roc_error_msg_get;
 	roc_idev_cpt_get;
-- 
2.7.4

[dpdk-dev] [PATCH v2 07/17] common/cnxk: add CPT diagnostics

[Anoob Joseph]

From: Aakash Sasidharan <asasidharan@marvell.com>

Add routines to fetch and dump CPT statistics and states.

Signed-off-by: Aakash Sasidharan <asasidharan@marvell.com>
Signed-off-by: Srujana Challa <schalla@marvell.com>

---
 drivers/common/cnxk/meson.build     |   1 +
 drivers/common/cnxk/roc_cpt.c       |  29 +++++++
 drivers/common/cnxk/roc_cpt.h       |   3 +
 drivers/common/cnxk/roc_cpt_debug.c | 167 ++++++++++++++++++++++++++++++++++++
 drivers/common/cnxk/version.map     |   2 +
 5 files changed, 202 insertions(+)
 create mode 100644 drivers/common/cnxk/roc_cpt_debug.c

diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build
index 739e0e4..f139e0b 100644
--- a/drivers/common/cnxk/meson.build
+++ b/drivers/common/cnxk/meson.build
@@ -12,6 +12,7 @@ config_flag_fmt = 'RTE_LIBRTE_@0@_COMMON'
 deps = ['eal', 'pci', 'bus_pci', 'mbuf']
 sources = files(
         'roc_cpt.c',
+        'roc_cpt_debug.c',
         'roc_dev.c',
         'roc_idev.c',
         'roc_irq.c',
diff --git a/drivers/common/cnxk/roc_cpt.c b/drivers/common/cnxk/roc_cpt.c
index 02062c1..21c7704 100644
--- a/drivers/common/cnxk/roc_cpt.c
+++ b/drivers/common/cnxk/roc_cpt.c
@@ -188,6 +188,34 @@ cpt_lf_unregister_irqs(struct roc_cpt_lf *lf)
 	cpt_lf_unregister_done_irq(lf);
 }
 
+static void
+cpt_lf_dump(struct roc_cpt_lf *lf)
+{
+	plt_cpt_dbg("CPT LF");
+	plt_cpt_dbg("RBASE: 0x%016" PRIx64, lf->rbase);
+	plt_cpt_dbg("LMT_BASE: 0x%016" PRIx64, lf->lmt_base);
+	plt_cpt_dbg("MSIXOFF: 0x%x", lf->msixoff);
+	plt_cpt_dbg("LF_ID: 0x%x", lf->lf_id);
+	plt_cpt_dbg("NB DESC: %d", lf->nb_desc);
+	plt_cpt_dbg("FC_ADDR: 0x%016" PRIx64, (uintptr_t)lf->fc_addr);
+	plt_cpt_dbg("CQ.VADDR: 0x%016" PRIx64, (uintptr_t)lf->iq_vaddr);
+
+	plt_cpt_dbg("CPT LF REG:");
+	plt_cpt_dbg("LF_CTL[0x%016llx]: 0x%016" PRIx64, CPT_LF_CTL,
+		    plt_read64(lf->rbase + CPT_LF_CTL));
+	plt_cpt_dbg("Q_SIZE[0x%016llx]: 0x%016" PRIx64, CPT_LF_INPROG,
+		    plt_read64(lf->rbase + CPT_LF_INPROG));
+
+	plt_cpt_dbg("Q_BASE[0x%016llx]: 0x%016" PRIx64, CPT_LF_Q_BASE,
+		    plt_read64(lf->rbase + CPT_LF_Q_BASE));
+	plt_cpt_dbg("Q_SIZE[0x%016llx]: 0x%016" PRIx64, CPT_LF_Q_SIZE,
+		    plt_read64(lf->rbase + CPT_LF_Q_SIZE));
+	plt_cpt_dbg("Q_INST_PTR[0x%016llx]: 0x%016" PRIx64, CPT_LF_Q_INST_PTR,
+		    plt_read64(lf->rbase + CPT_LF_Q_INST_PTR));
+	plt_cpt_dbg("Q_GRP_PTR[0x%016llx]: 0x%016" PRIx64, CPT_LF_Q_GRP_PTR,
+		    plt_read64(lf->rbase + CPT_LF_Q_GRP_PTR));
+}
+
 int
 roc_cpt_rxc_time_cfg(struct roc_cpt *roc_cpt, struct roc_cpt_rxc_time_cfg *cfg)
 {
@@ -484,6 +512,7 @@ cpt_lf_init(struct roc_cpt_lf *lf)
 	if (rc)
 		goto disable_iq;
 
+	cpt_lf_dump(lf);
 	return 0;
 
 disable_iq:
diff --git a/drivers/common/cnxk/roc_cpt.h b/drivers/common/cnxk/roc_cpt.h
index e258ca5..73ecb4e 100644
--- a/drivers/common/cnxk/roc_cpt.h
+++ b/drivers/common/cnxk/roc_cpt.h
@@ -63,5 +63,8 @@ int __roc_api roc_cpt_dev_configure(struct roc_cpt *roc_cpt, int nb_lf);
 void __roc_api roc_cpt_dev_clear(struct roc_cpt *roc_cpt);
 int __roc_api roc_cpt_lf_init(struct roc_cpt *roc_cpt, struct roc_cpt_lf *lf);
 void __roc_api roc_cpt_lf_fini(struct roc_cpt_lf *lf);
+int __roc_api roc_cpt_afs_print(struct roc_cpt *roc_cpt);
+int __roc_api roc_cpt_lfs_print(struct roc_cpt *roc_cpt);
 void __roc_api roc_cpt_iq_disable(struct roc_cpt_lf *lf);
+
 #endif /* _ROC_CPT_H_ */
diff --git a/drivers/common/cnxk/roc_cpt_debug.c b/drivers/common/cnxk/roc_cpt_debug.c
new file mode 100644
index 0000000..9a9dcba
--- /dev/null
+++ b/drivers/common/cnxk/roc_cpt_debug.c
@@ -0,0 +1,167 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#include "roc_api.h"
+#include "roc_priv.h"
+
+static int
+cpt_af_reg_read(struct roc_cpt *roc_cpt, uint64_t reg, uint64_t *val)
+{
+	struct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt);
+	struct cpt_rd_wr_reg_msg *msg;
+	struct dev *dev = &cpt->dev;
+	int ret;
+
+	msg = mbox_alloc_msg_cpt_rd_wr_register(dev->mbox);
+	if (msg == NULL)
+		return -EIO;
+
+	msg->hdr.pcifunc = dev->pf_func;
+
+	msg->is_write = 0;
+	msg->reg_offset = reg;
+	msg->ret_val = val;
+
+	ret = mbox_process_msg(dev->mbox, (void *)&msg);
+	if (ret)
+		return -EIO;
+
+	*val = msg->val;
+
+	return 0;
+}
+
+static int
+cpt_sts_print(struct roc_cpt *roc_cpt)
+{
+	struct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt);
+	struct dev *dev = &cpt->dev;
+	struct cpt_sts_req *req;
+	struct cpt_sts_rsp *rsp;
+	int ret;
+
+	req = mbox_alloc_msg_cpt_sts_get(dev->mbox);
+	if (req == NULL)
+		return -EIO;
+
+	req->blkaddr = 0;
+	ret = mbox_process_msg(dev->mbox, (void *)&rsp);
+	if (ret)
+		return -EIO;
+
+	plt_print("    %s:\t0x%016" PRIx64, "inst_req_pc", rsp->inst_req_pc);
+	plt_print("    %s:\t0x%016" PRIx64, "inst_lat_pc", rsp->inst_lat_pc);
+	plt_print("    %s:\t\t0x%016" PRIx64, "rd_req_pc", rsp->rd_req_pc);
+	plt_print("    %s:\t\t0x%016" PRIx64, "rd_lat_pc", rsp->rd_lat_pc);
+	plt_print("    %s:\t\t0x%016" PRIx64, "rd_uc_pc", rsp->rd_uc_pc);
+	plt_print("    %s:\t0x%016" PRIx64, "active_cycles_pc",
+		  rsp->active_cycles_pc);
+	plt_print("    %s:\t\t0x%016" PRIx64, "ctx_mis_pc", rsp->ctx_mis_pc);
+	plt_print("    %s:\t\t0x%016" PRIx64, "ctx_hit_pc", rsp->ctx_hit_pc);
+	plt_print("    %s:\t\t0x%016" PRIx64, "ctx_aop_pc", rsp->ctx_aop_pc);
+	plt_print("    %s:\t0x%016" PRIx64, "ctx_aop_lat_pc",
+		  rsp->ctx_aop_lat_pc);
+	plt_print("    %s:\t0x%016" PRIx64, "ctx_ifetch_pc",
+		  rsp->ctx_ifetch_pc);
+	plt_print("    %s:\t0x%016" PRIx64, "ctx_ifetch_lat_pc",
+		  rsp->ctx_ifetch_lat_pc);
+	plt_print("    %s:\t0x%016" PRIx64, "ctx_ffetch_pc",
+		  rsp->ctx_ffetch_pc);
+	plt_print("    %s:\t0x%016" PRIx64, "ctx_ffetch_lat_pc",
+		  rsp->ctx_ffetch_lat_pc);
+	plt_print("    %s:\t0x%016" PRIx64, "ctx_wback_pc", rsp->ctx_wback_pc);
+	plt_print("    %s:\t0x%016" PRIx64, "ctx_wback_lat_pc",
+		  rsp->ctx_wback_lat_pc);
+	plt_print("    %s:\t\t0x%016" PRIx64, "ctx_psh_pc", rsp->ctx_psh_pc);
+	plt_print("    %s:\t0x%016" PRIx64, "ctx_psh_lat_pc",
+		  rsp->ctx_psh_lat_pc);
+	plt_print("    %s:\t\t0x%016" PRIx64, "ctx_err", rsp->ctx_err);
+	plt_print("    %s:\t\t0x%016" PRIx64, "ctx_enc_id", rsp->ctx_enc_id);
+	plt_print("    %s:\t0x%016" PRIx64, "ctx_flush_timer",
+		  rsp->ctx_flush_timer);
+	plt_print("    %s:\t\t0x%016" PRIx64, "rxc_time", rsp->rxc_time);
+	plt_print("    %s:\t0x%016" PRIx64, "rxc_time_cfg", rsp->rxc_time_cfg);
+	plt_print("    %s:\t0x%016" PRIx64, "rxc_active_sts",
+		  rsp->rxc_active_sts);
+	plt_print("    %s:\t0x%016" PRIx64, "rxc_zombie_sts",
+		  rsp->rxc_zombie_sts);
+	plt_print("    %s:\t0x%016" PRIx64, "rxc_dfrg", rsp->rxc_dfrg);
+	plt_print("    %s:\t0x%016" PRIx64, "x2p_link_cfg0",
+		  rsp->x2p_link_cfg0);
+	plt_print("    %s:\t0x%016" PRIx64, "x2p_link_cfg1",
+		  rsp->x2p_link_cfg1);
+	plt_print("    %s:\t0x%016" PRIx64, "busy_sts_ae", rsp->busy_sts_ae);
+	plt_print("    %s:\t0x%016" PRIx64, "free_sts_ae", rsp->free_sts_ae);
+	plt_print("    %s:\t0x%016" PRIx64, "busy_sts_se", rsp->busy_sts_se);
+	plt_print("    %s:\t0x%016" PRIx64, "free_sts_se", rsp->free_sts_se);
+	plt_print("    %s:\t0x%016" PRIx64, "busy_sts_ie", rsp->busy_sts_ie);
+	plt_print("    %s:\t0x%016" PRIx64, "free_sts_ie", rsp->free_sts_ie);
+	plt_print("    %s:\t0x%016" PRIx64, "exe_err_info", rsp->exe_err_info);
+	plt_print("    %s:\t\t0x%016" PRIx64, "cptclk_cnt", rsp->cptclk_cnt);
+	plt_print("    %s:\t\t0x%016" PRIx64, "diag", rsp->diag);
+
+	return 0;
+}
+
+int
+roc_cpt_afs_print(struct roc_cpt *roc_cpt)
+{
+	uint64_t reg_val;
+
+	plt_print("CPT AF registers:");
+
+	if (cpt_af_reg_read(roc_cpt, CPT_AF_LFX_CTL(0), &reg_val))
+		return -EIO;
+
+	plt_print("    CPT_AF_LF0_CTL:\t0x%016" PRIx64, reg_val);
+
+	if (cpt_af_reg_read(roc_cpt, CPT_AF_LFX_CTL2(0), &reg_val))
+		return -EIO;
+
+	plt_print("    CPT_AF_LF0_CTL2:\t0x%016" PRIx64, reg_val);
+
+	cpt_sts_print(roc_cpt);
+
+	return 0;
+}
+
+static void
+cpt_lf_print(struct roc_cpt_lf *lf)
+{
+	uint64_t reg_val;
+
+	reg_val = plt_read64(lf->rbase + CPT_LF_CTX_ENC_BYTE_CNT);
+	plt_print("    Encrypted byte count:\t%" PRIu64, reg_val);
+
+	reg_val = plt_read64(lf->rbase + CPT_LF_CTX_ENC_PKT_CNT);
+	plt_print("    Encrypted packet count:\t%" PRIu64, reg_val);
+
+	reg_val = plt_read64(lf->rbase + CPT_LF_CTX_DEC_BYTE_CNT);
+	plt_print("    Decrypted byte count:\t%" PRIu64, reg_val);
+
+	reg_val = plt_read64(lf->rbase + CPT_LF_CTX_ENC_PKT_CNT);
+	plt_print("    Decrypted packet count:\t%" PRIu64, reg_val);
+}
+
+int
+roc_cpt_lfs_print(struct roc_cpt *roc_cpt)
+{
+	struct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt);
+	struct roc_cpt_lf *lf;
+	int lf_id;
+
+	if (cpt == NULL)
+		return -EINVAL;
+
+	for (lf_id = 0; lf_id < roc_cpt->nb_lf; lf_id++) {
+		lf = roc_cpt->lf[lf_id];
+		if (lf == NULL)
+			continue;
+
+		plt_print("Count registers for CPT LF%d:", lf_id);
+		cpt_lf_print(lf);
+	}
+
+	return 0;
+}
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 128997e..87130df 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -11,6 +11,7 @@ INTERNAL {
 	cnxk_logtype_tim;
 	cnxk_logtype_tm;
 	roc_clk_freq_get;
+	roc_cpt_afs_print;
 	roc_cpt_dev_clear;
 	roc_cpt_dev_configure;
 	roc_cpt_dev_fini;
@@ -19,6 +20,7 @@ INTERNAL {
 	roc_cpt_iq_disable;
 	roc_cpt_lf_init;
 	roc_cpt_lf_fini;
+	roc_cpt_lfs_print;
 	roc_cpt_rxc_time_cfg;
 	roc_error_msg_get;
 	roc_idev_cpt_get;
-- 
2.7.4

[dpdk-dev] [PATCH v2 08/17] common/cnxk: add CPT LF flush

[Anoob Joseph]

From: Aakash Sasidharan <asasidharan@marvell.com>

Add routine to flush context from CPT context processor cache.

Signed-off-by: Aakash Sasidharan <asasidharan@marvell.com>
Signed-off-by: Vidya Sagar Velumuri <vvelumuri@marvell.com>

---
 drivers/common/cnxk/roc_cpt.c   | 18 ++++++++++++++++++
 drivers/common/cnxk/roc_cpt.h   |  1 +
 drivers/common/cnxk/version.map |  1 +
 3 files changed, 20 insertions(+)

diff --git a/drivers/common/cnxk/roc_cpt.c b/drivers/common/cnxk/roc_cpt.c
index 21c7704..fd92de3 100644
--- a/drivers/common/cnxk/roc_cpt.c
+++ b/drivers/common/cnxk/roc_cpt.c
@@ -599,6 +599,24 @@ roc_cpt_dev_init(struct roc_cpt *roc_cpt)
 	return rc;
 }
 
+int
+roc_cpt_lf_ctx_flush(struct roc_cpt_lf *lf, uint64_t cptr)
+{
+	union cpt_lf_ctx_flush reg;
+
+	if (lf == NULL)
+		return -ENOTSUP;
+
+	reg.u = 0;
+	reg.s.pf_func = lf->pf_func;
+	reg.s.inval = 1;
+	reg.s.cptr = cptr;
+
+	plt_write64(reg.u, lf->rbase + CPT_LF_CTX_FLUSH);
+
+	return 0;
+}
+
 void
 cpt_lf_fini(struct roc_cpt_lf *lf)
 {
diff --git a/drivers/common/cnxk/roc_cpt.h b/drivers/common/cnxk/roc_cpt.h
index 73ecb4e..022c8ad 100644
--- a/drivers/common/cnxk/roc_cpt.h
+++ b/drivers/common/cnxk/roc_cpt.h
@@ -63,6 +63,7 @@ int __roc_api roc_cpt_dev_configure(struct roc_cpt *roc_cpt, int nb_lf);
 void __roc_api roc_cpt_dev_clear(struct roc_cpt *roc_cpt);
 int __roc_api roc_cpt_lf_init(struct roc_cpt *roc_cpt, struct roc_cpt_lf *lf);
 void __roc_api roc_cpt_lf_fini(struct roc_cpt_lf *lf);
+int __roc_api roc_cpt_lf_ctx_flush(struct roc_cpt_lf *lf, uint64_t cptr);
 int __roc_api roc_cpt_afs_print(struct roc_cpt *roc_cpt);
 int __roc_api roc_cpt_lfs_print(struct roc_cpt *roc_cpt);
 void __roc_api roc_cpt_iq_disable(struct roc_cpt_lf *lf);
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 87130df..0827b77 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -18,6 +18,7 @@ INTERNAL {
 	roc_cpt_dev_init;
 	roc_cpt_eng_grp_add;
 	roc_cpt_iq_disable;
+	roc_cpt_lf_ctx_flush;
 	roc_cpt_lf_init;
 	roc_cpt_lf_fini;
 	roc_cpt_lfs_print;
-- 
2.7.4

[dpdk-dev] [PATCH v2 09/17] common/cnxk: add inline IPsec configuration mbox

[Anoob Joseph]

From: Vidya Sagar Velumuri <vvelumuri@marvell.com>

Add mbox to configure inbound & outbound inline IPsec.

Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
Signed-off-by: Vidya Sagar Velumuri <vvelumuri@marvell.com>
---
 drivers/common/cnxk/roc_cpt.c      | 61 ++++++++++++++++++++++++++++++++++++++
 drivers/common/cnxk/roc_cpt.h      |  5 ++++
 drivers/common/cnxk/roc_cpt_priv.h |  2 ++
 drivers/common/cnxk/version.map    |  2 ++
 4 files changed, 70 insertions(+)

diff --git a/drivers/common/cnxk/roc_cpt.c b/drivers/common/cnxk/roc_cpt.c
index fd92de3..81e8b15 100644
--- a/drivers/common/cnxk/roc_cpt.c
+++ b/drivers/common/cnxk/roc_cpt.c
@@ -217,6 +217,67 @@ cpt_lf_dump(struct roc_cpt_lf *lf)
 }
 
 int
+cpt_lf_outb_cfg(struct dev *dev, uint16_t sso_pf_func, uint16_t nix_pf_func,
+		uint8_t lf_id, bool ena)
+{
+	struct cpt_inline_ipsec_cfg_msg *req;
+	struct mbox *mbox = dev->mbox;
+
+	req = mbox_alloc_msg_cpt_inline_ipsec_cfg(mbox);
+	if (req == NULL)
+		return -ENOSPC;
+
+	req->dir = CPT_INLINE_OUTBOUND;
+	req->slot = lf_id;
+	if (ena) {
+		req->enable = 1;
+		req->sso_pf_func = sso_pf_func;
+		req->nix_pf_func = nix_pf_func;
+	} else {
+		req->enable = 0;
+	}
+
+	return mbox_process(mbox);
+}
+
+int
+roc_cpt_inline_ipsec_cfg(struct dev *cpt_dev, uint8_t lf_id,
+			 struct roc_nix *roc_nix)
+{
+	bool ena = roc_nix ? true : false;
+	uint16_t nix_pf_func = 0;
+	uint16_t sso_pf_func = 0;
+
+	if (ena) {
+		nix_pf_func = roc_nix_get_pf_func(roc_nix);
+		sso_pf_func = idev_sso_pffunc_get();
+	}
+
+	return cpt_lf_outb_cfg(cpt_dev, sso_pf_func, nix_pf_func, lf_id, ena);
+}
+
+int
+roc_cpt_inline_ipsec_inb_cfg(struct roc_cpt *roc_cpt, uint16_t param1,
+			     uint16_t param2)
+{
+	struct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt);
+	struct cpt_rx_inline_lf_cfg_msg *req;
+	struct mbox *mbox;
+
+	mbox = cpt->dev.mbox;
+
+	req = mbox_alloc_msg_cpt_rx_inline_lf_cfg(mbox);
+	if (req == NULL)
+		return -ENOSPC;
+
+	req->sso_pf_func = idev_sso_pffunc_get();
+	req->param1 = param1;
+	req->param2 = param2;
+
+	return mbox_process(mbox);
+}
+
+int
 roc_cpt_rxc_time_cfg(struct roc_cpt *roc_cpt, struct roc_cpt_rxc_time_cfg *cfg)
 {
 	struct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt);
diff --git a/drivers/common/cnxk/roc_cpt.h b/drivers/common/cnxk/roc_cpt.h
index 022c8ad..83ef5c7 100644
--- a/drivers/common/cnxk/roc_cpt.h
+++ b/drivers/common/cnxk/roc_cpt.h
@@ -29,6 +29,7 @@ struct roc_cpt_lf {
 	uint64_t *fc_addr;
 	uint64_t io_addr;
 	uint8_t *iq_vaddr;
+	struct roc_nix *inl_outb_nix;
 } __plt_cache_aligned;
 
 struct roc_cpt {
@@ -64,6 +65,10 @@ void __roc_api roc_cpt_dev_clear(struct roc_cpt *roc_cpt);
 int __roc_api roc_cpt_lf_init(struct roc_cpt *roc_cpt, struct roc_cpt_lf *lf);
 void __roc_api roc_cpt_lf_fini(struct roc_cpt_lf *lf);
 int __roc_api roc_cpt_lf_ctx_flush(struct roc_cpt_lf *lf, uint64_t cptr);
+int __roc_api roc_cpt_inline_ipsec_cfg(struct dev *dev, uint8_t slot,
+				       struct roc_nix *nix);
+int __roc_api roc_cpt_inline_ipsec_inb_cfg(struct roc_cpt *roc_cpt,
+					   uint16_t param1, uint16_t param2);
 int __roc_api roc_cpt_afs_print(struct roc_cpt *roc_cpt);
 int __roc_api roc_cpt_lfs_print(struct roc_cpt *roc_cpt);
 void __roc_api roc_cpt_iq_disable(struct roc_cpt_lf *lf);
diff --git a/drivers/common/cnxk/roc_cpt_priv.h b/drivers/common/cnxk/roc_cpt_priv.h
index 6cfa4df..0880ec0 100644
--- a/drivers/common/cnxk/roc_cpt_priv.h
+++ b/drivers/common/cnxk/roc_cpt_priv.h
@@ -33,6 +33,8 @@ int cpt_lfs_free(struct dev *dev);
 int cpt_lf_init(struct roc_cpt_lf *lf);
 void cpt_lf_fini(struct roc_cpt_lf *lf);
 
+int cpt_lf_outb_cfg(struct dev *dev, uint16_t sso_pf_func, uint16_t nix_pf_func,
+		    uint8_t lf_id, bool ena);
 int cpt_get_msix_offset(struct dev *dev, struct msix_offset_rsp **msix_rsp);
 uint64_t cpt_get_blkaddr(struct dev *dev);
 
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 0827b77..59d7d91 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -17,6 +17,8 @@ INTERNAL {
 	roc_cpt_dev_fini;
 	roc_cpt_dev_init;
 	roc_cpt_eng_grp_add;
+	roc_cpt_inline_ipsec_cfg;
+	roc_cpt_inline_ipsec_inb_cfg;
 	roc_cpt_iq_disable;
 	roc_cpt_lf_ctx_flush;
 	roc_cpt_lf_init;
-- 
2.7.4

[dpdk-dev] [PATCH v2 10/17] common/cnxk: add SE microcode defines

[Anoob Joseph]

From: Kiran Kumar Kokkilagadda <kirankumark@marvell.com>

Microcode SE opcodes support symmetric operations. Add defines
and structs defined by microcode.

Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Kiran Kumar Kokkilagadda <kirankumark@marvell.com>
Signed-off-by: Vidya Sagar Velumuri <vvelumuri@marvell.com>
---
 drivers/common/cnxk/roc_api.h |   3 +
 drivers/common/cnxk/roc_cpt.h |  34 ++++++
 drivers/common/cnxk/roc_se.h  | 267 ++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 304 insertions(+)
 create mode 100644 drivers/common/cnxk/roc_se.h

diff --git a/drivers/common/cnxk/roc_api.h b/drivers/common/cnxk/roc_api.h
index 88a5611..6511614 100644
--- a/drivers/common/cnxk/roc_api.h
+++ b/drivers/common/cnxk/roc_api.h
@@ -109,4 +109,7 @@
 /* CPT */
 #include "roc_cpt.h"
 
+/* CPT microcode */
+#include "roc_se.h"
+
 #endif /* _ROC_API_H_ */
diff --git a/drivers/common/cnxk/roc_cpt.h b/drivers/common/cnxk/roc_cpt.h
index 83ef5c7..cb2838e 100644
--- a/drivers/common/cnxk/roc_cpt.h
+++ b/drivers/common/cnxk/roc_cpt.h
@@ -14,6 +14,40 @@
 
 #define ROC_CPT_MAX_LFS 64
 
+/* CPT helper macros */
+#define ROC_CPT_AH_HDR_LEN	 12
+#define ROC_CPT_AES_GCM_IV_LEN	 8
+#define ROC_CPT_AES_GCM_MAC_LEN	 16
+#define ROC_CPT_AES_CBC_IV_LEN	 16
+#define ROC_CPT_SHA1_HMAC_LEN	 12
+#define ROC_CPT_AUTH_KEY_LEN_MAX 64
+
+#define ROC_CPT_DES3_KEY_LEN	  24
+#define ROC_CPT_AES128_KEY_LEN	  16
+#define ROC_CPT_AES192_KEY_LEN	  24
+#define ROC_CPT_AES256_KEY_LEN	  32
+#define ROC_CPT_MD5_KEY_LENGTH	  16
+#define ROC_CPT_SHA1_KEY_LENGTH	  20
+#define ROC_CPT_SHA256_KEY_LENGTH 32
+#define ROC_CPT_SHA384_KEY_LENGTH 48
+#define ROC_CPT_SHA512_KEY_LENGTH 64
+#define ROC_CPT_AUTH_KEY_LEN_MAX  64
+
+#define ROC_CPT_DES_BLOCK_LENGTH 8
+#define ROC_CPT_AES_BLOCK_LENGTH 16
+
+#define ROC_CPT_AES_GCM_ROUNDUP_BYTE_LEN 4
+#define ROC_CPT_AES_CBC_ROUNDUP_BYTE_LEN 16
+
+/* Salt length for AES-CTR/GCM/CCM and AES-GMAC */
+#define ROC_CPT_SALT_LEN 4
+
+#define ROC_CPT_ESP_HDR_LEN	    8
+#define ROC_CPT_ESP_TRL_LEN	    2
+#define ROC_CPT_AH_HDR_LEN	    12
+#define ROC_CPT_TUNNEL_IPV4_HDR_LEN 20
+#define ROC_CPT_TUNNEL_IPV6_HDR_LEN 40
+
 struct roc_cpt_lf {
 	/* Input parameters */
 	uint16_t lf_id;
diff --git a/drivers/common/cnxk/roc_se.h b/drivers/common/cnxk/roc_se.h
new file mode 100644
index 0000000..ffae065
--- /dev/null
+++ b/drivers/common/cnxk/roc_se.h
@@ -0,0 +1,267 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef __ROC_SE_H__
+#define __ROC_SE_H__
+
+/* SE opcodes */
+#define ROC_SE_MAJOR_OP_FC	      0x33
+#define ROC_SE_FC_MINOR_OP_ENCRYPT    0x0
+#define ROC_SE_FC_MINOR_OP_DECRYPT    0x1
+#define ROC_SE_FC_MINOR_OP_HMAC_FIRST 0x10
+
+#define ROC_SE_MAJOR_OP_HASH	   0x34
+#define ROC_SE_MAJOR_OP_HMAC	   0x35
+#define ROC_SE_MAJOR_OP_ZUC_SNOW3G 0x37
+#define ROC_SE_MAJOR_OP_KASUMI	   0x38
+#define ROC_SE_MAJOR_OP_MISC	   0x01
+
+#define ROC_SE_MAX_AAD_SIZE 64
+#define ROC_SE_MAX_MAC_LEN  64
+
+#define ROC_SE_OFF_CTRL_LEN 8
+#define ROC_SE_DMA_MODE	    (1 << 7)
+
+#define ROC_SE_MAX_SG_IN_OUT_CNT 32
+#define ROC_SE_MAX_SG_CNT	 (ROC_SE_MAX_SG_IN_OUT_CNT / 2)
+
+#define ROC_SE_SG_LIST_HDR_SIZE (8u)
+#define ROC_SE_SG_ENTRY_SIZE	sizeof(struct roc_se_sglist_comp)
+
+#define ROC_SE_ZS_EA 0x1
+#define ROC_SE_ZS_IA 0x2
+#define ROC_SE_K_F8  0x4
+#define ROC_SE_K_F9  0x8
+
+#define ROC_SE_FC_GEN	 0x1
+#define ROC_SE_PDCP	 0x2
+#define ROC_SE_KASUMI	 0x3
+#define ROC_SE_HASH_HMAC 0x4
+
+#define ROC_SE_OP_CIPHER_ENCRYPT 0x1
+#define ROC_SE_OP_CIPHER_DECRYPT 0x2
+#define ROC_SE_OP_CIPHER_MASK                                                  \
+	(ROC_SE_OP_CIPHER_ENCRYPT | ROC_SE_OP_CIPHER_DECRYPT)
+
+#define ROC_SE_OP_AUTH_VERIFY	0x4
+#define ROC_SE_OP_AUTH_GENERATE 0x8
+#define ROC_SE_OP_AUTH_MASK                                                    \
+	(ROC_SE_OP_AUTH_VERIFY | ROC_SE_OP_AUTH_GENERATE)
+
+#define ROC_SE_OP_ENCODE (ROC_SE_OP_CIPHER_ENCRYPT | ROC_SE_OP_AUTH_GENERATE)
+#define ROC_SE_OP_DECODE (ROC_SE_OP_CIPHER_DECRYPT | ROC_SE_OP_AUTH_VERIFY)
+
+#define ROC_SE_ALWAYS_USE_SEPARATE_BUF
+
+/*
+ * Parameters for Flexi Crypto
+ * requests
+ */
+#define ROC_SE_VALID_AAD_BUF	       0x01
+#define ROC_SE_VALID_MAC_BUF	       0x02
+#define ROC_SE_VALID_IV_BUF	       0x04
+#define ROC_SE_SINGLE_BUF_INPLACE      0x08
+#define ROC_SE_SINGLE_BUF_HEADROOM     0x10
+
+#define ROC_SE_ENCR_IV_OFFSET(__d_offs) (((__d_offs) >> 32) & 0xffff)
+#define ROC_SE_ENCR_OFFSET(__d_offs)	(((__d_offs) >> 16) & 0xffff)
+#define ROC_SE_AUTH_OFFSET(__d_offs)	((__d_offs) & 0xffff)
+#define ROC_SE_ENCR_DLEN(__d_lens)	((__d_lens) >> 32)
+#define ROC_SE_AUTH_DLEN(__d_lens)	((__d_lens) & 0xffffffff)
+
+typedef enum { ROC_SE_FROM_CTX = 0, ROC_SE_FROM_DPTR = 1 } roc_se_input_type;
+
+typedef enum {
+	ROC_SE_MD5_TYPE = 1,
+	ROC_SE_SHA1_TYPE = 2,
+	ROC_SE_SHA2_SHA224 = 3,
+	ROC_SE_SHA2_SHA256 = 4,
+	ROC_SE_SHA2_SHA384 = 5,
+	ROC_SE_SHA2_SHA512 = 6,
+	ROC_SE_GMAC_TYPE = 7,
+	ROC_SE_POLY1305 = 8,
+	ROC_SE_SHA3_SHA224 = 10,
+	ROC_SE_SHA3_SHA256 = 11,
+	ROC_SE_SHA3_SHA384 = 12,
+	ROC_SE_SHA3_SHA512 = 13,
+	ROC_SE_SHA3_SHAKE256 = 14,
+	ROC_SE_SHA3_SHAKE512 = 15,
+
+	/* These are only for software use */
+	ROC_SE_ZUC_EIA3 = 0x90,
+	ROC_SE_SNOW3G_UIA2 = 0x91,
+	ROC_SE_AES_CMAC_EIA2 = 0x92,
+	ROC_SE_KASUMI_F9_CBC = 0x93,
+	ROC_SE_KASUMI_F9_ECB = 0x94,
+} roc_se_auth_type;
+
+typedef enum {
+	/* To support passthrough */
+	ROC_SE_PASSTHROUGH = 0x0,
+	/*
+	 * These are defined by MC for Flexi crypto
+	 * for field of 4 bits
+	 */
+	ROC_SE_DES3_CBC = 0x1,
+	ROC_SE_DES3_ECB = 0x2,
+	ROC_SE_AES_CBC = 0x3,
+	ROC_SE_AES_ECB = 0x4,
+	ROC_SE_AES_CFB = 0x5,
+	ROC_SE_AES_CTR = 0x6,
+	ROC_SE_AES_GCM = 0x7,
+	ROC_SE_AES_XTS = 0x8,
+	ROC_SE_CHACHA20 = 0x9,
+
+	/* These are only for software use */
+	ROC_SE_ZUC_EEA3 = 0x90,
+	ROC_SE_SNOW3G_UEA2 = 0x91,
+	ROC_SE_AES_CTR_EEA2 = 0x92,
+	ROC_SE_KASUMI_F8_CBC = 0x93,
+	ROC_SE_KASUMI_F8_ECB = 0x94,
+} roc_se_cipher_type;
+
+typedef enum {
+	/* Microcode errors */
+	ROC_SE_NO_ERR = 0x00,
+	ROC_SE_ERR_OPCODE_UNSUPPORTED = 0x01,
+
+	/* SCATTER GATHER */
+	ROC_SE_ERR_SCATTER_GATHER_WRITE_LENGTH = 0x02,
+	ROC_SE_ERR_SCATTER_GATHER_LIST = 0x03,
+	ROC_SE_ERR_SCATTER_GATHER_NOT_SUPPORTED = 0x04,
+
+	/* SE GC */
+	ROC_SE_ERR_GC_LENGTH_INVALID = 0x41,
+	ROC_SE_ERR_GC_RANDOM_LEN_INVALID = 0x42,
+	ROC_SE_ERR_GC_DATA_LEN_INVALID = 0x43,
+	ROC_SE_ERR_GC_DRBG_TYPE_INVALID = 0x44,
+	ROC_SE_ERR_GC_CTX_LEN_INVALID = 0x45,
+	ROC_SE_ERR_GC_CIPHER_UNSUPPORTED = 0x46,
+	ROC_SE_ERR_GC_AUTH_UNSUPPORTED = 0x47,
+	ROC_SE_ERR_GC_OFFSET_INVALID = 0x48,
+	ROC_SE_ERR_GC_HASH_MODE_UNSUPPORTED = 0x49,
+	ROC_SE_ERR_GC_DRBG_ENTROPY_LEN_INVALID = 0x4a,
+	ROC_SE_ERR_GC_DRBG_ADDNL_LEN_INVALID = 0x4b,
+	ROC_SE_ERR_GC_ICV_MISCOMPARE = 0x4c,
+	ROC_SE_ERR_GC_DATA_UNALIGNED = 0x4d,
+
+	/* API Layer */
+	ROC_SE_ERR_REQ_PENDING = 0xfe,
+	ROC_SE_ERR_REQ_TIMEOUT = 0xff,
+
+} roc_se_error_code;
+
+typedef enum {
+	ROC_SE_AES_128_BIT = 0x1,
+	ROC_SE_AES_192_BIT = 0x2,
+	ROC_SE_AES_256_BIT = 0x3
+} roc_se_aes_type;
+
+struct roc_se_sglist_comp {
+	union {
+		uint64_t len;
+		struct {
+			uint16_t len[4];
+		} s;
+	} u;
+	uint64_t ptr[4];
+};
+
+struct roc_se_enc_context {
+	uint64_t iv_source : 1;
+	uint64_t aes_key : 2;
+	uint64_t rsvd_60 : 1;
+	uint64_t enc_cipher : 4;
+	uint64_t auth_input_type : 1;
+	uint64_t rsvd_52_54 : 3;
+	uint64_t hash_type : 4;
+	uint64_t mac_len : 8;
+	uint64_t rsvd_39_0 : 40;
+	uint8_t encr_key[32];
+	uint8_t encr_iv[16];
+};
+
+struct roc_se_hmac_context {
+	uint8_t ipad[64];
+	uint8_t opad[64];
+};
+
+struct roc_se_context {
+	struct roc_se_enc_context enc;
+	struct roc_se_hmac_context hmac;
+};
+
+struct roc_se_zuc_snow3g_ctx {
+	uint8_t encr_auth_iv[16];
+	uint8_t ci_key[16];
+	uint8_t zuc_const[32];
+};
+
+struct roc_se_kasumi_ctx {
+	uint8_t reg_A[8];
+	uint8_t ci_key[16];
+};
+
+/* Buffer pointer */
+struct roc_se_buf_ptr {
+	void *vaddr;
+	uint32_t size;
+	uint32_t resv;
+};
+
+/* IOV Pointer */
+struct roc_se_iov_ptr {
+	int buf_cnt;
+	struct roc_se_buf_ptr bufs[0];
+};
+
+struct roc_se_fc_params {
+	/* 0th cache line */
+	union {
+		struct roc_se_buf_ptr bufs[1];
+		struct {
+			struct roc_se_iov_ptr *src_iov;
+			struct roc_se_iov_ptr *dst_iov;
+		};
+	};
+	void *iv_buf;
+	void *auth_iv_buf;
+	struct roc_se_buf_ptr meta_buf;
+	struct roc_se_buf_ptr ctx_buf;
+	uint64_t rsvd2;
+
+	/* 1st cache line */
+	struct roc_se_buf_ptr aad_buf __plt_cache_aligned;
+	struct roc_se_buf_ptr mac_buf;
+};
+
+PLT_STATIC_ASSERT((offsetof(struct roc_se_fc_params, aad_buf) % 128) == 0);
+
+#define ROC_SE_PDCP_ALG_TYPE_ZUC     0
+#define ROC_SE_PDCP_ALG_TYPE_SNOW3G  1
+#define ROC_SE_PDCP_ALG_TYPE_AES_CTR 2
+
+struct roc_se_ctx {
+	/* Below fields are accessed by sw */
+	uint64_t enc_cipher : 8;
+	uint64_t hash_type : 8;
+	uint64_t mac_len : 8;
+	uint64_t auth_key_len : 8;
+	uint64_t fc_type : 4;
+	uint64_t hmac : 1;
+	uint64_t zsk_flags : 3;
+	uint64_t k_ecb : 1;
+	uint64_t pdcp_alg_type : 2;
+	uint64_t rsvd : 21;
+	union cpt_inst_w4 template_w4;
+	/* Below fields are accessed by hardware */
+	union {
+		struct roc_se_context fctx;
+		struct roc_se_zuc_snow3g_ctx zs_ctx;
+		struct roc_se_kasumi_ctx k_ctx;
+	} se_ctx;
+	uint8_t auth_key[1024];
+};
+
+#endif /* __ROC_SE_H__ */
-- 
2.7.4

[dpdk-dev] [PATCH v2 11/17] common/cnxk: add IE microcode defines

[Anoob Joseph]

From: Srujana Challa <schalla@marvell.com>

Microcode IE opcodes support IPsec operations. Add defines
and structs defined by microcode.

Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Srujana Challa <schalla@marvell.com>
Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
---
 drivers/common/cnxk/roc_api.h      |   2 +
 drivers/common/cnxk/roc_ie.h       |  19 ++
 drivers/common/cnxk/roc_ie_on.h    | 152 +++++++++++
 drivers/common/cnxk/roc_ie_ot.h    | 534 +++++++++++++++++++++++++++++++++++++
 drivers/common/cnxk/roc_platform.h |   1 +
 5 files changed, 708 insertions(+)
 create mode 100644 drivers/common/cnxk/roc_ie.h
 create mode 100644 drivers/common/cnxk/roc_ie_on.h
 create mode 100644 drivers/common/cnxk/roc_ie_ot.h

diff --git a/drivers/common/cnxk/roc_api.h b/drivers/common/cnxk/roc_api.h
index 6511614..d545bb9 100644
--- a/drivers/common/cnxk/roc_api.h
+++ b/drivers/common/cnxk/roc_api.h
@@ -110,6 +110,8 @@
 #include "roc_cpt.h"
 
 /* CPT microcode */
+#include "roc_ie_on.h"
+#include "roc_ie_ot.h"
 #include "roc_se.h"
 
 #endif /* _ROC_API_H_ */
diff --git a/drivers/common/cnxk/roc_ie.h b/drivers/common/cnxk/roc_ie.h
new file mode 100644
index 0000000..a330ea1
--- /dev/null
+++ b/drivers/common/cnxk/roc_ie.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef __ROC_IE_H__
+#define __ROC_IE_H__
+
+/* CNXK IPSEC helper macros */
+#define ROC_IE_AH_HDR_LEN      12
+#define ROC_IE_AES_GCM_IV_LEN  8
+#define ROC_IE_AES_GCM_MAC_LEN 16
+#define ROC_IE_AES_CBC_IV_LEN  16
+#define ROC_IE_SHA1_HMAC_LEN   12
+#define ROC_IE_AUTH_KEY_LEN_MAX 64
+
+#define ROC_IE_AES_GCM_ROUNDUP_BYTE_LEN 4
+#define ROC_IE_AES_CBC_ROUNDUP_BYTE_LEN 16
+
+#endif /* __ROC_IE_H__ */
diff --git a/drivers/common/cnxk/roc_ie_on.h b/drivers/common/cnxk/roc_ie_on.h
new file mode 100644
index 0000000..508654a
--- /dev/null
+++ b/drivers/common/cnxk/roc_ie_on.h
@@ -0,0 +1,152 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef __ROC_IE_ON_H__
+#define __ROC_IE_ON_H__
+
+/* CN9K IPSEC LA opcodes */
+#define ROC_IE_ONL_MAJOR_OP_WRITE_IPSEC_OUTBOUND   0x20
+#define ROC_IE_ONL_MAJOR_OP_WRITE_IPSEC_INBOUND	   0x21
+#define ROC_IE_ONL_MAJOR_OP_PROCESS_OUTBOUND_IPSEC 0x23
+#define ROC_IE_ONL_MAJOR_OP_PROCESS_INBOUND_IPSEC  0x24
+
+/* CN9K IPSEC FP opcodes */
+#define ROC_IE_ONF_MAJOR_OP_PROCESS_OUTBOUND_IPSEC 0x25UL
+#define ROC_IE_ONF_MAJOR_OP_PROCESS_INBOUND_IPSEC  0x26UL
+
+/* Ucode completion codes */
+#define ROC_IE_ONF_UCC_SUCCESS 0
+
+enum {
+	ROC_IE_ON_SA_DIR_INBOUND = 0,
+	ROC_IE_ON_SA_DIR_OUTBOUND = 1,
+};
+
+enum {
+	ROC_IE_ON_SA_IP_VERSION_4 = 0,
+	ROC_IE_ON_SA_IP_VERSION_6 = 1,
+};
+
+enum {
+	ROC_IE_ON_SA_MODE_TRANSPORT = 0,
+	ROC_IE_ON_SA_MODE_TUNNEL = 1,
+};
+
+enum {
+	ROC_IE_ON_SA_PROTOCOL_AH = 0,
+	ROC_IE_ON_SA_PROTOCOL_ESP = 1,
+};
+
+enum {
+	ROC_IE_ON_SA_AES_KEY_LEN_128 = 1,
+	ROC_IE_ON_SA_AES_KEY_LEN_192 = 2,
+	ROC_IE_ON_SA_AES_KEY_LEN_256 = 3,
+};
+
+enum {
+	ROC_IE_ON_SA_ENC_NULL = 0,
+	ROC_IE_ON_SA_ENC_DES_CBC = 1,
+	ROC_IE_ON_SA_ENC_3DES_CBC = 2,
+	ROC_IE_ON_SA_ENC_AES_CBC = 3,
+	ROC_IE_ON_SA_ENC_AES_CTR = 4,
+	ROC_IE_ON_SA_ENC_AES_GCM = 5,
+	ROC_IE_ON_SA_ENC_AES_CCM = 6,
+};
+
+enum {
+	ROC_IE_ON_SA_AUTH_NULL = 0,
+	ROC_IE_ON_SA_AUTH_MD5 = 1,
+	ROC_IE_ON_SA_AUTH_SHA1 = 2,
+	ROC_IE_ON_SA_AUTH_SHA2_224 = 3,
+	ROC_IE_ON_SA_AUTH_SHA2_256 = 4,
+	ROC_IE_ON_SA_AUTH_SHA2_384 = 5,
+	ROC_IE_ON_SA_AUTH_SHA2_512 = 6,
+	ROC_IE_ON_SA_AUTH_AES_GMAC = 7,
+	ROC_IE_ON_SA_AUTH_AES_XCBC_128 = 8,
+};
+
+enum {
+	ROC_IE_ON_SA_FRAG_POST = 0,
+	ROC_IE_ON_SA_FRAG_PRE = 1,
+};
+
+enum {
+	ROC_IE_ON_SA_ENCAP_NONE = 0,
+	ROC_IE_ON_SA_ENCAP_UDP = 1,
+};
+
+struct roc_ie_onf_sa_ctl {
+	uint32_t spi;
+	uint64_t exp_proto_inter_frag : 8;
+	uint64_t rsvd_41_40 : 2;
+	/* Disable SPI, SEQ data in RPTR for Inbound inline */
+	uint64_t spi_seq_dis : 1;
+	uint64_t esn_en : 1;
+	uint64_t rsvd_44_45 : 2;
+	uint64_t encap_type : 2;
+	uint64_t enc_type : 3;
+	uint64_t rsvd_48 : 1;
+	uint64_t auth_type : 4;
+	uint64_t valid : 1;
+	uint64_t direction : 1;
+	uint64_t outer_ip_ver : 1;
+	uint64_t inner_ip_ver : 1;
+	uint64_t ipsec_mode : 1;
+	uint64_t ipsec_proto : 1;
+	uint64_t aes_key_len : 2;
+};
+
+struct roc_onf_ipsec_outb_sa {
+	/* w0 */
+	struct roc_ie_onf_sa_ctl ctl;
+
+	/* w1 */
+	uint8_t nonce[4];
+	uint16_t udp_src;
+	uint16_t udp_dst;
+
+	/* w2 */
+	uint32_t ip_src;
+	uint32_t ip_dst;
+
+	/* w3-w6 */
+	uint8_t cipher_key[32];
+
+	/* w7-w12 */
+	uint8_t hmac_key[48];
+};
+
+struct roc_onf_ipsec_inb_sa {
+	/* w0 */
+	struct roc_ie_onf_sa_ctl ctl;
+
+	/* w1 */
+	uint8_t nonce[4]; /* Only for AES-GCM */
+	uint32_t unused;
+
+	/* w2 */
+	uint32_t esn_hi;
+	uint32_t esn_low;
+
+	/* w3-w6 */
+	uint8_t cipher_key[32];
+
+	/* w7-w12 */
+	uint8_t hmac_key[48];
+};
+
+#define ROC_ONF_IPSEC_INB_MAX_L2_SZ	  32UL
+#define ROC_ONF_IPSEC_OUTB_MAX_L2_SZ	  30UL
+#define ROC_ONF_IPSEC_OUTB_MAX_L2_INFO_SZ (ROC_ONF_IPSEC_OUTB_MAX_L2_SZ + 2)
+
+#define ROC_ONF_IPSEC_INB_RES_OFF    80
+#define ROC_ONF_IPSEC_INB_SPI_SEQ_SZ 16
+
+struct roc_onf_ipsec_outb_hdr {
+	uint32_t ip_id;
+	uint32_t seq;
+	uint8_t iv[16];
+};
+
+#endif /* __ROC_IE_ON_H__ */
diff --git a/drivers/common/cnxk/roc_ie_ot.h b/drivers/common/cnxk/roc_ie_ot.h
new file mode 100644
index 0000000..aeb4be2
--- /dev/null
+++ b/drivers/common/cnxk/roc_ie_ot.h
@@ -0,0 +1,534 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef __ROC_IE_OT_H__
+#define __ROC_IE_OT_H__
+
+/* PKIND to be used for CPT Meta parsing */
+#define ROC_OT_CPT_META_PKIND 58
+
+/* CN10K IPSEC opcodes */
+#define ROC_IE_OT_MAJOR_OP_PROCESS_OUTBOUND_IPSEC 0x28UL
+#define ROC_IE_OT_MAJOR_OP_PROCESS_INBOUND_IPSEC  0x29UL
+
+enum roc_ie_ot_ucc_ipsec {
+	ROC_IE_OT_UCC_SUCCESS = 0x00,
+	ROC_IE_OT_UCC_SUCCESS_PKT_IP_GOODCSUM = 0x02,
+	ROC_IE_OT_UCC_ERR_SA_INVAL = 0x03,
+	ROC_IE_OT_UCC_SUCCESS_PKT_IP_BADCSUM = 0x04,
+	ROC_IE_OT_UCC_ERR_SA_EXPIRED = 0x05,
+	ROC_IE_OT_UCC_SUCCESS_PKT_L4_GOODCSUM = 0x06,
+	ROC_IE_OT_UCC_ERR_SA_OVERFLOW = 0x07,
+	ROC_IE_OT_UCC_SUCCESS_PKT_L4_BADCSUM = 0x08,
+	ROC_IE_OT_UCC_ERR_SA_ESP_BAD_ALGO = 0x09,
+	ROC_IE_OT_UCC_SUCCESS_PKT_UDPESP_NZCSUM = 0x0a,
+	ROC_IE_OT_UCC_ERR_SA_ESP_BAD_KEYS = 0x0b,
+	ROC_IE_OT_UCC_SUCCESS_SA_SOFTEXP_FIRST = 0x0c,
+	ROC_IE_OT_UCC_ERR_SA_AH_BAD_ALGO = 0x0d,
+	ROC_IE_OT_UCC_SUCCESS_SA_SOFTEXP_AGAIN = 0x0e,
+	ROC_IE_OT_UCC_ERR_SA_AH_BAD_KEYS = 0x0f,
+	ROC_IE_OT_UCC_ERR_SA_BAD_IP = 0x11,
+	ROC_IE_OT_UCC_ERR_SA_BAD_CTX = 0x13,
+	ROC_IE_OT_UCC_ERR_AOP_IPSEC = 0x17,
+	ROC_IE_OT_UCC_ERR_PKT_IP = 0x23,
+	ROC_IE_OT_UCC_ERR_PKT_IP6_BAD_EXT = 0x25,
+	ROC_IE_OT_UCC_ERR_PKT_IP6_HBH = 0x27,
+	ROC_IE_OT_UCC_ERR_PKT_IP6_BIGEXT = 0x29,
+	ROC_IE_OT_UCC_ERR_PKT_IP_FRAG = 0x2b,
+	ROC_IE_OT_UCC_ERR_PKT_IP_ULP = 0x2d,
+	ROC_IE_OT_UCC_ERR_PKT_SA_MISMATCH = 0x2f,
+	ROC_IE_OT_UCC_ERR_PKT_SPI_MISMATCH = 0x31,
+	ROC_IE_OT_UCC_ERR_PKT_ESP_BADPAD = 0x33,
+	ROC_IE_OT_UCC_ERR_PKT_BADICV = 0x35,
+	ROC_IE_OT_UCC_ERR_PKT_REPLAY_SEQ = 0x37,
+	ROC_IE_OT_UCC_ERR_PKT_REPLAY_WINDOW = 0x39,
+	ROC_IE_OT_UCC_ERR_PKT_BADNH = 0x3b,
+	ROC_IE_OT_UCC_ERR_PKT_SA_PORT_MISMATCH = 0x3d,
+};
+
+enum {
+	ROC_IE_OT_SA_AR_WIN_DISABLED = 0,
+	ROC_IE_OT_SA_AR_WIN_64 = 1,
+	ROC_IE_OT_SA_AR_WIN_128 = 2,
+	ROC_IE_OT_SA_AR_WIN_256 = 3,
+	ROC_IE_OT_SA_AR_WIN_512 = 4,
+	ROC_IE_OT_SA_AR_WIN_1024 = 5,
+	ROC_IE_OT_SA_AR_WIN_2048 = 6,
+	ROC_IE_OT_SA_AR_WIN_4096 = 7,
+};
+
+enum {
+	ROC_IE_OT_SA_PKT_FMT_FULL = 0,
+	ROC_IE_OT_SA_PKT_FMT_META = 1,
+};
+
+enum {
+	ROC_IE_OT_SA_PKT_OUTPUT_DECRYPTED = 0,
+	ROC_IE_OT_SA_PKT_OUTPUT_NO_FRAG = 1,
+	ROC_IE_OT_SA_PKT_OUTPUT_HW_BASED_DEFRAG = 2,
+	ROC_IE_OT_SA_PKT_OUTPUT_UCODE_BASED_DEFRAG = 3,
+};
+
+enum {
+	ROC_IE_OT_SA_DEFRAG_ALL = 0,
+	ROC_IE_OT_SA_DEFRAG_IN_ORDER = 1,
+	ROC_IE_OT_SA_DEFRAG_IN_REV_ORDER = 2,
+};
+
+enum {
+	ROC_IE_OT_SA_IV_SRC_DEFAULT = 0,
+	ROC_IE_OT_SA_IV_SRC_ENC_CTR = 1,
+	ROC_IE_OT_SA_IV_SRC_FROM_SA = 2,
+};
+
+enum {
+	ROC_IE_OT_SA_COPY_FROM_SA = 0,
+	ROC_IE_OT_SA_COPY_FROM_INNER_IP_HDR = 1,
+};
+
+enum {
+	ROC_IE_OT_SA_INNER_PKT_IP_CSUM_ENABLE = 0,
+	ROC_IE_OT_SA_INNER_PKT_IP_CSUM_DISABLE = 1,
+};
+
+enum {
+	ROC_IE_OT_SA_INNER_PKT_L4_CSUM_ENABLE = 0,
+	ROC_IE_OT_SA_INNER_PKT_L4_CSUM_DISABLE = 1,
+};
+
+enum {
+	ROC_IE_OT_SA_DIR_INBOUND = 0,
+	ROC_IE_OT_SA_DIR_OUTBOUND = 1,
+};
+
+enum {
+	ROC_IE_OT_SA_IP_VERSION_4 = 0,
+	ROC_IE_OT_SA_IP_VERSION_6 = 1,
+};
+
+enum {
+	ROC_IE_OT_SA_MODE_TRANSPORT = 0,
+	ROC_IE_OT_SA_MODE_TUNNEL = 1,
+};
+
+enum {
+	ROC_IE_OT_SA_PROTOCOL_AH = 0,
+	ROC_IE_OT_SA_PROTOCOL_ESP = 1,
+};
+
+enum {
+	ROC_IE_OT_SA_AES_KEY_LEN_128 = 1,
+	ROC_IE_OT_SA_AES_KEY_LEN_192 = 2,
+	ROC_IE_OT_SA_AES_KEY_LEN_256 = 3,
+};
+
+enum {
+	ROC_IE_OT_SA_ENC_NULL = 0,
+	ROC_IE_OT_SA_ENC_3DES_CBC = 2,
+	ROC_IE_OT_SA_ENC_AES_CBC = 3,
+	ROC_IE_OT_SA_ENC_AES_CTR = 4,
+	ROC_IE_OT_SA_ENC_AES_GCM = 5,
+	ROC_IE_OT_SA_ENC_AES_CCM = 6,
+};
+
+enum {
+	ROC_IE_OT_SA_AUTH_NULL = 0,
+	ROC_IE_OT_SA_AUTH_SHA1 = 2,
+	ROC_IE_OT_SA_AUTH_SHA2_256 = 4,
+	ROC_IE_OT_SA_AUTH_SHA2_384 = 5,
+	ROC_IE_OT_SA_AUTH_SHA2_512 = 6,
+	ROC_IE_OT_SA_AUTH_AES_GMAC = 7,
+	ROC_IE_OT_SA_AUTH_AES_XCBC_128 = 8,
+};
+
+enum {
+	ROC_IE_OT_SA_ENCAP_NONE = 0,
+	ROC_IE_OT_SA_ENCAP_UDP = 1,
+	ROC_IE_OT_SA_ENCAP_TCP = 2,
+};
+
+enum {
+	ROC_IE_OT_SA_LIFE_UNIT_OCTETS = 0,
+	ROC_IE_OT_SA_LIFE_UNIT_PKTS = 1,
+};
+
+enum {
+	ROC_IE_OT_SA_IP_HDR_VERIFY_DISABLED = 0,
+	ROC_IE_OT_SA_IP_HDR_VERIFY_DST_ADDR = 1,
+	ROC_IE_OT_SA_IP_HDR_VERIFY_SRC_DST_ADDR = 2,
+};
+
+enum {
+	ROC_IE_OT_REAS_STS_SUCCESS = 0,
+	ROC_IE_OT_REAS_STS_TIMEOUT = 1,
+	ROC_IE_OT_REAS_STS_EVICT = 2,
+	ROC_IE_OT_REAS_STS_BAD_ORDER = 3,
+	ROC_IE_OT_REAS_STS_TOO_MANY = 4,
+	ROC_IE_OT_REAS_STS_HSH_EVICT = 5,
+	ROC_IE_OT_REAS_STS_OVERLAP = 6,
+	ROC_IE_OT_REAS_STS_ZOMBIE = 7,
+	ROC_IE_OT_REAS_STS_L3P_ERR = 8,
+	ROC_IE_OT_REAS_STS_MAX = 9
+};
+/* Context units in bytes */
+#define ROC_CTX_UNIT_8B		  8
+#define ROC_CTX_UNIT_128B	  128
+#define ROC_CTX_MAX_CKEY_LEN	  32
+#define ROC_CTX_MAX_OPAD_IPAD_LEN 128
+
+/* Anti reply window size supported */
+#define ROC_AR_WIN_SIZE_MIN	   64
+#define ROC_AR_WIN_SIZE_MAX	   4096
+#define ROC_LOG_MIN_AR_WIN_SIZE_M1 5
+
+/* u64 array size to fit anti replay window bits */
+#define ROC_AR_WINBITS_SZ                                                      \
+	(PLT_ALIGN_CEIL(ROC_AR_WIN_SIZE_MAX, BITS_PER_LONG_LONG) /             \
+	 BITS_PER_LONG_LONG)
+
+/* Common bit fields between inbound and outbound SA */
+union roc_ot_ipsec_sa_word2 {
+	struct {
+		uint64_t valid : 1;
+		uint64_t dir : 1;
+		uint64_t outer_ip_ver : 1;
+		uint64_t rsvd0 : 1;
+		uint64_t mode : 1;
+		uint64_t protocol : 1;
+		uint64_t aes_key_len : 2;
+
+		uint64_t enc_type : 3;
+		uint64_t life_unit : 1;
+		uint64_t auth_type : 4;
+
+		uint64_t encap_type : 2;
+		uint64_t rsvd1 : 6;
+
+		uint64_t rsvd2 : 7;
+		uint64_t async_mode : 1;
+
+		uint64_t spi : 32;
+	} s;
+	uint64_t u64;
+};
+
+PLT_STATIC_ASSERT(sizeof(union roc_ot_ipsec_sa_word2) == 1 * sizeof(uint64_t));
+
+union roc_ot_ipsec_outer_ip_hdr {
+	struct {
+		uint32_t dst_addr;
+		uint32_t src_addr;
+	} ipv4;
+	struct {
+		uint8_t src_addr[16];
+		uint8_t dst_addr[16];
+	} ipv6;
+};
+
+struct roc_ot_ipsec_inb_ctx_update_reg {
+	uint64_t ar_base;
+	uint64_t ar_valid_mask;
+	uint64_t hard_life;
+	uint64_t soft_life;
+	uint64_t mib_octs;
+	uint64_t mib_pkts;
+	uint64_t ar_winbits[ROC_AR_WINBITS_SZ];
+};
+
+union roc_ot_ipsec_outb_iv {
+	uint64_t u64[2];
+	uint8_t iv_dbg[16];
+	struct {
+		uint8_t iv_dbg1[4];
+		uint8_t salt[4];
+
+		uint32_t rsvd;
+		uint8_t iv_dbg2[4];
+	} s;
+};
+
+struct roc_ot_ipsec_outb_ctx_update_reg {
+	uint64_t rsvd;
+	uint64_t esn_val;
+	uint64_t hard_life;
+	uint64_t soft_life;
+	uint64_t mib_octs;
+	uint64_t mib_pkts;
+};
+
+union roc_ot_ipsec_outb_param1 {
+	uint16_t u16;
+	struct {
+		uint16_t l4_csum_disable : 1;
+		uint16_t ip_csum_disable : 1;
+		uint16_t ttl_or_hop_limit : 1;
+		uint16_t dummy_pkt : 1;
+		uint16_t rfc_or_override_mode : 1;
+		uint16_t reserved_5_15 : 11;
+	} s;
+};
+
+union roc_ot_ipsec_inb_param1 {
+	uint16_t u16;
+	struct {
+		uint16_t l4_csum_disable : 1;
+		uint16_t ip_csum_disable : 1;
+		uint16_t esp_trailer_disable : 1;
+		uint16_t reserved_3_15 : 13;
+	} s;
+};
+
+struct roc_ot_ipsec_inb_sa {
+	/* Word0 */
+	union {
+		struct {
+			uint64_t ar_win : 3;
+			uint64_t hard_life_dec : 1;
+			uint64_t soft_life_dec : 1;
+			uint64_t count_glb_octets : 1;
+			uint64_t count_glb_pkts : 1;
+			uint64_t count_mib_bytes : 1;
+
+			uint64_t count_mib_pkts : 1;
+			uint64_t hw_ctx_off : 7;
+
+			uint64_t ctx_id : 16;
+
+			uint64_t orig_pkt_fabs : 1;
+			uint64_t orig_pkt_free : 1;
+			uint64_t pkind : 6;
+
+			uint64_t rsvd0 : 1;
+			uint64_t et_ovrwr : 1;
+			uint64_t pkt_output : 2;
+			uint64_t pkt_format : 1;
+			uint64_t defrag_opt : 2;
+			uint64_t x2p_dst : 1;
+
+			uint64_t ctx_push_size : 7;
+			uint64_t rsvd1 : 1;
+
+			uint64_t ctx_hdr_size : 2;
+			uint64_t aop_valid : 1;
+			uint64_t rsvd2 : 1;
+			uint64_t ctx_size : 4;
+		} s;
+		uint64_t u64;
+	} w0;
+
+	/* Word1 */
+	union {
+		struct {
+			uint64_t orig_pkt_aura : 20;
+			uint64_t rsvd3 : 4;
+			uint64_t orig_pkt_foff : 8;
+			uint64_t cookie : 32;
+		} s;
+		uint64_t u64;
+	} w1;
+
+	/* Word 2 */
+	union {
+		struct {
+			uint64_t valid : 1;
+			uint64_t dir : 1;
+			uint64_t outer_ip_ver : 1;
+			uint64_t rsvd4 : 1;
+			uint64_t ipsec_mode : 1;
+			uint64_t ipsec_protocol : 1;
+			uint64_t aes_key_len : 2;
+
+			uint64_t enc_type : 3;
+			uint64_t life_unit : 1;
+			uint64_t auth_type : 4;
+
+			uint64_t encap_type : 2;
+			uint64_t et_ovrwr_ddr_en : 1;
+			uint64_t esn_en : 1;
+			uint64_t tport_l4_incr_csum : 1;
+			uint64_t ip_hdr_verify : 2;
+			uint64_t rsvd5 : 1;
+
+			uint64_t rsvd6 : 7;
+			uint64_t async_mode : 1;
+
+			uint64_t spi : 32;
+		} s;
+		uint64_t u64;
+	} w2;
+
+	/* Word3 */
+	uint64_t rsvd7;
+
+	/* Word4 - Word7 */
+	uint8_t cipher_key[ROC_CTX_MAX_CKEY_LEN];
+
+	/* Word8 - Word9 */
+	union {
+		struct {
+			uint32_t rsvd8;
+			uint8_t salt[4];
+		} s;
+		uint64_t u64;
+	} w8;
+	uint64_t rsvd9;
+
+	/* Word10 */
+	union {
+		struct {
+			uint64_t rsvd10 : 32;
+			uint64_t udp_src_port : 16;
+			uint64_t udp_dst_port : 16;
+		} s;
+		uint64_t u64;
+	} w10;
+
+	/* Word11 - Word14 */
+	union roc_ot_ipsec_outer_ip_hdr outer_hdr;
+
+	/* Word15 - Word30 */
+	uint8_t hmac_opad_ipad[ROC_CTX_MAX_OPAD_IPAD_LEN];
+
+	/* Word31 - Word100 */
+	struct roc_ot_ipsec_inb_ctx_update_reg ctx;
+};
+
+PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_inb_sa, w1) ==
+		  1 * sizeof(uint64_t));
+PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_inb_sa, w2) ==
+		  2 * sizeof(uint64_t));
+PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_inb_sa, cipher_key) ==
+		  4 * sizeof(uint64_t));
+PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_inb_sa, w8) ==
+		  8 * sizeof(uint64_t));
+PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_inb_sa, w10) ==
+		  10 * sizeof(uint64_t));
+PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_inb_sa, outer_hdr) ==
+		  11 * sizeof(uint64_t));
+PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_inb_sa, hmac_opad_ipad) ==
+		  15 * sizeof(uint64_t));
+PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_inb_sa, ctx) ==
+		  31 * sizeof(uint64_t));
+
+struct roc_ot_ipsec_outb_sa {
+	/* Word0 */
+	union {
+		struct {
+			uint64_t esn_en : 1;
+			uint64_t ip_id : 1;
+			uint64_t rsvd0 : 1;
+			uint64_t hard_life_dec : 1;
+			uint64_t soft_life_dec : 1;
+			uint64_t count_glb_octets : 1;
+			uint64_t count_glb_pkts : 1;
+			uint64_t count_mib_bytes : 1;
+
+			uint64_t count_mib_pkts : 1;
+			uint64_t hw_ctx_off : 7;
+
+			uint64_t rsvd1 : 32;
+
+			uint64_t ctx_push_size : 7;
+			uint64_t rsvd2 : 1;
+
+			uint64_t ctx_hdr_size : 2;
+			uint64_t aop_valid : 1;
+			uint64_t rsvd3 : 1;
+			uint64_t ctx_size : 4;
+		} s;
+		uint64_t u64;
+	} w0;
+
+	/* Word1 */
+	union {
+		struct {
+			uint64_t rsvd4 : 32;
+			uint64_t cookie : 32;
+		} s;
+		uint64_t u64;
+	} w1;
+
+	/* Word 2 */
+	union {
+		struct {
+			uint64_t valid : 1;
+			uint64_t dir : 1;
+			uint64_t outer_ip_ver : 1;
+			uint64_t rsvd5 : 1;
+			uint64_t ipsec_mode : 1;
+			uint64_t ipsec_protocol : 1;
+			uint64_t aes_key_len : 2;
+
+			uint64_t enc_type : 3;
+			uint64_t life_unit : 1;
+			uint64_t auth_type : 4;
+
+			uint64_t encap_type : 2;
+			uint64_t ipv4_df_src_or_ipv6_flw_lbl_src : 1;
+			uint64_t dscp_src : 1;
+			uint64_t iv_src : 2;
+			uint64_t ipid_gen : 1;
+			uint64_t rsvd6 : 1;
+
+			uint64_t rsvd7 : 7;
+			uint64_t async_mode : 1;
+
+			uint64_t spi : 32;
+		} s;
+		uint64_t u64;
+	} w2;
+
+	/* Word3 */
+	uint64_t rsvd8;
+
+	/* Word4 - Word7 */
+	uint8_t cipher_key[ROC_CTX_MAX_CKEY_LEN];
+
+	/* Word8 - Word9 */
+	union roc_ot_ipsec_outb_iv iv;
+
+	/* Word10 */
+	union {
+		struct {
+			uint64_t rsvd9 : 4;
+			uint64_t ipv4_df_or_ipv6_flw_lbl : 20;
+
+			uint64_t dscp : 6;
+			uint64_t rsvd10 : 2;
+
+			uint64_t udp_dst_port : 16;
+
+			uint64_t udp_src_port : 16;
+		} s;
+		uint64_t u64;
+	} w10;
+
+	/* Word11 - Word14 */
+	union roc_ot_ipsec_outer_ip_hdr outer_hdr;
+
+	/* Word15 - Word30 */
+	uint8_t hmac_opad_ipad[ROC_CTX_MAX_OPAD_IPAD_LEN];
+
+	/* Word31 - Word36 */
+	struct roc_ot_ipsec_outb_ctx_update_reg ctx;
+};
+
+PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_outb_sa, w1) ==
+		  1 * sizeof(uint64_t));
+PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_outb_sa, w2) ==
+		  2 * sizeof(uint64_t));
+PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_outb_sa, cipher_key) ==
+		  4 * sizeof(uint64_t));
+PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_outb_sa, iv) ==
+		  8 * sizeof(uint64_t));
+PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_outb_sa, w10) ==
+		  10 * sizeof(uint64_t));
+PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_outb_sa, outer_hdr) ==
+		  11 * sizeof(uint64_t));
+PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_outb_sa, hmac_opad_ipad) ==
+		  15 * sizeof(uint64_t));
+PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_outb_sa, ctx) ==
+		  31 * sizeof(uint64_t));
+
+#endif /* __ROC_IE_OT_H__ */
diff --git a/drivers/common/cnxk/roc_platform.h b/drivers/common/cnxk/roc_platform.h
index daee100..685ec29 100644
--- a/drivers/common/cnxk/roc_platform.h
+++ b/drivers/common/cnxk/roc_platform.h
@@ -49,6 +49,7 @@
 #define PLT_MODEL_MZ_NAME	 "roc_model_mz"
 #define PLT_CACHE_LINE_SIZE      RTE_CACHE_LINE_SIZE
 #define BITMASK_ULL		 GENMASK_ULL
+#define PLT_ALIGN_CEIL		 RTE_ALIGN_CEIL
 
 /** Divide ceil */
 #define PLT_DIV_CEIL(x, y)			\
-- 
2.7.4

[dpdk-dev] [PATCH v2 12/17] common/cnxk: add AE microcode defines

[Anoob Joseph]

From: Kiran Kumar Kokkilagadda <kirankumark@marvell.com>

Microcode AE opcodes support asymmetric operations. Add defines
and structs defined by microcode.

Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Kiran Kumar Kokkilagadda <kirankumark@marvell.com>

---
 drivers/common/cnxk/roc_ae.h  | 56 +++++++++++++++++++++++++++++++++++++++++++
 drivers/common/cnxk/roc_api.h |  1 +
 drivers/common/cnxk/roc_cpt.h |  3 +++
 3 files changed, 60 insertions(+)
 create mode 100644 drivers/common/cnxk/roc_ae.h

diff --git a/drivers/common/cnxk/roc_ae.h b/drivers/common/cnxk/roc_ae.h
new file mode 100644
index 0000000..c549e18
--- /dev/null
+++ b/drivers/common/cnxk/roc_ae.h
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef __ROC_AE_H__
+#define __ROC_AE_H__
+
+/* AE opcodes */
+#define ROC_AE_MAJOR_OP_MODEX	     0x03
+#define ROC_AE_MAJOR_OP_ECDSA	     0x04
+#define ROC_AE_MAJOR_OP_ECC	     0x05
+#define ROC_AE_MINOR_OP_MODEX	     0x01
+#define ROC_AE_MINOR_OP_PKCS_ENC     0x02
+#define ROC_AE_MINOR_OP_PKCS_ENC_CRT 0x03
+#define ROC_AE_MINOR_OP_PKCS_DEC     0x04
+#define ROC_AE_MINOR_OP_PKCS_DEC_CRT 0x05
+#define ROC_AE_MINOR_OP_MODEX_CRT    0x06
+#define ROC_AE_MINOR_OP_ECDSA_SIGN   0x01
+#define ROC_AE_MINOR_OP_ECDSA_VERIFY 0x02
+#define ROC_AE_MINOR_OP_ECC_UMP	     0x03
+
+/**
+ * Enumeration roc_ae_ec_id
+ *
+ * Enumerates supported elliptic curves
+ */
+typedef enum {
+	ROC_AE_EC_ID_P192 = 0,
+	ROC_AE_EC_ID_P224 = 1,
+	ROC_AE_EC_ID_P256 = 2,
+	ROC_AE_EC_ID_P384 = 3,
+	ROC_AE_EC_ID_P521 = 4,
+	ROC_AE_EC_ID_PMAX = 5
+} roc_ae_ec_id;
+
+/* Prime and order fields of built-in elliptic curves */
+struct roc_ae_ec_group {
+	struct {
+		/* P521 maximum length */
+		uint8_t data[66];
+		unsigned int length;
+	} prime;
+
+	struct {
+		/* P521 maximum length */
+		uint8_t data[66];
+		unsigned int length;
+	} order;
+};
+
+struct roc_ae_ec_ctx {
+	/* Prime length defined by microcode for EC operations */
+	uint8_t curveid;
+};
+
+#endif /* __ROC_AE_H__ */
diff --git a/drivers/common/cnxk/roc_api.h b/drivers/common/cnxk/roc_api.h
index d545bb9..546818d 100644
--- a/drivers/common/cnxk/roc_api.h
+++ b/drivers/common/cnxk/roc_api.h
@@ -110,6 +110,7 @@
 #include "roc_cpt.h"
 
 /* CPT microcode */
+#include "roc_ae.h"
 #include "roc_ie_on.h"
 #include "roc_ie_ot.h"
 #include "roc_se.h"
diff --git a/drivers/common/cnxk/roc_cpt.h b/drivers/common/cnxk/roc_cpt.h
index cb2838e..5577fea 100644
--- a/drivers/common/cnxk/roc_cpt.h
+++ b/drivers/common/cnxk/roc_cpt.h
@@ -7,6 +7,9 @@
 
 #include "roc_api.h"
 
+#define ROC_AE_CPT_BLOCK_TYPE1 0
+#define ROC_AE_CPT_BLOCK_TYPE2 1
+
 /* Default engine groups */
 #define ROC_CPT_DFLT_ENG_GRP_SE	   0UL
 #define ROC_CPT_DFLT_ENG_GRP_SE_IE 1UL
-- 
2.7.4

[dpdk-dev] [PATCH v2 13/17] common/cnxk: add lmtline init

[Anoob Joseph]

Add routine to initialize LMTLINE which facilitates instruction
submission to CPT. Add common macros required in the enqueue
operations.

Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Ankur Dwivedi <adwivedi@marvell.com>

---
 drivers/common/cnxk/roc_cpt.c   | 20 ++++++++++++++++++++
 drivers/common/cnxk/roc_cpt.h   | 32 ++++++++++++++++++++++++++++++++
 drivers/common/cnxk/version.map |  1 +
 3 files changed, 53 insertions(+)

diff --git a/drivers/common/cnxk/roc_cpt.c b/drivers/common/cnxk/roc_cpt.c
index 81e8b15..788b28a 100644
--- a/drivers/common/cnxk/roc_cpt.c
+++ b/drivers/common/cnxk/roc_cpt.c
@@ -806,3 +806,23 @@ roc_cpt_iq_disable(struct roc_cpt_lf *lf)
 	lf_inprog.s.eena = 0x0;
 	plt_write64(lf_inprog.u, lf->rbase + CPT_LF_INPROG);
 }
+
+int
+roc_cpt_lmtline_init(struct roc_cpt *roc_cpt, struct roc_cpt_lmtline *lmtline,
+		     int lf_id)
+{
+	struct roc_cpt_lf *lf;
+
+	lf = roc_cpt->lf[lf_id];
+	if (lf == NULL)
+		return -ENOTSUP;
+
+	lmtline->io_addr = lf->io_addr;
+	if (roc_model_is_cn10k())
+		lmtline->io_addr |= ROC_CN10K_CPT_INST_DW_M1 << 4;
+
+	lmtline->fc_addr = lf->fc_addr;
+	lmtline->lmt_base = lf->lmt_base;
+
+	return 0;
+}
diff --git a/drivers/common/cnxk/roc_cpt.h b/drivers/common/cnxk/roc_cpt.h
index 5577fea..8dd2b5e 100644
--- a/drivers/common/cnxk/roc_cpt.h
+++ b/drivers/common/cnxk/roc_cpt.h
@@ -16,6 +16,30 @@
 #define ROC_CPT_DFLT_ENG_GRP_AE	   2UL
 
 #define ROC_CPT_MAX_LFS 64
+#define ROC_CN10K_CPT_INST_DW_M1                                               \
+	((uint64_t)(((sizeof(struct cpt_inst_s) / 16) - 1) & 0x7))
+#define ROC_CN10K_TWO_CPT_INST_DW_M1                                           \
+	((uint64_t)(((sizeof(struct cpt_inst_s) * 2 / 16) - 1) & 0x7))
+
+/* Vector of sizes in the burst of 16 CPT inst except first in 63:19 of
+ * APT_LMT_ARG_S
+ */
+#define ROC_CN10K_CPT_LMT_ARG                                                  \
+	(ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 0) |                            \
+	 ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 1) |                            \
+	 ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 2) |                            \
+	 ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 3) |                            \
+	 ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 4) |                            \
+	 ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 5) |                            \
+	 ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 6) |                            \
+	 ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 7) |                            \
+	 ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 8) |                            \
+	 ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 9) |                            \
+	 ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 10) |                           \
+	 ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 11) |                           \
+	 ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 12) |                           \
+	 ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 13) |                           \
+	 ROC_CN10K_CPT_INST_DW_M1 << (19 + 3 * 14))
 
 /* CPT helper macros */
 #define ROC_CPT_AH_HDR_LEN	 12
@@ -51,6 +75,12 @@
 #define ROC_CPT_TUNNEL_IPV4_HDR_LEN 20
 #define ROC_CPT_TUNNEL_IPV6_HDR_LEN 40
 
+struct roc_cpt_lmtline {
+	uint64_t io_addr;
+	uint64_t *fc_addr;
+	uintptr_t lmt_base;
+};
+
 struct roc_cpt_lf {
 	/* Input parameters */
 	uint16_t lf_id;
@@ -109,5 +139,7 @@ int __roc_api roc_cpt_inline_ipsec_inb_cfg(struct roc_cpt *roc_cpt,
 int __roc_api roc_cpt_afs_print(struct roc_cpt *roc_cpt);
 int __roc_api roc_cpt_lfs_print(struct roc_cpt *roc_cpt);
 void __roc_api roc_cpt_iq_disable(struct roc_cpt_lf *lf);
+int __roc_api roc_cpt_lmtline_init(struct roc_cpt *roc_cpt,
+				   struct roc_cpt_lmtline *lmtline, int lf_id);
 
 #endif /* _ROC_CPT_H_ */
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 59d7d91..e079bc7 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -24,6 +24,7 @@ INTERNAL {
 	roc_cpt_lf_init;
 	roc_cpt_lf_fini;
 	roc_cpt_lfs_print;
+	roc_cpt_lmtline_init;
 	roc_cpt_rxc_time_cfg;
 	roc_error_msg_get;
 	roc_idev_cpt_get;
-- 
2.7.4

[dpdk-dev] [PATCH v2 14/17] common/cnxk: add fpm tables

[Anoob Joseph]

From: Kiran Kumar Kokkilagadda <kirankumark@marvell.com>

Add scalar FPM tables to be used for asymmetric operations.

Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Kiran Kumar Kokkilagadda <kirankumark@marvell.com>

---
 drivers/common/cnxk/meson.build         |    1 +
 drivers/common/cnxk/roc_ae_fpm_tables.c | 1140 +++++++++++++++++++++++++++++++
 drivers/common/cnxk/roc_ae_fpm_tables.h |   13 +
 drivers/common/cnxk/roc_api.h           |    1 +
 drivers/common/cnxk/version.map         |    2 +
 5 files changed, 1157 insertions(+)
 create mode 100644 drivers/common/cnxk/roc_ae_fpm_tables.c
 create mode 100644 drivers/common/cnxk/roc_ae_fpm_tables.h

diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build
index f139e0b..181b58e 100644
--- a/drivers/common/cnxk/meson.build
+++ b/drivers/common/cnxk/meson.build
@@ -11,6 +11,7 @@ endif
 config_flag_fmt = 'RTE_LIBRTE_@0@_COMMON'
 deps = ['eal', 'pci', 'bus_pci', 'mbuf']
 sources = files(
+        'roc_ae_fpm_tables.c',
         'roc_cpt.c',
         'roc_cpt_debug.c',
         'roc_dev.c',
diff --git a/drivers/common/cnxk/roc_ae_fpm_tables.c b/drivers/common/cnxk/roc_ae_fpm_tables.c
new file mode 100644
index 0000000..afb2a50
--- /dev/null
+++ b/drivers/common/cnxk/roc_ae_fpm_tables.c
@@ -0,0 +1,1140 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#include "roc_ae_fpm_tables.h"
+#include "roc_ae.h"
+
+#define AE_FPM_TBL_NAME "ae_fpm_tbl"
+
+/*
+ * AE FPM table sizes Enumeration
+ *
+ * 15 table entries * (X, Y, Z coordinates) * Coordinate Offset
+ * Coordinate Offset depends on elliptic curve as mentioned below,
+ * 6 quadwords for P-192, P-224 and P-256
+ * 7 quadwords for P-384
+ * 9 quadwords for P-521
+ */
+typedef enum {
+	AE_FPM_P192_LEN = 2160,
+	AE_FPM_P224_LEN = 2160,
+	AE_FPM_P256_LEN = 2160,
+	AE_FPM_P384_LEN = 2520,
+	AE_FPM_P521_LEN = 3240
+} ae_fpm_len;
+
+/* FPM table address and length */
+struct ae_fpm_entry {
+	const uint8_t *data;
+	int len;
+};
+
+struct ae_fpm_tbl {
+	uint64_t refcount;
+	uint8_t fpm_tbl[];
+};
+
+/*
+ * Pre-computed ECC FMUL tables needed by cpt microcode
+ * for NIST curves P-192, P-256, P-384, P-521, P-224.
+ */
+
+const uint8_t ae_fpm_tbl_p192[AE_FPM_P192_LEN] = {
+	0xf4, 0xff, 0x0a, 0xfd, 0x82, 0xff, 0x10, 0x12, 0x7c, 0xbf, 0x20, 0xeb,
+	0x43, 0xa1, 0x88, 0x00, 0x18, 0x8d, 0xa8, 0x0e, 0xb0, 0x30, 0x90, 0xf6,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x73, 0xf9, 0x77, 0xa1, 0x1e, 0x79, 0x48, 0x11, 0x63, 0x10, 0x11, 0xed,
+	0x6b, 0x24, 0xcd, 0xd5, 0x07, 0x19, 0x2b, 0x95, 0xff, 0xc8, 0xda, 0x78,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xc3, 0x96, 0x49, 0xc5, 0x5d, 0x7c, 0x48, 0xd8, 0xeb, 0x2c, 0xdf, 0xae,
+	0x5a, 0x92, 0x7c, 0x35, 0x67, 0xe3, 0x0c, 0xbd, 0xcb, 0xa6, 0x71, 0xfb,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x7a, 0x83, 0xce, 0xe1, 0xec, 0xbf, 0xbe, 0x7d, 0xce, 0x32, 0xd0, 0x3c,
+	0x06, 0x30, 0x15, 0x77, 0xa9, 0x35, 0x49, 0xc4, 0x58, 0x10, 0xf5, 0xc3,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x6f, 0x5e, 0xf8, 0x89, 0x66, 0xe3, 0xea, 0xd3, 0xf2, 0x9e, 0x6f, 0xea,
+	0xdf, 0xc9, 0xbf, 0x1a, 0xce, 0x21, 0x6b, 0xb8, 0x45, 0x20, 0x06, 0xe0,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x46, 0xb9, 0x09, 0x2d, 0x92, 0x7b, 0x37, 0x79, 0x1d, 0x0a, 0xeb, 0x4b,
+	0xb5, 0xb8, 0x0a, 0x20, 0xd9, 0x8a, 0x2e, 0xe2, 0x5a, 0xae, 0xc9, 0x58,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xb1, 0x99, 0x63, 0xd8, 0xc0, 0xa1, 0xe3, 0x40, 0x47, 0x30, 0xd4, 0xf4,
+	0x80, 0xd1, 0x09, 0x0b, 0x51, 0xa5, 0x81, 0xd9, 0x18, 0x4a, 0xc7, 0x37,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xec, 0xc5, 0x67, 0x31, 0xe6, 0x99, 0x12, 0xa5, 0x7c, 0xdf, 0xce, 0xa0,
+	0x2f, 0x68, 0x3f, 0x16, 0x5b, 0xd8, 0x1e, 0xe2, 0xe0, 0xbb, 0x9f, 0x6e,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xe4, 0xb1, 0x5a, 0x2d, 0xd4, 0xf4, 0x33, 0x74, 0x07, 0x57, 0xee, 0xa7,
+	0xf2, 0x92, 0xc3, 0x41, 0x0c, 0x73, 0x06, 0x91, 0xd0, 0xf8, 0xdc, 0x24,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xdf, 0x79, 0x78, 0x90, 0xbb, 0xf4, 0x5e, 0x00, 0x00, 0x8a, 0x9e, 0x83,
+	0xe9, 0xde, 0x87, 0x08, 0x31, 0xb2, 0x4c, 0x31, 0x93, 0x54, 0xde, 0x3e,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xcb, 0x5e, 0xc0, 0x43, 0xdd, 0xf6, 0x3a, 0xba, 0xc9, 0x4c, 0x21, 0xd9,
+	0xf8, 0x4f, 0x41, 0xe1, 0xf0, 0xf4, 0x08, 0x83, 0x61, 0xd2, 0x44, 0x16,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xf3, 0x75, 0x85, 0xb0, 0x40, 0x64, 0x95, 0xf7, 0xe5, 0xde, 0x3b, 0x5b,
+	0x16, 0xbc, 0xd0, 0xca, 0x27, 0x85, 0x3c, 0x1a, 0xe1, 0x3e, 0xa4, 0x88,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xd0, 0x74, 0x23, 0x2a, 0x8e, 0x8a, 0xe6, 0x8f, 0x74, 0x9e, 0x52, 0x8e,
+	0xee, 0x29, 0xf7, 0xa9, 0x06, 0x11, 0xde, 0xa3, 0x97, 0x16, 0x46, 0x9f,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x66, 0xb8, 0x67, 0xdd, 0x0d, 0x80, 0x43, 0xcc, 0x6a, 0x65, 0x46, 0x54,
+	0x3a, 0x72, 0x7d, 0xe6, 0xf9, 0x54, 0x60, 0x52, 0x83, 0x38, 0xbd, 0xc9,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xb6, 0xeb, 0x71, 0x93, 0x0c, 0x5d, 0x8f, 0x50, 0x1c, 0x24, 0x5c, 0x02,
+	0xb9, 0x04, 0xb5, 0x96, 0x04, 0xbc, 0x1f, 0x71, 0x95, 0x1f, 0x75, 0x13,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xa4, 0xd0, 0x91, 0x6e, 0xbe, 0x34, 0x80, 0x3d, 0x8b, 0xec, 0x94, 0x8a,
+	0x8c, 0x21, 0x96, 0x2a, 0x15, 0x00, 0x96, 0xe7, 0xfd, 0x69, 0xf8, 0xd0,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xbd, 0x44, 0xff, 0xe8, 0xe7, 0x1a, 0xac, 0x0c, 0x7d, 0x69, 0xa0, 0xb0,
+	0x43, 0x22, 0xd0, 0x65, 0x9f, 0x56, 0xd9, 0x6c, 0xec, 0xa3, 0xba, 0x2a,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xee, 0x59, 0xf0, 0xd1, 0x25, 0xa5, 0x9d, 0xce, 0x83, 0x7d, 0x62, 0xdd,
+	0xc3, 0xf4, 0x57, 0x5a, 0xa4, 0xe0, 0x7f, 0xb3, 0x35, 0xde, 0x73, 0xd9,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xec, 0x76, 0x76, 0x0c, 0x1c, 0xf4, 0x6a, 0xe2, 0xff, 0x54, 0x98, 0x32,
+	0xa3, 0x3d, 0x44, 0xb0, 0xe9, 0x5a, 0xd2, 0x10, 0xf3, 0x18, 0x5c, 0x11,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x27, 0x3e, 0x5e, 0xc5, 0x38, 0xed, 0x37, 0x2e, 0x51, 0xd3, 0x91, 0x36,
+	0xb0, 0xab, 0x11, 0x69, 0xa5, 0xea, 0x86, 0xf6, 0x8f, 0x3a, 0x27, 0xc8,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x29, 0x12, 0x37, 0xea, 0x74, 0xd2, 0xd7, 0xd5, 0x95, 0x36, 0x36, 0xee,
+	0x56, 0x33, 0x8e, 0x9b, 0x0d, 0xa6, 0x5e, 0x86, 0x28, 0x5c, 0x12, 0x0c,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x13, 0x02, 0xf0, 0x4c, 0xf1, 0x3c, 0x32, 0x33, 0xfc, 0x89, 0x8a, 0xb9,
+	0x97, 0x83, 0x91, 0xb2, 0x26, 0xd6, 0x5c, 0x2e, 0x3a, 0xa0, 0x62, 0x72,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xd5, 0x09, 0x47, 0xa8, 0x18, 0xc5, 0xef, 0xe6, 0x45, 0xdb, 0x23, 0xae,
+	0xfe, 0x11, 0x3c, 0x6c, 0x91, 0xf1, 0x99, 0xf2, 0xe5, 0xbb, 0xe8, 0x6d,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x37, 0x68, 0x81, 0xb6, 0x60, 0xfe, 0xc0, 0x64, 0x38, 0x73, 0x43, 0xe9,
+	0x47, 0x5d, 0xae, 0xa4, 0xec, 0xcd, 0x57, 0xe8, 0xac, 0x8d, 0x8a, 0x19,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xc9, 0xfe, 0xf5, 0xb9, 0x5b, 0x51, 0x02, 0x28, 0x37, 0x4c, 0x0a, 0x4c,
+	0x19, 0x2e, 0xbc, 0xd6, 0x22, 0x98, 0xf2, 0x04, 0xce, 0x6a, 0x83, 0xf9,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x46, 0xe4, 0xb8, 0x20, 0xf4, 0xc5, 0x74, 0xd0, 0x06, 0xd5, 0x86, 0x44,
+	0xef, 0xeb, 0x2c, 0xc0, 0xe7, 0x13, 0xa4, 0x00, 0x10, 0xc3, 0xc9, 0x49,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x61, 0x78, 0xcb, 0x0e, 0x2d, 0x64, 0xee, 0xdf, 0x27, 0xaf, 0x7d, 0x5e,
+	0xb8, 0x5e, 0x1f, 0x99, 0xd8, 0x73, 0xce, 0xd7, 0x6c, 0xb7, 0xbe, 0x1f,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xef, 0xc9, 0x12, 0x9c, 0x52, 0xa6, 0x7f, 0x9c, 0xa3, 0xd7, 0xb9, 0x57,
+	0x60, 0x04, 0xd9, 0xad, 0xfc, 0x59, 0x98, 0x08, 0xdc, 0x41, 0xf8, 0xe2,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xbb, 0x6c, 0x6b, 0x59, 0x7f, 0xdf, 0x92, 0x8a, 0xad, 0x16, 0x7e, 0xf0,
+	0xd7, 0xf9, 0x3b, 0xf4, 0xfa, 0xa9, 0xe4, 0x32, 0x15, 0x4e, 0x06, 0x1c,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x0c, 0x3d, 0x0d, 0x63, 0xd5, 0x2c, 0x8f, 0x3f, 0x61, 0x01, 0xb2, 0xbe,
+	0xd5, 0xf7, 0xe0, 0x8f, 0xd8, 0x77, 0xcd, 0xdd, 0xd6, 0xae, 0x3c, 0xf3,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01
+};
+
+const uint8_t ae_fpm_tbl_p224[AE_FPM_P224_LEN] = {
+	0x34, 0x32, 0x80, 0xd6, 0x11, 0x5c, 0x1d, 0x21, 0x4a, 0x03, 0xc1, 0xd3,
+	0x56, 0xc2, 0x11, 0x22, 0x6b, 0xb4, 0xbf, 0x7f, 0x32, 0x13, 0x90, 0xb9,
+	0x00, 0x00, 0x00, 0x00, 0xb7, 0x0e, 0x0c, 0xbd, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x44, 0xd5, 0x81, 0x99, 0x85, 0x00, 0x7e, 0x34, 0xcd, 0x43, 0x75, 0xa0,
+	0x5a, 0x07, 0x47, 0x64, 0xb5, 0xf7, 0x23, 0xfb, 0x4c, 0x22, 0xdf, 0xe6,
+	0x00, 0x00, 0x00, 0x00, 0xbd, 0x37, 0x63, 0x88, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xc8, 0xae, 0x4d, 0x94, 0xff, 0x48, 0xdb, 0xc5, 0xb5, 0xc8, 0x8b, 0x66,
+	0x32, 0xc8, 0x7a, 0x44, 0x66, 0xc7, 0x27, 0x87, 0x2b, 0x8d, 0x08, 0x1c,
+	0x00, 0x00, 0x00, 0x00, 0x5b, 0xe5, 0xde, 0x8b, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xc6, 0xf8, 0x1e, 0x08, 0x47, 0xfb, 0x64, 0xdb, 0xc8, 0xe3, 0x75, 0x3e,
+	0x9d, 0x5a, 0x58, 0x31, 0xa2, 0x13, 0x38, 0x8c, 0x65, 0x8a, 0x02, 0xae,
+	0x00, 0x00, 0x00, 0x00, 0xde, 0x52, 0x6c, 0x0d, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xee, 0x8f, 0x93, 0x0d, 0x2b, 0x30, 0x9e, 0xe8, 0xb6, 0x78, 0xea, 0x1a,
+	0x0f, 0x59, 0x7e, 0x02, 0x14, 0x74, 0x52, 0x56, 0x6c, 0x25, 0x7d, 0x3e,
+	0x00, 0x00, 0x00, 0x00, 0x09, 0xbe, 0x54, 0xb7, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xf6, 0x12, 0x1f, 0xdd, 0x96, 0xa2, 0x05, 0xda, 0x12, 0xa8, 0xe4, 0xf9,
+	0x98, 0x15, 0x8e, 0xe1, 0x1b, 0x1d, 0x05, 0x44, 0x47, 0xf2, 0xc3, 0x3a,
+	0x00, 0x00, 0x00, 0x00, 0x32, 0xf7, 0x1c, 0x32, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x26, 0x73, 0x99, 0x28, 0x0e, 0x4e, 0x09, 0x58, 0x79, 0xab, 0xae, 0x5c,
+	0xa8, 0xeb, 0x9c, 0x0b, 0xe9, 0xa8, 0xac, 0xf0, 0x74, 0x0e, 0xa3, 0x35,
+	0x00, 0x00, 0x00, 0x00, 0x0f, 0xb6, 0xce, 0x42, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x92, 0x09, 0xdc, 0xfe, 0x40, 0x85, 0x7c, 0x64, 0xa2, 0x3f, 0xe4, 0x34,
+	0x50, 0xb4, 0x25, 0x87, 0x2a, 0x6f, 0x38, 0x62, 0xb6, 0xfe, 0x44, 0xb1,
+	0x00, 0x00, 0x00, 0x00, 0x9e, 0xd1, 0x3b, 0x1b, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xf9, 0xfb, 0xf4, 0x91, 0x9a, 0x5f, 0x1c, 0x42, 0x56, 0x8b, 0xc4, 0x34,
+	0x8a, 0x69, 0xdd, 0x65, 0x3d, 0x01, 0x11, 0x6e, 0x47, 0x78, 0xdf, 0x49,
+	0x00, 0x00, 0x00, 0x00, 0x56, 0x65, 0xff, 0xd2, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xca, 0x4b, 0x80, 0x12, 0xe5, 0x3d, 0x3f, 0xb4, 0xe7, 0x61, 0x44, 0x25,
+	0x89, 0xec, 0x86, 0x76, 0x1f, 0xde, 0x69, 0x6f, 0xcb, 0x2b, 0xe1, 0x15,
+	0x00, 0x00, 0x00, 0x00, 0xc5, 0xf0, 0x98, 0xeb, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xe6, 0xf2, 0x88, 0xf1, 0x39, 0xb0, 0xa5, 0xad, 0x0c, 0x76, 0x16, 0x85,
+	0x58, 0x72, 0xd0, 0x94, 0x8a, 0xbc, 0x69, 0xb6, 0x6d, 0x7a, 0xc7, 0xfb,
+	0x00, 0x00, 0x00, 0x00, 0x64, 0xe1, 0x68, 0x02, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xe1, 0x94, 0x7b, 0x17, 0x96, 0xa9, 0x76, 0xcf, 0x67, 0x78, 0x38, 0x8a,
+	0xd9, 0xb7, 0x68, 0xd7, 0x75, 0x39, 0xb7, 0x24, 0x17, 0x76, 0xa8, 0x39,
+	0x00, 0x00, 0x00, 0x00, 0xb4, 0xdb, 0x5a, 0x94, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x86, 0x5a, 0x09, 0xbe, 0xdf, 0x5b, 0x10, 0x74, 0x74, 0xc0, 0xce, 0xf5,
+	0x95, 0xab, 0xef, 0xf7, 0xba, 0x69, 0x9c, 0xe4, 0x14, 0xb3, 0x90, 0xb1,
+	0x00, 0x00, 0x00, 0x00, 0xc0, 0xca, 0x10, 0xcb, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x55, 0x87, 0xbb, 0x19, 0x41, 0x02, 0x67, 0xde, 0xa7, 0x71, 0xb8, 0xce,
+	0xa6, 0x3f, 0xcc, 0x78, 0xbc, 0xa5, 0x91, 0x7d, 0x0e, 0x8d, 0x16, 0x65,
+	0x00, 0x00, 0x00, 0x00, 0x63, 0x9e, 0x9e, 0x20, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xe8, 0xb7, 0x37, 0x97, 0x4e, 0x1b, 0xfb, 0x82, 0x16, 0x71, 0x58, 0x39,
+	0x55, 0xb6, 0x32, 0xb8, 0xf6, 0x75, 0x2f, 0xdd, 0x34, 0x7a, 0x0d, 0x7b,
+	0x00, 0x00, 0x00, 0x00, 0xff, 0x24, 0xb5, 0x67, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xea, 0xce, 0x1f, 0x14, 0x00, 0xe2, 0xe0, 0x16, 0x71, 0xe5, 0x9b, 0x8c,
+	0x60, 0x8d, 0x20, 0x97, 0x2b, 0x07, 0xec, 0x89, 0x89, 0x37, 0x5d, 0x09,
+	0x00, 0x00, 0x00, 0x00, 0xc3, 0xe2, 0x8c, 0xdc, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x9a, 0x88, 0x5f, 0xdf, 0xf5, 0x12, 0x07, 0xbf, 0xc5, 0xbd, 0xd8, 0x15,
+	0x01, 0x55, 0x75, 0x02, 0xf1, 0x96, 0x50, 0x03, 0x6b, 0xbd, 0xd0, 0x72,
+	0x00, 0x00, 0x00, 0x00, 0xda, 0x9b, 0x7e, 0x0c, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xf2, 0xa7, 0x4c, 0xce, 0x47, 0xb9, 0x7d, 0x42, 0xf7, 0xb5, 0x5d, 0x63,
+	0x28, 0xf5, 0xde, 0x75, 0x06, 0x13, 0xe9, 0x5d, 0x9b, 0x48, 0x88, 0x67,
+	0x00, 0x00, 0x00, 0x00, 0xd6, 0x05, 0x07, 0x13, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xa4, 0xee, 0x4e, 0xe7, 0xb4, 0x4a, 0xda, 0x48, 0xe3, 0x67, 0x5f, 0xf9,
+	0x15, 0xda, 0x1a, 0x27, 0x33, 0x6b, 0x97, 0x6a, 0x82, 0x0d, 0xa0, 0x86,
+	0x00, 0x00, 0x00, 0x00, 0x5b, 0x6e, 0x9f, 0xfd, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xf5, 0x2c, 0xd8, 0x87, 0x2f, 0xf4, 0xa8, 0x85, 0x53, 0x29, 0x86, 0xf1,
+	0xb9, 0x1a, 0x28, 0xdc, 0xaf, 0x35, 0x40, 0xdd, 0x75, 0xbf, 0x86, 0x56,
+	0x00, 0x00, 0x00, 0x00, 0xce, 0x4f, 0x78, 0xa9, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x4d, 0x51, 0xfa, 0xb9, 0xe8, 0x49, 0xeb, 0x79, 0xd4, 0xc3, 0x0d, 0x04,
+	0xdd, 0xf6, 0xb1, 0xcd, 0x6d, 0x51, 0xe5, 0x58, 0x06, 0x2a, 0x7e, 0x65,
+	0x00, 0x00, 0x00, 0x00, 0xe6, 0xe4, 0xf0, 0x9a, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xe0, 0x85, 0xf1, 0x4f, 0xe7, 0x07, 0x60, 0xb5, 0x45, 0x7a, 0xc8, 0x3d,
+	0xf3, 0x26, 0xd8, 0xb0, 0xc7, 0x94, 0x33, 0x72, 0x7e, 0xef, 0x87, 0x70,
+	0x00, 0x00, 0x00, 0x00, 0x74, 0x6d, 0x83, 0xb0, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x7a, 0x24, 0xee, 0x7e, 0x21, 0x7b, 0x0a, 0x33, 0x4e, 0xa1, 0x1e, 0x5c,
+	0xca, 0x30, 0xf9, 0x68, 0xc2, 0xc4, 0x7d, 0x0a, 0xa0, 0xc7, 0xbe, 0xeb,
+	0x00, 0x00, 0x00, 0x00, 0xca, 0x62, 0xa6, 0x8b, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x5c, 0x26, 0x7c, 0x9c, 0xfb, 0xe5, 0x6a, 0x33, 0x89, 0x37, 0x74, 0x21,
+	0x13, 0x71, 0x46, 0x6b, 0x60, 0xd0, 0x38, 0xc4, 0x90, 0xef, 0x7d, 0xec,
+	0x00, 0x00, 0x00, 0x00, 0x27, 0xde, 0xcf, 0x82, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x23, 0x14, 0xf5, 0x42, 0xbe, 0x9e, 0x07, 0x9c, 0x4a, 0x60, 0x56, 0x3b,
+	0xcf, 0xe2, 0x06, 0x81, 0xb0, 0xc0, 0x46, 0x49, 0xfb, 0x97, 0x61, 0x5a,
+	0x00, 0x00, 0x00, 0x00, 0x2f, 0xa4, 0x2d, 0x2b, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x86, 0xe5, 0x99, 0xb4, 0xcf, 0x64, 0x05, 0x25, 0xa3, 0x44, 0xe4, 0x18,
+	0x5f, 0x72, 0x58, 0x47, 0x7f, 0xbd, 0x84, 0xd7, 0x0a, 0x38, 0xa0, 0xd4,
+	0x00, 0x00, 0x00, 0x00, 0x11, 0x8d, 0x15, 0xd5, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xe8, 0x5b, 0x13, 0xf0, 0x09, 0xc6, 0x14, 0x58, 0xc4, 0xf3, 0x1b, 0x3d,
+	0x17, 0x0f, 0x1c, 0xfa, 0x7d, 0x61, 0x7e, 0x7e, 0x9c, 0xea, 0x52, 0x0a,
+	0x00, 0x00, 0x00, 0x00, 0x89, 0x05, 0xdb, 0xb7, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x26, 0xf8, 0xab, 0x68, 0xb4, 0x27, 0x56, 0x1d, 0x04, 0xed, 0x8c, 0x65,
+	0xfd, 0xd1, 0x62, 0x2e, 0x80, 0x4c, 0x4a, 0x1d, 0x67, 0x90, 0x50, 0xed,
+	0x00, 0x00, 0x00, 0x00, 0x3b, 0x02, 0x2a, 0x4b, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x11, 0xe9, 0x36, 0x25, 0x8d, 0x97, 0x84, 0xea, 0xe9, 0x50, 0x4a, 0x27,
+	0x66, 0x6e, 0x0c, 0xd2, 0xce, 0x40, 0xfe, 0xfb, 0xf2, 0xc6, 0x53, 0xb4,
+	0x00, 0x00, 0x00, 0x00, 0xb6, 0x32, 0x22, 0x76, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xfc, 0x88, 0xcf, 0x76, 0x3c, 0x0b, 0x0d, 0x76, 0xb2, 0xc3, 0xc7, 0x8c,
+	0x8c, 0x53, 0x5f, 0x4c, 0xba, 0x0d, 0x13, 0xdb, 0x7b, 0xac, 0xf0, 0x19,
+	0x00, 0x00, 0x00, 0x00, 0x7e, 0x11, 0x95, 0x29, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01
+};
+
+const uint8_t ae_fpm_tbl_p256[AE_FPM_P256_LEN] = {
+	0xf4, 0xa1, 0x39, 0x45, 0xd8, 0x98, 0xc2, 0x96, 0x77, 0x03, 0x7d, 0x81,
+	0x2d, 0xeb, 0x33, 0xa0, 0xf8, 0xbc, 0xe6, 0xe5, 0x63, 0xa4, 0x40, 0xf2,
+	0x6b, 0x17, 0xd1, 0xf2, 0xe1, 0x2c, 0x42, 0x47, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xcb, 0xb6, 0x40, 0x68, 0x37, 0xbf, 0x51, 0xf5, 0x2b, 0xce, 0x33, 0x57,
+	0x6b, 0x31, 0x5e, 0xce, 0x8e, 0xe7, 0xeb, 0x4a, 0x7c, 0x0f, 0x9e, 0x16,
+	0x4f, 0xe3, 0x42, 0xe2, 0xfe, 0x1a, 0x7f, 0x9b, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x90, 0xe7, 0x5c, 0xb4, 0x8e, 0x14, 0xdb, 0x63, 0x29, 0x49, 0x3b, 0xaa,
+	0xad, 0x65, 0x1f, 0x7e, 0x84, 0x92, 0x59, 0x2e, 0x32, 0x6e, 0x25, 0xde,
+	0x0f, 0xa8, 0x22, 0xbc, 0x28, 0x11, 0xaa, 0xa5, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xe4, 0x11, 0x24, 0x54, 0x5f, 0x46, 0x2e, 0xe7, 0x34, 0xb1, 0xa6, 0x50,
+	0x50, 0xfe, 0x82, 0xf5, 0x6f, 0x4a, 0xd4, 0xbc, 0xb3, 0xdf, 0x18, 0x8b,
+	0xbf, 0xf4, 0x4a, 0xe8, 0xf5, 0xdb, 0xa8, 0x0d, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x93, 0x39, 0x1c, 0xe2, 0x09, 0x79, 0x92, 0xaf, 0xe9, 0x6c, 0x98, 0xfd,
+	0x0d, 0x35, 0xf1, 0xfa, 0xb2, 0x57, 0xc0, 0xde, 0x95, 0xe0, 0x27, 0x89,
+	0x30, 0x0a, 0x4b, 0xbc, 0x89, 0xd6, 0x72, 0x6f, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xaa, 0x54, 0xa2, 0x91, 0xc0, 0x81, 0x27, 0xa0, 0x5b, 0xb1, 0xee, 0xad,
+	0xa9, 0xd8, 0x06, 0xa5, 0x7f, 0x1d, 0xdb, 0x25, 0xff, 0x1e, 0x3c, 0x6f,
+	0x72, 0xaa, 0xc7, 0xe0, 0xd0, 0x9b, 0x46, 0x44, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x57, 0xc8, 0x4f, 0xc9, 0xd7, 0x89, 0xbd, 0x85, 0xfc, 0x35, 0xff, 0x7d,
+	0xc2, 0x97, 0xea, 0xc3, 0xfb, 0x98, 0x2f, 0xd5, 0x88, 0xc6, 0x76, 0x6e,
+	0x44, 0x7d, 0x73, 0x9b, 0xee, 0xdb, 0x5e, 0x67, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x0c, 0x7e, 0x33, 0xc9, 0x72, 0xe2, 0x5b, 0x32, 0x3d, 0x34, 0x9b, 0x95,
+	0xa7, 0xfa, 0xe5, 0x00, 0xe1, 0x2e, 0x9d, 0x95, 0x3a, 0x4a, 0xaf, 0xf7,
+	0x2d, 0x48, 0x25, 0xab, 0x83, 0x41, 0x31, 0xee, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x13, 0x94, 0x9c, 0x93, 0x2a, 0x1d, 0x36, 0x7f, 0xef, 0x7f, 0xbd, 0x2b,
+	0x1a, 0x0a, 0x11, 0xb7, 0xdd, 0xc6, 0x06, 0x8b, 0xb9, 0x1d, 0xfc, 0x60,
+	0xef, 0x95, 0x19, 0x32, 0x8a, 0x9c, 0x72, 0xff, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x19, 0x60, 0x35, 0xa7, 0x73, 0x76, 0xd8, 0xa8, 0x23, 0x18, 0x3b, 0x08,
+	0x95, 0xca, 0x17, 0x40, 0xc1, 0xee, 0x98, 0x07, 0x02, 0x2c, 0x21, 0x9c,
+	0x61, 0x1e, 0x9f, 0xc3, 0x7d, 0xbb, 0x2c, 0x9b, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xca, 0xe2, 0xb1, 0x92, 0x0b, 0x57, 0xf4, 0xbc, 0x29, 0x36, 0xdf, 0x5e,
+	0xc6, 0xc9, 0xbc, 0x36, 0x7d, 0xea, 0x64, 0x82, 0xe1, 0x12, 0x38, 0xbf,
+	0x55, 0x06, 0x63, 0x79, 0x7b, 0x51, 0xf5, 0xd8, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x44, 0xff, 0xe2, 0x16, 0x34, 0x8a, 0x96, 0x4c, 0x9f, 0xb3, 0xd5, 0x76,
+	0xdb, 0xde, 0xfb, 0xe1, 0x0a, 0xfa, 0x40, 0x01, 0x8d, 0x9d, 0x50, 0xe5,
+	0x15, 0x71, 0x64, 0x84, 0x8a, 0xec, 0xb8, 0x51, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xe4, 0x8e, 0xca, 0xff, 0xfc, 0x5c, 0xde, 0x01, 0x7c, 0xcd, 0x84, 0xe7,
+	0x0d, 0x71, 0x5f, 0x26, 0xa2, 0xe8, 0xf4, 0x83, 0xf4, 0x3e, 0x43, 0x91,
+	0xeb, 0x5d, 0x77, 0x45, 0xb2, 0x11, 0x41, 0xea, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xca, 0xc9, 0x17, 0xe2, 0x73, 0x1a, 0x34, 0x79, 0x85, 0xf2, 0x2c, 0xfe,
+	0x28, 0x44, 0xb6, 0x45, 0x09, 0x90, 0xe6, 0xa1, 0x58, 0x00, 0x6c, 0xee,
+	0xea, 0xfd, 0x72, 0xeb, 0xdb, 0xec, 0xc1, 0x7b, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x6c, 0xf2, 0x0f, 0xfb, 0x31, 0x37, 0x28, 0xbe, 0x96, 0x43, 0x95, 0x91,
+	0xa3, 0xc6, 0xb9, 0x4a, 0x27, 0x36, 0xff, 0x83, 0x44, 0x31, 0x5f, 0xc5,
+	0xa6, 0xd3, 0x96, 0x77, 0xa7, 0x84, 0x92, 0x76, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xf2, 0xba, 0xb8, 0x33, 0xc3, 0x57, 0xf5, 0xf4, 0x82, 0x4a, 0x92, 0x0c,
+	0x22, 0x84, 0x05, 0x9b, 0x66, 0xb8, 0xba, 0xbd, 0x2d, 0x27, 0xec, 0xdf,
+	0x67, 0x4f, 0x84, 0x74, 0x9b, 0x0b, 0x88, 0x16, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x2d, 0xf4, 0x8c, 0x04, 0x67, 0x7c, 0x8a, 0x3e, 0x74, 0xe0, 0x2f, 0x08,
+	0x02, 0x03, 0xa5, 0x6b, 0x31, 0x85, 0x5f, 0x7d, 0xb8, 0xc7, 0xfe, 0xdb,
+	0x4e, 0x76, 0x9e, 0x76, 0x72, 0xc9, 0xdd, 0xad, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xa4, 0xc3, 0x61, 0x65, 0xb8, 0x24, 0xbb, 0xb0, 0xfb, 0x9a, 0xe1, 0x6f,
+	0x3b, 0x91, 0x22, 0xa5, 0x1e, 0xc0, 0x05, 0x72, 0x06, 0x94, 0x72, 0x81,
+	0x42, 0xb9, 0x90, 0x82, 0xde, 0x83, 0x06, 0x63, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x6e, 0xf9, 0x51, 0x50, 0xdd, 0xa8, 0x68, 0xb9, 0xd1, 0xf8, 0x9e, 0x79,
+	0x9c, 0x0c, 0xe1, 0x31, 0x7f, 0xdc, 0x1c, 0xa0, 0x08, 0xa1, 0xc4, 0x78,
+	0x78, 0x87, 0x8e, 0xf6, 0x1c, 0x6c, 0xe0, 0x4d, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x9c, 0x62, 0xb9, 0x12, 0x1f, 0xe0, 0xd9, 0x76, 0x6a, 0xce, 0x57, 0x0e,
+	0xbd, 0xe0, 0x8d, 0x4f, 0xde, 0x53, 0x14, 0x2c, 0x12, 0x30, 0x9d, 0xef,
+	0xb6, 0xcb, 0x3f, 0x5d, 0x7b, 0x72, 0xc3, 0x21, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x7f, 0x99, 0x1e, 0xd2, 0xc3, 0x1a, 0x35, 0x73, 0x5b, 0x82, 0xdd, 0x5b,
+	0xd5, 0x4f, 0xb4, 0x96, 0x59, 0x5c, 0x52, 0x20, 0x81, 0x2f, 0xfc, 0xae,
+	0x0c, 0x88, 0xbc, 0x4d, 0x71, 0x6b, 0x12, 0x87, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x3a, 0x57, 0xbf, 0x63, 0x5f, 0x48, 0xac, 0xa8, 0x7c, 0x81, 0x81, 0xf4,
+	0xdf, 0x25, 0x64, 0xf3, 0x18, 0xd1, 0xb5, 0xb3, 0x9c, 0x04, 0xe6, 0xaa,
+	0xdd, 0x5d, 0xde, 0xa3, 0xf3, 0x90, 0x1d, 0xc6, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xe9, 0x6a, 0x79, 0xfb, 0x3e, 0x72, 0xad, 0x0c, 0x43, 0xa0, 0xa2, 0x8c,
+	0x42, 0xba, 0x79, 0x2f, 0xef, 0xe0, 0xa4, 0x23, 0x08, 0x3e, 0x49, 0xf3,
+	0x68, 0xf3, 0x44, 0xaf, 0x6b, 0x31, 0x74, 0x66, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xcd, 0xfe, 0x17, 0xdb, 0x3f, 0xb2, 0x4d, 0x4a, 0x66, 0x8b, 0xfc, 0x22,
+	0x71, 0xf5, 0xc6, 0x26, 0x60, 0x4e, 0xd9, 0x3c, 0x24, 0xd6, 0x7f, 0xf3,
+	0x31, 0xb9, 0xc4, 0x05, 0xf8, 0x54, 0x0a, 0x20, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xd3, 0x6b, 0x47, 0x89, 0xa2, 0x58, 0x2e, 0x7f, 0x0d, 0x1a, 0x10, 0x14,
+	0x4e, 0xc3, 0x9c, 0x28, 0x66, 0x3c, 0x62, 0xc3, 0xed, 0xba, 0xd7, 0xa0,
+	0x40, 0x52, 0xbf, 0x4b, 0x6f, 0x46, 0x1d, 0xb9, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x23, 0x5a, 0x27, 0xc3, 0x18, 0x8d, 0x25, 0xeb, 0xe7, 0x24, 0xf3, 0x39,
+	0x99, 0xbf, 0xcc, 0x5b, 0x86, 0x2b, 0xe6, 0xbd, 0x71, 0xd7, 0x0c, 0xc8,
+	0xfe, 0xcf, 0x4d, 0x51, 0x90, 0xb0, 0xfc, 0x61, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x74, 0x34, 0x6c, 0x10, 0xa1, 0xd4, 0xcf, 0xac, 0xaf, 0xdf, 0x5c, 0xc0,
+	0x85, 0x26, 0xa7, 0xa4, 0x12, 0x32, 0x02, 0xa8, 0xf6, 0x2b, 0xff, 0x7a,
+	0x1e, 0xdd, 0xba, 0xe2, 0xc8, 0x02, 0xe4, 0x1a, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x8f, 0xa0, 0xaf, 0x2d, 0xd6, 0x03, 0xf8, 0x44, 0x36, 0xe0, 0x6b, 0x7e,
+	0x4c, 0x70, 0x19, 0x17, 0x0c, 0x45, 0xf4, 0x52, 0x73, 0xdb, 0x33, 0xa0,
+	0x43, 0x10, 0x4d, 0x86, 0x56, 0x0e, 0xbc, 0xfc, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x96, 0x15, 0xb5, 0x11, 0x0d, 0x1d, 0x78, 0xe5, 0x66, 0xb0, 0xde, 0x32,
+	0x25, 0xc4, 0x74, 0x4b, 0x0a, 0x4a, 0x46, 0xfb, 0x6a, 0xaf, 0x36, 0x3a,
+	0xb4, 0x8e, 0x26, 0xb4, 0x84, 0xf7, 0xa2, 0x1c, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x06, 0xeb, 0xb0, 0xf6, 0x21, 0xa0, 0x1b, 0x2d, 0xc0, 0x04, 0xe4, 0x04,
+	0x8b, 0x7b, 0x0f, 0x98, 0x64, 0x13, 0x1b, 0xcd, 0xfe, 0xd6, 0xf6, 0x68,
+	0xfa, 0xc0, 0x15, 0x40, 0x4d, 0x4d, 0x3d, 0xab, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01
+};
+
+const uint8_t ae_fpm_tbl_p384[AE_FPM_P384_LEN] = {
+	0x3a, 0x54, 0x5e, 0x38, 0x72, 0x76, 0x0a, 0xb7, 0x55, 0x02, 0xf2, 0x5d,
+	0xbf, 0x55, 0x29, 0x6c, 0x59, 0xf7, 0x41, 0xe0, 0x82, 0x54, 0x2a, 0x38,
+	0x6e, 0x1d, 0x3b, 0x62, 0x8b, 0xa7, 0x9b, 0x98, 0x8e, 0xb1, 0xc7, 0x1e,
+	0xf3, 0x20, 0xad, 0x74, 0xaa, 0x87, 0xca, 0x22, 0xbe, 0x8b, 0x05, 0x37,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7a, 0x43, 0x1d, 0x7c,
+	0x90, 0xea, 0x0e, 0x5f, 0x0a, 0x60, 0xb1, 0xce, 0x1d, 0x7e, 0x81, 0x9d,
+	0xe9, 0xda, 0x31, 0x13, 0xb5, 0xf0, 0xb8, 0xc0, 0xf8, 0xf4, 0x1d, 0xbd,
+	0x28, 0x9a, 0x14, 0x7c, 0x5d, 0x9e, 0x98, 0xbf, 0x92, 0x92, 0xdc, 0x29,
+	0x36, 0x17, 0xde, 0x4a, 0x96, 0x26, 0x2c, 0x6f, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x39, 0xc1, 0xb3, 0x28, 0xd8, 0xee, 0x21, 0xc9, 0x2c, 0x3e, 0x0c, 0x91,
+	0x55, 0x87, 0x17, 0xdb, 0x4b, 0x58, 0x80, 0x8b, 0x3f, 0x86, 0x86, 0xa9,
+	0x43, 0x60, 0x39, 0x09, 0x18, 0x14, 0x1b, 0x1a, 0xd6, 0xe9, 0x8b, 0x0d,
+	0x37, 0xca, 0x7a, 0xbc, 0xf5, 0x32, 0x38, 0x9a, 0x06, 0x0c, 0xbd, 0x1b,
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x10, 0xb0, 0x56, 0x58, 0x5f, 0x86, 0x3b, 0xbd, 0xe9, 0x2c, 0xdc, 0x5a,
+	0xb4, 0x83, 0x28, 0x3d, 0xeb, 0xb3, 0x12, 0x09, 0xdc, 0x7c, 0x42, 0x1d,
+	0x3a, 0xfc, 0xbd, 0x79, 0x6d, 0x01, 0xa5, 0xa8, 0xe2, 0xb0, 0x67, 0xca,
+	0xa0, 0x8b, 0x6a, 0x51, 0x02, 0x6e, 0x0d, 0xc2, 0xe8, 0xcb, 0x7a, 0xeb,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xd8, 0xc3, 0x50, 0x29,
+	0x02, 0xdd, 0xe1, 0x8a, 0x64, 0xc1, 0x5f, 0xac, 0xd8, 0xc6, 0xcf, 0x36,
+	0x17, 0xea, 0x27, 0x01, 0x10, 0x78, 0x1e, 0x45, 0xd6, 0x8d, 0x1f, 0xfc,
+	0x1f, 0x34, 0x43, 0xd8, 0x4b, 0xe2, 0x56, 0x37, 0x8c, 0x74, 0x61, 0xa5,
+	0xae, 0x88, 0x66, 0xba, 0xd8, 0xef, 0x24, 0xe1, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xac, 0x3a, 0x78, 0xd0, 0xd2, 0x65, 0xa9, 0x1c, 0x1a, 0x29, 0xf8, 0xef,
+	0x6c, 0x8f, 0x83, 0xd3, 0xef, 0x98, 0xfd, 0xde, 0x8f, 0xd8, 0xd8, 0x17,
+	0xdf, 0x45, 0x9e, 0xa1, 0xc4, 0x2b, 0xf7, 0x48, 0x14, 0xda, 0xfc, 0x39,
+	0x81, 0xa7, 0x3d, 0xc7, 0xb0, 0x3d, 0xfa, 0x54, 0xc5, 0x2a, 0xfa, 0x2d,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xcc, 0x40, 0x6f, 0x6e,
+	0x6c, 0x0d, 0x2c, 0xe7, 0xcd, 0x12, 0x0b, 0x2b, 0x41, 0xfd, 0x72, 0xca,
+	0xef, 0x5d, 0x90, 0x06, 0x78, 0xf6, 0x02, 0xdd, 0xf5, 0xf8, 0xa2, 0xd1,
+	0x8a, 0xcc, 0xf2, 0x29, 0xaa, 0xfd, 0x1f, 0xcf, 0xce, 0x6d, 0x90, 0x8a,
+	0x2c, 0xe2, 0x88, 0x5a, 0x0e, 0x6d, 0x85, 0xf2, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x89, 0x10, 0x9a, 0x0e, 0xc6, 0x26, 0x66, 0xde, 0xc8, 0xc1, 0x2e, 0x75,
+	0x7f, 0xfc, 0xd0, 0x1e, 0xa8, 0x20, 0x61, 0x69, 0xc4, 0x8b, 0x5a, 0xb0,
+	0x4b, 0xc2, 0xfd, 0xcf, 0xf9, 0x83, 0xac, 0x6c, 0x59, 0xcf, 0xca, 0x71,
+	0x55, 0x97, 0x7d, 0x23, 0x12, 0x64, 0xcb, 0x33, 0x57, 0x66, 0xc9, 0x6a,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x6b, 0x69, 0x13, 0x81,
+	0x2e, 0x01, 0x4b, 0x4b, 0x31, 0xd2, 0x87, 0x07, 0xe4, 0x48, 0x3e, 0xc5,
+	0xcb, 0xf7, 0x19, 0x0c, 0xff, 0xb1, 0x97, 0x58, 0xb6, 0x67, 0x17, 0xa0,
+	0x65, 0xa5, 0xf2, 0x48, 0xd9, 0x4a, 0xd8, 0xfa, 0xc5, 0x3b, 0x4f, 0x69,
+	0x11, 0x9e, 0xbe, 0xee, 0xa1, 0xa1, 0xa3, 0x76, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01
+};
+
+const uint8_t ae_fpm_tbl_p521[AE_FPM_P521_LEN] = {
+	0xf9, 0x7e, 0x7e, 0x31, 0xc2, 0xe5, 0xbd, 0x66, 0x33, 0x48, 0xb3, 0xc1,
+	0x85, 0x6a, 0x42, 0x9b, 0xfe, 0x1d, 0xc1, 0x27, 0xa2, 0xff, 0xa8, 0xde,
+	0xa1, 0x4b, 0x5e, 0x77, 0xef, 0xe7, 0x59, 0x28, 0xf8, 0x28, 0xaf, 0x60,
+	0x6b, 0x4d, 0x3d, 0xba, 0x9c, 0x64, 0x81, 0x39, 0x05, 0x3f, 0xb5, 0x21,
+	0x9e, 0x3e, 0xcb, 0x66, 0x23, 0x95, 0xb4, 0x42, 0x85, 0x8e, 0x06, 0xb7,
+	0x04, 0x04, 0xe9, 0xcd, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc6,
+	0x88, 0xbe, 0x94, 0x76, 0x9f, 0xd1, 0x66, 0x50, 0x35, 0x3c, 0x70, 0x86,
+	0xa2, 0x72, 0xc2, 0x40, 0xc5, 0x50, 0xb9, 0x01, 0x3f, 0xad, 0x07, 0x61,
+	0x97, 0xee, 0x72, 0x99, 0x5e, 0xf4, 0x26, 0x40, 0x17, 0xaf, 0xbd, 0x17,
+	0x27, 0x3e, 0x66, 0x2c, 0x98, 0xf5, 0x44, 0x49, 0x57, 0x9b, 0x44, 0x68,
+	0x5c, 0x8a, 0x5f, 0xb4, 0x2c, 0x7d, 0x1b, 0xd9, 0x39, 0x29, 0x6a, 0x78,
+	0x9a, 0x3b, 0xc0, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x18,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x69, 0xca, 0xd3, 0xcc, 0xc4, 0xd6, 0xab, 0x08, 0x3a, 0xdb, 0x57, 0x77,
+	0x3b, 0x89, 0x90, 0xb8, 0xd0, 0xca, 0xd8, 0xce, 0x8d, 0x95, 0x88, 0x01,
+	0xcb, 0x57, 0x2e, 0x66, 0x6d, 0x72, 0x8f, 0x9e, 0xe3, 0xd9, 0xe7, 0xc4,
+	0xcd, 0x51, 0x31, 0xfc, 0xaf, 0xce, 0xb6, 0xb0, 0x61, 0x45, 0xdc, 0x06,
+	0x12, 0xec, 0xd3, 0x92, 0xe2, 0x13, 0x04, 0x3a, 0xbd, 0x59, 0x92, 0x94,
+	0x3a, 0x64, 0xc8, 0x7c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b,
+	0x86, 0x23, 0xbd, 0xbb, 0xf6, 0xea, 0x9c, 0xf1, 0x3a, 0xad, 0x94, 0x95,
+	0x54, 0x7a, 0xa6, 0x50, 0xd3, 0xd8, 0x53, 0xfc, 0xbe, 0xb2, 0x71, 0x59,
+	0x3d, 0x25, 0xa6, 0x48, 0x30, 0xb4, 0x08, 0x33, 0x12, 0xd1, 0x88, 0xe8,
+	0xde, 0xc5, 0x1b, 0xd1, 0x83, 0x63, 0x30, 0xd2, 0xb3, 0x48, 0xc3, 0xfa,
+	0x9d, 0xf5, 0x0c, 0xfe, 0x73, 0xc2, 0xea, 0x59, 0xb5, 0xdf, 0xfb, 0x20,
+	0x61, 0xde, 0xd0, 0xb8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x8a,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xdc, 0x33, 0x41, 0x6e, 0xc8, 0xc5, 0xbc, 0xb2, 0xde, 0xfb, 0x4a, 0x9c,
+	0xe2, 0x44, 0x91, 0x0b, 0x27, 0xc3, 0x56, 0x1b, 0x53, 0xa8, 0xf7, 0xb9,
+	0x10, 0x88, 0xbb, 0x9e, 0xf6, 0x94, 0xd7, 0xb1, 0x98, 0xfa, 0x92, 0xaa,
+	0xa6, 0xd2, 0xc7, 0x82, 0x53, 0xc2, 0xa3, 0xdb, 0x3b, 0xa3, 0x7d, 0xd4,
+	0x67, 0xfc, 0x7c, 0xab, 0xd5, 0x93, 0x4b, 0xbc, 0x0c, 0x72, 0xcf, 0x96,
+	0x93, 0xbb, 0x09, 0x63, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaf,
+	0xf3, 0x2e, 0xbb, 0x1f, 0x13, 0xda, 0xb4, 0x57, 0x7c, 0x36, 0x11, 0xdf,
+	0xad, 0x23, 0x53, 0x70, 0xd8, 0x6d, 0x54, 0xdb, 0xab, 0x9e, 0x13, 0x10,
+	0xbf, 0x40, 0x10, 0xf1, 0x61, 0x85, 0xbf, 0x0d, 0x94, 0x6d, 0xb5, 0x6e,
+	0x31, 0x3c, 0x69, 0xf5, 0x3b, 0x67, 0x3c, 0x92, 0xe3, 0x77, 0x73, 0x27,
+	0x58, 0x7a, 0x4e, 0xa7, 0x47, 0x7a, 0xbd, 0xe6, 0xae, 0x87, 0xa6, 0x00,
+	0xd8, 0xaa, 0xa4, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x09,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xbf, 0x2f, 0xfc, 0xb7, 0x6e, 0x64, 0x0a, 0x8d, 0x63, 0x47, 0x95, 0x01,
+	0xa0, 0xb5, 0xa0, 0x7e, 0x55, 0xbb, 0x30, 0x01, 0x5f, 0x36, 0xf2, 0xe7,
+	0x98, 0x90, 0xf9, 0x99, 0x05, 0x8a, 0x67, 0x6a, 0xd9, 0xee, 0x34, 0x1b,
+	0x45, 0x5c, 0x0d, 0x27, 0x6c, 0x95, 0x78, 0x0c, 0x18, 0xe0, 0x8f, 0xc8,
+	0xeb, 0x63, 0xa6, 0x75, 0x44, 0x2a, 0x07, 0x5d, 0xce, 0x46, 0xa1, 0xa5,
+	0xfb, 0x69, 0xda, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x6b,
+	0x8c, 0x61, 0x89, 0x34, 0xf3, 0xed, 0x62, 0x53, 0xe0, 0x03, 0x42, 0x44,
+	0x6e, 0x94, 0x33, 0xb4, 0x98, 0x9b, 0x99, 0x21, 0x42, 0x60, 0xb2, 0xc5,
+	0x11, 0x69, 0x98, 0x04, 0xd9, 0xdf, 0x47, 0x47, 0x12, 0x5f, 0xe6, 0x1f,
+	0x76, 0x3a, 0x7f, 0x63, 0xa9, 0x72, 0x78, 0x6d, 0xc6, 0xec, 0x39, 0x5a,
+	0x66, 0x2f, 0x9f, 0xe7, 0xb7, 0xb7, 0xb8, 0xc6, 0xfb, 0x64, 0x4a, 0x61,
+	0x54, 0x56, 0x55, 0x6e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8a,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x52, 0x3c, 0xf9, 0xb2, 0xfd, 0xe7, 0x22, 0x35, 0x5c, 0x90, 0xde, 0xf0,
+	0xe8, 0xe0, 0x99, 0x59, 0xfe, 0x13, 0x1b, 0x9c, 0xd3, 0xcf, 0x46, 0x66,
+	0xc9, 0x14, 0x31, 0x30, 0xc1, 0x32, 0x76, 0xad, 0xa7, 0xdc, 0xdd, 0xc1,
+	0x85, 0xe2, 0x36, 0x37, 0x09, 0x45, 0x74, 0xcc, 0xf5, 0x14, 0x11, 0xd7,
+	0xf3, 0xfc, 0x87, 0xc4, 0xbd, 0x29, 0xfe, 0xd7, 0x2c, 0xc3, 0x2d, 0x3f,
+	0x17, 0x1c, 0xef, 0xb7, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x32,
+	0xdf, 0xa9, 0x2d, 0x3e, 0x35, 0xcc, 0x7a, 0x6c, 0xdd, 0x6d, 0xc6, 0x86,
+	0xd4, 0xe4, 0x78, 0x8b, 0xcb, 0x66, 0xcd, 0xe2, 0x1f, 0x74, 0xbb, 0xe0,
+	0xb0, 0xe9, 0xff, 0x6a, 0xf6, 0x7e, 0xc3, 0x95, 0x18, 0x6c, 0xfa, 0x86,
+	0x07, 0xb9, 0xdd, 0xff, 0xe8, 0x67, 0xde, 0x2f, 0xcf, 0x2d, 0xfd, 0x72,
+	0x49, 0x8c, 0x21, 0x91, 0xe2, 0x4e, 0xd3, 0x15, 0x2d, 0xf0, 0xac, 0xf8,
+	0xf7, 0x37, 0xe8, 0xc6, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x9f,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x52, 0x6f, 0x00, 0x95, 0x74, 0x31, 0x82, 0x2a, 0x18, 0x5d, 0x92, 0xc3,
+	0xeb, 0x0c, 0x4e, 0xf8, 0xc8, 0x78, 0x13, 0x76, 0x38, 0x89, 0x30, 0x98,
+	0x32, 0x54, 0x7e, 0xec, 0x6a, 0x55, 0x72, 0xd0, 0xe1, 0xe8, 0xea, 0xe8,
+	0xf5, 0x94, 0x62, 0x73, 0x9a, 0x9e, 0x24, 0x00, 0xc8, 0x2f, 0x4f, 0x17,
+	0xfb, 0x98, 0xab, 0xff, 0xdb, 0x9f, 0x0e, 0x9b, 0x3c, 0x20, 0x1a, 0xa5,
+	0x83, 0x28, 0x87, 0xa5, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x95,
+	0x58, 0x76, 0x12, 0xa4, 0x41, 0xc2, 0xb1, 0x4a, 0x11, 0x91, 0xb7, 0x1d,
+	0xfd, 0xbf, 0x12, 0x43, 0x97, 0x39, 0x6e, 0xe7, 0xbc, 0xf5, 0x3f, 0x43,
+	0xd1, 0x4b, 0xf1, 0xa7, 0x90, 0xec, 0xf9, 0x76, 0x7f, 0x14, 0x7a, 0x72,
+	0x0b, 0xc6, 0xa0, 0xea, 0x40, 0x95, 0x18, 0xf8, 0xaf, 0xcb, 0xff, 0x46,
+	0x30, 0x21, 0xdc, 0xa5, 0x32, 0x17, 0x0c, 0x93, 0x88, 0x16, 0xd3, 0xee,
+	0x33, 0xf2, 0x46, 0xdd, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xcc, 0x7d, 0x6e, 0x15, 0x2f, 0x97, 0x03, 0x30, 0x50, 0xb1, 0xf6, 0x9e,
+	0x03, 0x00, 0x75, 0x86, 0xfc, 0x0e, 0x37, 0x04, 0x58, 0x25, 0x83, 0x51,
+	0xa8, 0x5d, 0x47, 0xe3, 0x56, 0xd8, 0xaf, 0x60, 0x1c, 0x89, 0x3b, 0x86,
+	0x8a, 0xc7, 0x42, 0x7f, 0x8e, 0x70, 0xdd, 0xd9, 0x5c, 0xcf, 0x72, 0xde,
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+	0x85, 0x42, 0x8e, 0x55, 0xee, 0x3a, 0x97, 0x81, 0x71, 0xc3, 0x42, 0x1b,
+	0x5b, 0x6d, 0x51, 0xc0, 0x01, 0xed, 0x96, 0x12, 0x52, 0x56, 0x02, 0x26,
+	0x6c, 0xc1, 0xdb, 0xed, 0x90, 0x72, 0x2e, 0x36, 0xfa, 0xa6, 0x4f, 0x19,
+	0xc2, 0xc7, 0x0c, 0xba, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x5b,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01
+};
+
+const struct ae_fpm_entry ae_fpm_tbl_scalar[ROC_AE_EC_ID_PMAX] = {
+	{
+		.data = ae_fpm_tbl_p192,
+		.len = sizeof(ae_fpm_tbl_p192)
+	},
+	{
+		.data = ae_fpm_tbl_p224,
+		.len = sizeof(ae_fpm_tbl_p224)
+	},
+	{
+		.data = ae_fpm_tbl_p256,
+		.len = sizeof(ae_fpm_tbl_p256)
+	},
+	{
+		.data = ae_fpm_tbl_p384,
+		.len = sizeof(ae_fpm_tbl_p384)
+	},
+	{
+		.data = ae_fpm_tbl_p521,
+		.len = sizeof(ae_fpm_tbl_p521)
+	}
+};
+
+int
+roc_ae_fpm_get(uint64_t *tbl)
+{
+	const char name[] = AE_FPM_TBL_NAME;
+	const struct plt_memzone *mz;
+	struct ae_fpm_tbl *fpm;
+	int i, len = 0;
+	uint8_t *data;
+
+	if (tbl == NULL)
+		return -EINVAL;
+
+	/* Compute FPM table size for all supported curves */
+	for (i = 0; i < ROC_AE_EC_ID_PMAX; i++)
+		len += ae_fpm_tbl_scalar[i].len;
+
+	mz = plt_memzone_lookup(name);
+	if (mz == NULL) {
+		/* Create memzone first time */
+		mz = plt_memzone_reserve_cache_align(
+			name, sizeof(struct ae_fpm_tbl) + len);
+		if (mz == NULL)
+			return -ENOMEM;
+	}
+
+	fpm = (struct ae_fpm_tbl *)mz->addr;
+
+	if (__atomic_fetch_add(&fpm->refcount, 1, __ATOMIC_SEQ_CST) != 0)
+		return 0;
+
+	data = PLT_PTR_ADD(mz->addr, sizeof(uint64_t));
+
+	for (i = ROC_AE_EC_ID_P192; i < ROC_AE_EC_ID_PMAX; i++) {
+		memcpy(data, ae_fpm_tbl_scalar[i].data,
+		       ae_fpm_tbl_scalar[i].len);
+		tbl[i] = plt_cpu_to_be_64((uintptr_t)data);
+		data = PLT_PTR_ADD(data, ae_fpm_tbl_scalar[i].len);
+	}
+
+	return 0;
+}
+
+void
+roc_ae_fpm_put(void)
+{
+	const char name[] = AE_FPM_TBL_NAME;
+	const struct plt_memzone *mz;
+	struct ae_fpm_tbl *fpm;
+
+	mz = plt_memzone_lookup(name);
+	if (mz == NULL)
+		return;
+
+	fpm = (struct ae_fpm_tbl *)mz->addr;
+	/* Decrement number of devices using FPM table */
+	if (__atomic_sub_fetch(&fpm->refcount, 1, __ATOMIC_SEQ_CST) == 0)
+		plt_memzone_free(mz);
+}
diff --git a/drivers/common/cnxk/roc_ae_fpm_tables.h b/drivers/common/cnxk/roc_ae_fpm_tables.h
new file mode 100644
index 0000000..1cc5b02
--- /dev/null
+++ b/drivers/common/cnxk/roc_ae_fpm_tables.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef _ROC_AE_FPM_TABLES_H_
+#define _ROC_AE_FPM_TABLES_H_
+
+#include "roc_api.h"
+
+int __roc_api roc_ae_fpm_get(uint64_t *tbl);
+void __roc_api roc_ae_fpm_put(void);
+
+#endif /* _ROC_AE_FPM_TABLES_H_ */
diff --git a/drivers/common/cnxk/roc_api.h b/drivers/common/cnxk/roc_api.h
index 546818d..37c151e 100644
--- a/drivers/common/cnxk/roc_api.h
+++ b/drivers/common/cnxk/roc_api.h
@@ -111,6 +111,7 @@
 
 /* CPT microcode */
 #include "roc_ae.h"
+#include "roc_ae_fpm_tables.h"
 #include "roc_ie_on.h"
 #include "roc_ie_ot.h"
 #include "roc_se.h"
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index e079bc7..7a3b4a6 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -10,6 +10,8 @@ INTERNAL {
 	cnxk_logtype_sso;
 	cnxk_logtype_tim;
 	cnxk_logtype_tm;
+	roc_ae_fpm_get;
+	roc_ae_fpm_put;
 	roc_clk_freq_get;
 	roc_cpt_afs_print;
 	roc_cpt_dev_clear;
-- 
2.7.4

[dpdk-dev] [PATCH v2 15/17] common/cnxk: add EC grp static vectors

[Anoob Joseph]

From: Kiran Kumar Kokkilagadda <kirankumark@marvell.com>

EC group static vectors are required for CPT asymmetric operations.

Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Kiran Kumar Kokkilagadda <kirankumark@marvell.com>
---
 drivers/common/cnxk/meson.build |   1 +
 drivers/common/cnxk/roc_ae.c    | 142 ++++++++++++++++++++++++++++++++++++++++
 drivers/common/cnxk/roc_ae.h    |   7 ++
 drivers/common/cnxk/version.map |   2 +
 4 files changed, 152 insertions(+)
 create mode 100644 drivers/common/cnxk/roc_ae.c

diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build
index 181b58e..4c5d318 100644
--- a/drivers/common/cnxk/meson.build
+++ b/drivers/common/cnxk/meson.build
@@ -11,6 +11,7 @@ endif
 config_flag_fmt = 'RTE_LIBRTE_@0@_COMMON'
 deps = ['eal', 'pci', 'bus_pci', 'mbuf']
 sources = files(
+        'roc_ae.c',
         'roc_ae_fpm_tables.c',
         'roc_cpt.c',
         'roc_cpt_debug.c',
diff --git a/drivers/common/cnxk/roc_ae.c b/drivers/common/cnxk/roc_ae.c
new file mode 100644
index 0000000..cf3f7fc
--- /dev/null
+++ b/drivers/common/cnxk/roc_ae.c
@@ -0,0 +1,142 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#include "roc_api.h"
+
+#define AE_EC_GRP_TBL_NAME "ae_ec_grp_tbl"
+
+struct ae_ec_grp_tbl {
+	uint64_t refcount;
+	uint8_t ec_grp_tbl[];
+};
+
+const struct roc_ae_ec_group ae_ec_grp[ROC_AE_EC_ID_PMAX] = {
+	{
+		.prime = {.data = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+				   0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+				   0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF,
+				   0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF},
+			  .length = 24},
+		.order = {.data = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+				   0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+				   0x99, 0xDE, 0xF8, 0x36, 0x14, 0x6B,
+				   0xC9, 0xB1, 0xB4, 0xD2, 0x28, 0x31},
+			  .length = 24},
+	},
+	{
+		.prime = {.data = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+				   0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+				   0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00,
+				   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
+			  .length = 28},
+		.order = {.data = {0XFF, 0XFF, 0XFF, 0XFF, 0XFF, 0XFF, 0XFF,
+				   0XFF, 0XFF, 0XFF, 0XFF, 0XFF, 0XFF, 0XFF,
+				   0X16, 0XA2, 0XE0, 0XB8, 0XF0, 0X3E, 0X13,
+				   0XDD, 0X29, 0X45, 0X5C, 0X5C, 0X2A, 0X3D},
+			  .length = 28},
+	},
+	{
+		.prime = {.data = {0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00,
+				   0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+				   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF,
+				   0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+				   0xFF, 0xFF, 0xFF, 0xFF},
+			  .length = 32},
+		.order = {.data = {0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00,
+				   0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+				   0xFF, 0xFF, 0xBC, 0xE6, 0xFA, 0xAD, 0xA7,
+				   0x17, 0x9E, 0x84, 0xF3, 0xB9, 0xCA, 0xC2,
+				   0xFC, 0x63, 0x25, 0x51},
+			  .length = 32},
+	},
+	{.prime = {.data = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+			    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+			    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+			    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE,
+			    0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00,
+			    0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF},
+		   .length = 48},
+	 .order = {.data = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+			    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+			    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+			    0xC7, 0x63, 0x4D, 0x81, 0xF4, 0x37, 0x2D, 0xDF,
+			    0x58, 0x1A, 0x0D, 0xB2, 0x48, 0xB0, 0xA7, 0x7A,
+			    0xEC, 0xEC, 0x19, 0x6A, 0xCC, 0xC5, 0x29, 0x73},
+		   .length = 48}},
+	{.prime = {.data = {0x01, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+			    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+			    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+			    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+			    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+			    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+			    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+			    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+			    0xFF, 0xFF},
+		   .length = 66},
+	 .order = {.data = {0x01, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+			    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+			    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+			    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+			    0xFF, 0xFA, 0x51, 0x86, 0x87, 0x83, 0xBF, 0x2F,
+			    0x96, 0x6B, 0x7F, 0xCC, 0x01, 0x48, 0xF7, 0x09,
+			    0xA5, 0xD0, 0x3B, 0xB5, 0xC9, 0xB8, 0x89, 0x9C,
+			    0x47, 0xAE, 0xBB, 0x6F, 0xB7, 0x1E, 0x91, 0x38,
+			    0x64, 0x09},
+		   .length = 66}}};
+
+int
+roc_ae_ec_grp_get(struct roc_ae_ec_group **tbl)
+{
+	const char name[] = AE_EC_GRP_TBL_NAME;
+	struct ae_ec_grp_tbl *ec_grp;
+	const struct plt_memzone *mz;
+	int i, len = 0;
+	uint8_t *data;
+
+	if (tbl == NULL)
+		return -EINVAL;
+
+	len = sizeof(ae_ec_grp);
+
+	mz = plt_memzone_lookup(name);
+	if (mz == NULL) {
+		/* Create memzone first time */
+		mz = plt_memzone_reserve_cache_align(
+			name, len + sizeof(struct ae_ec_grp_tbl));
+		if (mz == NULL)
+			return -ENOMEM;
+	}
+
+	ec_grp = mz->addr;
+
+	if (__atomic_fetch_add(&ec_grp->refcount, 1, __ATOMIC_SEQ_CST) != 0)
+		return 0;
+
+	data = PLT_PTR_ADD(mz->addr, sizeof(uint64_t));
+
+	for (i = 0; i < ROC_AE_EC_ID_PMAX; i++) {
+		memcpy(data, &ae_ec_grp[i], sizeof(struct roc_ae_ec_group));
+		tbl[i] = (struct roc_ae_ec_group *)data;
+		data += sizeof(struct roc_ae_ec_group);
+	}
+
+	return 0;
+}
+
+void
+roc_ae_ec_grp_put(void)
+{
+	const char name[] = AE_EC_GRP_TBL_NAME;
+	const struct plt_memzone *mz;
+	struct ae_ec_grp_tbl *ec_grp;
+
+	mz = plt_memzone_lookup(name);
+	if (mz == NULL)
+		return;
+
+	ec_grp = mz->addr;
+	/* Decrement number of devices using EC grp table */
+	if (__atomic_sub_fetch(&ec_grp->refcount, 1, __ATOMIC_SEQ_CST) == 0)
+		plt_memzone_free(mz);
+}
diff --git a/drivers/common/cnxk/roc_ae.h b/drivers/common/cnxk/roc_ae.h
index c549e18..5072cc5 100644
--- a/drivers/common/cnxk/roc_ae.h
+++ b/drivers/common/cnxk/roc_ae.h
@@ -53,4 +53,11 @@ struct roc_ae_ec_ctx {
 	uint8_t curveid;
 };
 
+/* Buffer pointer */
+struct roc_ae_buf_ptr {
+	void *vaddr;
+};
+
+int __roc_api roc_ae_ec_grp_get(struct roc_ae_ec_group **tbl);
+void __roc_api roc_ae_ec_grp_put(void);
 #endif /* __ROC_AE_H__ */
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 7a3b4a6..9611217 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -10,6 +10,8 @@ INTERNAL {
 	cnxk_logtype_sso;
 	cnxk_logtype_tim;
 	cnxk_logtype_tm;
+	roc_ae_ec_grp_get;
+	roc_ae_ec_grp_put;
 	roc_ae_fpm_get;
 	roc_ae_fpm_put;
 	roc_clk_freq_get;
-- 
2.7.4

[dpdk-dev] [PATCH v2 16/17] common/cnxk: add IPsec common code

[Anoob Joseph]

From: Srujana Challa <schalla@marvell.com>

Add code that can be leveraged across
lookaside and inline IPsec on cn10k.

Signed-off-by: Srujana Challa <schalla@marvell.com>
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
---
 drivers/common/cnxk/cnxk_security.c | 468 ++++++++++++++++++++++++++++++++++++
 drivers/common/cnxk/cnxk_security.h |  49 ++++
 drivers/common/cnxk/meson.build     |   6 +-
 drivers/common/cnxk/version.map     |   8 +
 4 files changed, 530 insertions(+), 1 deletion(-)
 create mode 100644 drivers/common/cnxk/cnxk_security.c
 create mode 100644 drivers/common/cnxk/cnxk_security.h

diff --git a/drivers/common/cnxk/cnxk_security.c b/drivers/common/cnxk/cnxk_security.c
new file mode 100644
index 0000000..17889bb
--- /dev/null
+++ b/drivers/common/cnxk/cnxk_security.c
@@ -0,0 +1,468 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#include "cnxk_security.h"
+
+static int
+ot_ipsec_sa_common_param_fill(union roc_ot_ipsec_sa_word2 *w2,
+			      uint8_t *cipher_key, uint8_t *salt_key,
+			      struct rte_security_ipsec_xform *ipsec_xfrm,
+			      struct rte_crypto_sym_xform *crypto_xfrm)
+{
+	const uint8_t *key;
+	uint32_t *tmp_salt;
+	uint64_t *tmp_key;
+	int length, i;
+
+	/* Set direction */
+	switch (ipsec_xfrm->direction) {
+	case RTE_SECURITY_IPSEC_SA_DIR_INGRESS:
+		w2->s.dir = ROC_IE_OT_SA_DIR_INBOUND;
+		break;
+	case RTE_SECURITY_IPSEC_SA_DIR_EGRESS:
+		w2->s.dir = ROC_IE_OT_SA_DIR_OUTBOUND;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	/* Set protocol - ESP vs AH */
+	switch (ipsec_xfrm->proto) {
+	case RTE_SECURITY_IPSEC_SA_PROTO_ESP:
+		w2->s.protocol = ROC_IE_OT_SA_PROTOCOL_ESP;
+		break;
+	case RTE_SECURITY_IPSEC_SA_PROTO_AH:
+		w2->s.protocol = ROC_IE_OT_SA_PROTOCOL_AH;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	/* Set mode - transport vs tunnel */
+	switch (ipsec_xfrm->mode) {
+	case RTE_SECURITY_IPSEC_SA_MODE_TRANSPORT:
+		w2->s.mode = ROC_IE_OT_SA_MODE_TRANSPORT;
+		break;
+	case RTE_SECURITY_IPSEC_SA_MODE_TUNNEL:
+		w2->s.mode = ROC_IE_OT_SA_MODE_TUNNEL;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	/* Set encryption algorithm */
+	if (crypto_xfrm->type == RTE_CRYPTO_SYM_XFORM_AEAD) {
+		key = crypto_xfrm->aead.key.data;
+		length = crypto_xfrm->aead.key.length;
+
+		switch (crypto_xfrm->aead.algo) {
+		case RTE_CRYPTO_AEAD_AES_GCM:
+			w2->s.enc_type = ROC_IE_OT_SA_ENC_AES_GCM;
+			w2->s.auth_type = ROC_IE_OT_SA_AUTH_NULL;
+			memcpy(salt_key, &ipsec_xfrm->salt, 4);
+			tmp_salt = (uint32_t *)salt_key;
+			*tmp_salt = rte_be_to_cpu_32(*tmp_salt);
+			break;
+		default:
+			return -ENOTSUP;
+		}
+	} else {
+		return -ENOTSUP;
+	}
+
+	w2->s.spi = ipsec_xfrm->spi;
+
+	/* Copy encryption key */
+	memcpy(cipher_key, key, length);
+	tmp_key = (uint64_t *)cipher_key;
+	for (i = 0; i < (int)(ROC_CTX_MAX_CKEY_LEN / sizeof(uint64_t)); i++)
+		tmp_key[i] = rte_be_to_cpu_64(tmp_key[i]);
+
+	switch (length) {
+	case ROC_CPT_AES128_KEY_LEN:
+		w2->s.aes_key_len = ROC_IE_OT_SA_AES_KEY_LEN_128;
+		break;
+	case ROC_CPT_AES192_KEY_LEN:
+		w2->s.aes_key_len = ROC_IE_OT_SA_AES_KEY_LEN_192;
+		break;
+	case ROC_CPT_AES256_KEY_LEN:
+		w2->s.aes_key_len = ROC_IE_OT_SA_AES_KEY_LEN_256;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static size_t
+ot_ipsec_inb_ctx_size(struct roc_ot_ipsec_inb_sa *sa)
+{
+	size_t size;
+
+	/* Variable based on Anti-replay Window */
+	size = offsetof(struct roc_ot_ipsec_inb_sa, ctx) +
+	       offsetof(struct roc_ot_ipsec_inb_ctx_update_reg, ar_winbits);
+
+	if (sa->w0.s.ar_win)
+		size += (1 << (sa->w0.s.ar_win - 1)) * sizeof(uint64_t);
+
+	return size;
+}
+
+int
+cnxk_ot_ipsec_inb_sa_fill(struct roc_ot_ipsec_inb_sa *sa,
+			  struct rte_security_ipsec_xform *ipsec_xfrm,
+			  struct rte_crypto_sym_xform *crypto_xfrm)
+{
+	union roc_ot_ipsec_sa_word2 w2;
+	uint32_t replay_win_sz;
+	size_t offset;
+	int rc;
+
+	w2.u64 = 0;
+	rc = ot_ipsec_sa_common_param_fill(&w2, sa->cipher_key, sa->w8.s.salt,
+					   ipsec_xfrm, crypto_xfrm);
+	if (rc)
+		return rc;
+
+	/* Updata common word2 data */
+	sa->w2.u64 = w2.u64;
+
+	/* Only support power-of-two window sizes supported */
+	replay_win_sz = ipsec_xfrm->replay_win_sz;
+	if (replay_win_sz) {
+		if (!rte_is_power_of_2(replay_win_sz) ||
+		    replay_win_sz > ROC_AR_WIN_SIZE_MAX)
+			return -ENOTSUP;
+
+		sa->w0.s.ar_win = rte_log2_u32(replay_win_sz) - 5;
+	}
+
+	/* Default options for pkt_out and pkt_fmt are with
+	 * second pass meta and no defrag.
+	 */
+	sa->w0.s.pkt_format = ROC_IE_OT_SA_PKT_FMT_META;
+	sa->w0.s.pkt_output = ROC_IE_OT_SA_PKT_OUTPUT_HW_BASED_DEFRAG;
+	sa->w0.s.pkind = ROC_OT_CPT_META_PKIND;
+
+	/* ESN */
+	sa->w2.s.esn_en = !!ipsec_xfrm->options.esn;
+
+	offset = offsetof(struct roc_ot_ipsec_inb_sa, ctx);
+	/* Word offset for HW managed SA field */
+	sa->w0.s.hw_ctx_off = offset / 8;
+	/* Context push size for inbound spans up to hw_ctx including
+	 * ar_base field, in 8b units
+	 */
+	sa->w0.s.ctx_push_size = sa->w0.s.hw_ctx_off + 1;
+	/* Entire context size in 128B units */
+	sa->w0.s.ctx_size =
+		(PLT_ALIGN_CEIL(ot_ipsec_inb_ctx_size(sa), ROC_CTX_UNIT_128B) /
+		 ROC_CTX_UNIT_128B) -
+		1;
+
+	/* There are two words of CPT_CTX_HW_S for ucode to skip */
+	sa->w0.s.ctx_hdr_size = 1;
+	sa->w0.s.aop_valid = 1;
+
+	rte_wmb();
+
+	/* Enable SA */
+	sa->w2.s.valid = 1;
+	return 0;
+}
+
+int
+cnxk_ot_ipsec_outb_sa_fill(struct roc_ot_ipsec_outb_sa *sa,
+			   struct rte_security_ipsec_xform *ipsec_xfrm,
+			   struct rte_crypto_sym_xform *crypto_xfrm)
+{
+	struct rte_security_ipsec_tunnel_param *tunnel = &ipsec_xfrm->tunnel;
+	union roc_ot_ipsec_sa_word2 w2;
+	size_t offset;
+	int rc;
+
+	w2.u64 = 0;
+	rc = ot_ipsec_sa_common_param_fill(&w2, sa->cipher_key, sa->iv.s.salt,
+					   ipsec_xfrm, crypto_xfrm);
+	if (rc)
+		return rc;
+
+	/* Update common word2 data */
+	sa->w2.u64 = w2.u64;
+
+	if (ipsec_xfrm->mode != RTE_SECURITY_IPSEC_SA_MODE_TUNNEL)
+		goto skip_tunnel_info;
+
+	/* Tunnel header info */
+	switch (tunnel->type) {
+	case RTE_SECURITY_IPSEC_TUNNEL_IPV4:
+		sa->w2.s.outer_ip_ver = ROC_IE_OT_SA_IP_VERSION_4;
+		memcpy(&sa->outer_hdr.ipv4.src_addr, &tunnel->ipv4.src_ip,
+		       sizeof(struct in_addr));
+		memcpy(&sa->outer_hdr.ipv4.dst_addr, &tunnel->ipv4.dst_ip,
+		       sizeof(struct in_addr));
+
+		/* IP Source and Dest seems to be in LE/CPU endian */
+		sa->outer_hdr.ipv4.src_addr =
+			rte_be_to_cpu_32(sa->outer_hdr.ipv4.src_addr);
+		sa->outer_hdr.ipv4.dst_addr =
+			rte_be_to_cpu_32(sa->outer_hdr.ipv4.dst_addr);
+
+		/* Outer header DF bit source */
+		if (!ipsec_xfrm->options.copy_df) {
+			sa->w2.s.ipv4_df_src_or_ipv6_flw_lbl_src =
+				ROC_IE_OT_SA_COPY_FROM_SA;
+			sa->w10.s.ipv4_df_or_ipv6_flw_lbl = tunnel->ipv4.df;
+		} else {
+			sa->w2.s.ipv4_df_src_or_ipv6_flw_lbl_src =
+				ROC_IE_OT_SA_COPY_FROM_INNER_IP_HDR;
+		}
+
+		/* Outer header DSCP source */
+		if (!ipsec_xfrm->options.copy_dscp) {
+			sa->w2.s.dscp_src = ROC_IE_OT_SA_COPY_FROM_SA;
+			sa->w10.s.dscp = tunnel->ipv4.dscp;
+		} else {
+			sa->w2.s.dscp_src = ROC_IE_OT_SA_COPY_FROM_INNER_IP_HDR;
+		}
+		break;
+	case RTE_SECURITY_IPSEC_TUNNEL_IPV6:
+		sa->w2.s.outer_ip_ver = ROC_IE_OT_SA_IP_VERSION_6;
+		memcpy(&sa->outer_hdr.ipv6.src_addr, &tunnel->ipv6.src_addr,
+		       sizeof(struct in6_addr));
+		memcpy(&sa->outer_hdr.ipv6.dst_addr, &tunnel->ipv6.dst_addr,
+		       sizeof(struct in6_addr));
+
+		/* Outer header flow label source */
+		if (!ipsec_xfrm->options.copy_flabel) {
+			sa->w2.s.ipv4_df_src_or_ipv6_flw_lbl_src =
+				ROC_IE_OT_SA_COPY_FROM_SA;
+
+			sa->w10.s.ipv4_df_or_ipv6_flw_lbl = tunnel->ipv6.flabel;
+		} else {
+			sa->w2.s.ipv4_df_src_or_ipv6_flw_lbl_src =
+				ROC_IE_OT_SA_COPY_FROM_INNER_IP_HDR;
+		}
+
+		/* Outer header DSCP source */
+		if (!ipsec_xfrm->options.copy_dscp) {
+			sa->w2.s.dscp_src = ROC_IE_OT_SA_COPY_FROM_SA;
+			sa->w10.s.dscp = tunnel->ipv6.dscp;
+		} else {
+			sa->w2.s.dscp_src = ROC_IE_OT_SA_COPY_FROM_INNER_IP_HDR;
+		}
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	/* Default options of DSCP and Flow label/DF */
+	sa->w2.s.dscp_src = ROC_IE_OT_SA_COPY_FROM_SA;
+	sa->w2.s.ipv4_df_src_or_ipv6_flw_lbl_src = ROC_IE_OT_SA_COPY_FROM_SA;
+
+skip_tunnel_info:
+	/* ESN */
+	sa->w0.s.esn_en = !!ipsec_xfrm->options.esn;
+
+	offset = offsetof(struct roc_ot_ipsec_outb_sa, ctx);
+	/* Word offset for HW managed SA field */
+	sa->w0.s.hw_ctx_off = offset / 8;
+	/* Context push size is up to hmac_opad_ipad */
+	sa->w0.s.ctx_push_size = sa->w0.s.hw_ctx_off;
+	/* Entire context size in 128B units */
+	offset = sizeof(struct roc_ot_ipsec_outb_sa);
+	sa->w0.s.ctx_size = (PLT_ALIGN_CEIL(offset, ROC_CTX_UNIT_128B) /
+			     ROC_CTX_UNIT_128B) -
+			    1;
+
+	/* IPID gen */
+	sa->w2.s.ipid_gen = 1;
+
+	/* There are two words of CPT_CTX_HW_S for ucode to skip */
+	sa->w0.s.ctx_hdr_size = 1;
+	sa->w0.s.aop_valid = 1;
+
+	rte_wmb();
+
+	/* Enable SA */
+	sa->w2.s.valid = 1;
+	return 0;
+}
+
+bool
+cnxk_ot_ipsec_inb_sa_valid(struct roc_ot_ipsec_inb_sa *sa)
+{
+	return !!sa->w2.s.valid;
+}
+
+bool
+cnxk_ot_ipsec_outb_sa_valid(struct roc_ot_ipsec_outb_sa *sa)
+{
+	return !!sa->w2.s.valid;
+}
+
+uint8_t
+cnxk_ipsec_ivlen_get(enum rte_crypto_cipher_algorithm c_algo,
+		     enum rte_crypto_auth_algorithm a_algo,
+		     enum rte_crypto_aead_algorithm aead_algo)
+{
+	uint8_t ivlen = 0;
+
+	if (aead_algo == RTE_CRYPTO_AEAD_AES_GCM)
+		ivlen = 8;
+
+	switch (c_algo) {
+	case RTE_CRYPTO_CIPHER_AES_CTR:
+		ivlen = 8;
+		break;
+	case RTE_CRYPTO_CIPHER_3DES_CBC:
+		ivlen = ROC_CPT_DES_BLOCK_LENGTH;
+		break;
+	case RTE_CRYPTO_CIPHER_AES_CBC:
+		ivlen = ROC_CPT_AES_BLOCK_LENGTH;
+		break;
+	default:
+		break;
+	}
+
+	switch (a_algo) {
+	case RTE_CRYPTO_AUTH_AES_GMAC:
+		ivlen = 8;
+		break;
+	default:
+		break;
+	}
+
+	return ivlen;
+}
+
+uint8_t
+cnxk_ipsec_icvlen_get(enum rte_crypto_cipher_algorithm c_algo,
+		      enum rte_crypto_auth_algorithm a_algo,
+		      enum rte_crypto_aead_algorithm aead_algo)
+{
+	uint8_t icv = 0;
+
+	(void)c_algo;
+
+	switch (a_algo) {
+	case RTE_CRYPTO_AUTH_NULL:
+		icv = 0;
+		break;
+	case RTE_CRYPTO_AUTH_SHA1:
+		icv = 12;
+		break;
+	case RTE_CRYPTO_AUTH_SHA256:
+	case RTE_CRYPTO_AUTH_AES_GMAC:
+		icv = 16;
+		break;
+	case RTE_CRYPTO_AUTH_SHA384:
+		icv = 24;
+		break;
+	case RTE_CRYPTO_AUTH_SHA512:
+		icv = 32;
+		break;
+	default:
+		break;
+	}
+
+	switch (aead_algo) {
+	case RTE_CRYPTO_AEAD_AES_GCM:
+		icv = 16;
+		break;
+	default:
+		break;
+	}
+
+	return icv;
+}
+
+uint8_t
+cnxk_ipsec_outb_roundup_byte(enum rte_crypto_cipher_algorithm c_algo,
+			     enum rte_crypto_aead_algorithm aead_algo)
+{
+	uint8_t roundup_byte = 4;
+
+	if (aead_algo == RTE_CRYPTO_AEAD_AES_GCM)
+		return roundup_byte;
+
+	switch (c_algo) {
+	case RTE_CRYPTO_CIPHER_AES_CTR:
+		roundup_byte = 4;
+		break;
+	case RTE_CRYPTO_CIPHER_AES_CBC:
+		roundup_byte = 16;
+		break;
+	case RTE_CRYPTO_CIPHER_3DES_CBC:
+		roundup_byte = 8;
+		break;
+	case RTE_CRYPTO_CIPHER_NULL:
+		roundup_byte = 4;
+		break;
+	default:
+		break;
+	}
+
+	return roundup_byte;
+}
+
+int
+cnxk_ipsec_outb_rlens_get(struct cnxk_ipsec_outb_rlens *rlens,
+			  struct rte_security_ipsec_xform *ipsec_xfrm,
+			  struct rte_crypto_sym_xform *crypto_xfrm)
+{
+	struct rte_security_ipsec_tunnel_param *tunnel = &ipsec_xfrm->tunnel;
+	enum rte_crypto_cipher_algorithm c_algo = RTE_CRYPTO_CIPHER_NULL;
+	enum rte_crypto_auth_algorithm a_algo = RTE_CRYPTO_AUTH_NULL;
+	enum rte_crypto_aead_algorithm aead_algo = 0;
+	uint16_t partial_len = 0;
+	uint8_t roundup_byte = 0;
+	int8_t roundup_len = 0;
+
+	memset(rlens, 0, sizeof(struct cnxk_ipsec_outb_rlens));
+
+	/* Get Cipher and Auth algo */
+	if (crypto_xfrm->type == RTE_CRYPTO_SYM_XFORM_AEAD) {
+		aead_algo = crypto_xfrm->aead.algo;
+	} else {
+		if (crypto_xfrm->type == RTE_CRYPTO_SYM_XFORM_CIPHER)
+			c_algo = crypto_xfrm->cipher.algo;
+		else
+			a_algo = crypto_xfrm->auth.algo;
+
+		if (crypto_xfrm->next) {
+			if (crypto_xfrm->next->type ==
+			    RTE_CRYPTO_SYM_XFORM_CIPHER)
+				c_algo = crypto_xfrm->next->cipher.algo;
+			else
+				a_algo = crypto_xfrm->next->auth.algo;
+		}
+	}
+
+	if (ipsec_xfrm->proto == RTE_SECURITY_IPSEC_SA_PROTO_ESP) {
+		partial_len = ROC_CPT_ESP_HDR_LEN;
+		roundup_len = ROC_CPT_ESP_TRL_LEN;
+	} else {
+		partial_len = ROC_CPT_AH_HDR_LEN;
+	}
+
+	if (ipsec_xfrm->mode == RTE_SECURITY_IPSEC_SA_MODE_TUNNEL) {
+		if (tunnel->type == RTE_SECURITY_IPSEC_TUNNEL_IPV4)
+			partial_len += ROC_CPT_TUNNEL_IPV4_HDR_LEN;
+		else
+			partial_len += ROC_CPT_TUNNEL_IPV6_HDR_LEN;
+	}
+
+	partial_len += cnxk_ipsec_ivlen_get(c_algo, a_algo, aead_algo);
+	partial_len += cnxk_ipsec_icvlen_get(c_algo, a_algo, aead_algo);
+	roundup_byte = cnxk_ipsec_outb_roundup_byte(c_algo, aead_algo);
+
+	rlens->partial_len = partial_len;
+	rlens->roundup_len = roundup_len;
+	rlens->roundup_byte = roundup_byte;
+	rlens->max_extended_len = partial_len + roundup_len + roundup_byte;
+	return 0;
+}
diff --git a/drivers/common/cnxk/cnxk_security.h b/drivers/common/cnxk/cnxk_security.h
new file mode 100644
index 0000000..602f583
--- /dev/null
+++ b/drivers/common/cnxk/cnxk_security.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+#ifndef _CNXK_SECURITY_H__
+#define _CNXK_SECURITY_H__
+
+#include <rte_crypto.h>
+#include <rte_security.h>
+
+#include "roc_api.h"
+
+/* Response length calculation data */
+struct cnxk_ipsec_outb_rlens {
+	uint16_t partial_len;
+	uint8_t roundup_byte;
+	int8_t roundup_len;
+	uint16_t max_extended_len;
+};
+
+int __roc_api
+cnxk_ipsec_outb_rlens_get(struct cnxk_ipsec_outb_rlens *rlens,
+			  struct rte_security_ipsec_xform *ipsec_xfrm,
+			  struct rte_crypto_sym_xform *crypto_xfrm);
+uint8_t __roc_api
+cnxk_ipsec_ivlen_get(enum rte_crypto_cipher_algorithm c_algo,
+		     enum rte_crypto_auth_algorithm a_algo,
+		     enum rte_crypto_aead_algorithm aead_algo);
+uint8_t __roc_api
+cnxk_ipsec_icvlen_get(enum rte_crypto_cipher_algorithm c_algo,
+		      enum rte_crypto_auth_algorithm a_algo,
+		      enum rte_crypto_aead_algorithm aead_algo);
+
+uint8_t __roc_api
+cnxk_ipsec_outb_roundup_byte(enum rte_crypto_cipher_algorithm c_algo,
+			     enum rte_crypto_aead_algorithm aead_algo);
+
+/* [CN10K, .) */
+int __roc_api
+cnxk_ot_ipsec_inb_sa_fill(struct roc_ot_ipsec_inb_sa *sa,
+			  struct rte_security_ipsec_xform *ipsec_xfrm,
+			  struct rte_crypto_sym_xform *crypto_xfrm);
+int __roc_api
+cnxk_ot_ipsec_outb_sa_fill(struct roc_ot_ipsec_outb_sa *sa,
+			   struct rte_security_ipsec_xform *ipsec_xfrm,
+			   struct rte_crypto_sym_xform *crypto_xfrm);
+bool __roc_api cnxk_ot_ipsec_inb_sa_valid(struct roc_ot_ipsec_inb_sa *sa);
+bool __roc_api cnxk_ot_ipsec_outb_sa_valid(struct roc_ot_ipsec_outb_sa *sa);
+
+#endif /* _CNXK_SECURITY_H__ */
diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build
index 4c5d318..1f118ef 100644
--- a/drivers/common/cnxk/meson.build
+++ b/drivers/common/cnxk/meson.build
@@ -9,7 +9,7 @@ if not is_linux or not dpdk_conf.get('RTE_ARCH_64')
 endif
 
 config_flag_fmt = 'RTE_LIBRTE_@0@_COMMON'
-deps = ['eal', 'pci', 'bus_pci', 'mbuf']
+deps = ['eal', 'pci', 'bus_pci', 'mbuf', 'security']
 sources = files(
         'roc_ae.c',
         'roc_ae_fpm_tables.c',
@@ -51,4 +51,8 @@ sources = files(
         'roc_tim_irq.c',
         'roc_utils.c',
 )
+
+# Security common code
+sources += files('cnxk_security.c')
+
 includes += include_directories('../../bus/pci')
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 9611217..91e8b40 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -1,6 +1,10 @@
 INTERNAL {
 	global:
 
+	cnxk_ipsec_icvlen_get;
+	cnxk_ipsec_ivlen_get;
+	cnxk_ipsec_outb_rlens_get;
+	cnxk_ipsec_outb_roundup_byte;
 	cnxk_logtype_base;
 	cnxk_logtype_cpt;
 	cnxk_logtype_mbox;
@@ -10,6 +14,10 @@ INTERNAL {
 	cnxk_logtype_sso;
 	cnxk_logtype_tim;
 	cnxk_logtype_tm;
+	cnxk_ot_ipsec_inb_sa_fill;
+	cnxk_ot_ipsec_outb_sa_fill;
+	cnxk_ot_ipsec_inb_sa_valid;
+	cnxk_ot_ipsec_outb_sa_valid;
 	roc_ae_ec_grp_get;
 	roc_ae_ec_grp_put;
 	roc_ae_fpm_get;
-- 
2.7.4

[dpdk-dev] [PATCH v2 17/17] common/cnxk: add SE set key functions in roc

[Anoob Joseph]

From: Ankur Dwivedi <adwivedi@marvell.com>

The set key functions are added in roc.

Signed-off-by: Ankur Dwivedi <adwivedi@marvell.com>
---
 drivers/common/cnxk/meson.build |   1 +
 drivers/common/cnxk/roc_se.c    | 342 ++++++++++++++++++++++++++++++++++++++++
 drivers/common/cnxk/roc_se.h    |   8 +
 drivers/common/cnxk/version.map |   2 +
 4 files changed, 353 insertions(+)
 create mode 100644 drivers/common/cnxk/roc_se.c

diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build
index 1f118ef..08f54f5 100644
--- a/drivers/common/cnxk/meson.build
+++ b/drivers/common/cnxk/meson.build
@@ -44,6 +44,7 @@ sources = files(
         'roc_npc_parse.c',
         'roc_npc_utils.c',
         'roc_platform.c',
+        'roc_se.c',
         'roc_sso.c',
         'roc_sso_debug.c',
         'roc_sso_irq.c',
diff --git a/drivers/common/cnxk/roc_se.c b/drivers/common/cnxk/roc_se.c
new file mode 100644
index 0000000..3f74175
--- /dev/null
+++ b/drivers/common/cnxk/roc_se.c
@@ -0,0 +1,342 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#include "roc_api.h"
+
+static uint8_t zuc_d[32] = {0x44, 0xD7, 0x26, 0xBC, 0x62, 0x6B, 0x13, 0x5E,
+			    0x57, 0x89, 0x35, 0xE2, 0x71, 0x35, 0x09, 0xAF,
+			    0x4D, 0x78, 0x2F, 0x13, 0x6B, 0xC4, 0x1A, 0xF1,
+			    0x5E, 0x26, 0x3C, 0x4D, 0x78, 0x9A, 0x47, 0xAC};
+
+static inline void
+cpt_snow3g_key_gen(const uint8_t *ck, uint32_t *keyx)
+{
+	int i, base;
+
+	for (i = 0; i < 4; i++) {
+		base = 4 * i;
+		keyx[3 - i] = (ck[base] << 24) | (ck[base + 1] << 16) |
+			      (ck[base + 2] << 8) | (ck[base + 3]);
+		keyx[3 - i] = plt_cpu_to_be_32(keyx[3 - i]);
+	}
+}
+
+static inline int
+cpt_ciph_aes_key_validate(uint16_t key_len)
+{
+	switch (key_len) {
+	case 16:
+	case 24:
+	case 32:
+		return 0;
+	default:
+		return -1;
+	}
+}
+
+static inline int
+cpt_ciph_type_set(roc_se_cipher_type type, struct roc_se_ctx *ctx,
+		  uint16_t key_len)
+{
+	int fc_type = 0;
+
+	switch (type) {
+	case ROC_SE_PASSTHROUGH:
+		fc_type = ROC_SE_FC_GEN;
+		break;
+	case ROC_SE_DES3_CBC:
+	case ROC_SE_DES3_ECB:
+		fc_type = ROC_SE_FC_GEN;
+		break;
+	case ROC_SE_AES_CBC:
+	case ROC_SE_AES_ECB:
+	case ROC_SE_AES_CFB:
+	case ROC_SE_AES_CTR:
+	case ROC_SE_AES_GCM:
+		if (unlikely(cpt_ciph_aes_key_validate(key_len) != 0))
+			return -1;
+		fc_type = ROC_SE_FC_GEN;
+		break;
+	case ROC_SE_CHACHA20:
+		fc_type = ROC_SE_FC_GEN;
+		break;
+	case ROC_SE_AES_XTS:
+		key_len = key_len / 2;
+		if (unlikely(key_len == 24)) {
+			plt_err("Invalid AES key len for XTS");
+			return -1;
+		}
+		if (unlikely(cpt_ciph_aes_key_validate(key_len) != 0))
+			return -1;
+		fc_type = ROC_SE_FC_GEN;
+		break;
+	case ROC_SE_ZUC_EEA3:
+	case ROC_SE_SNOW3G_UEA2:
+		if (unlikely(key_len != 16))
+			return -1;
+		/* No support for AEAD yet */
+		if (unlikely(ctx->hash_type))
+			return -1;
+		fc_type = ROC_SE_PDCP;
+		break;
+	case ROC_SE_AES_CTR_EEA2:
+		fc_type = ROC_SE_PDCP;
+		break;
+	case ROC_SE_KASUMI_F8_CBC:
+	case ROC_SE_KASUMI_F8_ECB:
+		if (unlikely(key_len != 16))
+			return -1;
+		/* No support for AEAD yet */
+		if (unlikely(ctx->hash_type))
+			return -1;
+		fc_type = ROC_SE_KASUMI;
+		break;
+	default:
+		return -1;
+	}
+
+	ctx->fc_type = fc_type;
+	return 0;
+}
+
+static inline void
+cpt_ciph_aes_key_type_set(struct roc_se_context *fctx, uint16_t key_len)
+{
+	roc_se_aes_type aes_key_type = 0;
+
+	switch (key_len) {
+	case 16:
+		aes_key_type = ROC_SE_AES_128_BIT;
+		break;
+	case 24:
+		aes_key_type = ROC_SE_AES_192_BIT;
+		break;
+	case 32:
+		aes_key_type = ROC_SE_AES_256_BIT;
+		break;
+	default:
+		/* This should not happen */
+		plt_err("Invalid AES key len");
+		return;
+	}
+	fctx->enc.aes_key = aes_key_type;
+}
+
+int
+roc_se_auth_key_set(struct roc_se_ctx *se_ctx, roc_se_auth_type type,
+		    const uint8_t *key, uint16_t key_len, uint16_t mac_len)
+{
+	struct roc_se_zuc_snow3g_ctx *zs_ctx;
+	struct roc_se_kasumi_ctx *k_ctx;
+	struct roc_se_context *fctx;
+
+	if (se_ctx == NULL)
+		return -1;
+
+	zs_ctx = &se_ctx->se_ctx.zs_ctx;
+	k_ctx = &se_ctx->se_ctx.k_ctx;
+	fctx = &se_ctx->se_ctx.fctx;
+
+	if ((type >= ROC_SE_ZUC_EIA3) && (type <= ROC_SE_KASUMI_F9_ECB)) {
+		uint32_t keyx[4];
+
+		if (key_len != 16)
+			return -1;
+		/* No support for AEAD yet */
+		if (se_ctx->enc_cipher)
+			return -1;
+		/* For ZUC/SNOW3G/Kasumi */
+		switch (type) {
+		case ROC_SE_SNOW3G_UIA2:
+			se_ctx->pdcp_alg_type = ROC_SE_PDCP_ALG_TYPE_SNOW3G;
+			cpt_snow3g_key_gen(key, keyx);
+			memcpy(zs_ctx->ci_key, keyx, key_len);
+			se_ctx->fc_type = ROC_SE_PDCP;
+			se_ctx->zsk_flags = 0x1;
+			break;
+		case ROC_SE_ZUC_EIA3:
+			se_ctx->pdcp_alg_type = ROC_SE_PDCP_ALG_TYPE_ZUC;
+			memcpy(zs_ctx->ci_key, key, key_len);
+			memcpy(zs_ctx->zuc_const, zuc_d, 32);
+			se_ctx->fc_type = ROC_SE_PDCP;
+			se_ctx->zsk_flags = 0x1;
+			break;
+		case ROC_SE_AES_CMAC_EIA2:
+			se_ctx->pdcp_alg_type = ROC_SE_PDCP_ALG_TYPE_AES_CTR;
+			memcpy(zs_ctx->ci_key, key, key_len);
+			se_ctx->fc_type = ROC_SE_PDCP;
+			se_ctx->zsk_flags = 0x1;
+			break;
+		case ROC_SE_KASUMI_F9_ECB:
+			/* Kasumi ECB mode */
+			se_ctx->k_ecb = 1;
+			memcpy(k_ctx->ci_key, key, key_len);
+			se_ctx->fc_type = ROC_SE_KASUMI;
+			se_ctx->zsk_flags = 0x1;
+			break;
+		case ROC_SE_KASUMI_F9_CBC:
+			memcpy(k_ctx->ci_key, key, key_len);
+			se_ctx->fc_type = ROC_SE_KASUMI;
+			se_ctx->zsk_flags = 0x1;
+			break;
+		default:
+			return -1;
+		}
+		se_ctx->mac_len = 4;
+		se_ctx->hash_type = type;
+		return 0;
+	}
+
+	if (!se_ctx->fc_type ||
+	    (type && type != ROC_SE_GMAC_TYPE && !se_ctx->enc_cipher))
+		se_ctx->fc_type = ROC_SE_HASH_HMAC;
+
+	if (se_ctx->fc_type == ROC_SE_FC_GEN && key_len > 64)
+		return -1;
+
+	/* For GMAC auth, cipher must be NULL */
+	if (type == ROC_SE_GMAC_TYPE)
+		fctx->enc.enc_cipher = 0;
+
+	fctx->enc.hash_type = type;
+	se_ctx->hash_type = type;
+	fctx->enc.mac_len = mac_len;
+	se_ctx->mac_len = mac_len;
+
+	if (key_len) {
+		se_ctx->hmac = 1;
+		memset(se_ctx->auth_key, 0, sizeof(se_ctx->auth_key));
+		memcpy(se_ctx->auth_key, key, key_len);
+		se_ctx->auth_key_len = key_len;
+		memset(fctx->hmac.ipad, 0, sizeof(fctx->hmac.ipad));
+		memset(fctx->hmac.opad, 0, sizeof(fctx->hmac.opad));
+
+		if (key_len <= 64)
+			memcpy(fctx->hmac.opad, key, key_len);
+		fctx->enc.auth_input_type = 1;
+	}
+	return 0;
+}
+
+int
+roc_se_ciph_key_set(struct roc_se_ctx *se_ctx, roc_se_cipher_type type,
+		    const uint8_t *key, uint16_t key_len, uint8_t *salt)
+{
+	struct roc_se_context *fctx = &se_ctx->se_ctx.fctx;
+	struct roc_se_zuc_snow3g_ctx *zs_ctx;
+	uint32_t keyx[4];
+	int ret;
+
+	/* For AES-GCM, salt is taken from ctx even if IV source
+	 * is from DPTR
+	 */
+	if ((salt != NULL) && (type == ROC_SE_AES_GCM)) {
+		memcpy(fctx->enc.encr_iv, salt, 4);
+		/* Assuming it was just salt update
+		 * and nothing else
+		 */
+		if (key == NULL)
+			return 0;
+	}
+
+	ret = cpt_ciph_type_set(type, se_ctx, key_len);
+	if (unlikely(ret))
+		return -1;
+
+	if (se_ctx->fc_type == ROC_SE_FC_GEN) {
+		/*
+		 * We need to always say IV is from DPTR as user can
+		 * sometimes iverride IV per operation.
+		 */
+		fctx->enc.iv_source = ROC_SE_FROM_DPTR;
+
+		if (se_ctx->auth_key_len > 64)
+			return -1;
+	}
+
+	switch (type) {
+	case ROC_SE_PASSTHROUGH:
+		se_ctx->enc_cipher = 0;
+		fctx->enc.enc_cipher = 0;
+		goto success;
+	case ROC_SE_DES3_CBC:
+		/* CPT performs DES using 3DES with the 8B DES-key
+		 * replicated 2 more times to match the 24B 3DES-key.
+		 * Eg. If org. key is "0x0a 0x0b", then new key is
+		 * "0x0a 0x0b 0x0a 0x0b 0x0a 0x0b"
+		 */
+		if (key_len == 8) {
+			/* Skipping the first 8B as it will be copied
+			 * in the regular code flow
+			 */
+			memcpy(fctx->enc.encr_key + key_len, key, key_len);
+			memcpy(fctx->enc.encr_key + 2 * key_len, key, key_len);
+		}
+		break;
+	case ROC_SE_DES3_ECB:
+		/* For DES3_ECB IV need to be from CTX. */
+		fctx->enc.iv_source = ROC_SE_FROM_CTX;
+		break;
+	case ROC_SE_AES_CBC:
+	case ROC_SE_AES_ECB:
+	case ROC_SE_AES_CFB:
+	case ROC_SE_AES_CTR:
+	case ROC_SE_CHACHA20:
+		cpt_ciph_aes_key_type_set(fctx, key_len);
+		break;
+	case ROC_SE_AES_GCM:
+		cpt_ciph_aes_key_type_set(fctx, key_len);
+		break;
+	case ROC_SE_AES_XTS:
+		key_len = key_len / 2;
+		cpt_ciph_aes_key_type_set(fctx, key_len);
+
+		/* Copy key2 for XTS into ipad */
+		memset(fctx->hmac.ipad, 0, sizeof(fctx->hmac.ipad));
+		memcpy(fctx->hmac.ipad, &key[key_len], key_len);
+		break;
+	case ROC_SE_SNOW3G_UEA2:
+		se_ctx->pdcp_alg_type = ROC_SE_PDCP_ALG_TYPE_SNOW3G;
+		cpt_snow3g_key_gen(key, keyx);
+		memcpy(se_ctx->se_ctx.zs_ctx.ci_key, keyx, key_len);
+		se_ctx->zsk_flags = 0;
+		goto success;
+	case ROC_SE_ZUC_EEA3:
+		zs_ctx = &se_ctx->se_ctx.zs_ctx;
+		se_ctx->pdcp_alg_type = ROC_SE_PDCP_ALG_TYPE_ZUC;
+		memcpy(zs_ctx->ci_key, key, key_len);
+		memcpy(zs_ctx->zuc_const, zuc_d, 32);
+		se_ctx->zsk_flags = 0;
+		goto success;
+	case ROC_SE_AES_CTR_EEA2:
+		se_ctx->pdcp_alg_type = ROC_SE_PDCP_ALG_TYPE_AES_CTR;
+		memcpy(se_ctx->se_ctx.zs_ctx.ci_key, key, key_len);
+		se_ctx->zsk_flags = 0;
+		goto success;
+	case ROC_SE_KASUMI_F8_ECB:
+		se_ctx->k_ecb = 1;
+		memcpy(se_ctx->se_ctx.k_ctx.ci_key, key, key_len);
+		se_ctx->zsk_flags = 0;
+		goto success;
+	case ROC_SE_KASUMI_F8_CBC:
+		memcpy(se_ctx->se_ctx.k_ctx.ci_key, key, key_len);
+		se_ctx->zsk_flags = 0;
+		goto success;
+	default:
+		return -1;
+	}
+
+	/* Only for ROC_SE_FC_GEN case */
+
+	/* For GMAC auth, cipher must be NULL */
+	if (se_ctx->hash_type != ROC_SE_GMAC_TYPE)
+		fctx->enc.enc_cipher = type;
+
+	memcpy(fctx->enc.encr_key, key, key_len);
+
+success:
+	se_ctx->enc_cipher = type;
+
+	return 0;
+}
diff --git a/drivers/common/cnxk/roc_se.h b/drivers/common/cnxk/roc_se.h
index ffae065..43a40dd 100644
--- a/drivers/common/cnxk/roc_se.h
+++ b/drivers/common/cnxk/roc_se.h
@@ -264,4 +264,12 @@ struct roc_se_ctx {
 	uint8_t auth_key[1024];
 };
 
+int __roc_api roc_se_auth_key_set(struct roc_se_ctx *se_ctx,
+				  roc_se_auth_type type, const uint8_t *key,
+				  uint16_t key_len, uint16_t mac_len);
+
+int __roc_api roc_se_ciph_key_set(struct roc_se_ctx *se_ctx,
+				  roc_se_cipher_type type, const uint8_t *key,
+				  uint16_t key_len, uint8_t *salt);
+
 #endif /* __ROC_SE_H__ */
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 91e8b40..9089717 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -47,6 +47,8 @@ INTERNAL {
 	roc_idev_npa_nix_get;
 	roc_idev_num_lmtlines_get;
 	roc_model;
+	roc_se_auth_key_set;
+	roc_se_ciph_key_set;
 	roc_nix_cq_dump;
 	roc_nix_cq_fini;
 	roc_nix_cq_init;
-- 
2.7.4

Re: [dpdk-dev] [PATCH v2 00/17] Add CPT in Marvell CNXK common driver

[Akhil Goyal]

> This patchset adds initial support for CPT in common code for Marvell CN10K
> SoC.
> 
> CPT is the hardware cryptographic block available in 'cnxk' family SoC. CPT,
> with its microcoded engines can support symmetric, asymmetric and IPsec
> operations. CPT can associate with NIX (rte_ethdev) to enable inline IPsec
> functionality. Similarly, CPT can associate with SSO (rte_eventdev) to
> enable crypto adapter.
> 
> Based on CNXK common driver, new crypto PMDs would be added under
> 'crypto/cnxk'.
> 
> Changes in v2
> - Moved FPM & EC tables to RoC
> - Moved set_key routines to RoC
> - Added inline IPsec required mboxes and framework
> - Added security common code
> - Added plt_dp_* log based on Akhil's comment
> 
Series Acked-by: Akhil Goyal <gakhil@marvell.com>

Re: [dpdk-dev] [PATCH v2 00/17] Add CPT in Marvell CNXK common driver

[Akhil Goyal]

> > This patchset adds initial support for CPT in common code for Marvell
> CN10K
> > SoC.
> >
> > CPT is the hardware cryptographic block available in 'cnxk' family SoC. CPT,
> > with its microcoded engines can support symmetric, asymmetric and IPsec
> > operations. CPT can associate with NIX (rte_ethdev) to enable inline IPsec
> > functionality. Similarly, CPT can associate with SSO (rte_eventdev) to
> > enable crypto adapter.
> >
> > Based on CNXK common driver, new crypto PMDs would be added under
> > 'crypto/cnxk'.
> >
> > Changes in v2
> > - Moved FPM & EC tables to RoC
> > - Moved set_key routines to RoC
> > - Added inline IPsec required mboxes and framework
> > - Added security common code
> > - Added plt_dp_* log based on Akhil's comment
> >
> Series Acked-by: Akhil Goyal <gakhil@marvell.com>

A couple of small issues fixed while applying in patch title/description.

Applied to dpdk-next-crypto

Thanks.