From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D65ABA0C4A; Wed, 7 Jul 2021 15:26:24 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id AF7EC41535; Wed, 7 Jul 2021 15:26:00 +0200 (CEST) Received: from lb.pantheon.sk (lb.pantheon.sk [46.229.239.20]) by mails.dpdk.org (Postfix) with ESMTP id 76BD241529 for ; Wed, 7 Jul 2021 15:25:57 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by lb.pantheon.sk (Postfix) with ESMTP id DE565E757D; Wed, 7 Jul 2021 15:25:55 +0200 (CEST) X-Virus-Scanned: amavisd-new at siecit.sk Received: from lb.pantheon.sk ([127.0.0.1]) by localhost (lb.pantheon.sk [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id UDUHmwjuSe0Y; Wed, 7 Jul 2021 15:25:53 +0200 (CEST) Received: from service-node1.lab.pantheon.local (unknown [46.229.239.141]) by lb.pantheon.sk (Postfix) with ESMTP id C2F54E7575; Wed, 7 Jul 2021 15:25:48 +0200 (CEST) From: =?UTF-8?q?Juraj=20Linke=C5=A1?= To: thomas@monjalon.net, david.marchand@redhat.com, bruce.richardson@intel.com, aconole@redhat.com, maicolgabriel@hotmail.com, Honnappa.Nagarahalli@arm.com, Ruifeng.Wang@arm.com, ajit.khaparde@broadcom.com, ferruh.yigit@intel.com, jerinjacobk@gmail.com, jerinj@marvell.com Cc: juraj.linkes@pantheon.tech, dev@dpdk.org Date: Wed, 7 Jul 2021 15:25:41 +0200 Message-Id: <1625664343-26498-6-git-send-email-juraj.linkes@pantheon.tech> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1625664343-26498-1-git-send-email-juraj.linkes@pantheon.tech> References: <1619095749-7948-1-git-send-email-juraj.linkes@pantheon.tech> <1625664343-26498-1-git-send-email-juraj.linkes@pantheon.tech> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [dpdk-dev] [PATCH v18 5/7] build: add aarch32 meson build flags X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add aarch32 armv8 SoC to build config. Also modify how arm flags are updated in meson build - for 32-bit build, update only if cross-compiling. Signed-off-by: Juraj Linkeš Acked-by: Ruifeng Wang --- config/arm/meson.build | 88 +++++++++++++++++++++++++++++------------- 1 file changed, 61 insertions(+), 27 deletions(-) diff --git a/config/arm/meson.build b/config/arm/meson.build index 9b147c0b93..4170b14c80 100644 --- a/config/arm/meson.build +++ b/config/arm/meson.build @@ -24,9 +24,9 @@ flags_common = [ ] ## Part numbers are specific to Arm implementers -# implementer specific aarch64 flags have middle priority +# implementer specific armv8 flags have middle priority # (will overwrite common flags) -# part number specific aarch64 flags have higher priority +# part number specific armv8 flags have higher priority # (will overwrite both common and implementer specific flags) implementer_generic = { 'description': 'Generic armv8', @@ -37,7 +37,18 @@ implementer_generic = { ['RTE_MAX_NUMA_NODES', 4] ], 'part_number_config': { - 'generic': {'machine_args': ['-march=armv8-a+crc', '-moutline-atomics']} + 'generic': { + 'machine_args': ['-march=armv8-a+crc', '-moutline-atomics'] + }, + 'generic_aarch32': { + 'machine_args': ['-march=armv8-a', '-mfpu=neon'], + 'flags': [ + ['RTE_ARCH_ARM_NEON_MEMCPY', false], + ['RTE_ARCH_STRICT_ALIGN', true], + ['RTE_ARCH_ARMv8_AARCH32', true], + ['RTE_CACHE_LINE_SIZE', 64] + ] + } } } @@ -193,14 +204,20 @@ implementers = { '0x51': implementer_qualcomm } -# SoC specific aarch64 flags have the highest priority +# SoC specific armv8 flags have the highest priority # (will overwrite all other flags) soc_generic = { - 'description': 'Generic un-optimized build for all aarch64 machines', + 'description': 'Generic un-optimized build for armv8 aarch64 exec mode', 'implementer': 'generic', 'part_number': 'generic' } +soc_generic_aarch32 = { + 'description': 'Generic un-optimized build for armv8 aarch32 exec mode', + 'implementer': 'generic', + 'part_number': 'generic_aarch32' +} + soc_armada = { 'description': 'Marvell ARMADA', 'implementer': '0x41', @@ -330,28 +347,30 @@ soc_thunderxt88 = { ''' Start of SoCs list -generic: Generic un-optimized build for all aarch64 machines. -armada: Marvell ARMADA -bluefield: NVIDIA BlueField -centriq2400: Qualcomm Centriq 2400 -cn10k: Marvell OCTEON 10 -dpaa: NXP DPAA -emag: Ampere eMAG -graviton2: AWS Graviton2 -kunpeng920: HiSilicon Kunpeng 920 -kunpeng930: HiSilicon Kunpeng 930 -n1sdp: Arm Neoverse N1SDP -n2: Arm Neoverse N2 -octeontx2: Marvell OCTEON TX2 -stingray: Broadcom Stingray -thunderx2: Marvell ThunderX2 T99 -thunderxt88: Marvell ThunderX T88 +generic: Generic un-optimized build for armv8 aarch64 execution mode. +generic_aarch32: Generic un-optimized build for armv8 aarch32 execution mode. +armada: Marvell ARMADA +bluefield: NVIDIA BlueField +centriq2400: Qualcomm Centriq 2400 +cn10k: Marvell OCTEON 10 +dpaa: NXP DPAA +emag: Ampere eMAG +graviton2: AWS Graviton2 +kunpeng920: HiSilicon Kunpeng 920 +kunpeng930: HiSilicon Kunpeng 930 +n1sdp: Arm Neoverse N1SDP +n2: Arm Neoverse N2 +octeontx2: Marvell OCTEON TX2 +stingray: Broadcom Stingray +thunderx2: Marvell ThunderX2 T99 +thunderxt88: Marvell ThunderX T88 End of SoCs list ''' # The string above is included in the documentation, keep it in sync with the # SoCs list below. socs = { 'generic': soc_generic, + 'generic_aarch32': soc_generic_aarch32, 'armada': soc_armada, 'bluefield': soc_bluefield, 'centriq2400': soc_centriq2400, @@ -372,14 +391,28 @@ socs = { dpdk_conf.set('RTE_ARCH_ARM', 1) dpdk_conf.set('RTE_FORCE_INTRINSICS', 1) +update_flags = false +soc_flags = [] if dpdk_conf.get('RTE_ARCH_32') - # armv7 build + # 32-bit build dpdk_conf.set('RTE_CACHE_LINE_SIZE', 64) - dpdk_conf.set('RTE_ARCH_ARMv7', 1) - # the minimum architecture supported, armv7-a, needs the following, - machine_args += '-mfpu=neon' + if meson.is_cross_build() + update_flags = true + soc = meson.get_cross_property('platform', '') + if soc == '' + error('Arm SoC must be specified in the cross file.') + endif + soc_config = socs.get(soc, {'not_supported': true}) + flags_common = [] + else + # armv7 build + dpdk_conf.set('RTE_ARCH_ARMv7', true) + # the minimum architecture supported, armv7-a, needs the following, + machine_args += '-mfpu=neon' + endif else - # aarch64 build + # armv8 build + update_flags = true soc = get_option('platform') soc_config = {} if not meson.is_cross_build() @@ -415,8 +448,9 @@ else endif soc_config = socs.get(soc, {'not_supported': true}) endif +endif - soc_flags = [] +if update_flags if soc_config.has_key('not_supported') error('SoC @0@ not supported.'.format(soc)) elif soc_config != {} -- 2.20.1