From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C23A4A0C4A; Sat, 17 Jul 2021 04:03:59 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id CB13D4116E; Sat, 17 Jul 2021 04:03:50 +0200 (CEST) Received: from szxga02-in.huawei.com (szxga02-in.huawei.com [45.249.212.188]) by mails.dpdk.org (Postfix) with ESMTP id 0936A4068C for ; Sat, 17 Jul 2021 04:03:45 +0200 (CEST) Received: from dggeme756-chm.china.huawei.com (unknown [172.30.72.55]) by szxga02-in.huawei.com (SkyGuard) with ESMTP id 4GRWX83d7Sz7tFT for ; Sat, 17 Jul 2021 10:00:08 +0800 (CST) Received: from localhost.localdomain (10.69.192.56) by dggeme756-chm.china.huawei.com (10.3.19.102) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Sat, 17 Jul 2021 10:03:43 +0800 From: "Min Hu (Connor)" To: CC: , Date: Sat, 17 Jul 2021 10:02:52 +0800 Message-ID: <1626487376-30038-5-git-send-email-humin29@huawei.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1626487376-30038-1-git-send-email-humin29@huawei.com> References: <1626487376-30038-1-git-send-email-humin29@huawei.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.69.192.56] X-ClientProxiedBy: dggems701-chm.china.huawei.com (10.3.19.178) To dggeme756-chm.china.huawei.com (10.3.19.102) X-CFilter-Loop: Reflected Subject: [dpdk-dev] [PATCH 4/8] net/hns3: fix the timing issue of clearing interrupt source X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: HongBo Zheng Currently, the PF/VF does not clear the interrupt source immediately after receiving the interrupt. As a result, if the second interrupt task is triggered when processing the first interrupt task, clearing the interrupt source before exiting will clear the interrupt sources of the two tasks at the same time. As a result, no interrupt is triggered for the second task. Clearing interrupt source immediately after checking event cause ensures that: 1. Even if two interrupt tasks are triggered at the same time, they can be processed. 2. If the second task is triggered during the processing of the first task and the interrupt source is not cleared, the interrupt is reported after vector0 is enabled. Fixes: a5475d61fa34 ("net/hns3: support VF") Fixes: 3988ab0eee52 ("net/hns3: add abnormal interrupt process") Cc: stable@dpdk.org Signed-off-by: HongBo Zheng Signed-off-by: Min Hu (Connor) --- drivers/net/hns3/hns3_ethdev.c | 2 +- drivers/net/hns3/hns3_ethdev_vf.c | 5 ++--- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index 3699b56..f994c28 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -317,6 +317,7 @@ hns3_interrupt_handler(void *param) vector0_int = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG); ras_int = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG); cmdq_int = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG); + hns3_clear_event_cause(hw, event_cause, clearval); /* vector 0 interrupt is shared with reset and mailbox source events. */ if (event_cause == HNS3_VECTOR0_EVENT_ERR) { hns3_warn(hw, "received interrupt: vector0_int_stat:0x%x " @@ -335,7 +336,6 @@ hns3_interrupt_handler(void *param) vector0_int, ras_int, cmdq_int); } - hns3_clear_event_cause(hw, event_cause, clearval); /* Enable interrupt if it is not cause by reset */ hns3_pf_enable_irq0(hw); } diff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c index 8f3be64..de659c0 100644 --- a/drivers/net/hns3/hns3_ethdev_vf.c +++ b/drivers/net/hns3/hns3_ethdev_vf.c @@ -1116,6 +1116,8 @@ hns3vf_interrupt_handler(void *param) /* Read out interrupt causes */ event_cause = hns3vf_check_event_cause(hns, &clearval); + /* Clear interrupt causes */ + hns3vf_clear_event_cause(hw, clearval); switch (event_cause) { case HNS3VF_VECTOR0_EVENT_RST: @@ -1128,9 +1130,6 @@ hns3vf_interrupt_handler(void *param) break; } - /* Clear interrupt causes */ - hns3vf_clear_event_cause(hw, clearval); - /* Enable interrupt */ hns3vf_enable_irq0(hw); } -- 2.7.4