From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id F2937A0C45; Fri, 13 Aug 2021 18:51:45 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 98C1741275; Fri, 13 Aug 2021 18:51:37 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mails.dpdk.org (Postfix) with ESMTP id 3508440DF4 for ; Fri, 13 Aug 2021 18:51:35 +0200 (CEST) X-IronPort-AV: E=McAfee;i="6200,9189,10075"; a="215320177" X-IronPort-AV: E=Sophos;i="5.84,319,1620716400"; d="scan'208";a="215320177" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Aug 2021 09:51:33 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.84,319,1620716400"; d="scan'208";a="486025100" Received: from unknown (HELO icx-npg-scs1-cp1.localdomain) ([10.233.180.245]) by fmsmga008.fm.intel.com with ESMTP; 13 Aug 2021 09:51:33 -0700 From: Nicolas Chautru To: dev@dpdk.org, gakhil@marvell.com Cc: thomas@monjalon.net, trix@redhat.com, hemant.agrawal@nxp.com, mingshan.zhang@intel.com, Nicolas Chautru Date: Fri, 13 Aug 2021 09:51:21 -0700 Message-Id: <1628873485-30596-3-git-send-email-nicolas.chautru@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1628873485-30596-1-git-send-email-nicolas.chautru@intel.com> References: <1628873485-30596-1-git-send-email-nicolas.chautru@intel.com> Subject: [dpdk-dev] [PATCH v1 2/6] baseband/turbo_sw: add support for CRC16 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This is to support the case for operation where CRC16 is to be appended or checked. Signed-off-by: Nicolas Chautru --- doc/guides/rel_notes/release_21_11.rst | 3 +++ drivers/baseband/turbo_sw/bbdev_turbo_software.c | 17 +++++++++++++++++ 2 files changed, 20 insertions(+) diff --git a/doc/guides/rel_notes/release_21_11.rst b/doc/guides/rel_notes/release_21_11.rst index 69dd518..8ca59b7 100644 --- a/doc/guides/rel_notes/release_21_11.rst +++ b/doc/guides/rel_notes/release_21_11.rst @@ -55,6 +55,9 @@ New Features Also, make sure to start the actual text at the margin. ======================================================= +* **Updated the turbo_sw bbdev PMD.** + + Added support for more comprehensive CRC options. Removed Items ------------- diff --git a/drivers/baseband/turbo_sw/bbdev_turbo_software.c b/drivers/baseband/turbo_sw/bbdev_turbo_software.c index 77e9a2e..e570044 100644 --- a/drivers/baseband/turbo_sw/bbdev_turbo_software.c +++ b/drivers/baseband/turbo_sw/bbdev_turbo_software.c @@ -199,6 +199,7 @@ struct turbo_sw_queue { .cap.ldpc_enc = { .capability_flags = RTE_BBDEV_LDPC_RATE_MATCH | + RTE_BBDEV_LDPC_CRC_16_ATTACH | RTE_BBDEV_LDPC_CRC_24A_ATTACH | RTE_BBDEV_LDPC_CRC_24B_ATTACH, .num_buffers_src = @@ -211,6 +212,7 @@ struct turbo_sw_queue { .type = RTE_BBDEV_OP_LDPC_DEC, .cap.ldpc_dec = { .capability_flags = + RTE_BBDEV_LDPC_CRC_TYPE_16_CHECK | RTE_BBDEV_LDPC_CRC_TYPE_24B_CHECK | RTE_BBDEV_LDPC_CRC_TYPE_24A_CHECK | RTE_BBDEV_LDPC_CRC_TYPE_24B_DROP | @@ -880,6 +882,12 @@ struct turbo_sw_queue { crc_req.len = in_length_in_bits - 24; crc_resp.data = q->enc_in; bblib_lte_crc24b_gen(&crc_req, &crc_resp); + } else if (enc->op_flags & RTE_BBDEV_LDPC_CRC_16_ATTACH) { + rte_memcpy(q->enc_in, in, in_length_in_bytes - 2); + crc_req.data = in; + crc_req.len = in_length_in_bits - 16; + crc_resp.data = q->enc_in; + bblib_lte_crc16_gen(&crc_req, &crc_resp); } else rte_memcpy(q->enc_in, in, in_length_in_bytes); @@ -1492,6 +1500,15 @@ struct turbo_sw_queue { if (!crc_resp.check_passed) op->status |= 1 << RTE_BBDEV_CRC_ERROR; } + if (check_bit(dec->op_flags, RTE_BBDEV_LDPC_CRC_TYPE_16_CHECK)) { + crc_req.data = adapter_input; + crc_req.len = K - dec->n_filler - 16; + crc_resp.check_passed = false; + crc_resp.data = adapter_input; + bblib_lte_crc16_check(&crc_req, &crc_resp); + if (!crc_resp.check_passed) + op->status |= 1 << RTE_BBDEV_CRC_ERROR; + } #ifdef RTE_BBDEV_OFFLOAD_COST q_stats->acc_offload_cycles += rte_rdtsc_precise() - start_time; -- 1.8.3.1