From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from out3-smtp.messagingengine.com (out3-smtp.messagingengine.com [66.111.4.27]) by dpdk.org (Postfix) with ESMTP id 35F6E727A for ; Sun, 28 Jan 2018 08:33:04 +0100 (CET) Received: from compute1.internal (compute1.nyi.internal [10.202.2.41]) by mailout.nyi.internal (Postfix) with ESMTP id A8F1B20DCE; Sun, 28 Jan 2018 02:33:03 -0500 (EST) Received: from frontend2 ([10.202.2.161]) by compute1.internal (MEProxy); Sun, 28 Jan 2018 02:33:03 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=monjalon.net; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to:x-me-sender :x-me-sender:x-sasl-enc; s=mesmtp; bh=FXoC7Kobczyyh0hNEh9+zY1yjl XEjHAosc6qmpDGDpA=; b=mVcHI9B73OYderodF25aTs0SD3NFt7sYiQPNIo7QyW wsm+eOhokXq5UOlWAxKmjuJ7iiy4BnXhwOv0KEHXCSuX3y9UMLR17J3hzFylkacR Fg12HWa2CxURYG7um7jw9IA9T5q4gC6AToDzlnSXwHaHAWnvdLp2KkaoABXVJkFJ E= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-sender:x-me-sender:x-sasl-enc; s=fm1; bh=FXoC7K obczyyh0hNEh9+zY1yjlXEjHAosc6qmpDGDpA=; b=K9hsJUzBsRJ4ig1AYKVf3X cbYKxY9TMFATLujiKiRCQ7LM72572lPTOCKtfBniHyRJCEp9VsMwBTJS+mR/hAsI ejYf0xT5q+cdJ2VYgRGrtR5hkpLvwA8gJIUyiY0+FgzzT40PNFyza5DUzcyBMT1h pfaqxGmzSiVs/HlSW1Bp/wHdNOKjRgRXl+pAm/uZQieNfTPWlxIcjLTMI2/b/fI5 Y/YJPqsr7C1g3H3SXjnvLoK4N4IQEEy09d1zojQC6ExWGFWBEusJxprTrnMsXJs+ TNWEfSpHhYCH/a+H/YqhgFJZFqUYCP1ZmT6P7H0HlI5xNUrho0rjVc6jjVEws6dA == X-ME-Sender: Received: from xps.localnet (207.83.136.77.rev.sfr.net [77.136.83.207]) by mail.messagingengine.com (Postfix) with ESMTPA id 0B16924406; Sun, 28 Jan 2018 02:33:03 -0500 (EST) From: Thomas Monjalon To: Yongseok Koh Cc: dev@dpdk.org, adrien.mazarguil@6wind.com, nelio.laranjeiro@6wind.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, chaozhu@linux.vnet.ibm.com, jerin.jacob@caviumnetworks.com, jianbo.liu@arm.com, arybchenko@solarflare.com, shahafs@mellanox.com Date: Sun, 28 Jan 2018 08:32:14 +0100 Message-ID: <1630418.Wd0Y6PPR5S@xps> In-Reply-To: <20180125210250.38233-1-yskoh@mellanox.com> References: <20180119004430.15305-1-yskoh@mellanox.com> <20180125210250.38233-1-yskoh@mellanox.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Subject: Re: [dpdk-dev] [PATCH v4 0/9] introduce coherent I/O memory barriers X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 28 Jan 2018 07:33:04 -0000 25/01/2018 22:02, Yongseok Koh: > This patchset is to introduce coherent I/O memory barriers, which could be more > efficient for coherent memory between I/O device and CPU, especially for ARMv8. > > v4: > * rename barriers to "coherent I/O memory barrier". > * Make groups for various barriers in Doxygen doc. > > v3: > * add more detailed comments about the new memory barriers. > > v2: > * introduce DMA memory barriers. > > Yongseok Koh (9): > eal: add Doxygen grouping for memory barriers > eal: introduce coherent I/O memory barriers > eal/x86: define coherent I/O memory barriers > eal/ppc64: define coherent I/O memory barriers > eal/armv7: define coherent I/O memory barriers > eal/arm64: define coherent I/O memory barriers > net/mlx5: remove unnecessary memory barrier > net/mlx5: replace I/O memory barrier with coherent version > net/mlx5: fix synchronization on polling Rx completions Applied, thanks