From: <skoteshwar@marvell.com>
To: Nithin Dabilpuram <ndabilpuram@marvell.com>,
Kiran Kumar K <kirankumark@marvell.com>,
Sunil Kumar Kori <skori@marvell.com>,
Satha Rao <skoteshwar@marvell.com>
Cc: <dev@dpdk.org>
Subject: [dpdk-dev] [PATCH 4/8] common/cnxk: handle packet mode shaper limits
Date: Wed, 1 Sep 2021 13:10:32 -0400 [thread overview]
Message-ID: <1630516236-10526-4-git-send-email-skoteshwar@marvell.com> (raw)
In-Reply-To: <1630516236-10526-1-git-send-email-skoteshwar@marvell.com>
From: Satha Rao <skoteshwar@marvell.com>
Add new macros to reflect HW shaper PPS limits. New API to validate
input rates for packet mode. Increase adjust value to support lesser
PPS (<61).
Signed-off-by: Satha Rao <skoteshwar@marvell.com>
---
drivers/common/cnxk/hw/nix.h | 3 +
drivers/common/cnxk/roc_nix_priv.h | 1 +
drivers/common/cnxk/roc_nix_tm_ops.c | 76 ++++++++++++++++++--------
drivers/common/cnxk/roc_nix_tm_utils.c | 4 +-
4 files changed, 60 insertions(+), 24 deletions(-)
diff --git a/drivers/common/cnxk/hw/nix.h b/drivers/common/cnxk/hw/nix.h
index d2054385c2..6a0eb019ac 100644
--- a/drivers/common/cnxk/hw/nix.h
+++ b/drivers/common/cnxk/hw/nix.h
@@ -2133,6 +2133,9 @@ struct nix_lso_format {
NIX_TM_SHAPER_RATE(NIX_TM_MAX_RATE_EXPONENT, NIX_TM_MAX_RATE_MANTISSA, \
0)
+#define NIX_TM_MIN_SHAPER_PPS_RATE 25
+#define NIX_TM_MAX_SHAPER_PPS_RATE (100ul << 20)
+
/* NIX burst limits */
#define NIX_TM_MAX_BURST_EXPONENT 0xful
#define NIX_TM_MAX_BURST_MANTISSA 0x7ffful
diff --git a/drivers/common/cnxk/roc_nix_priv.h b/drivers/common/cnxk/roc_nix_priv.h
index cc8e822427..3412bf25e5 100644
--- a/drivers/common/cnxk/roc_nix_priv.h
+++ b/drivers/common/cnxk/roc_nix_priv.h
@@ -90,6 +90,7 @@ struct nix_tm_shaper_profile {
struct nix_tm_tb commit;
struct nix_tm_tb peak;
int32_t pkt_len_adj;
+ int32_t pkt_mode_adj;
bool pkt_mode;
uint32_t id;
void (*free_fn)(void *profile);
diff --git a/drivers/common/cnxk/roc_nix_tm_ops.c b/drivers/common/cnxk/roc_nix_tm_ops.c
index a313023be2..69d58376ec 100644
--- a/drivers/common/cnxk/roc_nix_tm_ops.c
+++ b/drivers/common/cnxk/roc_nix_tm_ops.c
@@ -77,6 +77,51 @@ roc_nix_tm_free_resources(struct roc_nix *roc_nix, bool hw_only)
return nix_tm_free_resources(roc_nix, BIT(ROC_NIX_TM_USER), hw_only);
}
+static int
+nix_tm_adjust_shaper_pps_rate(struct nix_tm_shaper_profile *profile)
+{
+ uint64_t min_rate = profile->commit.rate;
+
+ if (!profile->pkt_mode)
+ return 0;
+
+ profile->pkt_mode_adj = 1;
+
+ if (profile->commit.rate &&
+ (profile->commit.rate < NIX_TM_MIN_SHAPER_PPS_RATE ||
+ profile->commit.rate > NIX_TM_MAX_SHAPER_PPS_RATE))
+ return NIX_ERR_TM_INVALID_COMMIT_RATE;
+
+ if (profile->peak.rate &&
+ (profile->peak.rate < NIX_TM_MIN_SHAPER_PPS_RATE ||
+ profile->peak.rate > NIX_TM_MAX_SHAPER_PPS_RATE))
+ return NIX_ERR_TM_INVALID_PEAK_RATE;
+
+ if (profile->peak.rate && min_rate > profile->peak.rate)
+ min_rate = profile->peak.rate;
+
+ /* Each packet accomulate single count, whereas HW
+ * considers each unit as Byte, so we need convert
+ * user pps to bps
+ */
+ profile->commit.rate = profile->commit.rate * 8;
+ profile->peak.rate = profile->peak.rate * 8;
+ min_rate = min_rate * 8;
+
+ if (min_rate && (min_rate < NIX_TM_MIN_SHAPER_RATE)) {
+ int adjust = NIX_TM_MIN_SHAPER_RATE / min_rate;
+
+ if (adjust > NIX_TM_LENGTH_ADJUST_MAX)
+ return NIX_ERR_TM_SHAPER_PKT_LEN_ADJUST;
+
+ profile->pkt_mode_adj += adjust;
+ profile->commit.rate += (adjust * profile->commit.rate);
+ profile->peak.rate += (adjust * profile->peak.rate);
+ }
+
+ return 0;
+}
+
static int
nix_tm_shaper_profile_add(struct roc_nix *roc_nix,
struct nix_tm_shaper_profile *profile, int skip_ins)
@@ -86,8 +131,13 @@ nix_tm_shaper_profile_add(struct roc_nix *roc_nix,
uint64_t min_burst, max_burst;
uint64_t peak_rate, peak_sz;
uint32_t id;
+ int rc;
id = profile->id;
+ rc = nix_tm_adjust_shaper_pps_rate(profile);
+ if (rc)
+ return rc;
+
commit_rate = profile->commit.rate;
commit_sz = profile->commit.size;
peak_rate = profile->peak.rate;
@@ -157,17 +207,8 @@ roc_nix_tm_shaper_profile_add(struct roc_nix *roc_nix,
profile->ref_cnt = 0;
profile->id = roc_profile->id;
- if (roc_profile->pkt_mode) {
- /* Each packet accomulate single count, whereas HW
- * considers each unit as Byte, so we need convert
- * user pps to bps
- */
- profile->commit.rate = roc_profile->commit_rate * 8;
- profile->peak.rate = roc_profile->peak_rate * 8;
- } else {
- profile->commit.rate = roc_profile->commit_rate;
- profile->peak.rate = roc_profile->peak_rate;
- }
+ profile->commit.rate = roc_profile->commit_rate;
+ profile->peak.rate = roc_profile->peak_rate;
profile->commit.size = roc_profile->commit_sz;
profile->peak.size = roc_profile->peak_sz;
profile->pkt_len_adj = roc_profile->pkt_len_adj;
@@ -185,17 +226,8 @@ roc_nix_tm_shaper_profile_update(struct roc_nix *roc_nix,
profile = (struct nix_tm_shaper_profile *)roc_profile->reserved;
- if (roc_profile->pkt_mode) {
- /* Each packet accomulate single count, whereas HW
- * considers each unit as Byte, so we need convert
- * user pps to bps
- */
- profile->commit.rate = roc_profile->commit_rate * 8;
- profile->peak.rate = roc_profile->peak_rate * 8;
- } else {
- profile->commit.rate = roc_profile->commit_rate;
- profile->peak.rate = roc_profile->peak_rate;
- }
+ profile->commit.rate = roc_profile->commit_rate;
+ profile->peak.rate = roc_profile->peak_rate;
profile->commit.size = roc_profile->commit_sz;
profile->peak.size = roc_profile->peak_sz;
diff --git a/drivers/common/cnxk/roc_nix_tm_utils.c b/drivers/common/cnxk/roc_nix_tm_utils.c
index 00604b10d3..83306248e8 100644
--- a/drivers/common/cnxk/roc_nix_tm_utils.c
+++ b/drivers/common/cnxk/roc_nix_tm_utils.c
@@ -628,8 +628,8 @@ nix_tm_shaper_reg_prep(struct nix_tm_node *node,
memset(&pir, 0, sizeof(pir));
nix_tm_shaper_conf_get(profile, &cir, &pir);
- if (node->pkt_mode)
- adjust = 1;
+ if (profile && node->pkt_mode)
+ adjust = profile->pkt_mode_adj;
else if (profile)
adjust = profile->pkt_len_adj;
--
2.25.1
next prev parent reply other threads:[~2021-09-01 17:11 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-01 17:10 [dpdk-dev] [PATCH 1/8] common/cnxk: use different macros for sdp and lbk max frames skoteshwar
2021-09-01 17:10 ` [dpdk-dev] [PATCH 2/8] common/cnxk: flush smq skoteshwar
2021-09-01 17:10 ` [dpdk-dev] [PATCH 3/8] common/cnxk: increase sched weight and shaper burst limit skoteshwar
2021-09-01 17:10 ` skoteshwar [this message]
2021-09-01 17:10 ` [dpdk-dev] [PATCH 5/8] common/cnxk: handler to get rte tm error type skoteshwar
2021-09-01 17:10 ` [dpdk-dev] [PATCH 6/8] common/cnxk: set of handlers to get tm hierarchy internals skoteshwar
2021-09-01 17:10 ` [dpdk-dev] [PATCH 7/8] net/cnxk: tm capabilities and queue rate limit handlers skoteshwar
2021-09-01 17:10 ` [dpdk-dev] [PATCH 8/8] net/cnxk: tm shaper and node operations skoteshwar
2021-09-16 7:17 ` [dpdk-dev] [PATCH 1/8] common/cnxk: use different macros for sdp and lbk max frames Jerin Jacob
2021-09-18 14:31 ` [dpdk-dev] [PATCH v2 0/8] Add TM Support for CN9K and CN10K skoteshwar
2021-09-18 14:31 ` [dpdk-dev] [PATCH v2 1/8] common/cnxk: use different macros for sdp and lbk max frames skoteshwar
2021-09-21 6:35 ` Jerin Jacob
2021-09-18 14:31 ` [dpdk-dev] [PATCH v2 2/8] common/cnxk: flush smq skoteshwar
2021-09-21 6:37 ` Jerin Jacob
2021-09-18 14:31 ` [dpdk-dev] [PATCH v2 3/8] common/cnxk: increase sched weight and shaper burst limit skoteshwar
2021-09-18 14:31 ` [dpdk-dev] [PATCH v2 4/8] common/cnxk: handle packet mode shaper limits skoteshwar
2021-09-18 14:31 ` [dpdk-dev] [PATCH v2 5/8] common/cnxk: handler to get rte tm error type skoteshwar
2021-09-21 6:41 ` Jerin Jacob
2021-09-18 14:31 ` [dpdk-dev] [PATCH v2 6/8] common/cnxk: set of handlers to get tm hierarchy internals skoteshwar
2021-09-18 14:31 ` [dpdk-dev] [PATCH v2 7/8] net/cnxk: tm capabilities and queue rate limit handlers skoteshwar
2021-09-21 6:43 ` Jerin Jacob
2021-09-18 14:31 ` [dpdk-dev] [PATCH v2 8/8] net/cnxk: tm shaper and node operations skoteshwar
2021-09-20 8:59 ` [dpdk-dev] [PATCH v2 0/8] Add TM Support for CN9K and CN10K nithind1988
2021-09-22 6:11 ` [dpdk-dev] [PATCH v3 " skoteshwar
2021-09-22 6:11 ` [dpdk-dev] [PATCH v3 1/8] common/cnxk: set appropriate max frame size for SDP and LBK skoteshwar
2021-09-27 13:29 ` Jerin Jacob
2021-09-22 6:11 ` [dpdk-dev] [PATCH v3 2/8] common/cnxk: support SMQ flush skoteshwar
2021-09-22 6:11 ` [dpdk-dev] [PATCH v3 3/8] common/cnxk: increase sched weight and shaper burst limit skoteshwar
2021-09-22 6:11 ` [dpdk-dev] [PATCH v3 4/8] common/cnxk: handle packet mode shaper limits skoteshwar
2021-09-22 6:11 ` [dpdk-dev] [PATCH v3 5/8] common/cnxk: support TM error type get skoteshwar
2021-09-22 6:11 ` [dpdk-dev] [PATCH v3 6/8] common/cnxk: set of handlers to get TM hierarchy internals skoteshwar
2021-09-22 6:11 ` [dpdk-dev] [PATCH v3 7/8] net/cnxk: TM capabilities and queue rate limit handlers skoteshwar
2021-09-22 6:11 ` [dpdk-dev] [PATCH v3 8/8] net/cnxk: TM shaper and node operations skoteshwar
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