From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from out2-smtp.messagingengine.com (out2-smtp.messagingengine.com [66.111.4.26]) by dpdk.org (Postfix) with ESMTP id 7A7DD1B1FE for ; Mon, 14 Jan 2019 12:32:31 +0100 (CET) Received: from compute1.internal (compute1.nyi.internal [10.202.2.41]) by mailout.nyi.internal (Postfix) with ESMTP id 0DA2529A91; Mon, 14 Jan 2019 06:32:31 -0500 (EST) Received: from mailfrontend1 ([10.202.2.162]) by compute1.internal (MEProxy); Mon, 14 Jan 2019 06:32:31 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=monjalon.net; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s=mesmtp; bh=bXPJJxul87y69EMl77X1ufZJaPXocaLQf+0SMM+KTjw=; b=kSwipmIF7Dh5 ONc/MkO3moOqMgoCAEHz8kPjXJGrdQFEXz1mQ+luUE3X8FfGs1v26tvC9ANxH8hM MvV0LdRujNlWETt/S7uV0aNvNAqdI2xRKbVuiR+pia1BucBxQ4a7A3H5ghBl8hqG 0kyHgeGJ8B8aMaHJNO5MLt8eF/61bTw= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-proxy:x-me-proxy:x-me-sender:x-me-sender :x-sasl-enc; s=fm1; bh=bXPJJxul87y69EMl77X1ufZJaPXocaLQf+0SMM+KT jw=; b=iP8izt5fGhu7il8hVN+ZxRdlqNmgeNmfaX5zMG2PBAE62z3FH3kgDvWgd NQcuqL78LxRR7KgBIWkOz9U0wYlqnmi0aCtrtcq3GKjgpvJrtznYyHXMRrmGnDm1 BGVipRbGCUxormfU41ugpclxrlcTierjMtSt0ujsrHmsCq4Q0Uz6GXIBJI48+QSg DZ+FTzJKjSH2UUWHgVNb7VrsrSMzBaUJOf1oIlteDE4ouUnSkJE9DwjShM+vFuta +Ons0tASea84lJfVxgChJAztOZ+Oowo/bJMFqk9RNKs3QWMyuTQ9bNJUgaKETqvb FNwGuDtNQDOwXB9yYSq4NciLcDd0w== X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedtledrgedugdeftdcutefuodetggdotefrodftvf curfhrohhfihhlvgemucfhrghsthforghilhdpqfhuthenuceurghilhhouhhtmecufedt tdenucesvcftvggtihhpihgvnhhtshculddquddttddmnecujfgurhephffvufffkfgjfh gggfgtsehtufertddttddvnecuhfhrohhmpefvhhhomhgrshcuofhonhhjrghlohhnuceo thhhohhmrghssehmohhnjhgrlhhonhdrnhgvtheqnecukfhppeejjedrudefgedrvddtfe drudekgeenucfrrghrrghmpehmrghilhhfrhhomhepthhhohhmrghssehmohhnjhgrlhho nhdrnhgvthenucevlhhushhtvghrufhiiigvpedt X-ME-Proxy: Received: from xps.localnet (184.203.134.77.rev.sfr.net [77.134.203.184]) by mail.messagingengine.com (Postfix) with ESMTPA id 64747E425A; Mon, 14 Jan 2019 06:32:29 -0500 (EST) From: Thomas Monjalon To: Pavan Nikhilesh Bhagavatula Cc: dev@dpdk.org, Jerin Jacob Kollanukkaran , "Gavin.Hu@arm.com" , "bruce.richardson@intel.com" Date: Mon, 14 Jan 2019 12:32:28 +0100 Message-ID: <1685344.eEdOqQplJK@xps> In-Reply-To: <20190109103915.29210-2-pbhagavatula@marvell.com> References: <20190106131933.7898-1-jerinj@marvell.com> <20190109103915.29210-1-pbhagavatula@marvell.com> <20190109103915.29210-2-pbhagavatula@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Subject: Re: [dpdk-dev] [PATCH v4 2/5] meson: add infra to support machine specific flags X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 14 Jan 2019 11:32:31 -0000 09/01/2019 11:39, Pavan Nikhilesh Bhagavatula: > From: Pavan Nikhilesh > > Currently, RTE_* flags are set based on the implementer ID but there might > be some micro arch specific differences from the same vendor > eg. CACHE_LINESIZE. > Add support to set micro arch specific flags. > > Signed-off-by: Jerin Jacob > Signed-off-by: Pavan Nikhilesh > --- > flags_cavium = [ > - ['RTE_MACHINE', '"thunderx"'], > ['RTE_CACHE_LINE_SIZE', 128], > ['RTE_MAX_NUMA_NODES', 2], > ['RTE_MAX_LCORE', 96], > - ['RTE_MAX_VFIO_GROUPS', 128], > - ['RTE_USE_C11_MEM_MODEL', false]] > + ['RTE_MAX_VFIO_GROUPS', 128]] [...] > +flags_thunderx_extra = [ > + ['RTE_MACHINE', '"thunderx"'], > + ['RTE_USE_C11_MEM_MODEL', false]] [..] > +machine_args_cavium = [ > + ['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']], > + ['native', ['-march=native']], > + ['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra], > + ['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra], > + ['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]] This patch is not only adding infra, it also change some Cavium config. What about splitting, and explaining the change of RTE_USE_C11_MEM_MODEL?