From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0012343D05; Wed, 20 Mar 2024 16:46:07 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 21EA942EDA; Wed, 20 Mar 2024 16:39:50 +0100 (CET) Received: from linux.microsoft.com (linux.microsoft.com [13.77.154.182]) by mails.dpdk.org (Postfix) with ESMTP id 98CBB42D2B for ; Wed, 20 Mar 2024 16:38:40 +0100 (CET) Received: by linux.microsoft.com (Postfix, from userid 1086) id BEFC120B2007; Wed, 20 Mar 2024 08:38:21 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com BEFC120B2007 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1710949105; bh=LIlUwOcsHY/zNtE1/hZMur9uSUBKnRGW0NSvlq7Sdro=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=rs5qe94mXRGPFfJo2LooCct8FP2fWrlF6vXmg5FkF8mpfNc63djpAgQsPgeI+zEJM f8rRTORyBULhc4T4gAI6djaYTB2znF/BL6jNE1uVZXRS43NU913QNMGIi4hMeVeFeX b5zYAYaHJmejgxDC+zg2Ir9p6OyF6il/u2kDxkWg= From: Tyler Retzlaff To: dev@dpdk.org Cc: =?UTF-8?q?Mattias=20R=C3=B6nnblom?= , "Min Hu (Connor)" , =?UTF-8?q?Morten=20Br=C3=B8rup?= , Abdullah Sevincer , Ajit Khaparde , Akhil Goyal , Alok Prasad , Amit Bernstein , Anatoly Burakov , Andrew Boyer , Andrew Rybchenko , Ankur Dwivedi , Anoob Joseph , Ashish Gupta , Ashwin Sekhar T K , Bruce Richardson , Byron Marohn , Chaoyong He , Chas Williams , Chenbo Xia , Chengwen Feng , Conor Walsh , Cristian Dumitrescu , Dariusz Sosnowski , David Hunt , Devendra Singh Rawat , Ed Czeck , Evgeny Schemeilin , Fan Zhang , Gagandeep Singh , Guoyang Zhou , Harman Kalra , Harry van Haaren , Hemant Agrawal , Honnappa Nagarahalli , Hyong Youb Kim , Jakub Grajciar , Jerin Jacob , Jian Wang , Jiawen Wu , Jie Hai , Jingjing Wu , John Daley , John Miller , Joyce Kong , Junfeng Guo , Kai Ji , Kevin Laatz , Kiran Kumar K , Konstantin Ananyev , Lee Daly , Liang Ma , Liron Himi , Long Li , Maciej Czekaj , Matan Azrad , Matt Peters , Maxime Coquelin , Michael Shamis , Nagadheeraj Rottela , Nicolas Chautru , Nithin Dabilpuram , Ori Kam , Pablo de Lara , Pavan Nikhilesh , Peter Mccarthy , Radu Nicolau , Rahul Lakkireddy , Rakesh Kudurumalla , Raveendra Padasalagi , Reshma Pattan , Ron Beider , Ruifeng Wang , Sachin Saxena , Selwin Sebastian , Shai Brandes , Shepard Siegel , Shijith Thotton , Sivaprasad Tummala , Somnath Kotur , Srikanth Yalavarthi , Stephen Hemminger , Steven Webster , Suanming Mou , Sunil Kumar Kori , Sunil Uttarwar , Sunila Sahu , Tejasree Kondoj , Viacheslav Ovsiienko , Vikas Gupta , Volodymyr Fialko , Wajeeh Atrash , Wisam Jaddo , Xiaoyun Wang , Yipeng Wang , Yisen Zhuang , Yuying Zhang , Zhangfei Gao , Zhirun Yan , Ziyang Xuan , Tyler Retzlaff Subject: [PATCH 49/83] dma/idxd: move alignment attribute on types Date: Wed, 20 Mar 2024 08:37:42 -0700 Message-Id: <1710949096-5786-50-git-send-email-roretzla@linux.microsoft.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1710949096-5786-1-git-send-email-roretzla@linux.microsoft.com> References: <1710949096-5786-1-git-send-email-roretzla@linux.microsoft.com> X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Move location of __rte_aligned(a) to new conventional location. The new placement between {struct,union} and the tag allows the desired alignment to be imparted on the type regardless of the toolchain being used for both C and C++. Additionally, it avoids confusion by Doxygen when generating documentation. Signed-off-by: Tyler Retzlaff --- drivers/dma/idxd/idxd_hw_defs.h | 38 +++++++++++++++++++------------------- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/drivers/dma/idxd/idxd_hw_defs.h b/drivers/dma/idxd/idxd_hw_defs.h index 7113d22..435c1cd 100644 --- a/drivers/dma/idxd/idxd_hw_defs.h +++ b/drivers/dma/idxd/idxd_hw_defs.h @@ -26,7 +26,7 @@ enum rte_idxd_ops { * Hardware descriptor used by DSA hardware, for both bursts and * for individual operations. */ -struct idxd_hw_desc { +struct __rte_aligned(64) idxd_hw_desc { uint32_t pasid; uint32_t op_flags; rte_iova_t completion; @@ -43,7 +43,7 @@ struct idxd_hw_desc { /* remaining 26 bytes are reserved */ uint16_t reserved[13]; -} __rte_aligned(64); +}; #define IDXD_COMP_STATUS_INCOMPLETE 0 #define IDXD_COMP_STATUS_SUCCESS 1 @@ -55,7 +55,7 @@ struct idxd_hw_desc { /** * Completion record structure written back by DSA */ -struct idxd_completion { +struct __rte_aligned(32) idxd_completion { uint8_t status; uint8_t result; /* 16-bits pad here */ @@ -63,7 +63,7 @@ struct idxd_completion { rte_iova_t fault_address; uint32_t invalid_flags; -} __rte_aligned(32); +}; /*** Definitions for Intel(R) Data Streaming Accelerator ***/ @@ -83,20 +83,20 @@ enum rte_idxd_cmds { /* General bar0 registers */ struct rte_idxd_bar0 { - uint32_t __rte_cache_aligned version; /* offset 0x00 */ - uint64_t __rte_aligned(0x10) gencap; /* offset 0x10 */ - uint64_t __rte_aligned(0x10) wqcap; /* offset 0x20 */ - uint64_t __rte_aligned(0x10) grpcap; /* offset 0x30 */ - uint64_t __rte_aligned(0x08) engcap; /* offset 0x38 */ - uint64_t __rte_aligned(0x10) opcap; /* offset 0x40 */ - uint64_t __rte_aligned(0x20) offsets[2]; /* offset 0x60 */ - uint32_t __rte_aligned(0x20) gencfg; /* offset 0x80 */ - uint32_t __rte_aligned(0x08) genctrl; /* offset 0x88 */ - uint32_t __rte_aligned(0x10) gensts; /* offset 0x90 */ - uint32_t __rte_aligned(0x08) intcause; /* offset 0x98 */ - uint32_t __rte_aligned(0x10) cmd; /* offset 0xA0 */ - uint32_t __rte_aligned(0x08) cmdstatus; /* offset 0xA8 */ - uint64_t __rte_aligned(0x20) swerror[4]; /* offset 0xC0 */ + alignas(RTE_CACHE_LINE_SIZE) uint32_t version; /* offset 0x00 */ + alignas(0x10) uint64_t gencap; /* offset 0x10 */ + alignas(0x10) uint64_t wqcap; /* offset 0x20 */ + alignas(0x10) uint64_t grpcap; /* offset 0x30 */ + alignas(0x08) uint64_t engcap; /* offset 0x38 */ + alignas(0x10) uint64_t opcap; /* offset 0x40 */ + alignas(0x20) uint64_t offsets[2]; /* offset 0x60 */ + alignas(0x20) uint32_t gencfg; /* offset 0x80 */ + alignas(0x08) uint32_t genctrl; /* offset 0x88 */ + alignas(0x10) uint32_t gensts; /* offset 0x90 */ + alignas(0x08) uint32_t intcause; /* offset 0x98 */ + alignas(0x10) uint32_t cmd; /* offset 0xA0 */ + alignas(0x08) uint32_t cmdstatus; /* offset 0xA8 */ + alignas(0x20) uint64_t swerror[4]; /* offset 0xC0 */ }; /* workqueue config is provided by array of uint32_t. */ @@ -118,7 +118,7 @@ enum rte_idxd_wqcfg { #define WQ_STATE_MASK 0x3 struct rte_idxd_grpcfg { - uint64_t grpwqcfg[4] __rte_cache_aligned; /* 64-byte register set */ + alignas(RTE_CACHE_LINE_SIZE) uint64_t grpwqcfg[4]; /* 64-byte register set */ uint64_t grpengcfg; /* offset 32 */ uint32_t grpflags; /* offset 40 */ }; -- 1.8.3.1