From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: <dev-bounces@dpdk.org> Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id EB2AA43D05; Wed, 20 Mar 2024 16:46:58 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 96E7342F01; Wed, 20 Mar 2024 16:39:59 +0100 (CET) Received: from linux.microsoft.com (linux.microsoft.com [13.77.154.182]) by mails.dpdk.org (Postfix) with ESMTP id 3214842DBB for <dev@dpdk.org>; Wed, 20 Mar 2024 16:38:43 +0100 (CET) Received: by linux.microsoft.com (Postfix, from userid 1086) id 7BF4D20B200E; Wed, 20 Mar 2024 08:38:21 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com 7BF4D20B200E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1710949106; bh=OV0xoi1l7wdbj+utF//CpVLtCY+cWePoG1UnQ6yppsg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=IGbCDVjb0pDlUsMuqnMr9BZhlrtZI/1Gsh/t6QmsuJdsqsvpSFVOWa7Nr7gJuuaOG lfVoGdbMQgyarBjidmCJv1cR9Sb4IIM05FbcZ1p65MXKNkOyc3Dthe8fMTHrc36HVq eXetmlinb3aZmdQmsUnNXpSiIfhjoDZt6gHaMWD4= From: Tyler Retzlaff <roretzla@linux.microsoft.com> To: dev@dpdk.org Cc: =?UTF-8?q?Mattias=20R=C3=B6nnblom?= <mattias.ronnblom@ericsson.com>, "Min Hu (Connor)" <humin29@huawei.com>, =?UTF-8?q?Morten=20Br=C3=B8rup?= <mb@smartsharesystems.com>, Abdullah Sevincer <abdullah.sevincer@intel.com>, Ajit Khaparde <ajit.khaparde@broadcom.com>, Akhil Goyal <gakhil@marvell.com>, Alok Prasad <palok@marvell.com>, Amit Bernstein <amitbern@amazon.com>, Anatoly Burakov <anatoly.burakov@intel.com>, Andrew Boyer <andrew.boyer@amd.com>, Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>, Ankur Dwivedi <adwivedi@marvell.com>, Anoob Joseph <anoobj@marvell.com>, Ashish Gupta <ashish.gupta@marvell.com>, Ashwin Sekhar T K <asekhar@marvell.com>, Bruce Richardson <bruce.richardson@intel.com>, Byron Marohn <byron.marohn@intel.com>, Chaoyong He <chaoyong.he@corigine.com>, Chas Williams <chas3@att.com>, Chenbo Xia <chenbox@nvidia.com>, Chengwen Feng <fengchengwen@huawei.com>, Conor Walsh <conor.walsh@intel.com>, Cristian Dumitrescu <cristian.dumitrescu@intel.com>, Dariusz Sosnowski <dsosnowski@nvidia.com>, David Hunt <david.hunt@intel.com>, Devendra Singh Rawat <dsinghrawat@marvell.com>, Ed Czeck <ed.czeck@atomicrules.com>, Evgeny Schemeilin <evgenys@amazon.com>, Fan Zhang <fanzhang.oss@gmail.com>, Gagandeep Singh <g.singh@nxp.com>, Guoyang Zhou <zhouguoyang@huawei.com>, Harman Kalra <hkalra@marvell.com>, Harry van Haaren <harry.van.haaren@intel.com>, Hemant Agrawal <hemant.agrawal@nxp.com>, Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>, Hyong Youb Kim <hyonkim@cisco.com>, Jakub Grajciar <jgrajcia@cisco.com>, Jerin Jacob <jerinj@marvell.com>, Jian Wang <jianwang@trustnetic.com>, Jiawen Wu <jiawenwu@trustnetic.com>, Jie Hai <haijie1@huawei.com>, Jingjing Wu <jingjing.wu@intel.com>, John Daley <johndale@cisco.com>, John Miller <john.miller@atomicrules.com>, Joyce Kong <joyce.kong@arm.com>, Junfeng Guo <junfeng.guo@intel.com>, Kai Ji <kai.ji@intel.com>, Kevin Laatz <kevin.laatz@intel.com>, Kiran Kumar K <kirankumark@marvell.com>, Konstantin Ananyev <konstantin.v.ananyev@yandex.ru>, Lee Daly <lee.daly@intel.com>, Liang Ma <liangma@liangbit.com>, Liron Himi <lironh@marvell.com>, Long Li <longli@microsoft.com>, Maciej Czekaj <mczekaj@marvell.com>, Matan Azrad <matan@nvidia.com>, Matt Peters <matt.peters@windriver.com>, Maxime Coquelin <maxime.coquelin@redhat.com>, Michael Shamis <michaelsh@marvell.com>, Nagadheeraj Rottela <rnagadheeraj@marvell.com>, Nicolas Chautru <nicolas.chautru@intel.com>, Nithin Dabilpuram <ndabilpuram@marvell.com>, Ori Kam <orika@nvidia.com>, Pablo de Lara <pablo.de.lara.guarch@intel.com>, Pavan Nikhilesh <pbhagavatula@marvell.com>, Peter Mccarthy <peter.mccarthy@intel.com>, Radu Nicolau <radu.nicolau@intel.com>, Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>, Rakesh Kudurumalla <rkudurumalla@marvell.com>, Raveendra Padasalagi <raveendra.padasalagi@broadcom.com>, Reshma Pattan <reshma.pattan@intel.com>, Ron Beider <rbeider@amazon.com>, Ruifeng Wang <ruifeng.wang@arm.com>, Sachin Saxena <sachin.saxena@nxp.com>, Selwin Sebastian <selwin.sebastian@amd.com>, Shai Brandes <shaibran@amazon.com>, Shepard Siegel <shepard.siegel@atomicrules.com>, Shijith Thotton <sthotton@marvell.com>, Sivaprasad Tummala <sivaprasad.tummala@amd.com>, Somnath Kotur <somnath.kotur@broadcom.com>, Srikanth Yalavarthi <syalavarthi@marvell.com>, Stephen Hemminger <stephen@networkplumber.org>, Steven Webster <steven.webster@windriver.com>, Suanming Mou <suanmingm@nvidia.com>, Sunil Kumar Kori <skori@marvell.com>, Sunil Uttarwar <sunilprakashrao.uttarwar@amd.com>, Sunila Sahu <ssahu@marvell.com>, Tejasree Kondoj <ktejasree@marvell.com>, Viacheslav Ovsiienko <viacheslavo@nvidia.com>, Vikas Gupta <vikas.gupta@broadcom.com>, Volodymyr Fialko <vfialko@marvell.com>, Wajeeh Atrash <atrwajee@amazon.com>, Wisam Jaddo <wisamm@nvidia.com>, Xiaoyun Wang <cloud.wangxiaoyun@huawei.com>, Yipeng Wang <yipeng1.wang@intel.com>, Yisen Zhuang <yisen.zhuang@huawei.com>, Yuying Zhang <Yuying.Zhang@intel.com>, Zhangfei Gao <zhangfei.gao@linaro.org>, Zhirun Yan <yanzhirun_163@163.com>, Ziyang Xuan <xuanziyang2@huawei.com>, Tyler Retzlaff <roretzla@linux.microsoft.com> Subject: [PATCH 60/83] crypto/ccp: move alignment attribute on types Date: Wed, 20 Mar 2024 08:37:53 -0700 Message-Id: <1710949096-5786-61-git-send-email-roretzla@linux.microsoft.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1710949096-5786-1-git-send-email-roretzla@linux.microsoft.com> References: <1710949096-5786-1-git-send-email-roretzla@linux.microsoft.com> X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions <dev.dpdk.org> List-Unsubscribe: <https://mails.dpdk.org/options/dev>, <mailto:dev-request@dpdk.org?subject=unsubscribe> List-Archive: <http://mails.dpdk.org/archives/dev/> List-Post: <mailto:dev@dpdk.org> List-Help: <mailto:dev-request@dpdk.org?subject=help> List-Subscribe: <https://mails.dpdk.org/listinfo/dev>, <mailto:dev-request@dpdk.org?subject=subscribe> Errors-To: dev-bounces@dpdk.org Move location of __rte_aligned(a) to new conventional location. The new placement between {struct,union} and the tag allows the desired alignment to be imparted on the type regardless of the toolchain being used for both C and C++. Additionally, it avoids confusion by Doxygen when generating documentation. Signed-off-by: Tyler Retzlaff <roretzla@linux.microsoft.com> --- drivers/crypto/ccp/ccp_crypto.h | 4 ++-- drivers/crypto/ccp/ccp_dev.h | 8 ++++---- drivers/crypto/ccp/ccp_pmd_private.h | 8 ++++---- 3 files changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/crypto/ccp/ccp_crypto.h b/drivers/crypto/ccp/ccp_crypto.h index d307f73..d0b417c 100644 --- a/drivers/crypto/ccp/ccp_crypto.h +++ b/drivers/crypto/ccp/ccp_crypto.h @@ -246,7 +246,7 @@ enum ccp_hash_op { }; /* CCP crypto private session structure */ -struct ccp_session { +struct __rte_cache_aligned ccp_session { bool auth_opt; enum ccp_cmd_order cmd_id; /**< chain order mode */ @@ -314,7 +314,7 @@ struct ccp_session { /**< AEAD Algorithm */ uint32_t reserved; -} __rte_cache_aligned; +}; extern uint8_t ccp_cryptodev_driver_id; diff --git a/drivers/crypto/ccp/ccp_dev.h b/drivers/crypto/ccp/ccp_dev.h index e3ec481..cd63830 100644 --- a/drivers/crypto/ccp/ccp_dev.h +++ b/drivers/crypto/ccp/ccp_dev.h @@ -178,7 +178,7 @@ static inline uint32_t ccp_pci_reg_read(void *base, int offset) /** * A structure describing a CCP command queue. */ -struct ccp_queue { +struct __rte_cache_aligned ccp_queue { struct ccp_device *dev; char memz_name[RTE_MEMZONE_NAMESIZE]; @@ -214,12 +214,12 @@ struct ccp_queue { /**< lsb assigned for sha ctx */ uint32_t sb_hmac; /**< lsb assigned for hmac ctx */ -} __rte_cache_aligned; +}; /** * A structure describing a CCP device. */ -struct ccp_device { +struct __rte_cache_aligned ccp_device { TAILQ_ENTRY(ccp_device) next; int id; /**< ccp dev id on platform */ @@ -237,7 +237,7 @@ struct ccp_device { /**< current queue index */ int hwrng_retries; /**< retry counter for CCP TRNG */ -} __rte_cache_aligned; +}; /**< CCP H/W engine related */ /** diff --git a/drivers/crypto/ccp/ccp_pmd_private.h b/drivers/crypto/ccp/ccp_pmd_private.h index 6704e39..390442f 100644 --- a/drivers/crypto/ccp/ccp_pmd_private.h +++ b/drivers/crypto/ccp/ccp_pmd_private.h @@ -46,7 +46,7 @@ struct ccp_private { }; /* CCP batch info */ -struct ccp_batch_info { +struct __rte_cache_aligned ccp_batch_info { struct rte_crypto_op *op[CCP_MAX_BURST]; /**< optable populated at enque time from app*/ int op_idx; @@ -66,10 +66,10 @@ struct ccp_batch_info { int lsb_buf_idx; uint16_t auth_ctr; /**< auth only ops batch for CPU based auth */ -} __rte_cache_aligned; +}; /**< CCP crypto queue pair */ -struct ccp_qp { +struct __rte_cache_aligned ccp_qp { uint16_t id; /**< Queue Pair Identifier */ char name[RTE_CRYPTODEV_NAME_MAX_LEN]; @@ -91,7 +91,7 @@ struct ccp_qp { * by the driver when verifying a digest provided * by the user (using authentication verify operation) */ -} __rte_cache_aligned; +}; /**< device specific operations function pointer structure */ -- 1.8.3.1