From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 484EC45D13; Fri, 15 Nov 2024 16:25:47 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 450C242FEB; Fri, 15 Nov 2024 16:25:46 +0100 (CET) Received: from linux.microsoft.com (linux.microsoft.com [13.77.154.182]) by mails.dpdk.org (Postfix) with ESMTP id D406142F95 for ; Fri, 15 Nov 2024 16:25:44 +0100 (CET) Received: by linux.microsoft.com (Postfix, from userid 1213) id 167DC206BCDC; Fri, 15 Nov 2024 07:25:44 -0800 (PST) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com 167DC206BCDC DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1731684344; bh=7S6F9sOAsfHM5KyHtlarvQ1XbcEfFnmMPyBrk0dUUSA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=s9rOEWyn+ha16CbedxniaezPQ0YR6RBBF4P1NhIb9vX6Wybz90nvyRd275+bv8X16 ty5aq8yrxEELE8R/ZN/zb5OIJ+K9LO1u+4oPdWJKyxAw26Bh+khjwyTCT/4npjBvfP FAwAk2KcZhdjg7hifW+SPhiih3n5/jcLgP0G9oDk= From: Andre Muezerie To: dev@dpdk.org Cc: honnappa.nagarahalli@arm.com, doug.foster@arm.com, david.marchand@redhat.com, Andre Muezerie Subject: [PATCH v3] rcu: shift 64-bit constant to avoid implicit 32 to 64 bit conversion Date: Fri, 15 Nov 2024 07:25:30 -0800 Message-Id: <1731684330-5735-1-git-send-email-andremue@linux.microsoft.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1731448959-18046-1-git-send-email-andremue@linux.microsoft.com> References: <1731448959-18046-1-git-send-email-andremue@linux.microsoft.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org ../lib/rcu/rte_rcu_qsbr.c(101): warning C4334: '<<': result of 32-bit shift implicitly converted to 64 bits (was 64-bit shift intended?) ../lib/rcu/rte_rcu_qsbr.c(107): warning C4334: '<<': result of 32-bit shift implicitly converted to 64 bits (was 64-bit shift intended?) ../lib/rcu/rte_rcu_qsbr.c(145): warning C4334: '<<': result of 32-bit shift implicitly converted to 64 bits (was 64-bit shift intended?) These warnings are being issued by the MSVC compiler. Since the result is being stored in a variable of type uint64_t, it makes sense to shift a 64-bit number instead of shifting a 32-bit number and then having the compiler to convert the result implicitly to 64 bits. UINT64_C was used in the fix as it is the portable way to define a 64-bit constant (ULL suffix is architecture dependent). >From reading the code this is also a bugfix: (1 << id), where id = thread_id & 0x3f, was wrong when thread_id > 0x1f. Fixes: 64994b56cfd7 ("rcu: add RCU library supporting QSBR mechanism") Signed-off-by: Andre Muezerie Reviewed-by: Honnappa Nagarahalli Reviewed-by: Morten Brørup --- lib/rcu/rte_rcu_qsbr.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/lib/rcu/rte_rcu_qsbr.c b/lib/rcu/rte_rcu_qsbr.c index 40d7c566c8..dbf31501a6 100644 --- a/lib/rcu/rte_rcu_qsbr.c +++ b/lib/rcu/rte_rcu_qsbr.c @@ -99,12 +99,12 @@ rte_rcu_qsbr_thread_register(struct rte_rcu_qsbr *v, unsigned int thread_id) /* Add the thread to the bitmap of registered threads */ old_bmap = rte_atomic_fetch_or_explicit(__RTE_QSBR_THRID_ARRAY_ELM(v, i), - (1UL << id), rte_memory_order_release); + RTE_BIT64(id), rte_memory_order_release); /* Increment the number of threads registered only if the thread was not already * registered */ - if (!(old_bmap & (1UL << id))) + if (!(old_bmap & RTE_BIT64(id))) rte_atomic_fetch_add_explicit(&v->num_threads, 1, rte_memory_order_relaxed); return 0; @@ -137,12 +137,12 @@ rte_rcu_qsbr_thread_unregister(struct rte_rcu_qsbr *v, unsigned int thread_id) * reporting threads. */ old_bmap = rte_atomic_fetch_and_explicit(__RTE_QSBR_THRID_ARRAY_ELM(v, i), - ~(1UL << id), rte_memory_order_release); + ~RTE_BIT64(id), rte_memory_order_release); /* Decrement the number of threads unregistered only if the thread was not already * unregistered */ - if (old_bmap & (1UL << id)) + if (old_bmap & RTE_BIT64(id)) rte_atomic_fetch_sub_explicit(&v->num_threads, 1, rte_memory_order_relaxed); return 0; @@ -198,7 +198,7 @@ rte_rcu_qsbr_dump(FILE *f, struct rte_rcu_qsbr *v) t = rte_ctz64(bmap); fprintf(f, "%u ", id + t); - bmap &= ~(1UL << t); + bmap &= ~RTE_BIT64(t); } } @@ -225,7 +225,7 @@ rte_rcu_qsbr_dump(FILE *f, struct rte_rcu_qsbr *v) rte_atomic_load_explicit( &v->qsbr_cnt[id + t].lock_cnt, rte_memory_order_relaxed)); - bmap &= ~(1UL << t); + bmap &= ~RTE_BIT64(t); } } -- 2.34.1