[PATCH v7 06/29] drivers/baseband: replace packed attributes

[Andre Muezerie <andremue@linux.microsoft.com>]

MSVC struct packing is not compatible with GCC. Replace macro
__rte_packed with __rte_packed_begin to push existing pack value
and set packing to 1-byte and macro __rte_packed_end to restore
the pack value prior to the push.

Macro __rte_packed_end is deliberately utilized to trigger a
MSVC compiler warning if no existing packing has been pushed allowing
easy identification of locations where the __rte_packed_begin is
missing.

Signed-off-by: Andre Muezerie <andremue@linux.microsoft.com>
Reviewed-by: Tyler Retlzaff <roretzla@linux.microsoft.com>
---
 drivers/baseband/acc/acc_common.h             | 59 +++++++++++--------
 drivers/baseband/fpga_5gnr_fec/agx100_pmd.h   | 16 ++---
 .../baseband/fpga_5gnr_fec/fpga_5gnr_fec.h    |  4 +-
 drivers/baseband/fpga_5gnr_fec/vc_5gnr_pmd.h  |  8 +--
 drivers/baseband/fpga_lte_fec/fpga_lte_fec.c  | 12 ++--
 drivers/baseband/la12xx/bbdev_la12xx_ipc.h    | 32 +++++-----
 6 files changed, 72 insertions(+), 59 deletions(-)

diff --git a/drivers/baseband/acc/acc_common.h b/drivers/baseband/acc/acc_common.h
index bf218332be..74c6787e4b 100644
--- a/drivers/baseband/acc/acc_common.h
+++ b/drivers/baseband/acc/acc_common.h
@@ -160,6 +160,7 @@ extern int acc_common_logtype;
 	RTE_LOG_LINE(level, ACC_COMMON, __VA_ARGS__)
 
 /* ACC100 DMA Descriptor triplet */
+__rte_packed_begin
 struct acc_dma_triplet {
 	uint64_t address;
 	uint32_t blen:20,
@@ -168,7 +169,7 @@ struct acc_dma_triplet {
 		dma_ext:1,
 		res1:2,
 		blkid:4;
-} __rte_packed;
+} __rte_packed_end;
 
 
 /* ACC100 Queue Manager Enqueue PCI Register */
@@ -183,7 +184,8 @@ union acc_enqueue_reg_fmt {
 };
 
 /* FEC 4G Uplink Frame Control Word */
-struct __rte_packed acc_fcw_td {
+__rte_packed_begin
+struct acc_fcw_td {
 	uint8_t fcw_ver:4,
 		num_maps:4; /* Unused in ACC100 */
 	uint8_t filler:6, /* Unused in ACC100 */
@@ -220,10 +222,11 @@ struct __rte_packed acc_fcw_td {
 				rsrvd4:10;
 		};
 	};
-};
+} __rte_packed_end;
 
 /* FEC 4G Downlink Frame Control Word */
-struct __rte_packed acc_fcw_te {
+__rte_packed_begin
+struct acc_fcw_te {
 	uint16_t k_neg;
 	uint16_t k_pos;
 	uint8_t c_neg;
@@ -251,10 +254,11 @@ struct __rte_packed acc_fcw_te {
 	uint8_t code_block_mode:1,
 		rsrvd8:7;
 	uint64_t rsrvd9;
-};
+} __rte_packed_end;
 
 /* FEC 5GNR Downlink Frame Control Word */
-struct __rte_packed acc_fcw_le {
+__rte_packed_begin
+struct acc_fcw_le {
 	uint32_t FCWversion:4,
 		qm:4,
 		nfiller:11,
@@ -279,10 +283,11 @@ struct __rte_packed acc_fcw_le {
 	uint32_t res6;
 	uint32_t res7;
 	uint32_t res8;
-};
+} __rte_packed_end;
 
 /* FEC 5GNR Uplink Frame Control Word */
-struct __rte_packed acc_fcw_ld {
+__rte_packed_begin
+struct acc_fcw_ld {
 	uint32_t FCWversion:4,
 		qm:4,
 		nfiller:11,
@@ -326,10 +331,11 @@ struct __rte_packed acc_fcw_ld {
 		tb_crc_select:2, /* Not supported in ACC100 */
 		dec_llrclip:2,  /* Not supported in VRB1 */
 		tb_trailer_size:20; /* Not supported in ACC100 */
-};
+} __rte_packed_end;
 
 /* FFT Frame Control Word */
-struct __rte_packed acc_fcw_fft {
+__rte_packed_begin
+struct acc_fcw_fft {
 	uint32_t in_frame_size:16,
 		leading_pad_size:16;
 	uint32_t out_frame_size:16,
@@ -351,10 +357,11 @@ struct __rte_packed acc_fcw_fft {
 		power_shift:4,
 		power_en:1,
 		res:19;
-};
+} __rte_packed_end;
 
 /* FFT Frame Control Word. */
-struct __rte_packed acc_fcw_fft_3 {
+__rte_packed_begin
+struct acc_fcw_fft_3 {
 	uint32_t in_frame_size:16,
 		leading_pad_size:16;
 	uint32_t out_frame_size:16,
@@ -381,11 +388,12 @@ struct __rte_packed acc_fcw_fft_3 {
 	uint16_t cs_theta_0[ACC_MAX_CS];
 	uint32_t cs_theta_d[ACC_MAX_CS];
 	int8_t cs_time_offset[ACC_MAX_CS];
-};
+} __rte_packed_end;
 
 
 /* MLD-TS Frame Control Word */
-struct __rte_packed acc_fcw_mldts {
+__rte_packed_begin
+struct acc_fcw_mldts {
 	uint32_t fcw_version:4,
 		res0:12,
 		nrb:13, /* 1 to 1925 */
@@ -409,7 +417,7 @@ struct __rte_packed acc_fcw_mldts {
 	uint32_t pad2;
 	uint32_t pad3;
 	uint32_t pad4;
-};
+} __rte_packed_end;
 
 /* DMA Response Descriptor */
 union acc_dma_rsp_desc {
@@ -435,7 +443,8 @@ union acc_dma_rsp_desc {
 };
 
 /* DMA Request Descriptor */
-struct __rte_packed acc_dma_req_desc {
+__rte_packed_begin
+struct acc_dma_req_desc {
 	union {
 		struct{
 			uint32_t type:4,
@@ -496,7 +505,7 @@ struct __rte_packed acc_dma_req_desc {
 		};
 		uint64_t pad3[ACC_DMA_DESC_PADDINGS]; /* pad to 64 bits */
 	};
-};
+} __rte_packed_end;
 
 /* ACC100 DMA Descriptor */
 union acc_dma_desc {
@@ -506,6 +515,7 @@ union acc_dma_desc {
 };
 
 /* Union describing Info Ring entry */
+__rte_packed_begin
 union acc_info_ring_data {
 	uint32_t val;
 	struct {
@@ -534,25 +544,28 @@ union acc_info_ring_data {
 		uint32_t loop_vrb2: 1;
 		uint32_t valid_vrb2: 1;
 	};
-} __rte_packed;
+} __rte_packed_end;
 
-struct __rte_packed acc_pad_ptr {
+__rte_packed_begin
+struct acc_pad_ptr {
 	void *op_addr;
 	uint64_t pad1;  /* pad to 64 bits */
-};
+} __rte_packed_end;
 
-struct __rte_packed acc_ptrs {
+__rte_packed_begin
+struct acc_ptrs {
 	struct acc_pad_ptr ptr[ACC_COMPANION_PTRS];
-};
+} __rte_packed_end;
 
 /* Union describing Info Ring entry */
+__rte_packed_begin
 union acc_harq_layout_data {
 	uint32_t val;
 	struct {
 		uint16_t offset;
 		uint16_t size0;
 	};
-} __rte_packed;
+} __rte_packed_end;
 
 /**
  * Structure with details about RTE_BBDEV_EVENT_DEQUEUE event. It's passed to
diff --git a/drivers/baseband/fpga_5gnr_fec/agx100_pmd.h b/drivers/baseband/fpga_5gnr_fec/agx100_pmd.h
index 5e562376c9..b6ef1d3f20 100644
--- a/drivers/baseband/fpga_5gnr_fec/agx100_pmd.h
+++ b/drivers/baseband/fpga_5gnr_fec/agx100_pmd.h
@@ -49,7 +49,7 @@ enum {
 };
 
 /* AGX100 TX Slice Descriptor. */
-struct __rte_packed agx100_input_slice_desc {
+__rte_packed_begin struct agx100_input_slice_desc {
 	uint32_t input_start_addr_lo;
 	uint32_t input_start_addr_hi;
 	uint32_t input_slice_length:21,
@@ -58,10 +58,10 @@ struct __rte_packed agx100_input_slice_desc {
 		start_of_pkt:1;
 	uint32_t input_slice_time_stamp:31,
 		input_c:1;
-};
+} __rte_packed_end;
 
 /* AGX100 RX Slice Descriptor. */
-struct __rte_packed agx100_output_slice_desc {
+__rte_packed_begin struct agx100_output_slice_desc {
 	uint32_t output_start_addr_lo;
 	uint32_t output_start_addr_hi;
 	uint32_t output_slice_length:21,
@@ -70,10 +70,10 @@ struct __rte_packed agx100_output_slice_desc {
 		start_of_pkt:1;
 	uint32_t output_slice_time_stamp:31,
 		output_c:1;
-};
+} __rte_packed_end;
 
 /* AGX100 DL DMA Encoding Request Descriptor. */
-struct __rte_packed agx100_dma_enc_desc {
+__rte_packed_begin struct agx100_dma_enc_desc {
 	uint32_t done:1, /**< 0: not completed 1: completed. */
 		rsrvd0:17,
 		error_msg:2,
@@ -161,10 +161,10 @@ struct __rte_packed agx100_dma_enc_desc {
 		uint8_t sw_ctxt[AGX100_RING_DESC_LEN_UNIT_BYTES *
 					(AGX100_RING_DESC_ENTRY_LENGTH - 1)];
 	};
-};
+} __rte_packed_end;
 
 /* AGX100 UL DMA Decoding Request Descriptor. */
-struct __rte_packed agx100_dma_dec_desc {
+__rte_packed_begin struct agx100_dma_dec_desc {
 	uint32_t done:1, /**< 0: not completed 1: completed. */
 		tb_crc_pass:1, /**< 0: doesn't pass 1: pass. */
 		cb_crc_all_pass:1, /**< 0: doesn't pass 1: pass. */
@@ -262,7 +262,7 @@ struct __rte_packed agx100_dma_dec_desc {
 		uint8_t sw_ctxt[AGX100_RING_DESC_LEN_UNIT_BYTES *
 					(AGX100_RING_DESC_ENTRY_LENGTH - 1)];
 	};
-};
+} __rte_packed_end;
 
 /* AGX100 DMA Descriptor. */
 union agx100_dma_desc {
diff --git a/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h b/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h
index 10a19e4dec..24797b8ef3 100644
--- a/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h
+++ b/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h
@@ -89,7 +89,7 @@ enum {
 };
 
 /* FPGA 5GNR Ring Control Register. */
-struct __rte_packed fpga_5gnr_ring_ctrl_reg {
+__rte_packed_begin struct fpga_5gnr_ring_ctrl_reg {
 	uint64_t ring_base_addr;
 	uint64_t ring_head_addr;
 	uint16_t ring_size:11;
@@ -107,7 +107,7 @@ struct __rte_packed fpga_5gnr_ring_ctrl_reg {
 	uint16_t rsrvd3;
 	uint16_t head_point;
 	uint16_t rsrvd4;
-};
+} __rte_packed_end;
 
 /* Private data structure for each FPGA 5GNR device. */
 struct fpga_5gnr_fec_device {
diff --git a/drivers/baseband/fpga_5gnr_fec/vc_5gnr_pmd.h b/drivers/baseband/fpga_5gnr_fec/vc_5gnr_pmd.h
index 9a488ae8d6..ca05ddd593 100644
--- a/drivers/baseband/fpga_5gnr_fec/vc_5gnr_pmd.h
+++ b/drivers/baseband/fpga_5gnr_fec/vc_5gnr_pmd.h
@@ -46,7 +46,7 @@ enum {
 };
 
 /* VC 5GNR FPGA FEC DMA Encoding Request Descriptor. */
-struct __rte_packed vc_5gnr_dma_enc_desc {
+__rte_packed_begin struct vc_5gnr_dma_enc_desc {
 	uint32_t done:1,
 		rsrvd0:7,
 		error:4,
@@ -84,10 +84,10 @@ struct __rte_packed vc_5gnr_dma_enc_desc {
 		uint8_t sw_ctxt[VC_5GNR_RING_DESC_LEN_UNIT_BYTES *
 					(VC_5GNR_RING_DESC_ENTRY_LENGTH - 1)];
 	};
-};
+} __rte_packed_end;
 
 /* VC 5GNR FPGA DPC FEC DMA Decoding Request Descriptor. */
-struct __rte_packed vc_5gnr_dma_dec_desc {
+__rte_packed_begin struct vc_5gnr_dma_dec_desc {
 	uint32_t done:1,
 		iter:5,
 		et_pass:1,
@@ -128,7 +128,7 @@ struct __rte_packed vc_5gnr_dma_dec_desc {
 
 		uint32_t sw_ctxt[8 * (VC_5GNR_RING_DESC_ENTRY_LENGTH - 1)];
 	};
-};
+} __rte_packed_end;
 
 /* Vista Creek 5GNR DMA Descriptor. */
 union vc_5gnr_dma_desc {
diff --git a/drivers/baseband/fpga_lte_fec/fpga_lte_fec.c b/drivers/baseband/fpga_lte_fec/fpga_lte_fec.c
index ed21a18b62..c67027618c 100644
--- a/drivers/baseband/fpga_lte_fec/fpga_lte_fec.c
+++ b/drivers/baseband/fpga_lte_fec/fpga_lte_fec.c
@@ -114,7 +114,7 @@ enum {
 };
 
 /* FPGA LTE FEC DMA Encoding Request Descriptor */
-struct __rte_packed fpga_dma_enc_desc {
+__rte_packed_begin struct fpga_dma_enc_desc {
 	uint32_t done:1,
 		rsrvd0:11,
 		error:4,
@@ -148,10 +148,10 @@ struct __rte_packed fpga_dma_enc_desc {
 		uint8_t sw_ctxt[FPGA_RING_DESC_LEN_UNIT_BYTES *
 					(FPGA_RING_DESC_ENTRY_LENGTH - 1)];
 	};
-};
+} __rte_packed_end;
 
 /* FPGA LTE FEC DMA Decoding Request Descriptor */
-struct __rte_packed fpga_dma_dec_desc {
+__rte_packed_begin struct fpga_dma_dec_desc {
 	uint32_t done:1,
 		iter:5,
 		rsrvd0:2,
@@ -188,7 +188,7 @@ struct __rte_packed fpga_dma_dec_desc {
 
 		uint32_t sw_ctxt[8 * (FPGA_RING_DESC_ENTRY_LENGTH - 1)];
 	};
-};
+} __rte_packed_end;
 
 /* FPGA LTE DMA Descriptor */
 union fpga_dma_desc {
@@ -197,7 +197,7 @@ union fpga_dma_desc {
 };
 
 /* FPGA LTE FEC Ring Control Register */
-struct __rte_packed fpga_ring_ctrl_reg {
+__rte_packed_begin struct fpga_ring_ctrl_reg {
 	uint64_t ring_base_addr;
 	uint64_t ring_head_addr;
 	uint16_t ring_size:11;
@@ -216,7 +216,7 @@ struct __rte_packed fpga_ring_ctrl_reg {
 	uint16_t head_point;
 	uint16_t rsrvd4;
 
-};
+} __rte_packed_end;
 
 /* Private data structure for each FPGA FEC device */
 struct fpga_lte_fec_device {
diff --git a/drivers/baseband/la12xx/bbdev_la12xx_ipc.h b/drivers/baseband/la12xx/bbdev_la12xx_ipc.h
index b6a7f677d0..b915a71cca 100644
--- a/drivers/baseband/la12xx/bbdev_la12xx_ipc.h
+++ b/drivers/baseband/la12xx/bbdev_la12xx_ipc.h
@@ -93,7 +93,7 @@ typedef struct {
 #define IPC_GET_CI_INDEX(x)	(x & IPC_PI_CI_INDEX_MASK)
 
 /** buffer ring common metadata */
-typedef struct ipc_bd_ring_md {
+typedef __rte_packed_begin struct ipc_bd_ring_md {
 	volatile uint32_t pi;		/**< Producer index and flag (MSB)
 					  *  which flip for each Ring wrapping
 					  */
@@ -102,10 +102,10 @@ typedef struct ipc_bd_ring_md {
 					  */
 	uint32_t ring_size;	/**< depth (Used to roll-over pi/ci) */
 	uint32_t msg_size;	/**< Size of the each buffer */
-} __rte_packed ipc_br_md_t;
+} __rte_packed_end ipc_br_md_t;
 
 /** IPC buffer descriptor */
-typedef struct ipc_buffer_desc {
+typedef __rte_packed_begin struct ipc_buffer_desc {
 	union {
 		uint64_t host_virt;	/**< msg's host virtual address */
 		struct {
@@ -115,9 +115,9 @@ typedef struct ipc_buffer_desc {
 	};
 	uint32_t modem_ptr;	/**< msg's modem physical address */
 	uint32_t len;		/**< msg len */
-} __rte_packed ipc_bd_t;
+} __rte_packed_end ipc_bd_t;
 
-typedef struct ipc_channel {
+typedef __rte_packed_begin struct ipc_channel {
 	uint32_t ch_id;		/**< Channel id */
 	ipc_br_md_t md;			/**< Metadata for BD ring */
 	ipc_bd_t bd_h[IPC_MAX_DEPTH];	/**< Buffer Descriptor on Host */
@@ -134,22 +134,22 @@ typedef struct ipc_channel {
 					  * circular buffer size
 					  */
 	uint32_t host_ipc_params;	/**< Address for host IPC parameters */
-} __rte_packed ipc_ch_t;
+} __rte_packed_end ipc_ch_t;
 
-typedef struct ipc_instance {
+typedef __rte_packed_begin struct ipc_instance {
 	uint32_t instance_id;		/**< instance id, use to init this
 					  * instance by ipc_init API
 					  */
 	uint32_t initialized;		/**< Set in ipc_init */
 	ipc_ch_t ch_list[IPC_MAX_CHANNEL_COUNT];
 		/**< Channel descriptors in this instance */
-} __rte_packed ipc_instance_t;
+} __rte_packed_end ipc_instance_t;
 
-typedef struct ipc_metadata {
+typedef __rte_packed_begin struct ipc_metadata {
 	uint32_t ipc_host_signature; /**< IPC host signature, Set by host/L2 */
 	uint32_t ipc_geul_signature; /**< IPC geul signature, Set by modem */
 	ipc_instance_t instance_list[IPC_MAX_INSTANCE_COUNT];
-} __rte_packed ipc_metadata_t;
+} __rte_packed_end ipc_metadata_t;
 
 typedef struct ipc_channel_us_priv {
 	int32_t		eventfd;
@@ -221,24 +221,24 @@ struct bbdev_ipc_dequeue_op {
  * of the parameters which are also part of Shared BD ring. Read access
  * of these parameters from the host side would not be over PCI.
  */
-typedef struct host_ipc_params {
+typedef __rte_packed_begin struct host_ipc_params {
 	volatile uint32_t pi;
 	volatile uint32_t ci;
 	volatile uint32_t bd_m_modem_ptr[IPC_MAX_DEPTH];
-} __rte_packed host_ipc_params_t;
+} __rte_packed_end host_ipc_params_t;
 
-struct hif_ipc_regs {
+__rte_packed_begin struct hif_ipc_regs {
 	uint32_t ipc_mdata_offset;
 	uint32_t ipc_mdata_size;
-} __rte_packed;
+} __rte_packed_end;
 
-struct gul_hif {
+__rte_packed_begin struct gul_hif {
 	uint32_t ver;
 	uint32_t hif_ver;
 	uint32_t status;
 	volatile uint32_t host_ready;
 	volatile uint32_t mod_ready;
 	struct hif_ipc_regs ipc_regs;
-} __rte_packed;
+} __rte_packed_end;
 
 #endif
-- 
2.47.0.vfs.0.3