From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E9D4443CE6; Mon, 18 Mar 2024 15:56:45 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9279140289; Mon, 18 Mar 2024 15:56:45 +0100 (CET) Received: from wfout4-smtp.messagingengine.com (wfout4-smtp.messagingengine.com [64.147.123.147]) by mails.dpdk.org (Postfix) with ESMTP id 7E7C84027F for ; Mon, 18 Mar 2024 15:56:43 +0100 (CET) Received: from compute3.internal (compute3.nyi.internal [10.202.2.43]) by mailfout.west.internal (Postfix) with ESMTP id 6FC811C000BF; Mon, 18 Mar 2024 10:56:41 -0400 (EDT) Received: from mailfrontend2 ([10.202.2.163]) by compute3.internal (MEProxy); Mon, 18 Mar 2024 10:56:42 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=monjalon.net; h= cc:cc:content-transfer-encoding:content-type:content-type:date :date:from:from:in-reply-to:in-reply-to:message-id:mime-version :references:reply-to:subject:subject:to:to; s=fm2; t=1710773800; x=1710860200; bh=oQTTXoSmFNPRMC10nI5imZHX2I13XUWI8mY5NyKpRhU=; b= dQ1sOgqXKPN7eHbyXIKGV83IBW4Eqj8n/ffD08NdGWIvSfKx/TU6S0+kGF0Ni/kx O4Bk7hbj3orcmbopJGOsXxp6W3z2qWZUc95nLoBuyEnYRVyZqQI2qnkD0PQzfjnH w/iNoGJm09vugBZXpyTl9lgNOM6aOiFMcbaT7cocdH4a7vkfuaS7qVUmUIJ6/xMW iDn67Z+Ywo1TwjFGsINV5xAsaPOHFWeOLMRUmBLl2DLsdr/Ip36TQO4/PLPy4PTh CL2nxdQG8m8VTWDKJqQAFEdVmS7GtpSpl3yVO7zw1JLOSSjyvZzgc5USCTLkMdke UXTYy1Pc+0pyDyRaBXW/kw== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding :content-type:content-type:date:date:feedback-id:feedback-id :from:from:in-reply-to:in-reply-to:message-id:mime-version :references:reply-to:subject:subject:to:to:x-me-proxy:x-me-proxy :x-me-sender:x-me-sender:x-sasl-enc; s=fm2; t=1710773800; x= 1710860200; bh=oQTTXoSmFNPRMC10nI5imZHX2I13XUWI8mY5NyKpRhU=; b=g MaqRIlt7tEB58NSDKk8cu+rUasgrece9Oyidpoy5prZuOaSgkmh2H4n+R9JeLQ+b EjfVt6Jmcz/VOFOXmYsz2pglxg2pIKevRhtPwDpzyT/gKzcDLSFKmZkeNErhZyjX /UflkWGP87SW0VgQlS8MjYy0dWfmZjbkj2X1pqGmvi9xnAuqKC7kdUqJFUACHGjx fnjm+1aeuoko2sHQxG3e6pZof2NrwcESGVfJm4W7pnTw+C7DrMWMVI3sEtMuDFbm 0I7ljawptZOFtd0wZiMVE6Oo5pLxgYJWI2tkaax4b/dKET9G2YFedEC3ll5bvnHC tj0q2rXfxQ5FDVkwcko4Q== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvledrkeejgdejtdcutefuodetggdotefrodftvf curfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfghnecu uegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenuc fjughrpefhvfevufffkfgjfhgggfgtsehtufertddttdejnecuhfhrohhmpefvhhhomhgr shcuofhonhhjrghlohhnuceothhhohhmrghssehmohhnjhgrlhhonhdrnhgvtheqnecugg ftrfgrthhtvghrnhepjeduveehieevuddutdevfffgtdegkeeuveejffejgedtgeegkefg vdeugfefkeejnecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehmrghilhhfrh homhepthhhohhmrghssehmohhnjhgrlhhonhdrnhgvth X-ME-Proxy: Feedback-ID: i47234305:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Mon, 18 Mar 2024 10:56:38 -0400 (EDT) From: Thomas Monjalon To: Dengdui Huang Cc: dev@dpdk.org, ferruh.yigit@amd.com, aman.deep.singh@intel.com, yuying.zhang@intel.com, andrew.rybchenko@oktetlabs.ru, liuyonglong@huawei.com, fengchengwen@huawei.com, haijie1@huawei.com, lihuisong@huawei.com Subject: Re: [PATCH 0/3] support setting lanes Date: Mon, 18 Mar 2024 15:56:37 +0100 Message-ID: <1759403.vCJZsxu672@thomas> In-Reply-To: <20240312075238.3319480-1-huangdengdui@huawei.com> References: <20240312075238.3319480-1-huangdengdui@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="utf-8" X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org 12/03/2024 08:52, Dengdui Huang: > Some speeds can be achieved with different number of lanes. For example, > 100Gbps can be achieved using two lanes of 50Gbps or four lanes of 25Gbps. > When use different lanes, the port cannot be up. I'm not sure what you are referring to. I suppose it is not PCI lanes. Please could you link to an explanation of how a port is split in lanes? Which hardware does this?