From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id EB7A0A0544; Fri, 2 Sep 2022 09:17:06 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D6D2D40693; Fri, 2 Sep 2022 09:17:06 +0200 (CEST) Received: from out3-smtp.messagingengine.com (out3-smtp.messagingengine.com [66.111.4.27]) by mails.dpdk.org (Postfix) with ESMTP id BC0BD40684 for ; Fri, 2 Sep 2022 09:17:05 +0200 (CEST) Received: from compute2.internal (compute2.nyi.internal [10.202.2.46]) by mailout.nyi.internal (Postfix) with ESMTP id 1508A5C0172; Fri, 2 Sep 2022 03:17:05 -0400 (EDT) Received: from mailfrontend2 ([10.202.2.163]) by compute2.internal (MEProxy); Fri, 02 Sep 2022 03:17:05 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=monjalon.net; h= cc:cc:content-transfer-encoding:content-type:date:date:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to; s=fm1; t=1662103025; x= 1662189425; bh=bxc2OlBNDizqq2eZQkT83paL1ixDs28tWnqy7vIzU+A=; b=E yBEXdlSCPG7Dtdv4nv0bf7adqlLK6JITYiWNj1PSzavJ/fQW4aWFyAoYqw3p5tbz 2l7FK47Uh6h0ywkFexW50dbOOx9XhRxUVfavy0ixl/bQMGhA1regtWlR8tjz+6eM EiAKUVWHTOoF7riDlot6sVR1WVPyaM4uiR+ZqGV4K1ox4Ln5TmqBNrfK15Rpx4rP fxizMApPregTby94DR4WbJTjfShXApYyLIpfwW0IubQYoPDfs8fPSVYkoOkjfreb SHzn98HUcsawpy1e4CCAzgXpeWUiBxa7GzbBtOSo0Kqw1j5KKh24XqgBk5YjVxxo sXc3kuc5ieN/pDs8GmQJw== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding :content-type:date:date:feedback-id:feedback-id:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to:x-me-proxy:x-me-proxy :x-me-sender:x-me-sender:x-sasl-enc; s=fm1; t=1662103025; x= 1662189425; bh=bxc2OlBNDizqq2eZQkT83paL1ixDs28tWnqy7vIzU+A=; b=T JWhhV+boUzdLou7dHpZlGKv/R9JT5cJ82KkYvWMDJ+WlO6IVI7VO3V+vBmjguODy D+wBcogNXEGsqysjKWvhpp+02B+CbXoBVLqcZFWfqzp1ZXgc+6ZQbkFA04olb/mN MpYO2kNtOg6lQJzAbIxP+WKcHAvuFEAHQbmXFWYB3KA+g09sMhNGKqWBX7d4Np4X BXrURMtLHq7ngF8HiaSZ2SILN4fibvBl+RFc3sTy6seftfbF0iQIj7nVxanUPIkZ 1EwnUDi4BnukOCg6ZjiQQL4qmPpO3V2XeTgQ3So6twdXK1bQISeEQsOGMt/stmih OFAGb/Z1w2oVzP/LueUqg== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvfedrvdekledguddukecutefuodetggdotefrod ftvfcurfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfgh necuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd enucfjughrpefhvfevufffkfgjfhgggfgtsehtqhertddttdejnecuhfhrohhmpefvhhho mhgrshcuofhonhhjrghlohhnuceothhhohhmrghssehmohhnjhgrlhhonhdrnhgvtheqne cuggftrfgrthhtvghrnhepgedttdeljeejgeffkeekkedtjeevtdehvedtkeeivdeuuedv ieduvdelveejueejnecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehmrghilh hfrhhomhepthhhohhmrghssehmohhnjhgrlhhonhdrnhgvth X-ME-Proxy: Feedback-ID: i47234305:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Fri, 2 Sep 2022 03:17:03 -0400 (EDT) From: Thomas Monjalon To: xing_wang Cc: Honnappa Nagarahalli , "dev@dpdk.org" , dali_chen , howard_wang , Ruifeng Wang , nd , Hau Subject: Re: about RTL8168 PMD on ARM SoC Date: Fri, 02 Sep 2022 09:17:01 +0200 Message-ID: <1780183.b8e9qBsS6s@thomas> In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="UTF-8" X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org When do you expect or desire to merge it into upstream DPDK? It's always better to know the intended roadmap, thanks. 29/08/2022 17:40, Hau: > Hi Honnappa, >=20 > Thanks for prompt reply. > Currently our pmd driver still has other issues. After we fix it, we will= submit our code as RFC. >=20 > Thanks, > Hau >=20 > From: Honnappa Nagarahalli [mailto:Honnappa.Nagarahalli@arm.com] > Sent: Saturday, August 27, 2022 12:44 AM > To: xing_wang ; dev@dpdk.org > Cc: dali_chen ; howard_wang ; Ruifeng Wang ; Hau ; nd <= nd@arm.com> > Subject: RE: about RTL8168 PMD on ARM SoC >=20 > Hi Xing Wang, > Can you submit this code as RFC, it will enable us to prov= ide review comments? >=20 > Thanks, > Honnappa >=20 >=20 > From: =E7=8E=8B=E6=98=9F > > Sent: Thursday, August 25, 2022 9:36 PM > To: Honnappa Nagarahalli >; dev@dpdk.org > Cc: =E9=99=88=E7=AB=8B >; =E7=8E=8B=E9=A2=A2 >; Ruifeng Wang >; nd >; nd >; Hau > > Subject: =E7=AD=94=E5=A4=8D: about RTL8168 PMD on ARM SoC >=20 > Hi Honnappa, >=20 > I=E2=80=99m sorry I have to make a little correction, > This issue was actually on our new 2.5 Gigabit RTL8125 series, the attach= ment is latest r8125pmd, > There is no essential difference w.r.t ARM platform though. >=20 > BRs, > Xing Wang >=20 > =E5=8F=91=E4=BB=B6=E4=BA=BA: =E7=8E=8B=E6=98=9F > =E5=8F=91=E9=80=81=E6=97=B6=E9=97=B4: 2022=E5=B9=B48=E6=9C=8826=E6=97=A5 = 10:06 > =E6=94=B6=E4=BB=B6=E4=BA=BA: 'Honnappa Nagarahalli' >; dev@dpdk.org > =E6=8A=84=E9=80=81: =E9=99=88=E7=AB=8B >; =E7=8E=8B=E9=A2=A2 >; Ruifeng Wang >; nd >; nd >; Hau > > =E4=B8=BB=E9=A2=98: =E7=AD=94=E5=A4=8D: about RTL8168 PMD on ARM SoC >=20 > Hi Honnappa, >=20 > The attachment is our current r8168pmd code for RTL8111/8168 Giga series > (currently 8111G, 8111H are supported, we will add others later) > I will contact the SoC vendor to consult you about this issue and let you= know some details about that SoC > Thanks a lot! >=20 > BRs > Xing Wang > =E5=8F=91=E4=BB=B6=E4=BA=BA: Honnappa Nagarahalli [mailto:Honnappa.Nagara= halli@arm.com] > =E5=8F=91=E9=80=81=E6=97=B6=E9=97=B4: 2022=E5=B9=B48=E6=9C=8825=E6=97=A5 = 22:41 > =E6=94=B6=E4=BB=B6=E4=BA=BA: =E7=8E=8B=E6=98=9F >; dev@dpdk.org > =E6=8A=84=E9=80=81: =E9=99=88=E7=AB=8B >; =E7=8E=8B=E9=A2=A2 >; Ruifeng Wang >; nd >; nd > > =E4=B8=BB=E9=A2=98: RE: about RTL8168 PMD on ARM SoC >=20 > Hello, > I cannot find many details of the SoC on the internet. Doe= s it use coherent IO? Depending on that, different barriers might be needed= =2E Other than this, I would not think it needs anything special. >=20 > If you could send an RFC to the DPDK mailing list, I am happy to review a= nd provide any feedback. >=20 > Thanks, > Honnappa >=20 >=20 > From: =E7=8E=8B=E6=98=9F > > Sent: Wednesday, August 24, 2022 9:53 PM > To: dev@dpdk.org > Cc: =E9=99=88=E7=AB=8B >; =E7=8E=8B=E9=A2=A2 > > Subject: about RTL8168 PMD on ARM SoC >=20 > Hi DPDK, >=20 > I am a pmd driver developer from Realtek NIC department, > when I was porting r8168pmd already verified on x86 to an ARM64 SoC Uniso= c: UIS8650 > I found that after NIC Rx init (in general, Rx ring and buffers should ha= ve been prepared for NIC to DMA read), > the NIC status reg showed RDU (Rx Descriptor Unavailable), which means NI= C cannot read the proper desc content, >=20 > later I sended some packets to NIC hold by testpmd rx_only mode, HW inter= nal Rx packet counter can grow to some value, then stuck, 8168pmd Rx debug = print reported it received less packets than that value, and the print show= ed up even some minutes later! >=20 > I doubt the phenomenon is caused by improper HW-based IO coherency suppor= t on this ARM SoC, > I have read the ARM SoC support list on DPDK website, to name it: NV Blue= field, NXP DPAA, Marvell Octeon TX =E2=80=A6 >=20 > Does DPDK (or UIO/VFIO driver or hugetlb driver) need special HW IO cache= coherency support on ARM platform, say, ACE and Device side MMU etc? > Should the SoC provide specialized UIO/VFIO driver or hugetlb driver and/= or specific DPDK lib to support such user mode DMA? > Will you please give suggestions, thanks a lot! >=20 > BRs >=20 > ------Please consider the environment before printing this e-mail. >=20