From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id EC631A0542; Tue, 4 Oct 2022 18:50:28 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C774140DDC; Tue, 4 Oct 2022 18:50:28 +0200 (CEST) Received: from out5-smtp.messagingengine.com (out5-smtp.messagingengine.com [66.111.4.29]) by mails.dpdk.org (Postfix) with ESMTP id 40DFA40A79 for ; Tue, 4 Oct 2022 18:50:27 +0200 (CEST) Received: from compute1.internal (compute1.nyi.internal [10.202.2.41]) by mailout.nyi.internal (Postfix) with ESMTP id AACE65C0114; Tue, 4 Oct 2022 12:50:26 -0400 (EDT) Received: from mailfrontend2 ([10.202.2.163]) by compute1.internal (MEProxy); Tue, 04 Oct 2022 12:50:26 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=monjalon.net; h= cc:cc:content-transfer-encoding:content-type:date:date:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to; s=fm2; t=1664902226; x= 1664988626; bh=NC8Tc5LqHXSSn5zGC1Ju1Gn+s5aOHJIAEz8u/jBmPKg=; b=I DNFQvCv9ts5d0b8PEZ6Apj6GtzYfT4agpXD37/95hnxMWlyPt4PcnhIGsih6u97L t1JriJtXgIOQZmbdviakqIl0mcK4mUn/J11TyLyVwnfnDlyS6VL/VYYw7VAch4B/ Ut766AA9xKZbTUkOjTP5tt2rQY6zokNLeUwAwfDO+X5tpvahnEvTjwQoLNQLuvwc 1Xl/HvzXDCASh23s8IpFUVxP5M9IQ8JiSqD3he1i0EfArYCTBOXy01bV8lTIBeSe erClx98sMBhDOS2lE0US+JsleQxhPLljr4OrOAjmWmhFYDFOjxqMa9fs6SDYl3Oc /TyXVoQuWNyU3RvpioX6Q== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding :content-type:date:date:feedback-id:feedback-id:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to:x-me-proxy:x-me-proxy :x-me-sender:x-me-sender:x-sasl-enc; s=fm2; t=1664902226; x= 1664988626; bh=NC8Tc5LqHXSSn5zGC1Ju1Gn+s5aOHJIAEz8u/jBmPKg=; b=M T0DMs2UUbbU422MF7RLmaIzjK9Eu45dAYBIZHWjKVU+wV55zELuFyFF9TG8c0CiC umTlMswuVFQ5Gppvhe2ksuYn1H51PxcS6ijub2BXyloM07vzIlOggE5J1nlCMW6K 9ahlvvgd26UUYB0C/0l8TA4ac/bTM6J7dWcld6pAxrTTWk0QXWDi2t40x2UL3Xj0 SU0fGTnuwgFaaz8Nchum0DkAMZ0/EdTUgYeIuW1NNNjye7m5ctPL43h9cwcar2ul GUIkuP4gU3E7TVNlk7bw2uVHYlPt4hFVC7a+EC2z7x/tKGmfNh9SS7E+kNAv/EQQ aWBtcjsrWdrYqOOZ0skzA== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvfedrfeeiuddguddthecutefuodetggdotefrod ftvfcurfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfgh necuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd enucfjughrpefhvfevufffkfgjfhgggfgtsehtufertddttddvnecuhfhrohhmpefvhhho mhgrshcuofhonhhjrghlohhnuceothhhohhmrghssehmohhnjhgrlhhonhdrnhgvtheqne cuggftrfgrthhtvghrnheptdejieeifeehtdffgfdvleetueeffeehueejgfeuteeftddt ieekgfekudehtdfgnecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehmrghilh hfrhhomhepthhhohhmrghssehmohhnjhgrlhhonhdrnhgvth X-ME-Proxy: Feedback-ID: i47234305:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Tue, 4 Oct 2022 12:50:25 -0400 (EDT) From: Thomas Monjalon To: Dariusz Sosnowski Cc: Ferruh Yigit , Andrew Rybchenko , dev@dpdk.org Subject: Re: [PATCH 1/7] ethdev: introduce hairpin memory capabilities Date: Tue, 04 Oct 2022 18:50:24 +0200 Message-ID: <1781971.b8e9qBsS6s@thomas> In-Reply-To: <20220919163731.1540454-2-dsosnowski@nvidia.com> References: <20220919163731.1540454-1-dsosnowski@nvidia.com> <20220919163731.1540454-2-dsosnowski@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org 19/09/2022 18:37, Dariusz Sosnowski: > This patch introduces new hairpin queue configuration options through > rte_eth_hairpin_conf struct, allowing to tune Rx and Tx hairpin queues > memory configuration. Hairpin configuration is extended with the > following fields: What is the benefit? How the user knows what to use? Isn't it too much low level for a user? Why it is not automatic in the driver? [...] > + /** > + * Use locked device memory as a backing storage. > + * > + * - When set, PMD will attempt to use on-device memory as a backing storage for descriptors > + * and/or data in hairpin queue. > + * - When set, PMD will use detault memory type as a backing storage. Please refer to PMD You probably mean "clear". Please make lines shorter. You should split lines logically, after a dot or at the end of a part. > + * documentation for details. > + * > + * API user should check if PMD supports this configuration flag using > + * @see rte_eth_dev_hairpin_capability_get. > + */ > + uint32_t use_locked_device_memory:1; > + > + /** > + * Use DPDK memory as backing storage. > + * > + * - When set, PMD will attempt to use memory managed by DPDK as a backing storage > + * for descriptors and/or data in hairpin queue. > + * - When clear, PMD will use default memory type as a backing storage. Please refer > + * to PMD documentation for details. > + * > + * API user should check if PMD supports this configuration flag using > + * @see rte_eth_dev_hairpin_capability_get. > + */ > + uint32_t use_rte_memory:1; > + > + /** > + * Force usage of hairpin memory configuration. > + * > + * - When set, PMD will attempt to use specified memory settings and > + * if resource allocation fails, then hairpin queue setup will result in an > + * error. > + * - When clear, PMD will attempt to use specified memory settings and > + * if resource allocation fails, then PMD will retry allocation with default > + * configuration. > + */ > + uint32_t force_memory:1; > + > + uint32_t reserved:11; /**< Reserved bits. */ You can insert a blank line here. > struct rte_eth_hairpin_peer peers[RTE_ETH_MAX_HAIRPIN_PEERS]; > };