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Mon, 5 Nov 2018 08:17:28 -0500 (EST) From: Thomas Monjalon <thomas@monjalon.net> To: Honnappa Nagarahalli <Honnappa.Nagarahalli@arm.com> Cc: stable@dpdk.org, "Gavin Hu (Arm Technology China)" <Gavin.Hu@arm.com>, Bruce Richardson <bruce.richardson@intel.com>, "dev@dpdk.org" <dev@dpdk.org>, "stephen@networkplumber.org" <stephen@networkplumber.org>, "olivier.matz@6wind.com" <olivier.matz@6wind.com>, "chaozhu@linux.vnet.ibm.com" <chaozhu@linux.vnet.ibm.com>, "konstantin.ananyev@intel.com" <konstantin.ananyev@intel.com>, "jerin.jacob@caviumnetworks.com" <jerin.jacob@caviumnetworks.com>, nd <nd@arm.com>, hemant.agrawal@nxp.com, shreyansh.jain@nxp.com Date: Mon, 05 Nov 2018 14:17:27 +0100 Message-ID: <1825633.NNxUzH26Cz@xps> In-Reply-To: <AM6PR08MB3672943D7FBAB69C5B84EF8398C80@AM6PR08MB3672.eurprd08.prod.outlook.com> References: <1541066031-29125-1-git-send-email-gavin.hu@arm.com> <VI1PR08MB316746F49E356F622E703BB18FC80@VI1PR08MB3167.eurprd08.prod.outlook.com> <AM6PR08MB3672943D7FBAB69C5B84EF8398C80@AM6PR08MB3672.eurprd08.prod.outlook.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Subject: Re: [dpdk-dev] [dpdk-stable] [PATCH v5 2/2] ring: move the atomic load of head above the loop X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions <dev.dpdk.org> List-Unsubscribe: <https://mails.dpdk.org/options/dev>, <mailto:dev-request@dpdk.org?subject=unsubscribe> List-Archive: <http://mails.dpdk.org/archives/dev/> List-Post: <mailto:dev@dpdk.org> List-Help: <mailto:dev-request@dpdk.org?subject=help> List-Subscribe: <https://mails.dpdk.org/listinfo/dev>, <mailto:dev-request@dpdk.org?subject=subscribe> X-List-Received-Date: Mon, 05 Nov 2018 13:17:33 -0000 03/11/2018 10:34, Honnappa Nagarahalli: > > > > --- > > > > doc/guides/rel_notes/release_18_11.rst | 7 +++++++ > > > > lib/librte_ring/rte_ring_c11_mem.h | 10 ++++------ > > > > 2 files changed, 11 insertions(+), 6 deletions(-) > > > > > > > > diff --git a/doc/guides/rel_notes/release_18_11.rst > > > > b/doc/guides/rel_notes/release_18_11.rst > > > > index 376128f..b68afab 100644 > > > > --- a/doc/guides/rel_notes/release_18_11.rst > > > > +++ b/doc/guides/rel_notes/release_18_11.rst > > > > @@ -69,6 +69,13 @@ New Features > > > > checked out against that dma mask and rejected if out of range. > > > > If more > > > than > > > > one device has addressing limitations, the dma mask is the more > > > restricted one. > > > > > > > > +* **Updated the ring library with C11 memory model.** > > > > + > > > > + Updated the ring library with C11 memory model, in our tests the > > > > + changes decreased latency by 27~29% and 3~15% for MPMC and SPSC > > > cases respectively. > > > > + The real improvements may vary with the number of contending > > > > + lcores and the size of ring. > > > > + > > > Is this a little misleading, and will users expect massive performance > > > improvements generally? The C11 model seems to be used only on some, > > > but not all, arm platforms, and then only with "make" builds. > > > > > > config/arm/meson.build: ['RTE_USE_C11_MEM_MODEL', false]] > This is an error. There is already an agreement that on Arm based platforms, C11 memory model would be used by default. Specific platforms can override it if required. > Would this be ab acceptable change for RC2 or RC3? If NXP and Cavium agrees, I think it can go in RC2. For RC3, not sure.