From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from out4-smtp.messagingengine.com (out4-smtp.messagingengine.com [66.111.4.28]) by dpdk.org (Postfix) with ESMTP id 349E7548B for ; Fri, 12 Apr 2019 10:45:15 +0200 (CEST) Received: from compute1.internal (compute1.nyi.internal [10.202.2.41]) by mailout.nyi.internal (Postfix) with ESMTP id 85F6421FFC; Fri, 12 Apr 2019 04:45:14 -0400 (EDT) Received: from mailfrontend2 ([10.202.2.163]) by compute1.internal (MEProxy); Fri, 12 Apr 2019 04:45:14 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=monjalon.net; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s=mesmtp; bh=z3MsNWGvzRwyhlTzNcUGXI5ASHfTYXS3qZ3ZrGdpy0E=; b=Y8Agdds/AVFr yfsZI2AT3RNvFsCZQ9xLX+mmThAdJpwxv8sFbTSwZ+Ik64dEeISF5VmcoG/JrBNy FTULPCijswwzd2YRvkmDo1CRhrybssika+sBYhHGsaD8vHZxkSDksnA71k9zuVDU pu1MRT5vbuxgJ8AEf+fJWIclw2QCkaA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-proxy:x-me-proxy:x-me-sender:x-me-sender :x-sasl-enc; s=fm2; bh=z3MsNWGvzRwyhlTzNcUGXI5ASHfTYXS3qZ3ZrGdpy 0E=; b=ZSDy5A/W45m/7dkJ7tmbCEDMueu352sj4mbF9XPYzvWarOe6MSWTuaEn7 qm4Igh49wJEEOXURaJBHuVIC/vFv0qEXbgjtVihV652qxDOFVcHrMfGaMXAjVhgz Qm/nKbcFjQItB7+0MWD+kgCrUIBp5u3A5QSU1nO6e/DTRYjUP29Ag+B9wDwA/K0i 2vpMAOUBz2lwP7YtuGkp04Dbxy1k0GqZLuOxFCbf9tXNZ4BH4Dc0OfTP7DLGY5Rz Sq+FTpQIIBUr8f9HT6HiqPVg5523i2HACIp2c9IkyVLklY+3y72mPlKxqh3qXFes klDaRNPvr29HygLf3+Xlw5ld6gqtQ== X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgeduuddrvddtgddufeegucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhephffvufffkfgjfhgggfgtsehtufertddttddvnecuhfhrohhmpefvhhhomhgr shcuofhonhhjrghlohhnuceothhhohhmrghssehmohhnjhgrlhhonhdrnhgvtheqnecukf hppeejjedrudefgedrvddtfedrudekgeenucfrrghrrghmpehmrghilhhfrhhomhepthhh ohhmrghssehmohhnjhgrlhhonhdrnhgvthenucevlhhushhtvghrufhiiigvpedt X-ME-Proxy: Received: from xps.localnet (184.203.134.77.rev.sfr.net [77.134.203.184]) by mail.messagingengine.com (Postfix) with ESMTPA id CE69410319; Fri, 12 Apr 2019 04:45:12 -0400 (EDT) From: Thomas Monjalon To: Jerin Jacob Kollanukkaran Cc: Pavan Nikhilesh Bhagavatula , "dev@dpdk.org" , "jerinjacobk@gmail.com" , "yskoh@mellanox.com" , "bruce.richardson@intel.com" Date: Fri, 12 Apr 2019 10:45:11 +0200 Message-ID: <1848175.uIgEXrQmFj@xps> In-Reply-To: References: <20190406142737.20091-1-jerinj@marvell.com> <7046361.HPUSkOkSIl@xps> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Subject: Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine specific flags X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 12 Apr 2019 08:45:15 -0000 12/04/2019 09:12, Jerin Jacob Kollanukkaran: > From: Thomas Monjalon > > 10/04/2019 18:13, jerinjacobk@gmail.com: > > > From: Pavan Nikhilesh > > > > > > Currently, RTE_* flags are set based on the implementer ID but there > > > might be some micro arch specific differences from the same vendor eg. > > > CACHE_LINESIZE. Add support to set micro arch specific flags. > > > > I don't like how flags are set in config/arm/meson.build. > > It is a real mess to find which flag applies to which machine. > > Adding the flags_*_extra in the machine_args_* is adding more mess. > > > > [...] > > > flags_common_default = [ > > > # Accelarate rte_memcpy. Be sure to run unit test > > (memcpy_perf_autotest) > > > # to determine the best threshold in code. Refer to notes in source > > > file @@ -52,12 +33,10 @@ flags_generic = [ > > > ['RTE_USE_C11_MEM_MODEL', true], > > > ['RTE_CACHE_LINE_SIZE', 128]] > > > flags_cavium = [ > > > - ['RTE_MACHINE', '"thunderx"'], > > > ['RTE_CACHE_LINE_SIZE', 128], > > > ['RTE_MAX_NUMA_NODES', 2], > > > ['RTE_MAX_LCORE', 96], > > > - ['RTE_MAX_VFIO_GROUPS', 128], > > > - ['RTE_USE_C11_MEM_MODEL', false]] > > > + ['RTE_MAX_VFIO_GROUPS', 128]] > > > flags_dpaa = [ > > > ['RTE_MACHINE', '"dpaa"'], > > > ['RTE_USE_C11_MEM_MODEL', true], > > > @@ -71,6 +50,27 @@ flags_dpaa2 = [ > > > ['RTE_MAX_NUMA_NODES', 1], > > > ['RTE_MAX_LCORE', 16], > > > ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]] > > > +flags_default_extra = [] > > > +flags_thunderx_extra = [ > > > + ['RTE_MACHINE', '"thunderx"'], > > > + ['RTE_USE_C11_MEM_MODEL', false]] > > > + > > > +machine_args_generic = [ > > > + ['default', ['-march=armv8-a+crc+crypto']], > > > + ['native', ['-march=native']], > > > + ['0xd03', ['-mcpu=cortex-a53']], > > > + ['0xd04', ['-mcpu=cortex-a35']], > > > + ['0xd07', ['-mcpu=cortex-a57']], > > > + ['0xd08', ['-mcpu=cortex-a72']], > > > + ['0xd09', ['-mcpu=cortex-a73']], > > > + ['0xd0a', ['-mcpu=cortex-a75']]] > > > + > > > +machine_args_cavium = [ > > > + ['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']], > > > + ['native', ['-march=native']], > > > + ['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra], > > > + ['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra], > > > + ['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]] > > > > I think we should have a simpler model. > > We need only to know the machine name and get all the related machine > > config. > > In native compilation, machine name is guessed from implementor id and pn > > (from config/arm/armv8_machine.py). We can directly output the machine > > name from this script and leave the naming logic in this script. > > In the cross-compilation config files (config/arm/*), we can just specify the > > machine name. > > Then every machine config (machine_args and dpdk_conf) would be > > specified in some arrays based on the machine name. > > Of course, we can keep some common default values. > > Thomas, > > This patch was around last three months. It reached upto v8. > I think, in that last minute for RC2, We cannot take major rework on this as it needs to tested for > Other arm64 platform too. It was pulled out from RC1 because other pcap issue from meson. > Now its not fair to say to rework the meson stuff now. > I suggest to take other rework in next release. I was not confortable with this patch without being able to say why. Yesterday I spent more time to understand and see what may be improved. I agree it is late, so it won't block this patch for 19.05. Do you agree this file can be improved? Please would you like to look at reworking during next cycle? Thanks From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by dpdk.space (Postfix) with ESMTP id 50AC2A0096 for ; Fri, 12 Apr 2019 10:45:17 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id B41C156A1; Fri, 12 Apr 2019 10:45:16 +0200 (CEST) Received: from out4-smtp.messagingengine.com (out4-smtp.messagingengine.com [66.111.4.28]) by dpdk.org (Postfix) with ESMTP id 349E7548B for ; Fri, 12 Apr 2019 10:45:15 +0200 (CEST) Received: from compute1.internal (compute1.nyi.internal [10.202.2.41]) by mailout.nyi.internal (Postfix) with ESMTP id 85F6421FFC; Fri, 12 Apr 2019 04:45:14 -0400 (EDT) Received: from mailfrontend2 ([10.202.2.163]) by compute1.internal (MEProxy); Fri, 12 Apr 2019 04:45:14 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=monjalon.net; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s=mesmtp; bh=z3MsNWGvzRwyhlTzNcUGXI5ASHfTYXS3qZ3ZrGdpy0E=; b=Y8Agdds/AVFr yfsZI2AT3RNvFsCZQ9xLX+mmThAdJpwxv8sFbTSwZ+Ik64dEeISF5VmcoG/JrBNy FTULPCijswwzd2YRvkmDo1CRhrybssika+sBYhHGsaD8vHZxkSDksnA71k9zuVDU pu1MRT5vbuxgJ8AEf+fJWIclw2QCkaA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-proxy:x-me-proxy:x-me-sender:x-me-sender :x-sasl-enc; s=fm2; bh=z3MsNWGvzRwyhlTzNcUGXI5ASHfTYXS3qZ3ZrGdpy 0E=; b=ZSDy5A/W45m/7dkJ7tmbCEDMueu352sj4mbF9XPYzvWarOe6MSWTuaEn7 qm4Igh49wJEEOXURaJBHuVIC/vFv0qEXbgjtVihV652qxDOFVcHrMfGaMXAjVhgz Qm/nKbcFjQItB7+0MWD+kgCrUIBp5u3A5QSU1nO6e/DTRYjUP29Ag+B9wDwA/K0i 2vpMAOUBz2lwP7YtuGkp04Dbxy1k0GqZLuOxFCbf9tXNZ4BH4Dc0OfTP7DLGY5Rz Sq+FTpQIIBUr8f9HT6HiqPVg5523i2HACIp2c9IkyVLklY+3y72mPlKxqh3qXFes klDaRNPvr29HygLf3+Xlw5ld6gqtQ== X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgeduuddrvddtgddufeegucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhephffvufffkfgjfhgggfgtsehtufertddttddvnecuhfhrohhmpefvhhhomhgr shcuofhonhhjrghlohhnuceothhhohhmrghssehmohhnjhgrlhhonhdrnhgvtheqnecukf hppeejjedrudefgedrvddtfedrudekgeenucfrrghrrghmpehmrghilhhfrhhomhepthhh ohhmrghssehmohhnjhgrlhhonhdrnhgvthenucevlhhushhtvghrufhiiigvpedt X-ME-Proxy: Received: from xps.localnet (184.203.134.77.rev.sfr.net [77.134.203.184]) by mail.messagingengine.com (Postfix) with ESMTPA id CE69410319; Fri, 12 Apr 2019 04:45:12 -0400 (EDT) From: Thomas Monjalon To: Jerin Jacob Kollanukkaran Cc: Pavan Nikhilesh Bhagavatula , "dev@dpdk.org" , "jerinjacobk@gmail.com" , "yskoh@mellanox.com" , "bruce.richardson@intel.com" Date: Fri, 12 Apr 2019 10:45:11 +0200 Message-ID: <1848175.uIgEXrQmFj@xps> In-Reply-To: References: <20190406142737.20091-1-jerinj@marvell.com> <7046361.HPUSkOkSIl@xps> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="UTF-8" Subject: Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine specific flags X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Message-ID: <20190412084511.qVkAdis3ra0T-v7xmMGLR_LhLCIZDER0bM8u5Htus1I@z> 12/04/2019 09:12, Jerin Jacob Kollanukkaran: > From: Thomas Monjalon > > 10/04/2019 18:13, jerinjacobk@gmail.com: > > > From: Pavan Nikhilesh > > > > > > Currently, RTE_* flags are set based on the implementer ID but there > > > might be some micro arch specific differences from the same vendor eg. > > > CACHE_LINESIZE. Add support to set micro arch specific flags. > > > > I don't like how flags are set in config/arm/meson.build. > > It is a real mess to find which flag applies to which machine. > > Adding the flags_*_extra in the machine_args_* is adding more mess. > > > > [...] > > > flags_common_default = [ > > > # Accelarate rte_memcpy. Be sure to run unit test > > (memcpy_perf_autotest) > > > # to determine the best threshold in code. Refer to notes in source > > > file @@ -52,12 +33,10 @@ flags_generic = [ > > > ['RTE_USE_C11_MEM_MODEL', true], > > > ['RTE_CACHE_LINE_SIZE', 128]] > > > flags_cavium = [ > > > - ['RTE_MACHINE', '"thunderx"'], > > > ['RTE_CACHE_LINE_SIZE', 128], > > > ['RTE_MAX_NUMA_NODES', 2], > > > ['RTE_MAX_LCORE', 96], > > > - ['RTE_MAX_VFIO_GROUPS', 128], > > > - ['RTE_USE_C11_MEM_MODEL', false]] > > > + ['RTE_MAX_VFIO_GROUPS', 128]] > > > flags_dpaa = [ > > > ['RTE_MACHINE', '"dpaa"'], > > > ['RTE_USE_C11_MEM_MODEL', true], > > > @@ -71,6 +50,27 @@ flags_dpaa2 = [ > > > ['RTE_MAX_NUMA_NODES', 1], > > > ['RTE_MAX_LCORE', 16], > > > ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]] > > > +flags_default_extra = [] > > > +flags_thunderx_extra = [ > > > + ['RTE_MACHINE', '"thunderx"'], > > > + ['RTE_USE_C11_MEM_MODEL', false]] > > > + > > > +machine_args_generic = [ > > > + ['default', ['-march=armv8-a+crc+crypto']], > > > + ['native', ['-march=native']], > > > + ['0xd03', ['-mcpu=cortex-a53']], > > > + ['0xd04', ['-mcpu=cortex-a35']], > > > + ['0xd07', ['-mcpu=cortex-a57']], > > > + ['0xd08', ['-mcpu=cortex-a72']], > > > + ['0xd09', ['-mcpu=cortex-a73']], > > > + ['0xd0a', ['-mcpu=cortex-a75']]] > > > + > > > +machine_args_cavium = [ > > > + ['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']], > > > + ['native', ['-march=native']], > > > + ['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra], > > > + ['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra], > > > + ['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]] > > > > I think we should have a simpler model. > > We need only to know the machine name and get all the related machine > > config. > > In native compilation, machine name is guessed from implementor id and pn > > (from config/arm/armv8_machine.py). We can directly output the machine > > name from this script and leave the naming logic in this script. > > In the cross-compilation config files (config/arm/*), we can just specify the > > machine name. > > Then every machine config (machine_args and dpdk_conf) would be > > specified in some arrays based on the machine name. > > Of course, we can keep some common default values. > > Thomas, > > This patch was around last three months. It reached upto v8. > I think, in that last minute for RC2, We cannot take major rework on this as it needs to tested for > Other arm64 platform too. It was pulled out from RC1 because other pcap issue from meson. > Now its not fair to say to rework the meson stuff now. > I suggest to take other rework in next release. I was not confortable with this patch without being able to say why. Yesterday I spent more time to understand and see what may be improved. I agree it is late, so it won't block this patch for 19.05. Do you agree this file can be improved? Please would you like to look at reworking during next cycle? Thanks