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From: Thomas Monjalon <thomas@monjalon.net>
To: jerinj@marvell.com
Cc: dev@dpdk.org, Nithin Dabilpuram <ndabilpuram@marvell.com>,
	Vamsi Attunuru <vattunuru@marvell.com>
Subject: Re: [dpdk-dev] [PATCH] common/octeontx2: fix to prevent STP instruction fissure
Date: Mon, 29 Jul 2019 21:54:17 +0200	[thread overview]
Message-ID: <1949620.u6UzGXYpOI@xps> (raw)
In-Reply-To: <20190726052443.21302-1-jerinj@marvell.com>

26/07/2019 07:24, jerinj@marvell.com:
> From: Jerin Jacob <jerinj@marvell.com>
> 
> OTX2 AP core can sometimes fissure STP instructions when it is more
> optimal to send such writes into the pipeline as 2 separate
> instructions. However registers should be excluded from such
> optimization. This commit ensures that no CSR write is ever fissured
> by introducing zero cost workaround by setting STP pre-index by zero to
> make sure OTX2 AP core prevent fissure.
> 
> Fixes: 8a4f835971f5 ("common/octeontx2: add IO handling APIs")
> 
> Signed-off-by: Jerin Jacob <jerinj@marvell.com>

Applied, thanks




  reply	other threads:[~2019-07-29 19:54 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-07-26  5:24 jerinj
2019-07-29 19:54 ` Thomas Monjalon [this message]
2019-07-27 11:51 Pavan Nikhilesh Bhagavatula

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