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> +; Supported features of the 'octeontx' crypto driver. > +; > +; Refer to default.ini for the full list of available PMD features. > +; > +[Features] > +Symmetric crypto = Y > +Sym operation chaining = Y > +HW Accelerated = Y > +Mbuf scatter gather = Y I do not see feature flags for scatter gather in the code. Please set what all is supported in the PMD. #define RTE_CRYPTODEV_FF_IN_PLACE_SGL                   (1ULL << 9) /**< In-place Scatter-gather (SGL) buffers, with multiple segments,  * are supported  */ #define RTE_CRYPTODEV_FF_OOP_SGL_IN_SGL_OUT             (1ULL << 10) /**< Out-of-place Scatter-gather (SGL) buffers are  * supported in input and output  */ #define RTE_CRYPTODEV_FF_OOP_SGL_IN_LB_OUT              (1ULL << 11) /**< Out-of-place Scatter-gather (SGL) buffers are supported  * in input, combined with linear buffers (LB), with a  * single segment in output  */ #define RTE_CRYPTODEV_FF_OOP_LB_IN_SGL_OUT              (1ULL << 12) /**< Out-of-place Scatter-gather (SGL) buffers are supported  * in output, combined with linear buffers (LB) in input  */ > + > +; > +; Supported crypto algorithms of 'octeontx' crypto driver. > +; > +[Cipher] > +NULL = Y > +3DES CBC = Y > +3DES ECB = Y > +AES CBC (128) = Y > +AES CBC (192) = Y > +AES CBC (256) = Y > +AES CTR (128) = Y > +AES CTR (192) = Y > +AES CTR (256) = Y > +AES XTS (128) = Y > +AES XTS (256) = Y > +DES CBC = Y > +KASUMI F8 = Y > +SNOW3G UEA2 = Y > +ZUC EEA3 = Y > + > +; > +; Supported authentication algorithms of 'octeontx' crypto driver. > +; > +[Auth] > +NULL = Y > +AES GMAC = Y > +KASUMI F9 = Y > +MD5 = Y > +MD5 HMAC = Y > +SHA1 = Y > +SHA1 HMAC = Y > +SHA224 = Y > +SHA224 HMAC = Y > +SHA256 = Y > +SHA256 HMAC = Y > +SHA384 = Y > +SHA384 HMAC = Y > +SHA512 = Y > +SHA512 HMAC = Y > +SNOW3G UIA2 = Y > +ZUC EIA3 = Y > + > +; > +; Supported AEAD algorithms of 'octeontx' crypto driver. > +; > +[AEAD] > +AES GCM (128) = Y > +AES GCM (192) = Y > +AES GCM (256) = Y > diff --git a/doc/guides/cryptodevs/octeontx.rst b/doc/guides/cryptodevs/octeontx.rst > new file mode 100644 > index 0000000..67bd441 > --- /dev/null > +++ b/doc/guides/cryptodevs/octeontx.rst > @@ -0,0 +1,121 @@ > +.. SPDX-License-Identifier: BSD-3-Clause > + Copyright(c) 2018 Cavium, Inc > + > +Cavium's OcteonTX Poll Mode Driver > +================================== > + > +The octeontx crypto poll mode driver provides support for offloading > +cryptographic operations on cryptographic accelerator units on OcteonTX > +family of processors (CN8XXX). The octeontx crypto poll mode driver enqueues > +the crypto request to this accelerator and dequeues the response once the > +operation is completed. > + > +Supported Algorithms > +--------------------- remove one extra '-'. Please check at other places as well > + > +Cipher Algorithms > +~~~~~~~~~~~~~~~~~ > + > +* ``RTE_CRYPTO_CIPHER_NULL`` > +* ``RTE_CRYPTO_CIPHER_3DES_CBC`` > +* ``RTE_CRYPTO_CIPHER_3DES_ECB`` > +* ``RTE_CRYPTO_CIPHER_AES_CBC`` > +* ``RTE_CRYPTO_CIPHER_AES_CTR`` > +* ``RTE_CRYPTO_CIPHER_AES_XTS`` > +* ``RTE_CRYPTO_CIPHER_DES_CBC`` > +* ``RTE_CRYPTO_CIPHER_KASUMI_F8`` > +* ``RTE_CRYPTO_CIPHER_SNOW3G_UEA2`` > +* ``RTE_CRYPTO_CIPHER_ZUC_EEA3`` > + > +Hash Algorithms > +~~~~~~~~~~~~~~~ > + > +* ``RTE_CRYPTO_AUTH_NULL`` > +* ``RTE_CRYPTO_AUTH_AES_GMAC`` > +* ``RTE_CRYPTO_AUTH_KASUMI_F9`` > +* ``RTE_CRYPTO_AUTH_MD5`` > +* ``RTE_CRYPTO_AUTH_MD5_HMAC`` > +* ``RTE_CRYPTO_AUTH_SHA1`` > +* ``RTE_CRYPTO_AUTH_SHA1_HMAC`` > +* ``RTE_CRYPTO_AUTH_SHA224`` > +* ``RTE_CRYPTO_AUTH_SHA224_HMAC`` > +* ``RTE_CRYPTO_AUTH_SHA256`` > +* ``RTE_CRYPTO_AUTH_SHA256_HMAC`` > +* ``RTE_CRYPTO_AUTH_SHA384`` > +* ``RTE_CRYPTO_AUTH_SHA384_HMAC`` > +* ``RTE_CRYPTO_AUTH_SHA512`` > +* ``RTE_CRYPTO_AUTH_SHA512_HMAC`` > +* ``RTE_CRYPTO_AUTH_SNOW3G_UIA2`` > +* ``RTE_CRYPTO_AUTH_ZUC_EIA3`` > + > +AEAD Algorithms > +~~~~~~~~~~~~~~~~ > + > +* ``RTE_CRYPTO_AEAD_AES_GCM`` > + > +Compilation > +------------ > + > +The OcteonTX board must be running the linux kernel based on sdk-6.2.0 patch 3. > +In this the OcteonTX pf driver is already built in. > + > +For compiling the OcteonTX crypto poll mode driver, please check if the > +CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO setting is set to `y` in > +config/common_base file. > + > +* ``CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO=y`` > + > +The following are the steps to compile the octeontx poll mode driver: > + > +.. code-block:: console > + > + cd > + make config T=arm64-thunderx-linuxapp-gcc > + make > + > +The example applications can be compiled using the following: > + > +.. code-block:: console > + > + cd > + export RTE_SDK=$PWD > + export RTE_TARGET=build > + cd examples/ > + make > + > +Execution > +---------- > + > +The sriov_numvfs should be assigned for the octeontx pf driver using the > +following: > + > +.. code-block:: console > + > + echo > /sys/bus/pci/devices//sriov_numvfs > + > +The device number can be ascertained by running the dpdk-devbind.py scripts in > +the dpdk sources. > + > +Then the corresponding vf should be binded to the vfio-pci driver using the > +following: > + > +.. code-block:: console > + > + cd > + ./usertools/dpdk-devbind.py -u > + ./usertools/dpdk-devbind.py -b vfio-pci > + > +Appropriate huge page need to be setup in order to run the examples dpdk > +application. > + > +.. code-block:: console > + > + echo 8 > /sys/kernel/mm/hugepages/hugepages-524288kB/nr_hugepages > + mkdir /mnt/huge > + mount -t hugetlbfs nodev /mnt/huge > + > +After that the example dpdk application can be executed on the hardware. > + > +.. code-block:: console > + ./build/ipsec-secgw --log-level=8 -c 0xff -- -P -p 0x3 -u 0x2 --config > + "(1,0,0),(0,0,0)" -f ep1.cfg >