From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 336C045501; Wed, 26 Jun 2024 14:00:09 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 66D8B433E6; Wed, 26 Jun 2024 13:55:54 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) by mails.dpdk.org (Postfix) with ESMTP id 8E66F42E95 for ; Wed, 26 Jun 2024 13:44:17 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719402257; x=1750938257; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=JFOvGinUehEFKiqzV9N8vlueW70Ii5iROrPrM/q+DqU=; b=FwiPLTU2YjzhNJySdVP7iod/FNbfU5EiMVC1ZfAYO6nECnh89bIkevhc bmoZgYe8YePzUPKHV8f87zINkL/0NRW7LNhzQ+8RlSqamXooY7jKMSlMI bDiPLSP/WP1hHQ88ouo/+hrfqJHAXv3tOMNyBVwkKqcLALId1MgxVBJFP vh8jz4glEwvG8C0RqJVS59uTdWrNYFB0TlhhS5yCfxTHGUFiDZWJCIBBE ojAc49MSORjfc58ti97DqXvUj8s4v7FnN4bQtuKRCROU5DQUjOLfcmF6l 3OHAO4sGB5tBxX3XbZ19ao0xzdpinB/3N42wkI4aupoiUvuNz1c2InKEF g==; X-CSE-ConnectionGUID: w39lRGinTW6klzV6KUPOaw== X-CSE-MsgGUID: N7ET3RyiTi6EBTOLnmx9lQ== X-IronPort-AV: E=McAfee;i="6700,10204,11114"; a="38979423" X-IronPort-AV: E=Sophos;i="6.08,266,1712646000"; d="scan'208";a="38979423" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jun 2024 04:44:17 -0700 X-CSE-ConnectionGUID: GaCAbK0TS7u6lSl26qZmMw== X-CSE-MsgGUID: DaUzfxpESLGZuZJVKk/Ctg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,266,1712646000"; d="scan'208";a="43873923" Received: from unknown (HELO silpixa00401119.ir.intel.com) ([10.55.129.167]) by orviesa010.jf.intel.com with ESMTP; 26 Jun 2024 04:44:16 -0700 From: Anatoly Burakov To: dev@dpdk.org Cc: Tomaszx Wakula , ian.stokes@intel.com, bruce.richardson@intel.com Subject: [PATCH v4 046/103] net/ice/base: add function to read SDP section from NVM Date: Wed, 26 Jun 2024 12:41:34 +0100 Message-ID: <1a96b3d633c21bdba10d0831e02b3080ab406636.1719401848.git.anatoly.burakov@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Tomaszx Wakula Add API and definitions related to reading Software Definable Pin section from NVM, related to PTP pins assignment. Signed-off-by: Tomaszx Wakula Signed-off-by: Ian Stokes --- drivers/net/ice/base/ice_adminq_cmd.h | 23 +++++++ drivers/net/ice/base/ice_ptp_hw.c | 87 +++++++++++++++++++++++++++ drivers/net/ice/base/ice_ptp_hw.h | 3 + 3 files changed, 113 insertions(+) diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h index 4a20a7ac35..d828731a5b 100644 --- a/drivers/net/ice/base/ice_adminq_cmd.h +++ b/drivers/net/ice/base/ice_adminq_cmd.h @@ -1976,6 +1976,29 @@ struct ice_aqc_nvm { #define ICE_AQC_NVM_LLDP_STATUS_M_LEN 4 /* In Bits */ #define ICE_AQC_NVM_LLDP_STATUS_RD_LEN 4 /* In Bytes */ +#define ICE_AQC_NVM_SDP_CFG_PTR_OFFSET 0xD8 +#define ICE_AQC_NVM_SDP_CFG_PTR_RD_LEN 2 /* In Bytes */ +#define ICE_AQC_NVM_SDP_CFG_PTR_M MAKEMASK(0x7FFF, 0) +#define ICE_AQC_NVM_SDP_CFG_PTR_TYPE_M BIT(15) +#define ICE_AQC_NVM_SDP_CFG_HEADER_LEN 2 /* In Bytes */ +#define ICE_AQC_NVM_SDP_CFG_SEC_LEN_LEN 2 /* In Bytes */ +#define ICE_AQC_NVM_SDP_CFG_DATA_LEN 14 /* In Bytes */ +#define ICE_AQC_NVM_SDP_CFG_MAX_SECTION_SIZE 7 +#define ICE_AQC_NVM_SDP_CFG_PIN_SIZE 10 +#define ICE_AQC_NVM_SDP_CFG_PIN_OFFSET 6 +#define ICE_AQC_NVM_SDP_CFG_PIN_MASK MAKEMASK(0x3FF, \ + ICE_AQC_NVM_SDP_CFG_PIN_OFFSET) +#define ICE_AQC_NVM_SDP_CFG_CHAN_OFFSET 4 +#define ICE_AQC_NVM_SDP_CFG_CHAN_MASK MAKEMASK(0x3, \ + ICE_AQC_NVM_SDP_CFG_CHAN_OFFSET) +#define ICE_AQC_NVM_SDP_CFG_DIR_OFFSET 3 +#define ICE_AQC_NVM_SDP_CFG_DIR_MASK MAKEMASK(0x1, \ + ICE_AQC_NVM_SDP_CFG_DIR_OFFSET) +#define ICE_AQC_NVM_SDP_CFG_SDP_NUM_OFFSET 0 +#define ICE_AQC_NVM_SDP_CFG_SDP_NUM_MASK MAKEMASK(0x7, \ + ICE_AQC_NVM_SDP_CFG_SDP_NUM_OFFSET) +#define ICE_AQC_NVM_SDP_CFG_NA_PIN_MASK MAKEMASK(0x1, 15) + #define ICE_AQC_NVM_TX_TOPO_MOD_ID 0x14B #define ICE_AQC_NVM_CMPO_MOD_ID 0x153 diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c index 5609145b8d..8ea4e77266 100644 --- a/drivers/net/ice/base/ice_ptp_hw.c +++ b/drivers/net/ice/base/ice_ptp_hw.c @@ -5073,6 +5073,93 @@ bool ice_is_pca9575_present(struct ice_hw *hw) return false; } +/** + * ice_ptp_read_sdp_section_from_nvm - reads SDP section from NVM + * @hw: pointer to the HW struct + * @section_exist: on return, returns true if section exist + * @pin_desc_num: on return, returns the number of ice_ptp_pin_desc entries + * @pin_config_num: on return, returns the number of pin that should be + * exposed on pin_config I/F + * @sdp_entries: on return, returns the SDP connection section from NVM + * @nvm_entries: on return, returns the number of valid entries in sdp_entries + * + * Reads SDP connection section from NVM + * Returns -1 if NVM read failed or section corrupted, otherwise 0 + */ +int ice_ptp_read_sdp_section_from_nvm(struct ice_hw *hw, bool *section_exist, + u8 *pin_desc_num, u8 *pin_config_num, + u16 *sdp_entries, u8 *nvm_entries) +{ + __le16 loc_raw_data, raw_nvm_entries; + u32 loc_data, i, all_pin_bitmap = 0; + int err; + + *section_exist = false; + *pin_desc_num = 0; + *pin_config_num = 0; + + err = ice_acquire_nvm(hw, ICE_RES_READ); + if (err) + goto exit; + + /* Read the offset of EMP_SR_PTR */ + err = ice_aq_read_nvm(hw, ICE_AQC_NVM_START_POINT, + ICE_AQC_NVM_SDP_CFG_PTR_OFFSET, + ICE_AQC_NVM_SDP_CFG_PTR_RD_LEN, + &loc_raw_data, false, true, NULL); + if (err) + goto exit; + + /* check if section exist */ + loc_data = LE16_TO_CPU(loc_raw_data); + if ((loc_data & ICE_AQC_NVM_SDP_CFG_PTR_M) == ICE_AQC_NVM_SDP_CFG_PTR_M) + goto exit; + + if (loc_data & ICE_AQC_NVM_SDP_CFG_PTR_TYPE_M) { + loc_data &= ICE_AQC_NVM_SDP_CFG_PTR_M; + loc_data *= ICE_AQC_NVM_SECTOR_UNIT; + } else { + loc_data *= ICE_AQC_NVM_WORD_UNIT; + } + + /* Skip SDP configuration section length (2 bytes) */ + loc_data += ICE_AQC_NVM_SDP_CFG_HEADER_LEN; + + /* read number of valid entries */ + err = ice_aq_read_nvm(hw, ICE_AQC_NVM_START_POINT, loc_data, + ICE_AQC_NVM_SDP_CFG_SEC_LEN_LEN, &raw_nvm_entries, + false, true, NULL); + if (err) + goto exit; + *nvm_entries = (u8)LE16_TO_CPU(raw_nvm_entries); + + /* Read entire SDP configuration section */ + loc_data += ICE_AQC_NVM_SDP_CFG_SEC_LEN_LEN; + err = ice_aq_read_nvm(hw, ICE_AQC_NVM_START_POINT, loc_data, + ICE_AQC_NVM_SDP_CFG_DATA_LEN, sdp_entries, + false, true, NULL); + if (err) + goto exit; + + /* get number of existing pin/connector */ + for (i = 0; i < *nvm_entries; i++) { + all_pin_bitmap |= (sdp_entries[i] & + ICE_AQC_NVM_SDP_CFG_PIN_MASK) >> + ICE_AQC_NVM_SDP_CFG_PIN_OFFSET; + if (sdp_entries[i] & ICE_AQC_NVM_SDP_CFG_NA_PIN_MASK) + *pin_desc_num += 1; + } + + for (i = 0; i < ICE_AQC_NVM_SDP_CFG_PIN_SIZE - 1; i++) + *pin_config_num += (all_pin_bitmap & (1 << i)) != 0; + *pin_desc_num += *pin_config_num; + + *section_exist = true; +exit: + ice_release_nvm(hw); + return err; +} + /** * ice_ptp_write_direct_incval_e830 - Prep PHY port increment value change * @hw: pointer to HW struct diff --git a/drivers/net/ice/base/ice_ptp_hw.h b/drivers/net/ice/base/ice_ptp_hw.h index 7c0c5ae562..4c63bba722 100644 --- a/drivers/net/ice/base/ice_ptp_hw.h +++ b/drivers/net/ice/base/ice_ptp_hw.h @@ -261,6 +261,9 @@ ice_write_pca9575_reg_e810t(struct ice_hw *hw, u8 offset, u8 data); int ice_read_sma_ctrl_e810t(struct ice_hw *hw, u8 *data); int ice_write_sma_ctrl_e810t(struct ice_hw *hw, u8 data); bool ice_is_pca9575_present(struct ice_hw *hw); +int ice_ptp_read_sdp_section_from_nvm(struct ice_hw *hw, bool *section_exist, + u8 *pin_desc_num, u8 *pin_config_num, + u16 *sdp_entries, u8 *nvm_entries); void ice_ptp_process_cgu_err(struct ice_hw *hw, struct ice_rq_event_info *event); -- 2.43.0