From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 18091A0547; Thu, 29 Apr 2021 16:31:48 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 86214410DD; Thu, 29 Apr 2021 16:31:47 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mails.dpdk.org (Postfix) with ESMTP id A26FF406FF; Thu, 29 Apr 2021 16:31:45 +0200 (CEST) IronPort-SDR: sQtTBS6X3Iu+lzGezIrUIJLhU2NgtK34QW5rCWU5/vQCvUCVmFxIrSaqdkmZKncJNHNn0y+WGF PD2y65mHtnkA== X-IronPort-AV: E=McAfee;i="6200,9189,9969"; a="197116438" X-IronPort-AV: E=Sophos;i="5.82,259,1613462400"; d="scan'208";a="197116438" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2021 07:31:20 -0700 IronPort-SDR: 9VebcG6ywZMS467aBZRdh4DM45GNOa414ejxAcWpAfRmL/KGpuRCLzs+yDQCsVK77CyGoZUuIq zdemMjafeG3g== X-IronPort-AV: E=Sophos;i="5.82,259,1613462400"; d="scan'208";a="526964864" Received: from fyigit-mobl1.ger.corp.intel.com (HELO [10.213.208.65]) ([10.213.208.65]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2021 07:31:18 -0700 To: Jiawen Wu , dev@dpdk.org Cc: stable@dpdk.org References: <20210429103335.23060-1-jiawenwu@trustnetic.com> <20210429103335.23060-2-jiawenwu@trustnetic.com> From: Ferruh Yigit X-User: ferruhy Message-ID: <1fd58ff8-5028-2216-eec7-1437630de896@intel.com> Date: Thu, 29 Apr 2021 15:31:14 +0100 MIME-Version: 1.0 In-Reply-To: <20210429103335.23060-2-jiawenwu@trustnetic.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Subject: Re: [dpdk-dev] [dpdk-stable] [PATCH v2 1/5] net/txgbe: fix RSS in QINQ X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On 4/29/2021 11:33 AM, Jiawen Wu wrote: > Support to enable and disable QINQ hardware strip, > when configure vlan offload with QINQ strip mask, > to avoid RSS does not work for QINQ packets. > Hi Jiawen, What was not working and fixed here? Is it RSS hash calculation is wrong when packet has double VLAN tag? Is it failing to calculate hash for VLAN field of the packet or calculation for any fields are wrong? Can't device detect/parse QinQ fields? And how enabling QinQ strip is solving the issue? Should user enable QinQ strip before configuring the RSS? What happens if user don't, should driver has checks to cover this, like fail to enable RSS if QinQ strip is not enable etc? Can you please provide more details? > Fixes: 220b0e49bc47 ("net/txgbe: support VLAN") > Cc: stable@dpdk.org > > Signed-off-by: Jiawen Wu > --- > drivers/net/txgbe/txgbe_ethdev.c | 39 +++++++++++++++++++++++++++----- > 1 file changed, 33 insertions(+), 6 deletions(-) > > diff --git a/drivers/net/txgbe/txgbe_ethdev.c b/drivers/net/txgbe/txgbe_ethdev.c > index 97796f040b..3d6d356102 100644 > --- a/drivers/net/txgbe/txgbe_ethdev.c > +++ b/drivers/net/txgbe/txgbe_ethdev.c > @@ -1209,7 +1209,6 @@ txgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev) > > ctrl = rd32(hw, TXGBE_PORTCTL); > ctrl &= ~TXGBE_PORTCTL_VLANEXT; > - ctrl &= ~TXGBE_PORTCTL_QINQ; > wr32(hw, TXGBE_PORTCTL, ctrl); > } > > @@ -1217,17 +1216,38 @@ static void > txgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev) > { > struct txgbe_hw *hw = TXGBE_DEV_HW(dev); > - struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode; > - struct rte_eth_txmode *txmode = &dev->data->dev_conf.txmode; > uint32_t ctrl; > > PMD_INIT_FUNC_TRACE(); > > ctrl = rd32(hw, TXGBE_PORTCTL); > ctrl |= TXGBE_PORTCTL_VLANEXT; > - if (rxmode->offloads & DEV_RX_OFFLOAD_QINQ_STRIP || > - txmode->offloads & DEV_TX_OFFLOAD_QINQ_INSERT) > - ctrl |= TXGBE_PORTCTL_QINQ; > + wr32(hw, TXGBE_PORTCTL, ctrl); > +} > + > +static void > +txgbe_qinq_hw_strip_disable(struct rte_eth_dev *dev) > +{ > + struct txgbe_hw *hw = TXGBE_DEV_HW(dev); > + uint32_t ctrl; > + > + PMD_INIT_FUNC_TRACE(); > + > + ctrl = rd32(hw, TXGBE_PORTCTL); > + ctrl &= ~TXGBE_PORTCTL_QINQ; > + wr32(hw, TXGBE_PORTCTL, ctrl); > +} > + > +static void > +txgbe_qinq_hw_strip_enable(struct rte_eth_dev *dev) > +{ > + struct txgbe_hw *hw = TXGBE_DEV_HW(dev); > + uint32_t ctrl; > + > + PMD_INIT_FUNC_TRACE(); > + > + ctrl = rd32(hw, TXGBE_PORTCTL); > + ctrl |= TXGBE_PORTCTL_QINQ | TXGBE_PORTCTL_VLANEXT; > wr32(hw, TXGBE_PORTCTL, ctrl); > } > > @@ -1294,6 +1314,13 @@ txgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask) > txgbe_vlan_hw_extend_disable(dev); > } > > + if (mask & ETH_QINQ_STRIP_MASK) { > + if (rxmode->offloads & DEV_RX_OFFLOAD_QINQ_STRIP) > + txgbe_qinq_hw_strip_enable(dev); > + else > + txgbe_qinq_hw_strip_disable(dev); > + } > + > return 0; > } > >