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Date: Thu, 2 Jan 2014 08:32:42 -0800
From: Stephen Hemminger <stephen@networkplumber.org>
To: Thomas Monjalon <thomas.monjalon@6wind.com>
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Cc: dev@dpdk.org
Subject: Re: [dpdk-dev] [PATCH] spinlock: fix atomic and out of order
execution
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On Sat, 21 Dec 2013 00:37:36 +0100
Thomas Monjalon <thomas.monjalon@6wind.com> wrote:
> From: Damien Millescamps <damien.millescamps@6wind.com>
>=20
> Add lock prefix before xchg instructions in order to be atomic
> and flush speculative values to ensure effective execution order
> (as an acquire barrier).
>=20
> MPLOCKED is a "lock" in multicore case.
>=20
> Signed-off-by: Damien Millescamps <damien.millescamps@6wind.com>
> Signed-off-by: Thomas Monjalon <thomas.monjalon@6wind.com>
> ---
> lib/librte_eal/common/include/rte_spinlock.h | 7 ++++---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>=20
> diff --git a/lib/librte_eal/common/include/rte_spinlock.h b/lib/librte_ea=
l/common/include/rte_spinlock.h
> index f7a245a..8edb971 100644
> --- a/lib/librte_eal/common/include/rte_spinlock.h
> +++ b/lib/librte_eal/common/include/rte_spinlock.h
> @@ -51,6 +51,7 @@
> extern "C" {
> #endif
> =20
> +#include <rte_atomic.h>
> #include <rte_lcore.h>
> #ifdef RTE_FORCE_INTRINSICS
> #include <rte_common.h>
> @@ -93,7 +94,7 @@ rte_spinlock_lock(rte_spinlock_t *sl)
> int lock_val =3D 1;
> asm volatile (
> "1:\n"
> - "xchg %[locked], %[lv]\n"
> + MPLOCKED "xchg %[locked], %[lv]\n"
> "test %[lv], %[lv]\n"
> "jz 3f\n"
> "2:\n"
> @@ -124,7 +125,7 @@ rte_spinlock_unlock (rte_spinlock_t *sl)
> #ifndef RTE_FORCE_INTRINSICS
> int unlock_val =3D 0;
> asm volatile (
> - "xchg %[locked], %[ulv]\n"
> + MPLOCKED "xchg %[locked], %[ulv]\n"
> : [locked] "=3Dm" (sl->locked), [ulv] "=3Dq" (unlock_val)
> : "[ulv]" (unlock_val)
> : "memory");
> @@ -148,7 +149,7 @@ rte_spinlock_trylock (rte_spinlock_t *sl)
> int lockval =3D 1;
> =20
> asm volatile (
> - "xchg %[locked], %[lockval]"
> + MPLOCKED "xchg %[locked], %[lockval]"
> : [locked] "=3Dm" (sl->locked), [lockval] "=3Dq" (lockval)
> : "[lockval]" (lockval)
> : "memory");
The locked prefix is required for xchg instruction.
The processor does it automatically.
http://www.intel.com/content/www/us/en/processors/architectures-software-de=
veloper-manuals.html
"The XCHG (exchange) instruction swaps the contents of two operands. This i=
nstruction takes the place of three
MOV instructions and does not require a temporary location to save the cont=
ents of one operand location while the
other is being loaded. When a memory operand is used with the XCHG instruct=
ion, the processor=E2=80=99s LOCK signal is
automatically asserted.