From: Stephen Hemminger <stephen@networkplumber.org>
To: Olivier MATZ <olivier.matz@6wind.com>
Cc: "dev@dpdk.org" <dev@dpdk.org>
Subject: Re: [dpdk-dev] memory barriers in rte_ring
Date: Thu, 27 Mar 2014 13:20:13 -0700 [thread overview]
Message-ID: <20140327132013.10011e6a@samsung-9> (raw)
In-Reply-To: <53348059.6000505@6wind.com>
On Thu, 27 Mar 2014 20:47:37 +0100
Olivier MATZ <olivier.matz@6wind.com> wrote:
> Hi Stephen,
>
> On 03/27/2014 08:06 PM, Stephen Hemminger wrote:
> > Long answer: for the multple CPU access ring, it is equivalent to smp_wmb and smp_rmb
> > in Linux kernel. For x86 where DPDK is used, this can normally be replaced by simpler
> > compiler barrier. In kernel there is a special flage X86_OOSTORE which is only enabled
> > for a few special cases, for most cases it is not. When cpu doesnt do out of order
> > stores, there are no cases where other cpu will see wrong state.
>
> Thank you for this clarification.
>
> So, if I understand properly, all usages of rte_*mb() sequencing memory
> operations between CPUs could be replaced by a compiler barrier. On the
> other hand, if the memory is also accessed by a device, a memory
> barrier has to be used.
>
> Olivier
>
I think so for the current architecture that DPDK runs on. It might be good
to abstract this in some way for eventual users in other environments.
next prev parent reply other threads:[~2014-03-27 20:18 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-03-27 16:48 Olivier MATZ
2014-03-27 19:06 ` Stephen Hemminger
2014-03-27 19:47 ` Olivier MATZ
2014-03-27 20:20 ` Stephen Hemminger [this message]
2014-03-27 23:53 ` Venkatesan, Venky
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