From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by dpdk.org (Postfix) with ESMTP id DE8BC6A80 for ; Wed, 15 Apr 2015 18:05:50 +0200 (CEST) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga102.jf.intel.com with ESMTP; 15 Apr 2015 09:05:30 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.11,582,1422950400"; d="scan'208";a="680578400" Received: from bricha3-mobl3.ger.corp.intel.com ([10.243.20.33]) by orsmga001.jf.intel.com with SMTP; 15 Apr 2015 09:05:28 -0700 Received: by (sSMTP sendmail emulation); Wed, 15 Apr 2015 17:05:27 +0025 Date: Wed, 15 Apr 2015 17:05:27 +0100 From: Bruce Richardson To: "Kavanagh, Mark B" Message-ID: <20150415160527.GA9836@bricha3-MOBL3> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Organization: Intel Shannon Ltd. User-Agent: Mutt/1.5.23 (2014-03-12) Cc: "dev@dpdk.org" Subject: Re: [dpdk-dev] Minimum Supported x86 microarchitecture X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 15 Apr 2015 16:05:51 -0000 On Wed, Apr 15, 2015 at 03:09:39PM +0000, Kavanagh, Mark B wrote: > Hi, > > The recent reimplementation of rte_memcpy in DPDK v2.0.0 seems to have a placed an implicit floor on the microarchitecture/Instruction set supported by DPDK. > > For example, I can't compile head of OVS against DPDK 2.0 with gcc without passing the 'msse3' flag; this points to an implicit minimum supported CPU of 'core2'. More discussion on same is available here: http://openvswitch.org/pipermail/dev/2015-April/053523.html > > Can anyone confirm or deny this, and is/should it be documented? > > Thanks in advance, > Mark SSE3 is the minimum necessary. However, I believe all x86_64 cpus have at least SSE3 support, so this should only be a problem with 32-bit builds. Is this the case for you? /Bruce