From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pd0-f175.google.com (mail-pd0-f175.google.com [209.85.192.175]) by dpdk.org (Postfix) with ESMTP id 048CBC428 for ; Mon, 11 May 2015 17:00:18 +0200 (CEST) Received: by pdbnk13 with SMTP id nk13so148444733pdb.0 for ; Mon, 11 May 2015 08:00:17 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:date:from:to:cc:subject:message-id:in-reply-to :references:mime-version:content-type:content-transfer-encoding; bh=HvYZMTrfCXTUTFDCZvXtuX82kKyMinAYiPC28j80HFw=; b=lrk2Y82WxjfuTTTVCJQo/R0Mi1CHOZ8HAhIzt7FmcgUmpKyy0zYY/7quurMFfj/sqT F8369bxDNZJokNAP7w5piQeHp3b7KEerHSWb6TOtTte5dSUry343vWLNpLW3D7KNVJcv PF6x8ZmfYf1nS8LcXE7cu9AvXQ/V189UQ7d/ADd5au+IrJzo5Y4QdJc/0PPgLaBCyhWX 31+dV7OGsFP4vC1dFRQlTLyiXmmgAcKX8sygPPVsqqFGNeDjQQjbUuc4W5o66R4buI+w Ub8QTBLByWjDcLCbZCRICaU8FGQ5FtgVol/dGY09L8jkIPRAt1FAEAIun00URd7idu2Q Gzrg== X-Gm-Message-State: ALoCoQmqb/9VSCzT//rIZB4Mn73Td9WFSmcN8RWb1ePN3OTMQAoKmXwr4nIkmK2QaeuUnk5OCjqU X-Received: by 10.66.250.166 with SMTP id zd6mr20454153pac.122.1431356417206; Mon, 11 May 2015 08:00:17 -0700 (PDT) Received: from urahara (static-50-53-82-155.bvtn.or.frontiernet.net. [50.53.82.155]) by mx.google.com with ESMTPSA id cp10sm13409839pdb.44.2015.05.11.08.00.16 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 11 May 2015 08:00:16 -0700 (PDT) Date: Mon, 11 May 2015 08:00:19 -0700 From: Stephen Hemminger To: "Liang, Cunming" Message-ID: <20150511080019.2b7b2982@urahara> In-Reply-To: <55503E98.805@intel.com> References: <1425012976-10173-1-git-send-email-cunming.liang@intel.com> <1430804386-28949-1-git-send-email-cunming.liang@intel.com> <1430804386-28949-9-git-send-email-cunming.liang@intel.com> <20150505113611.1359e2d8@urahara> <55503E98.805@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Cc: dev@dpdk.org Subject: Re: [dpdk-dev] [PATCH v7 08/10] ixgbe: enable rx queue interrupts for both PF and VF X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 May 2015 15:00:18 -0000 On Mon, 11 May 2015 13:31:04 +0800 "Liang, Cunming" wrote: > > Since MSI-X vectors are limited on many hardware platforms, this whole API > > should be changed so that max_intr is based on number of rx_queues actually > > used by the application. That means the setup needs to move from init to configure. > [LCM] When MSI-X is not used, intr_vec and set max_intr are useless. It > doesn't matter to non MSI-X mode. > As it allows the sequence "dev_stop->dev_reconfig->dev_start", the real > used number of queue may change. > So allocation only on dev_init and release only on dev_close, just make > it simple. During configure_msix, it do use the real useful queue number > to set queue/vector mapping, refer xxx_configure_msix(). The problem is that if a customer has 16 NIC's with 32 MSI vectors per NIC, it maybe that the MSI table in south bridge gets full. That is why the ixgbe driver for Linux limits itself to num_online_cpu() + 1 MSI interrrupts.