From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by dpdk.org (Postfix) with ESMTP id 30DE15A65 for ; Wed, 1 Jul 2015 14:59:23 +0200 (CEST) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga103.jf.intel.com with ESMTP; 01 Jul 2015 05:59:22 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.15,385,1432623600"; d="scan'208";a="738473410" Received: from bricha3-mobl3.ger.corp.intel.com ([10.237.208.162]) by fmsmga001.fm.intel.com with SMTP; 01 Jul 2015 05:59:19 -0700 Received: by (sSMTP sendmail emulation); Wed, 01 Jul 2015 13:59:18 +0025 Date: Wed, 1 Jul 2015 13:59:18 +0100 From: Bruce Richardson To: Pavel Odintsov Message-ID: <20150701125918.GA6960@bricha3-MOBL3> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Organization: Intel Shannon Ltd. User-Agent: Mutt/1.5.23 (2014-03-12) Cc: "dev@dpdk.org" Subject: Re: [dpdk-dev] Could not achieve wire speed for 40GE with any DPDK version on XL710 NIC's X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 01 Jul 2015 12:59:23 -0000 On Wed, Jul 01, 2015 at 03:44:57PM +0300, Pavel Odintsov wrote: > Thanks for answer, Vladimir! So we need look for x16 NIC if we want > achieve 40GE line rate... > Note that this would only apply for your minimal i.e. 64-byte, packet sizes. Once you go up to larger e.g. 128B packets, your PCI bandwidth requirements are lower and you can easier achieve line rate. /Bruce > On Wed, Jul 1, 2015 at 3:06 PM, Vladimir Medvedkin wrote: > > Hi Pavel, > > > > Looks like you ran into pcie bottleneck. So let's calculate xl710 rx only > > case. > > Assume we have 32byte descriptors (if we want more offload). > > DMA makes one pcie transaction with packet payload, one descriptor writeback > > and one memory request for free descriptors for every 4 packets. For > > Transaction Layer Packet (TLP) there is 30 bytes overhead (4 PHY + 6 DLL + > > 16 header + 4 ECRC). So for 1 rx packet dma sends 30 + 64(packet itself) + > > 30 + 32 (writeback descriptor) + (16 / 4) (read request for new > > descriptors). Note that we do not take into account PCIe ACK/NACK/FC Update > > DLLP. So we have 160 bytes per packet. One lane PCIe 3.0 transmits 1 byte in > > 1 ns, so x8 transmits 8 bytes in 1 ns. 1 packet transmits in 20 ns. Thus > > in theory pcie 3.0 x8 may transfer not more than 50mpps. > > Correct me if I'm wrong. > > > > Regards, > > Vladimir > > > >